Shift register unit, gate drive circuit, drive method, and display device

Abstract

The embodiments of the present disclosure disclose a shift register unit, a gate drive circuit, a driving method and a display device. An input sub-circuit is coupled with a first node and configured to provide a signal of an input signal terminal to the first node in response to a signal of a first clock signal terminal; a first control sub-circuit is coupled with a second node and configured to provide a signal of a first reference signal terminal to the second node in response to a signal of a first control signal terminal; a second control sub-circuit is coupled with the first node, the second node and a third node, and configured to control the signal of the second node according to a signal of a second reference signal terminal, and to turn on the first node and the third node in response to a signal of a third reference signal terminal; and an output sub-circuit is coupled with the second node and the third node, and configured to provide a signal of the third reference signal terminal to a driving output terminal in response to the signal of the third node, and to provide a signal of the second control signal terminal to the driving output terminal in response to the signal of the second node.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register unit, a gate driving circuit, a driving method and a display device. BACKGROUND

[0002] With the rapid development of display technology, display devices are increasingly developing towards high integration and low cost. Among them, the GOA (Gate Driver on Array) technology integrates the TFT (Thin Film Transistor) driving control circuit on the array substrate of the display device to form the driving of the display device. Among them, the driving control circuit is usually composed of a plurality of cascaded shift register units. However, the unstable output of the shift register unit will cause display abnormalities. SUMMARY

[0003] Embodiments of the present disclosure provide a shift register unit, comprising: an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit;

[0004] The input sub-circuit is coupled with a first node and is configured to provide a signal of an input signal terminal to the first node in response to a signal of a first clock signal terminal;

[0005] The first control sub-circuit is coupled with a second node and is configured to provide a signal of a first reference signal terminal to the second node in response to a signal of a first control signal terminal;

[0006] The second control sub-circuit is coupled with the first node, the second node and a third node, and is configured to control the signal of the second node according to a signal of a second reference signal terminal, and to turn on the first node and the third node in response to a signal of a third reference signal terminal;

[0007] The output sub-circuit is coupled with the second node and the third node, and is configured to provide a signal of the third reference signal terminal to a driving output terminal in response to a signal of the third node, and to provide a signal of a second control signal terminal to the driving output terminal in response to a signal of the second node;

[0008] Among them, the signal of the second reference signal terminal has a first level, the signals of the first reference signal terminal and the third reference signal terminal have a second level respectively, and the voltages of the first reference signal terminal and the third reference signal terminal are different.

[0009] In some possible implementation manners, the first control sub-circuit comprises: a first transistor and a second transistor;

[0010] a gate of the first transistor is coupled with the first control signal terminal, a first electrode of the first transistor is coupled with the first reference signal terminal, a second electrode of the first transistor is coupled with a first electrode of the second transistor, a gate of the second transistor is coupled with the third node or the first node, and a second electrode of the second transistor is coupled with the second node; or

[0011] a gate of the first transistor is coupled with the third node or the first node, a first electrode of the first transistor is coupled with the first reference signal terminal, a second electrode of the first transistor is coupled with a first electrode of the second transistor, a gate of the second transistor is coupled with the first control signal terminal, and a second electrode of the second transistor is coupled with the second node.

[0012] In some possible implementation manners, the first control signal terminal is the same as the input signal terminal or a second clock signal terminal; and / or,

[0013] a material of an active layer of the first transistor and the second transistor comprises a metal oxide semiconductor material.

[0014] In some possible implementation manners, the first control sub-circuit comprises a third transistor.

[0015] a gate of the third transistor is coupled with the first control signal terminal, a first electrode of the third transistor is coupled with the first reference signal terminal, and a second electrode of the third transistor is coupled with the second node.

[0016] In some possible implementation manners, the first control signal terminal comprises the first node or the third node; and / or,

[0017] a material of an active layer of the third transistor comprises a metal oxide semiconductor material.

[0018] In some possible implementation manners, the shift register unit further comprises a third control sub-circuit coupled with the third node and a second clock signal terminal, and configured to control a signal of the third node according to a signal of the second clock signal terminal.

[0019] In some possible implementation manners, the third control sub-circuit comprises a fourth transistor and a first capacitor.

[0020] a gate of the fourth transistor and a first electrode thereof are coupled with the third node, a second electrode of the fourth transistor is coupled with a first electrode plate of the first capacitor, a second electrode plate of the first capacitor is coupled with the second clock signal terminal; or,

[0021] A gate of the fourth transistor is coupled with the first node, a first pole of the fourth transistor is coupled with the second clock signal terminal, a second pole of the fourth transistor is coupled with the first capacitor first electrode plate, and the first capacitor second electrode plate is coupled with the third node.

[0022] In some possible implementation manners, the shift register unit further includes a fourth control sub-circuit coupled with the second reference signal terminal and the first node, and configured to control a signal of the first node according to a signal of the second reference signal terminal.

[0023] In some possible implementation manners, the fourth control sub-circuit includes a second capacitor, a first electrode plate of the second capacitor is coupled with the second reference signal terminal, and a second electrode plate of the second capacitor is coupled with the first node.

[0024] In some possible implementation manners, the second control sub-circuit includes a fifth transistor and a sixth transistor, a gate of the fifth transistor is coupled with the first node or the third node, a first pole of the fifth transistor is coupled with the second reference signal terminal, a second pole of the fifth transistor is coupled with the second node, a gate of the sixth transistor is coupled with the third reference signal terminal, a first pole of the sixth transistor is coupled with the first node, and a second pole of the sixth transistor is coupled with the third node; and / or,

[0025] The output sub-circuit includes a seventh transistor and an eighth transistor, a gate of the seventh transistor is coupled with the second node, a first pole of the seventh transistor is coupled with the second control signal terminal, and a second pole of the seventh transistor is coupled with the driving output terminal; a gate of the eighth transistor is coupled with the third node, a first pole of the eighth transistor is coupled with the third reference signal terminal, and a second pole of the eighth transistor is coupled with the driving output terminal; and / or,

[0026] The input sub-circuit includes a ninth transistor, a gate of the ninth transistor is coupled with the first clock signal terminal, a first pole of the ninth transistor is coupled with the input signal terminal, and a second pole of the ninth transistor is coupled with the first node.

[0027] In some possible implementation manners, the output sub-circuit further includes a third capacitor and / or a fourth capacitor.

[0028] A first electrode plate of the third capacitor is coupled with the second node, and a second electrode plate of the third capacitor is coupled with the second control signal terminal or the driving output terminal.

[0029] A first electrode plate of the fourth capacitor is coupled to the third node, and a second electrode plate of the fourth capacitor is coupled to the driving output terminal.

[0030] The present disclosure also provides a gate drive circuit, comprising: a plurality of the above-described shift register units connected in cascade.

[0031] The input signal terminal of the first-stage shift register unit is coupled to the frame start signal terminal.

[0032] In each of two adjacent shift register units, the input signal terminal of the next-stage shift register unit is coupled to the driving output terminal of the previous-stage shift register unit.

[0033] The present disclosure also provides a display device, comprising: the above-described gate drive circuit.

[0034] The present disclosure also provides a driving method of the above-described shift register unit, comprising:

[0035] In a first stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit controls the signal of the second node according to the second reference signal terminal, and turns on the first node and the third node in response to the signal of the third reference signal terminal; and the output sub-circuit provides the signal of the third reference signal terminal to the driving output terminal in response to the signal of the third node.

[0036] In a second stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit turns on the first node and the third node in response to the signal of the third reference signal terminal; the first control sub-circuit provides the signal of the first reference signal terminal to the second node in response to the signal of the first control signal terminal; and the output sub-circuit provides the signal of the second control signal terminal to the driving output terminal in response to the signal of the second node.

[0037] In a third stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit controls the signal of the second node according to the second reference signal terminal, and turns on the first node and the third node in response to the signal of the third reference signal terminal; and the output sub-circuit provides the signal of the third reference signal terminal to the driving output terminal in response to the signal of the third node. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 FIG. 1 is a structural schematic diagram of a display device in the present disclosure;

[0039] Figure 2 Structure schematic diagram of the gate driving circuit in the embodiment of the present disclosure;

[0040] Figure 3 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0041] Figure 4 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0042] Figure 5 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0043] Figure 6 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0044] Figure 7 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0045] Figure 8 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0046] Figure 9 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0047] Figure 10 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0048] Figure 11 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0049] Figure 12 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0050] Figure 13 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0051] Figure 14 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0052] Figure 15 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0053] Figure 16 Structure schematic diagram of the shift register unit in the embodiment of the present disclosure;

[0054] Figure 17These are further schematic diagrams illustrating specific structures of the shift register unit in the embodiments of this disclosure;

[0055] Figure 18 Here are some flowcharts of the driving method in the embodiments of this disclosure;

[0056] Figure 19 These are further schematic diagrams of the gate drive circuit in the embodiments of this disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0059] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0060] In some embodiments, such as Figure 1 As shown, the display device may include a display panel 100 and a driving circuit 200. The driving circuit 200 is electrically connected to the display panel 100 and can drive the display panel to operate. Exemplarily, the driving circuit 200 may take the form of an embodiment combining software and hardware aspects. For example, the driving circuit 200 may include an integrated circuit (IC).

[0061] Exemplarily, the display panel 100 can include a display area and a non-display area surrounding the display area, and the display area includes a plurality of pixel units arranged in an array. Optionally, each pixel unit includes a plurality of sub-pixels of different colors. For example, the pixel unit can include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that color display can be realized by mixing red, green and blue. Alternatively, the pixel unit can include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that color display can be realized by mixing red, green, blue and white. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0062] The display area further includes a plurality of gate lines and a plurality of data lines, wherein one row of sub-pixels can be connected to one gate line, and one column of sub-pixels can be connected to one data line. Of course, other connection modes can also be used, which will not be described herein.

[0063] Organic light emitting diode (OLED), quantum dot light emitting diode (QLED), micro light emitting diode (Micro LED) and mini light emitting diode (Mini LED) and other light emitting devices have the advantages of self-luminous and low energy consumption. In the embodiments of the present disclosure, each sub-pixel can include a light emitting device and a pixel circuit connected to the light emitting device. The pixel circuit can drive the connected light emitting device to emit light. Exemplarily, the light emitting device can include at least one of OLED, QLED, Micro LED and Mini LED.

[0064] Generally, the pixel circuit can include transistors and capacitors, and through cooperation of the transistors and the capacitors, the connected light emitting device is driven to emit light. Generally, the transistors with the active layer of the low temperature poly-silicon (LTPS) material have high mobility and can be made thinner and smaller, have lower power consumption, etc. In the implementation, the material of the active layer of some transistors in the pixel circuit can be set to the LTPS material. In this way, the transistors can be set to the LTPS transistors, so that the pixel circuit has high mobility and can be made thinner and smaller, has lower power consumption, etc. Generally, the transistors with the active layer of the metal oxide semiconductor material have small drain current. Therefore, in order to reduce the drain current, the material of the active layer of some transistors in the pixel circuit can also be set to the metal oxide semiconductor material, for example, the indium gallium zinc oxide (IGZO), and of course, other metal oxide semiconductor materials are also possible, which are not limited herein. In this way, the transistors can be set to the oxide transistors, so that the pixel circuit has small drain current.

[0065] By setting some transistors to the LTPS transistors and some transistors to the oxide transistors, the pixel circuit in the embodiments of the present disclosure can be set to the LTPO pixel circuit. In this way, by combining the processes of preparing the LTPS transistors and the oxide transistors to prepare the LTPO pixel circuit of the low temperature poly-silicon oxide, the drain current of the gate of the driving transistor can be small, and the power consumption can be low.

[0066] Exemplarily, as shown in FIG. 1, the display panel 100 includes a plurality of pixel circuits 20 arranged in an array, and each pixel circuit 20 is connected to a corresponding light emitting device 30. The pixel circuit 20 can be connected to the light emitting device 30 through a driving transistor T1, and the driving transistor T1 can be controlled to be turned on or turned off through a driving signal on a gate line GS connected to the driving transistor T1. Figure 2 As shown in FIG. 1, the non-display area of the display panel 100 also includes a gate driving circuit 10, the gate driving circuit 10 includes a plurality of cascaded shift register units 21, one shift register unit 21 is arranged corresponding to one gate line GS, and the driving output end of the shift register unit 21 is coupled with the corresponding gate line GS to input the driving signal to the connected gate line GS. In addition, the gate line GS is connected with the transistor in the pixel circuit, and the conduction and the cut-off of the transistor can be controlled through the driving signal on the gate line GS.

[0067] The embodiments of the present disclosure provide a shift register unit, by setting the voltages of the first reference signal end and the third reference signal end to be different, the risk of drain current of the related transistors in the shift register unit can be reduced, the output stability can be improved, and the display abnormality can be reduced.

[0068] As shown in FIG. 1, the non-display area of the display panel 100 also includes a gate driving circuit 10, the gate driving circuit 10 includes a plurality of cascaded shift register units 21, one shift register unit 21 is arranged corresponding to one gate line GS, and the driving output end of the shift register unit 21 is coupled with the corresponding gate line GS to input the driving signal to the connected gate line GS. In addition, the gate line GS is connected with the transistor in the pixel circuit, and the conduction and the cut-off of the transistor can be controlled through the driving signal on the gate line GS. Figure 3As shown, the shift register unit provided in this embodiment may include: an input sub-circuit 211, a first control sub-circuit 212, a second control sub-circuit 213, and an output sub-circuit 214. The input sub-circuit 211 is coupled to a first node N1, the first control sub-circuit 212 is coupled to a second node N2, the second control sub-circuit 213 is coupled to the first node N1, the second node N2, and a third node N3, and the output sub-circuit 214 is coupled to the second node N2 and the third node N3. Furthermore, the input sub-circuit 211 is configured to provide the input signal terminal INP to the first node N1 in response to the signal of the first clock signal terminal CK1. The first control sub-circuit 212 is configured to provide the signal of the first reference signal terminal VREF1 to the second node N2 in response to the signal of the first control signal terminal CS1. The second control sub-circuit 213 is configured to control the signal of the second node N2 according to the second reference signal terminal VREF2, and to turn on the first node N1 and the third node N3 in response to the signal of the third reference signal terminal VREF3. The output sub-circuit 214 is configured to provide the signal of the third reference signal terminal VREF3 to the drive output terminal OUTP in response to the signal of the third node N3, and to provide the signal of the second control signal terminal CS2 to the drive output terminal OUTP in response to the signal of the second node N2.

[0069] Furthermore, the signal level of the second reference signal terminal VREF2 is the first level, while the signal levels of the first reference signal terminal VREF1 and the third reference signal terminal VREF3 are the second levels, and the voltages of the first reference signal terminal VREF1 and the third reference signal terminal VREF3 are different. This configuration reduces the risk of leakage current in the relevant transistors of the shift register unit, improves output stability, and reduces display abnormalities.

[0070] In some examples, such as Figure 3 As shown, the first control sub-circuit 212 can also be coupled to the third node N3. With this configuration, the first control sub-circuit 212 can be configured to provide the signal of the first reference signal terminal VREF1 to the second node N2 in response to the signals of the first control signal terminal CS1 and the third node N3.

[0071] For example, such as Figure 4 As shown, the first control sub-circuit 212 includes: a first transistor M1 and a second transistor M2; wherein, the gate of the first transistor M1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor M1 is coupled to the first reference signal terminal VREF1, the second electrode of the first transistor M1 is coupled to the first electrode of the second transistor M2, the gate of the second transistor M2 is coupled to the third node N3, and the second electrode of the second transistor M2 is coupled to the second node N2.

[0072] Exemplarily, the first transistor M1 is turned on under the control of the active level of the first control signal at the first control signal end CS1, and is turned off under the control of the inactive level of the first control signal. Optionally, the first transistor M1 can be an N-type transistor, and the active level of the first control signal is high level and the inactive level is low level. The first transistor M1 can be a P-type transistor, and the active level of the first control signal is low level and the inactive level is high level.

[0073] Exemplarily, the second transistor M2 is turned on under the control of the active level of the signal at the third node N3, and is turned off under the control of the inactive level of the signal at the third node N3. Optionally, the second transistor M2 can be an N-type transistor, and the active level of the signal at the third node N3 is high level and the inactive level is low level. The second transistor M2 can be a P-type transistor, and the active level of the signal at the third node N3 is low level and the inactive level is high level.

[0074] Generally, the leakage current of the transistor with metal oxide semiconductor material as the active layer is small, and therefore, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of the first transistor M1 and the second transistor M2 can include metal oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide), and of course, other metal oxide semiconductor materials can also be used, which are not limited herein. In this way, the first transistor M1 and the second transistor M2 can be set as oxide transistors (Oxide Thin Film Transistor), so as to reduce the leakage current of the first transistor M1 and the second transistor M2, improve the voltage stability of the second node N2, and thus improve the output stability of the driving output end OUTP.

[0075] Exemplarily, when the first transistor M1 and the second transistor M2 are N-type transistors, the second level of the first reference signal end VREF1 and the third reference signal end VREF3 can be low level, and the first level of the second reference signal end VREF2 can be high level. And, the voltage of the signal at the first reference signal end VREF1 can be higher than the voltage of the signal at the third reference signal end VREF3, so as to be set that when it is needed to control the first transistor M1 to be turned off, the gate-source voltage Vgs of the first transistor M1 is lower than the threshold voltage Vth of the first transistor M1, and when it is needed to control the first transistor M1 to be turned on, the gate-source voltage Vgs of the first transistor M1 is higher than the threshold voltage Vth of the first transistor M1. M1 and the threshold voltage Vth M1 satisfy the relationship Vgs M1 -Vth M1<0V, so that the first transistor M1 is completely turned off. At the same time, when it is required to control the second transistor M2 to be turned off, since the gate of the second transistor M2 is coupled with the third node N3, the third node N3 will be pulled to a voltage lower than that of the third reference signal terminal VREF3 when bootstrapping, so the second transistor M2 can also be completely turned off. In combination with the first transistor M1 and the second transistor M2, the risk of leakage can be reduced, and the signal stability of the second node N2 can be improved.

[0076] As shown in Figure 4 exemplarily, the input sub-circuit 211 comprises a ninth transistor M9, wherein the gate of the ninth transistor M9 is coupled with the first clock signal terminal CK1, the first pole of the ninth transistor M9 is coupled with the input signal terminal INP, and the second pole of the ninth transistor M9 is coupled with the first node N1.

[0077] As shown in exemplarily, the ninth transistor M9 is turned on under the control of the active level of the first clock signal of the first clock signal terminal CK1, and is turned off under the control of the inactive level of the first clock signal. Optionally, the ninth transistor M9 can be an N-type transistor, and in this case, the active level of the first clock signal is high and the inactive level is low. Alternatively, the ninth transistor M9 can be a P-type transistor, and in this case, the active level of the first clock signal is low and the inactive level is high.

[0078] In some embodiments of the present disclosure, the material of the active layer of the ninth transistor M9 can be set as an LTPS material. In this way, the ninth transistor M9 can be set as an LTPS transistor, so that the shift register unit can be made thinner, smaller, and consume less power, etc.

[0079] Figure 4 As shown in exemplarily, the second control sub-circuit 213 comprises a fifth transistor M5 and a sixth transistor M6, the gate of the fifth transistor M5 is coupled with the third node N3, the first pole of the fifth transistor M5 is coupled with the second reference signal terminal VREF2, the second pole of the fifth transistor M5 is coupled with the second node N2, the gate of the sixth transistor M6 is coupled with the third reference signal terminal VREF3, the first pole of the sixth transistor M6 is coupled with the first node N1, and the second pole of the sixth transistor M6 is coupled with the third node N3.

[0080] As shown in

[0081] For example, the sixth transistor M6 is turned on under the control of the signal at the third reference signal terminal VREF3. Optionally, the sixth transistor M6 can be an N-type transistor, in which case the signal level at the third reference signal terminal VREF3 is high. The sixth transistor M6 can be a P-type transistor, in which case the signal level at the third reference signal terminal VREF3 is low.

[0082] In some embodiments of this disclosure, the active layers of the fifth transistor M5 and the sixth transistor M6 can be made of LTPS material. This allows the ninth transistor M9 to be configured as an LTPS transistor, enabling the shift register cell to achieve high mobility and to be made thinner, smaller, and with lower power consumption.

[0083] For example, such as Figure 4 As shown, the output sub-circuit 214 includes: a seventh transistor M7 and an eighth transistor M8; the gate of the seventh transistor M7 is coupled to the second node N2, the first terminal of the seventh transistor M7 is coupled to the second control signal terminal CS2, and the second terminal of the seventh transistor M7 is coupled to the drive output terminal OUTP; the gate of the eighth transistor M8 is coupled to the third node N3, the first terminal of the eighth transistor M8 is coupled to the third reference signal terminal VREF3, and the second terminal of the eighth transistor M8 is coupled to the drive output terminal OUTP.

[0084] For example, the second control signal terminal CS2 and the second reference signal terminal VREF2 can be the same signal terminal. For example, as Figure 4 As shown, the first terminal of the seventh transistor is connected to the second reference signal terminal VREF2.

[0085] For example, the seventh transistor M7 is turned on under the control of the effective level of the signal at the second node N2, and turned off under the control of the ineffective level of the signal at the second node N2. Optionally, the seventh transistor M7 can be an N-type transistor, in which case the effective level of the signal at the second node N2 is high and the ineffective level is low. The seventh transistor M7 can be a P-type transistor, in which case the effective level of the signal at the second node N2 is low and the ineffective level is high.

[0086] For example, the eighth transistor M8 is turned on under the control of the effective level of the signal at the third node N3, and turned off under the control of the ineffective level of the signal at the third node N3. Optionally, the eighth transistor M8 can be an N-type transistor, in which case the effective level of the signal at the third node N3 is high and the ineffective level is low. The eighth transistor M8 can be a P-type transistor, in which case the effective level of the signal at the third node N3 is low and the ineffective level is high.

[0087] In some embodiments of the present disclosure, the material of the active layer of the seventh transistor M7 and the eighth transistor M8 can be set as an LTPS material. In this way, the ninth transistor M9 can be set as an LTPS transistor, so that the shift register unit can be made thinner, smaller, and lower in power consumption, and the like.

[0088] As shown in FIG. 6, the output sub-circuit 214 further includes a third capacitor C3, a first electrode plate of the third capacitor C3 being coupled to the second node N2, and a second electrode plate of the third capacitor C3 being coupled to the second control signal terminal CS2. Alternatively, the second electrode plate of the third capacitor C3 can also be coupled to the driving output terminal OUTP, which is not limited herein. Figure 4 As shown in FIG. 6, the output sub-circuit 214 further includes a third capacitor C3, a first electrode plate of the third capacitor C3 being coupled to the second node N2, and a second electrode plate of the third capacitor C3 being coupled to the second control signal terminal CS2. Alternatively, the second electrode plate of the third capacitor C3 can also be coupled to the driving output terminal OUTP, which is not limited herein.

[0089] As shown in FIG. 6, the output sub-circuit 214 further includes a third capacitor C3, a first electrode plate of the third capacitor C3 being coupled to the second node N2, and a second electrode plate of the third capacitor C3 being coupled to the second control signal terminal CS2. Alternatively, the second electrode plate of the third capacitor C3 can also be coupled to the driving output terminal OUTP, which is not limited herein. Figure 4 As shown in FIG. 6, the output sub-circuit 214 further includes a third capacitor C3, a first electrode plate of the third capacitor C3 being coupled to the second node N2, and a second electrode plate of the third capacitor C3 being coupled to the second control signal terminal CS2. Alternatively, the second electrode plate of the third capacitor C3 can also be coupled to the driving output terminal OUTP, which is not limited herein.

[0090] In a specific implementation, according to the flow direction of the signal, the first pole of the above-mentioned transistor can be used as its source pole, and the second pole can be used as its drain pole; or the first pole can be used as its drain pole, and the second pole can be used as its source pole, which is not specifically distinguished herein.

[0091] In some embodiments of the present disclosure, the shift register unit can be set as an LTPO shift register unit by setting part of the transistors as LTPS transistors and part of the transistors as oxide transistors. In this way, the shift register unit can be prepared by combining the two processes of preparing LTPS transistors and oxide transistors, so that the prepared shift register unit can achieve a simple structure and a narrow frame scheme.

[0092] The above is only an example of the specific structure of the shift register unit provided by the embodiments of the present disclosure, and the specific structure of each sub-circuit is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which is not limited herein.

[0093] In some examples, as shown in FIG. 6, the first control signal of the first control signal terminal CS1 can be the same as the signal of the input signal terminal INP. Figure 5

[0094] The following will take the shift register unit shown in FIG. 6 as an example, and describe the working process of the above-mentioned shift register unit provided by the embodiments of the present disclosure in combination with the signal timing diagram shown in FIG. 7. Specifically, as shown in FIG. 7, the input signal terminal INP is set as a clock signal terminal, and the output signal terminal OUTP is set as a data signal terminal. Figure 4 Figure 5 The following will take the shift register unit shown in FIG. 6 as an example, and describe the working process of the above-mentioned shift register unit provided by the embodiments of the present disclosure in combination with the signal timing diagram shown in FIG. 7. Specifically, as shown in FIG. 7, the input signal terminal INP is set as a clock signal terminal, and the output signal terminal OUTP is set as a data signal terminal. Figure 5 ​​The first stage T1, the second stage T2, and the third stage T3 in the shown signal timing diagram. And, inp represents the input signal of the input signal terminal INP, ck1 represents the first clock signal of the first clock signal terminal CK1, outp represents the signal of the driving output terminal OUTP, and cs1 represents the first control signal of the first control signal terminal CS1. It should be noted that, Figure 5 The shown signal timing diagram is only the working process of one shift register unit in one frame time. The working processes of the shift register unit in other frames are basically the same as that in the frame, and are not described here.

[0095] In the first stage T1, first, the first clock signal cs1 is low, the ninth transistor M9 is turned on, and the low level of the input signal inp is input to the first node N1, so that the signal of the first node N1 is low. Since the sixth transistor M6 is turned on under the control of the third reference signal terminal VREF3, the low level of the first node N1 can be transmitted to the third node N3, so that the third node N3 is low, and the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal terminal VREF3 to the driving output terminal OUTP, so that the driving signal outp output by the driving output terminal OUTP is a low level signal. And, the first control signal is low, the first transistor M1 is cut off, and the second transistor M2 is cut off under the control of the low level of the third node N3, and the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is high, and the seventh transistor M7 is cut off.

[0096] Then, the first clock signal cs1 is high, the ninth transistor M9 is cut off, and the first node N1 is in a floating state, but due to the action of the fourth capacitor C4, the signal of the third node N3 can be kept low, and the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal terminal VREF3 to the driving output terminal OUTP, so that the driving signal outp output by the driving output terminal OUTP is a low level signal. And, the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal terminal VREF2 to the second node N2, so that the signal of the second node N2 is high, and the seventh transistor M7 is cut off.

[0097] In the second stage T2, first, the first clock signal cs1 is low, the ninth transistor M9 is turned on, and the high level of the input signal inp is input to the first node N1, so that the signal of the first node N1 is high. Since the sixth transistor M6 is turned on under the control of the third reference signal end VREF3, the high level of the first node N1 can be transmitted to the third node N3, so that the third node N3 is high, and the eighth transistor M8 and the fifth transistor M5 are both cut off. The first control signal cs1 is high, the first transistor M1 is turned on, and the second transistor M2 is turned on under the control of the high level of the third node N3, so as to provide the low level signal of the first reference signal end VREF1 to the second node N2, so that the signal of the second node N2 is low, and the seventh transistor M7 is turned on, so as to provide the high level signal of the second reference signal end VREF2 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a high level signal.

[0098] Then, the first clock signal cs1 is high, the ninth transistor M9 is cut off, and the first node N1 is in a floating state, but due to the action of the fourth capacitor C4, the signal of the third node N3 can be kept high, and the eighth transistor M8 and the fifth transistor M5 are both cut off. The first control signal cs1 is low, the first transistor M1 is cut off, and the second node N2 is in a floating state, but due to the action of the third capacitor C3, the signal of the second node N2 can be kept low, and the seventh transistor M7 is turned on, so as to provide the high level signal of the second reference signal end VREF2 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a high level signal.

[0099] In the third stage T3, first, the first clock signal cs1 is low, the ninth transistor M9 is turned on, and the low level of the input signal inp is input to the first node N1, so that the signal of the first node N1 is low. Since the sixth transistor M6 is turned on under the control of the third reference signal end VREF3, the low level of the first node N1 can be transmitted to the third node N3, so that the third node N3 is low, and the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal end VREF3 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a low level signal. And the first control signal is low, the first transistor M1 is cut off, and the second transistor M2 is cut off under the control of the low level of the third node N3, and the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal end VREF2 to the second node N2, so that the signal of the second node N2 is high, and the seventh transistor M7 is cut off.

[0100] Afterwards, the first clock signal cs1 is high, the ninth transistor M9 is off, the first node N1 is floating, but the signal of the third node N3 can be kept low due to the fourth capacitor C4, so the eighth transistor M8 is on, thereby providing the low signal of the third reference signal end VREF3 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a low signal. And the fifth transistor M5 is on under the control of the low signal of the third node N3, to provide the high signal of the second reference signal end VREF2 to the second node N2, so that the signal of the second node N2 is high, and the seventh transistor M7 is off.

[0101] After the third stage T3, the process of the third stage T3 is repeated until the next frame starts.

[0102] It should be noted that in the third stage T3 and the subsequent stages, since the first transistor M1 and the second transistor M2 are both off, the leakage current of the second node N2 can be reduced, and the signal stability of the second node N2 can be improved, thereby the output stability of the seventh transistor M7 can be improved, and the output stability of the driving output end OUTP can be improved.

[0103] And by setting the voltage of the signal of the first reference signal end VREF1 to be higher than the voltage of the signal of the third reference signal end VREF3, in the third stage T3 and the subsequent stages, the gate-source voltage Vgs of the first transistor M1 M1 and the threshold voltage Vth M1 satisfies the relationship Vgs M1 -Vth M1 <0V, so that the first transistor M1 is completely turned off. At the same time, since the gate of the second transistor M2 is coupled to the third node N3, the third node N3 will be pulled to a voltage lower than the signal of the third reference signal end VREF3 when self-boosting, so the second transistor M2 can also be completely turned off. Further combining the first transistor M1 and the second transistor M2, the risk of leakage current can be reduced, and the signal stability of the second node N2 can be improved.

[0104] The embodiments of the present disclosure provide some signal timing diagrams of shift register units, as shown in Figure 6 , which are modified for the implementation in the above-mentioned embodiments. Only the differences between the present embodiments and the above-mentioned embodiments will be described below, and the same parts will not be described here.

[0105] In the embodiments of the present disclosure, as shown in Figure 6 , the first control signal end CS1 and the input signal end INP can be set as the same signal end. For example, the gate of the first transistor M1 is coupled to the input signal end INP.

[0106] And, Figure 6 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein. Figure 5 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein. Figure 4 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein.

[0107] The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein. Figure 7 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein.

[0108] In the embodiment of the present disclosure, as shown in FIG. 8, the gate of the first transistor M1 can be coupled with the third node N3, the first electrode of the first transistor M1 can be coupled with the first reference signal end VREF1, the second electrode of the first transistor M1 can be coupled with the first electrode of the second transistor M2, the gate of the second transistor M2 can be coupled with the first control signal end CS1, and the second electrode of the second transistor M2 can be coupled with the second node N2. Figure 7 Further, as shown in FIG. 9, the first control signal end CS1 and the input signal end INP can be set as the same signal end. For example, the gate of the first transistor M1 is coupled with the input signal end INP.

[0109] Figure 7 Further, as shown in FIG. 9, the first control signal end CS1 and the input signal end INP can be set as the same signal end. For example, the gate of the first transistor M1 is coupled with the input signal end INP.

[0110] And, Figure 7 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein. Figure 5 And, Figure 7 The second transistor M2 in FIG. 10 can have a working process basically the same as that of the first transistor M1 in FIG. 9, Figure 4 The first transistor M1 in FIG. 10 can have a working process basically the same as that of the second transistor M2 in FIG. 9, and Figure 7 The first transistor M1 in FIG. 10 can have a working process basically the same as that of the second transistor M2 in FIG. 9, and Figure 4 The first transistor M1 in FIG. 10 can have a working process basically the same as that of the second transistor M2 in FIG. 9, and Figure 4 The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein.

[0111] The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein. Figure 8 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 7. The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described herein.

[0112] In the embodiment of the present disclosure, as shown in FIG. 8, the gate of the first transistor M1 can be coupled with the third node N3, the first electrode of the first transistor M1 can be coupled with the first reference signal end VREF1, the second electrode of the first transistor M1 can be coupled with the first electrode of the second transistor M2, the gate of the second transistor M2 can be coupled with the first control signal end CS1, and the second electrode of the second transistor M2 can be coupled with the second node N2. Figure 8 ​As shown, the first control sub-circuit 212 can also be coupled with the first node N1, so that the first control sub-circuit 212 can be configured to provide the signal of the first reference signal terminal VREF1 to the second node N2 in response to the signals of the first control signal terminal CS1 and the first node N1.

[0113] As shown, the first control sub-circuit 212 can also be coupled with the first node N1, so that the first control sub-circuit 212 can be configured to provide the signal of the first reference signal terminal VREF1 to the second node N2 in response to the signals of the first control signal terminal CS1 and the first node N1. Figure 8 As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2.

[0114] As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2.

[0115] As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2. Figure 8 As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2.

[0116] As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2. Figure 8 As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2. Figure 5 As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2. Figure 4 As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2.

[0117] As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2. Figure 9 As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2.

[0118] As shown, the gate of the first transistor M1 can be coupled with the first control signal terminal CS1, the first pole of the first transistor M1 can be coupled with the first reference signal terminal VREF1, the second pole of the first transistor M1 can be coupled with the first pole of the second transistor M2, the gate of the second transistor M2 can be coupled with the first node N1, and the second pole of the second transistor M2 can be coupled with the second node N2. Figure 9As shown, the first control signal terminal CS1 and the input signal terminal INP can be set to the same signal terminal. For example, the gate of the first transistor M1 is coupled to the input signal terminal INP.

[0119] and, Figure 9 The signal timing diagram corresponding to the shift register unit shown is as follows: Figure 5 As shown. Its specific working process in the first stage T1, the second stage T2, and the third stage T3 can be compared with... Figure 8 The operation of the shift register units shown is basically the same, and will not be described in detail here.

[0120] This disclosure provides further signal timing diagrams for some shift register units, such as... Figure 10 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; the similarities will not be repeated here.

[0121] In the embodiments disclosed herein, such as Figure 10 As shown, the gate of the first transistor M1 can also be coupled to the first node N1, the first terminal of the first transistor M1 can be coupled to the first reference signal terminal VREF1, the second terminal of the first transistor M1 can be coupled to the first terminal of the second transistor M2, the gate of the second transistor M2 can be coupled to the first control signal terminal CS1, and the second terminal of the second transistor M2 can be coupled to the second node N2.

[0122] Furthermore, such as Figure 10 As shown, the first control signal terminal CS1 and the input signal terminal INP can be set to the same signal terminal. For example, the gate of the first transistor M1 is coupled to the input signal terminal INP.

[0123] and, Figure 10 The signal timing diagram corresponding to the shift register unit shown is as follows: Figure 5 As shown. And, Figure 10 The second transistor M2 in the middle can be with Figure 8 The operation of the first transistor M1 in the process is basically the same. Figure 10 The first transistor M1 in the middle can be with Figure 8 The operation of the second transistor M2 is basically the same, and the remaining specific operation processes in the first stage T1, the second stage T2, and the third stage T3 can be compared with those in the second stage T2. Figure 8 The operation of the shift register units shown is basically the same, and will not be described in detail here.

[0124] This disclosure provides further signal timing diagrams for some shift register units, such as... Figure 11As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; the similarities will not be repeated here.

[0125] In the embodiments disclosed herein, such as Figure 11 As shown, the first control signal terminal CS1 and the second clock signal terminal CK2 can also be the same signal terminal, and the second control signal terminal CS2 and the second clock signal terminal CK2 can also be the same signal terminal. For example, the gate of the second transistor M2 is coupled to the second clock signal terminal CK2. Furthermore, the gates of the first transistor M1 and the fifth transistor M5 are coupled to the third node N3. Alternatively, the gate of the first transistor M1 can be coupled to the second clock signal terminal CK2, and the gates of the second transistor M2 and the fifth transistor M5 can be coupled to the third node N3. Alternatively, the gate of the second transistor M2 can be coupled to the second clock signal terminal CK2, the gate of the first transistor M1 can be coupled to the third node N3, and the gate of the fifth transistor M5 can be coupled to the first node N1.

[0126] The following is based on Figure 11 Taking the shift register unit shown as an example, combined with Figure 12 The signal timing diagram shown illustrates the operation of the shift register unit provided in the embodiments of this disclosure. Specifically, as shown in the diagram... Figure 12 The signal timing diagram shown represents stages T1, T2, and T3. Furthermore, inp represents the input signal at input signal terminal INP, ck1 represents the first clock signal at first clock signal terminal CK1, ck2 represents the second clock signal at second clock signal terminal CK2, outp represents the signal at drive output terminal OUTP, and cs1 represents the first control signal at first control signal terminal CS1. It should be noted that... Figure 12 The signal timing diagram shown only represents the operation of a single shift register unit within one frame. The operation of this shift register unit in other frames is basically the same as that in this frame, and will not be described in detail here.

[0127] In the first stage T1, first, the first clock signal cs1 is low, the ninth transistor M9 is turned on, and the low level of the input signal inp is input to the first node N1, so that the signal of the first node N1 is low. Since the sixth transistor M6 is turned on under the control of the third reference signal end VREF3, the low level of the first node N1 can be transmitted to the third node N3, so that the third node N3 is low, and then the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal end VREF3 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a low level signal. And the first control signal cs1 is high, the second transistor M2 is turned on, and the first transistor M1 is turned off under the control of the low level of the third node N3, and the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal end VREF2 to the second node N2, so that the signal of the second node N2 is high, and then the seventh transistor M7 is turned off.

[0128] Then, the first clock signal cs1 is high, the ninth transistor M9 is turned off, and the first node N1 is in a floating state, but due to the action of the fourth capacitor C4, the signal of the third node N3 can be kept low, so that the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal end VREF3 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a low level signal. And the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal end VREF2 to the second node N2, so that the signal of the second node N2 is high, and then the seventh transistor M7 is turned off.

[0129] In the second stage T2, first, the first clock signal cs1 is low, the ninth transistor M9 is turned on, and the high level of the input signal inp is input to the first node N1, so that the signal of the first node N1 is high. Since the sixth transistor M6 is turned on under the control of the third reference signal end VREF3, the high level of the first node N1 can be transmitted to the third node N3, so that the third node N3 is high, and then the eighth transistor M8 and the fifth transistor M5 are both turned off. The first control signal cs1 is high, the second transistor M2 is turned on, and the first transistor M1 is turned on under the control of the high level of the third node N3, so as to provide the low level signal of the first reference signal end VREF1 to the second node N2, so that the signal of the second node N2 is low, and then the seventh transistor M7 is turned on, so as to provide the high level signal of the second reference signal end VREF2 to the driving output end OUTP, so that the driving signal outp output by the driving output end OUTP is a high level signal.

[0130] Afterwards, the first clock signal cs1 is high level, the ninth transistor M9 is cut off, the first node N1 is in floating state, but due to the action of the fourth capacitor C4, the signal of the third node N3 and the first node N1 can be kept as high level, then the eighth transistor M8 and the fifth transistor M5 are all cut off. The first control signal is low level, the second transistor M2 is cut off, the second node N2 is in floating state, but due to the action of the third capacitor C3, the signal of the second node N2 can be kept as low level, then the seventh transistor M7 is turned on, so as to provide the high level signal of the second reference signal end VREF2 to the driving output end OUTP, and make the driving signal outp output by the driving output end OUTP as high level signal.

[0131] In the third stage T3, firstly, the first clock signal cs1 is low level, the ninth transistor M9 is turned on, and the low level input signal inp is input to the first node N1, so that the signal of the first node N1 is low level. Since the sixth transistor M6 is turned on under the control of the third reference signal end VREF3, the low level of the first node N1 can be transmitted to the third node N3, so that the third node N3 is low level, and then the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal end VREF3 to the driving output end OUTP, and make the driving signal outp output by the driving output end OUTP as low level signal. And the first control signal is high level, the second transistor M2 is turned on, and the first transistor M1 is cut off under the control of the low level of the third node N3, and the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal end VREF2 to the second node N2, so that the signal of the second node N2 is high level, and then the seventh transistor M7 is cut off.

[0132] Afterwards, the first clock signal cs1 is high level, the ninth transistor M9 is cut off, the first node N1 is in floating state, but due to the action of the fourth capacitor C4, the signal of the third node N3 can be kept as low level, then the eighth transistor M8 is turned on, so as to provide the low level signal of the third reference signal end VREF3 to the driving output end OUTP, and make the driving signal outp output by the driving output end OUTP as low level signal. And the fifth transistor M5 is turned on under the control of the low level of the third node N3, so as to provide the high level signal of the second reference signal end VREF2 to the second node N2, so that the signal of the second node N2 is high level, and then the seventh transistor M7 is cut off.

[0133] After the third stage T3, the process of the third stage T3 is repeated until the next frame starts.

[0134] It should be noted that by making the voltage of the signal of the first reference signal end VREF1 higher than the voltage of the signal of the third reference signal end VREF3, it is thus set that in the third stage T3 and the stages thereafter, the gate-source voltage Vgs of the first transistor M1 can be made to be M1 and the threshold voltage Vth M1 satisfies the relationship Vgs M1 -Vth M1 <0V, so that the first transistor M1 is completely turned off. At the same time, since the gate of the second transistor M2 is coupled with the third node N3, the third node N3 will be pulled to be lower than the voltage of the signal of the third reference signal end VREF3 when self-boosting, so that the second transistor M2 can also be completely turned off. Further in combination with the first transistor M1 and the second transistor M2, the risk of leakage can be reduced, and the signal stability of the second node N2 is improved.

[0135] The embodiments of the present disclosure provide some signal timing diagrams of shift register units, as shown in Figure 12 , which are deformed for the implementation in the above embodiments. Only the differences between the present embodiments and the above embodiments will be described below, and the same parts will not be described herein.

[0136] In the embodiments of the present disclosure, as shown in Figure 12 , the first control signal end CS1 and the second clock signal end CK2 can also be the same signal end. For example, the gate of the second transistor M2 is coupled with the second clock signal end CK2. And the gate of the first transistor M1 and the gate of the fifth transistor M5 are coupled with the first node N1. Alternatively, the gate of the first transistor M1 can be coupled with the second clock signal end CK2, and the gate of the second transistor M2 and the gate of the fifth transistor M5 are coupled with the first node N1.

[0137] And, Figure 13 , the signal timing diagram corresponding to the shift register unit is as shown in Figure 12 . The specific working process of the shift register unit in the first stage T1, the second stage T2, and the third stage T3 can be basically the same as that of the shift register unit shown in Figure 11 , and will not be described herein.

[0138] The embodiments of the present disclosure provide some signal timing diagrams of shift register units, as shown in Figure 14 and Figure 15 , which are deformed for the implementation in the above embodiments. Only the differences between the present embodiments and the above embodiments will be described below, and the same parts will not be described herein.

[0139] In the embodiments of the present disclosure, as shown in Figure 14 and Figure 15As shown, the shift register unit also includes a third control sub-circuit 215, which is coupled to the third node N3 and the second clock signal terminal CK2, and is configured to control the signal of the third node N3 according to the signal of the second clock signal terminal CK2.

[0140] For example, such as Figure 14 and Figure 15 As shown, the third control sub-circuit 215 includes: a fourth transistor M4 and a first capacitor C1; the gate and first electrode of the fourth transistor M4 are coupled to the third node N3, the second electrode of the fourth transistor M4 is coupled to the first electrode plate of the first capacitor C1, and the second electrode plate of the first capacitor C1 is coupled to the second clock signal terminal CK2. When the fourth transistor M4 is turned on under the control of the third node N3, the first electrode plate of the first capacitor C1 can be turned on to the third node N3. Furthermore, the active layer of the fourth transistor M4 can be made of LTPS material, thus configuring the fourth transistor M4 as an LTPS type transistor.

[0141] Alternatively, the gate of the fourth transistor M4 is coupled to the first node N1, the first electrode of the fourth transistor M4 is coupled to the second clock signal terminal CK2, the second electrode of the fourth transistor M4 is coupled to the first electrode plate of the first capacitor C1, and the second electrode plate of the first capacitor C1 is coupled to the third node N3.

[0142] Alternatively, the gate of the first transistor M1 can be coupled to the third node N3, and the gate of the fifth transistor M5 can be coupled to the first node N1.

[0143] Alternatively, the gate of the fourth transistor M4 can be coupled to the first node N1.

[0144] and, Figure 14 and Figure 15 The signal timing diagram corresponding to the shift register unit shown is as follows: Figure 12 As shown. Its specific working process in the first stage T1, the second stage T2, and the third stage T3 can be compared with... Figure 11 The operation of the shift register units shown is basically the same, and will not be described in detail here.

[0145] This disclosure provides further signal timing diagrams for some shift register units, such as... Figure 16 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; the similarities will not be repeated here.

[0146] In the embodiments disclosed herein, such as Figure 16As shown, the first control sub-circuit 212 includes: a third transistor M3; the gate of the third transistor M3 is coupled to the first control signal terminal CS1, the first terminal of the third transistor M3 is coupled to the first reference signal terminal VREF1, and the second terminal of the third transistor M3 is coupled to the second node N2.

[0147] For example, the third transistor M3 is turned on under the control of the effective level of the first control signal at the first control signal terminal CS1, and turned off under the control of the ineffective level of the first control signal. Optionally, the third transistor M3 can be an N-type transistor, in which case the effective level of the first control signal is high and the ineffective level is low. The third transistor M3 can be a P-type transistor, in which case the effective level of the first control signal is low and the ineffective level is high.

[0148] In some embodiments of this disclosure, the active layer of the third transistor M3 may be made of a metal oxide semiconductor material, thereby configuring the third transistor M3 as an oxide transistor.

[0149] For example, the first control signal terminal CS1 can include a first node N1 or a third node N3. For instance, as shown... Figure 16 As shown, the gate of the third transistor M3 is coupled to the first node N1. Therefore, the third transistor M3 can be turned on under the control of the signal from the first node N1.

[0150] and, Figure 16 The signal timing diagram corresponding to the shift register unit shown is as follows: Figure 5 As shown. Its specific working process in the first stage T1, the second stage T2, and the third stage T3 can be compared with... Figure 4 The operation of the shift register units shown is basically the same, and will not be described in detail here.

[0151] This disclosure provides further signal timing diagrams for some shift register units, such as... Figure 17 As shown, this embodiment is a variation of the implementation described in the above embodiments. The following only describes the differences between this embodiment and the above embodiments; the similarities will not be repeated here.

[0152] In some embodiments of this disclosure, such as Figure 17 As shown, the shift register unit further includes a fourth control sub-circuit 216, which is coupled to the second reference signal terminal VREF2 and the first node N1, and is configured to control the signal of the first node N1 according to the signal of the second reference signal terminal VREF2.

[0153] For example, such as Figure 17The fourth control sub-circuit 216 includes a second capacitor C2, a first electrode plate of the second capacitor C2 is coupled with the second reference signal terminal VREF2, and a second electrode plate of the second capacitor C2 is coupled with the first node N1.

[0154] And, Figure 17 The signal timing diagram corresponding to the shift register unit shown in FIG. 6 is shown in FIG. 6. Figure 5 The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described here. Figure 4 The specific working process of the shift register unit in the first stage T1, the second stage T2 and the third stage T3 can be basically the same as that of the shift register unit shown in FIG. 5, and details are not described here.

[0155] Based on the same disclosure concept, the disclosure embodiments also provide a driving method, as shown in FIG. 11, which includes: Figure 18

[0156] S11, in the first stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit controls the signal of the second node according to the signal of the second reference signal terminal, and turns on the first node and the third node in response to the signal of the third reference signal terminal; and the output sub-circuit provides the signal of the third reference signal terminal to the driving output terminal in response to the signal of the third node.

[0157] S12, in the second stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit turns on the first node and the third node in response to the signal of the third reference signal terminal; the first control sub-circuit provides the signal of the first reference signal terminal to the second node in response to the signal of the first control signal terminal; and the output sub-circuit provides the signal of the second control signal terminal to the driving output terminal in response to the signal of the second node.

[0158] S13, in the third stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit controls the signal of the second node according to the signal of the second reference signal terminal, and turns on the first node and the third node in response to the signal of the third reference signal terminal; and the output sub-circuit provides the signal of the third reference signal terminal to the driving output terminal in response to the signal of the third node.

[0159] Based on the same disclosure concept, the disclosure embodiments also provide a gate driving circuit, as shown in FIG. 12, which includes: Figure 19 ​As shown, it comprises: a plurality of the above-mentioned shift register units SR(1), SR(2), SR(3)…SR(N-1), SR(N) (N shift register units in total) in cascade. Wherein, the input signal end INP of the first stage shift register unit SR(1) is coupled with the frame start signal end STV. In each adjacent two shift register units, the input signal end INP of the next stage shift register unit is coupled with the driving output end OUTP of the previous stage shift register unit.

[0160] Specifically, the specific structure of each shift register unit in the above-mentioned gate drive circuit is the same as the above-mentioned shift register unit of the present disclosure in function and structure, and the repeated parts will not be described again. The gate drive circuit can be applied in electroluminescent display panels, which are not limited here.

[0161] Specifically, in the above-mentioned drive control circuit provided by the embodiments of the present disclosure, the first clock signals of the odd-numbered stage shift register units are all provided by the same clock end, i.e. the first clock end. The first clock signals of the even-numbered stage shift register units are all provided by the same clock end, i.e. the second clock end.

[0162] Based on the same disclosure concept, the embodiments of the present disclosure also provide a display device comprising the above-mentioned gate drive circuit provided by the embodiments of the present disclosure. The principle of solving the problem of the display device is similar to that of the aforementioned gate drive circuit, and therefore the implementation of the display device can be referred to the implementation of the aforementioned gate drive circuit, and the repeated parts will not be described again here.

[0163] In specific implementation, in the embodiments of the present disclosure, the display device can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with display function. Other essential parts of the display device should be understood by those skilled in the art, and will not be described again here, nor should it be regarded as a limitation on the present disclosure.

[0164] The embodiments of the present disclosure provide a shift register unit, a gate drive circuit, a driving method and a display device. By setting the voltages of the first reference signal end and the third reference signal end to be different, the risk of leakage of the related transistors in the shift register unit can be reduced, the output stability can be improved, and the display abnormality can be reduced.

[0165] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0166] It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that such changes and modifications be included within the scope of the present disclosure.

Claims

1. A shift register unit, characterized in that, The shift register unit comprises: an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit; the first control sub-circuit comprises a first transistor and a second transistor; the input sub-circuit is coupled with a first node and is configured to provide a signal of an input signal terminal to the first node in response to a signal of a first clock signal terminal; the first control sub-circuit is coupled with a second node and is configured to provide a signal of a first reference signal terminal to the second node in response to a signal of a first control signal terminal; the second control sub-circuit is coupled with the first node, the second node, and a third node, and is configured to control the signal of the second node according to a signal of a second reference signal terminal, and to turn on the first node and the third node in response to a signal of a third reference signal terminal; the output sub-circuit is coupled with the second node and the third node, and is configured to provide the signal of the third reference signal terminal to a driving output terminal in response to the signal of the third node, and to provide a signal of a second control signal terminal to the driving output terminal in response to the signal of the second node; wherein the signal of the second reference signal terminal is at a first level, the signals of the first reference signal terminal and the third reference signal terminal are at a second level respectively, and the voltages of the first reference signal terminal and the third reference signal terminal are different; the gate of the first transistor is coupled with the first control signal terminal, the first pole of the first transistor is coupled with the first reference signal terminal, the second pole of the first transistor is coupled with the first pole of the second transistor, the gate of the second transistor is coupled with the third node or the first node, and the second pole of the second transistor is coupled with the second node; or, the gate of the first transistor is coupled with the third node or the first node, the first pole of the first transistor is coupled with the first reference signal terminal, the second pole of the first transistor is coupled with the first pole of the second transistor, the gate of the second transistor is coupled with the first control signal terminal, and the second pole of the second transistor is coupled with the second node.

2. The shift register cell of claim 1, wherein, the first control signal terminal is the same signal terminal as the input signal terminal or a second clock signal terminal; and / or the material of the active layer of the first transistor and the second transistor comprises metal oxide semiconductor material.

3. The shift register cell of claim 1, wherein, the first control sub-circuit comprises a third transistor; the gate of the third transistor is coupled with the first control signal terminal, the first pole of the third transistor is coupled with the first reference signal terminal, and the second pole of the third transistor is coupled with the second node.

4. The shift register cell of claim 3, wherein, the first control signal terminal comprises the first node or the third node; and / or the material of the active layer of the third transistor comprises metal oxide semiconductor material.

5. A shift register cell as claimed in any one of claims 1-4, characterized in that, The shift register unit further comprises a third control sub-circuit coupled with the third node and a second clock signal terminal, and configured to control the signal of the third node according to the signal of the second clock signal terminal.

6. The shift register cell of claim 5, wherein, the third control sub-circuit comprises a fourth transistor and a first capacitor; The gate of the fourth transistor and its first electrode are coupled with the third node, the second electrode of the fourth transistor is coupled with the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor is coupled with the second clock signal end; or, The gate of the fourth transistor is coupled with the first node, the first electrode of the fourth transistor is coupled with the second clock signal end, the second electrode of the fourth transistor is coupled with the first electrode plate of the first capacitor, and the second electrode plate of the first capacitor is coupled with the third node.

7. The shift register cell of any one of claims 1 to 4, wherein, The shift register unit further comprises a fourth control sub-circuit, which is coupled with the second reference signal end and the first node, and is configured to control the signal of the first node according to the signal of the second reference signal end.

8. The shift register cell of claim 7, wherein, The fourth control sub-circuit comprises a second capacitor, the first electrode plate of the second capacitor is coupled with the second reference signal end, and the second electrode plate of the second capacitor is coupled with the first node.

9. The shift register cell of any one of claims 1-4, wherein, The second control sub-circuit comprises a fifth transistor and a sixth transistor; the gate of the fifth transistor is coupled with the first node or the third node, the first electrode of the fifth transistor is coupled with the second reference signal end, the second electrode of the fifth transistor is coupled with the second node, the gate of the sixth transistor is coupled with the third reference signal end, the first electrode of the sixth transistor is coupled with the first node, and the second electrode of the sixth transistor is coupled with the third node; and / or, The output sub-circuit comprises a seventh transistor and an eighth transistor; the gate of the seventh transistor is coupled with the second node, the first electrode of the seventh transistor is coupled with the second control signal end, and the second electrode of the seventh transistor is coupled with the driving output end; the gate of the eighth transistor is coupled with the third node, the first electrode of the eighth transistor is coupled with the third reference signal end, and the second electrode of the eighth transistor is coupled with the driving output end; and / or, The input sub-circuit comprises a ninth transistor, the gate of the ninth transistor is coupled with the first clock signal end, the first electrode of the ninth transistor is coupled with the input signal end, and the second electrode of the ninth transistor is coupled with the first node.

10. The shift register cell of claim 9, wherein, The output sub-circuit further comprises a third capacitor and / or a fourth capacitor; The first electrode plate of the third capacitor is coupled with the second node, and the second electrode plate of the third capacitor is coupled with the second control signal end or the driving output end; The first electrode plate of the fourth capacitor is coupled with the third node, and the second electrode plate of the fourth capacitor is coupled with the driving output end.

11. A gate drive circuit, characterized by comprising: It comprises: A plurality of shift register units as claimed in any one of claims 1-10 are cascaded; The input signal end of the first-stage shift register unit is coupled with a frame start signal end; In every two adjacent shift register units, the input signal end of the next-stage shift register unit is coupled with the driving output end of the previous-stage shift register unit.

12. A display device comprising: It comprises: The gate drive circuit as claimed in claim 11.

13. A driving method of a shift register unit as claimed in any one of claims 1-10, characterized in that, It comprises: In the first stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit controls the signal of the second node according to the signal of the second reference signal terminal, and turns on the first node and the third node in response to the signal of the third reference signal terminal; and the output sub-circuit provides the signal of the third reference signal terminal to the driving output terminal in response to the signal of the third node; In the second stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit turns on the first node and the third node in response to the signal of the third reference signal terminal; the first control sub-circuit provides the signal of the first reference signal terminal to the second node in response to the signal of the first control signal terminal; and the output sub-circuit provides the signal of the second control signal terminal to the driving output terminal in response to the signal of the second node; In the third stage, the input sub-circuit provides the signal of the input signal terminal to the first node in response to the signal of the first clock signal terminal; the second control sub-circuit controls the signal of the second node according to the signal of the second reference signal terminal, and turns on the first node and the third node in response to the signal of the third reference signal terminal; and the output sub-circuit provides the signal of the third reference signal terminal to the driving output terminal in response to the signal of the third node.

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