Gate driving circuit, array substrate, display panel and display device

Abstract

The present disclosure provides a gate driving circuit, an array substrate, a display panel and a display device, wherein the array substrate comprises a display area and a non-display area, at least one shift register is arranged in the non-display area, a common voltage feedback line, a first common voltage line and a clock signal line are arranged on one side of the shift register, and a second common voltage line is arranged on the other side of the shift register; the non-display area further comprises a virtual area opposite to a data binding area of the array substrate, the common voltage feedback line and the first common voltage line are conducted through a first connecting mechanism in the virtual area, the first common voltage line and the clock signal line are conducted through a second connecting mechanism, and the shift register is connected between the clock signal line and the second common voltage line. The array substrate can improve the uniformity of the in-plane common voltage signal Vcom of the display product.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of thin-film transistor liquid crystal display (TFT-LCD) technology, low-cost, narrow-bezel, and thin-and-light products have received more attention. Against this backdrop, Gate Driver on Array (GOA) technology has emerged. GOA technology integrates the gate driving circuit and the thin-film transistor (TFT) array on the array substrate. Through the cascading relationship of shift register units, pixels are turned on row by row, thereby enabling the display to show colorful images.

[0003] For medium to large-sized display products (≥7.9 inches), the stability and uniformity of the common voltage or reference voltage signal Vcom in the display area are key factors that need to be considered. However, for display products manufactured using a masking exposure process, the metal traces in the original GOA area are incomplete, which damages the Vcom circuit and results in poor uniformity of the in-plane Vcom signal. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a gate driving circuit, an array substrate, a display panel, and a display device that can improve the uniformity of the in-plane common voltage Vcom signal of the display product.

[0005] In a first aspect, this disclosure provides the following technical solution through an embodiment:

[0006] An array substrate includes a non-display area, wherein at least one shift register is provided in the non-display area, a common voltage feedback line, a first common voltage line and a clock signal line are located on one side of the shift register, and a second common voltage line is located on the other side of the shift register;

[0007] The non-display area also includes a virtual area located opposite the data binding area of ​​the array substrate. In the virtual area, the common voltage feedback line and the first common voltage line are connected through a first connection mechanism, the first common voltage line and the clock signal line are connected through a second connection mechanism, and the shift register is connected between the clock signal line and the second common voltage line.

[0008] In some embodiments, the clock signal line has a disconnected cut segment, the cut segment includes a via, the via is connected to the shift register through a CLK trace, and the second connection mechanism is connected to the cut segment.

[0009] In some embodiments, the shift register includes a first transistor, the first terminal of which is connected to the via via through the CLK trace, the second terminal of which is connected to the second common voltage line, and the first terminal and the second terminal are connected by a third connection mechanism.

[0010] In some embodiments, the control terminal of the first transistor is disconnected from the pull-up node, and the second terminal is disconnected from the second transistor.

[0011] In some embodiments, the signal output line of the second pole is connected to the second common voltage line through a fourth connection mechanism, the fourth connection mechanism being disposed in the overlapping area of ​​the signal output line and the second common voltage line.

[0012] In some embodiments, the signal output line connecting the second common voltage line and the thin-film transistor in the display area is disconnected.

[0013] In some embodiments, the clock signal line includes multiple clock signal sub-lines arranged in parallel, and the first common voltage line is connected to at least one of the clock signal sub-lines through the second connection mechanism.

[0014] Secondly, based on the same inventive concept, this disclosure provides the following technical solution through an embodiment:

[0015] A gate driving circuit includes at least one shift register disposed in a non-display area of ​​an array substrate, a common voltage feedback line, a first common voltage line and a clock signal line located on one side of the shift register, and a second common voltage line located on the other side of the shift register.

[0016] The non-display area also includes a virtual area located opposite the data binding area of ​​the array substrate. In the virtual area, the common voltage feedback line and the first common voltage line are connected through a first connection mechanism, the first common voltage line and the clock signal line are connected through a second connection mechanism, and the shift register is connected between the clock signal line and the second common voltage line.

[0017] Thirdly, this disclosure provides the following technical solution through an embodiment:

[0018] A display panel comprising any of the array substrates provided in the first aspect embodiment.

[0019] Fourthly, based on the same inventive concept, this disclosure provides the following technical solution through an embodiment:

[0020] A display device includes a display panel provided in a third aspect embodiment.

[0021] Through one or more technical solutions disclosed herein, this disclosure has the following beneficial effects or advantages:

[0022] This disclosure provides an array substrate in which a common voltage feedback line (Vcom FB), a first common voltage line (Vcom), and a clock signal line (CLK) are connected in a dummy area on the DPO side of the array substrate via a first connection mechanism and a second connection mechanism. Simultaneously, the clock signal line is connected to the second common voltage line Vcom AA through a shift register. This allows a complete Vcom compensation loop to be constructed in the GOA row within the dummy area. The common voltage feedback line can collect the in-plane Vcom coupling signal through this compensation loop and transmit it to the PCB board outside the plane. The Vcom compensation signal determined by the circuit reverse compensation can be transmitted to the second common voltage line through the compensation loop, and then to the common voltage line in the display area through the second common voltage line. This achieves the introduction of Vcom signal on the DPO side of the array substrate, avoiding the problem of in-plane Vcom signal imbalance caused by only introducing Vcom signal on the DP side, and is beneficial to improving the uniformity of in-plane Vcom signal in display products.

[0023] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0025] In the attached diagram:

[0026] Figure 1 A schematic diagram of the wiring layout for a 65-inch display product is shown.

[0027] Figure 2 A schematic diagram of the wiring layout for a 58.5-inch display product is shown.

[0028] Figure 3 A schematic diagram of the wiring of an array substrate in a non-display area according to an embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic diagram of the partitioning of an array substrate according to an embodiment of the present disclosure is shown;

[0030] Figure 5A schematic diagram showing the connection of the common voltage feedback line, the first common voltage line, and the clock signal line according to an embodiment of the present disclosure is provided.

[0031] Figure 6 A schematic diagram showing the first and second terminals of a first transistor being turned on according to an embodiment of the present disclosure is shown;

[0032] Figure 7 A schematic diagram is shown showing the signal output line Gout of the second pole and the second common voltage line VcomAA connected in the overlapping area by a fourth connection mechanism according to an embodiment of the present disclosure;

[0033] Figure 8 An equivalent circuit diagram of a gate drive circuit according to an embodiment of the present disclosure is shown;

[0034] Figure 9 A schematic diagram of a display device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0036] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0038] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0039] The reason for the poor in-plane Vcom signal uniformity issue in display products is that, currently, in order to save manufacturing costs, array substrates for some display products of similar sizes often share a single mask. However, to differentiate sizes, some array substrates will be manufactured using a masking exposure process. For example, please refer to [link to relevant documentation]. Figure 1 To ensure the stability and uniformity of the Vcom signal within the 65-inch product plane, a Vcom Feedback line (Vcom FB) is designed in the GOA region (array gate drive region) to collect the Vcom coupling signal within the plane and transmit it to the X-PCB (X-direction printed circuit board). After reverse compensation by the circuit, the Vcom signal within the plane tends to stabilize. This compensation point is generally located at both ends of the DPO side of the array substrate. The DP (DataPad) side of the array substrate refers to the data bonding side. The side opposite the DP side is the data bonding area opposite the array substrate, i.e., the DataPad Opposite, or DPO side.

[0040] The 58.5-inch display product is manufactured by blocking the exposure process on top of the 65-inch product. Please refer to [link / reference]. Figure 2The masking exposure process makes the metal traces in the GOA area incomplete and the Vcom loop on the DPO side is destroyed. Therefore, the product can only rely on the Vcom introduction point on the DP side to balance the in-plane common voltage, which results in poor in-plane Vcom uniformity, mainly manifested on the DPO side of the array substrate.

[0041] Figure 1 and Figure 2 The other routes indicated in the bid are:

[0042] GND: Ground signal line;

[0043] ADD: Array Data Pad test line;

[0044] Inner short ring: also known as an electrostatic loop;

[0045] ESD connection: Electrostatic discharge connection.

[0046] It should be noted that the above explanation uses 65-inch and 58.5-inch display products as examples, and does not mean that only 58.5-inch display products have the problem of poor in-plane Vcom signal uniformity. For medium and large-sized display products, if their array substrate uses a manufacturing process that shares a mask and blocks exposure, this problem may also occur.

[0047] Based on the above problem analysis, firstly, in an optional embodiment, please refer to... Figure 3 , Figure 4 and Figure 8 An array substrate is provided, including a non-display area, in which at least one shift register 20 is provided, a common voltage feedback line Vcom FB, a first common voltage line Vcom and a clock signal line are located on one side of the shift register 20, and a second common voltage line Vcom AA is located on the other side of the shift register 20; the non-display area also includes a virtual area located on the DPO side of the array substrate, in which the common voltage feedback line Vcom FB and the first common voltage line Vcom are connected through a first connection mechanism 11, the first common voltage line Vcom and the clock signal line are connected through a second connection mechanism 12, and the shift register 20 is connected between the clock signal line and the second common voltage line Vcom AA.

[0048] For details on the partitioning of the array substrate, please refer to [link / reference]. Figure 4The array consists of display and non-display areas. The display area is the pixel area on the array substrate, used to display images when the display device is working; it is abbreviated as AA area. The non-display area is the area without display function, including the GOA area and the dummy area. The GOA area contains GOA modules and various lines arranged on one side of the GOA modules, such as the common voltage feedback line Vcom FB, the first common voltage line Vcom, the clock signal line CLK, the noise reduction voltage lines (VDDE, VDDO), and the power supply line VSS. The GOA module includes multiple cascaded shift registers 20. One end of each shift register 20 is connected to various traces, and the other end is connected to the second common voltage line Vcom AA near the display area. For the dummy area, during patterning using the mask process, to ensure the accuracy and uniformity of the pattern formed within the AA area, a pattern is also formed around the AA area; the area containing this pattern is the dummy area.

[0049] exist Figure 4 In the array, the DP side of the array is located below the AA area, the DPO side is located above the AA area, and the dummy area is located on the DPO side, above the GOA area. The Vcom FB, Vcom, CLK, VDDE, VDDO, VSS and other lines in the GOA area will extend to the dummy area. At the same time, a shift register 20 is also formed in the dummy area, which is cascaded with the shift register 20 in the GOA module.

[0050] Within the virtual zone, the common voltage feedback line Vcom FB is connected to the first common voltage line Vcom via the first connection mechanism 11, and the first common voltage line Vcom is connected to the clock signal line via the second connection mechanism 12. The first connection mechanism 11 and the second connection mechanism 12 can be welded contacts formed by welding conductive metals, or conductive contacts formed between the two lines by metal powder deposition. Tungsten powder deposition utilizes the thermal and optical effects of lasers to deposit tungsten powder between the two conductive lines to form molten contacts for bridging, which can repair open circuits and also form conductive connections between the two lines. Furthermore, tungsten powder deposition equipment can also be used to laser-cut the lines, thereby creating cutting mechanisms or points that break the lines.

[0051] The principle behind the array substrate provided in this embodiment for improving in-plane Vcom uniformity is:

[0052] Through the first connection mechanism 11 and the second connection mechanism 12, the common voltage feedback line Vcom FB, the first common voltage line Vcom, and the clock signal line are connected in the dummy area on the DPO side of the array substrate. At the same time, the clock signal line is connected to the second common voltage line Vcom AA through the shift register 20. In this way, a complete Vcom compensation loop can be constructed in the GOA row within the dummy area. The common voltage feedback line Vcom FB can collect the in-plane Vcom coupling signal through this compensation loop and transmit it to the PCB board outside the plane. The Vcom compensation signal determined by the circuit reverse compensation can be transmitted to the second common voltage line Vcom AA through this compensation loop, and then transmitted to the common voltage line in the AA area through the second common voltage line. Thus, Vcom signal can also be introduced on the DPO side of the array substrate, avoiding the problem of in-plane Vcom signal imbalance caused by only introducing Vcom signal on the DP side, and significantly improving the uniformity of in-plane Vcom signal of the display product.

[0053] In some alternative embodiments, please refer to Figure 5 and Figure 8 The clock signal line has a disconnected cut segment, which includes a via 10. The via 10 is connected to the shift register 20 through the CLK trace, and the second connection mechanism 12 is connected to the cut segment.

[0054] Specifically, the CLK trace is the wire connecting the clock signal line and the shift register. One end of the CLK trace is connected to via 10, and the other end is connected to the input terminal of the shift register 20. The cut segment is a part of the clock signal line that is broken at both ends by a cut point or cut mechanism. The range of the cut segment can be determined according to the position of via 10 and the connection position of the second connection mechanism 12.

[0055] Setting a segment on the clock signal line within the virtual area ensures that the Vcom FB or Vcom signal will only be transmitted along the CLK trace, thereby further improving the accuracy and uniformity of Vcom compensation within the area.

[0056] In some embodiments, please refer to Figure 6 and Figure 8 The shift register 20 includes a first transistor M1. The first terminal of the first transistor M1 is connected to the via 10 through the CLK trace, and the second terminal is connected to the second common voltage line Vcom AA. The first terminal and the second terminal are connected through the third connection mechanism 13.

[0057] Specifically, the first terminal of the first transistor M1 can be either the source (collector) or the drain (emitter), and the second terminal corresponds to the first terminal, being either the drain (emitter) or the source (collector). In this embodiment, the first and second terminals of the transistor are connected through the third connection mechanism 13, indicating that the first and second terminals are either always in an open state or remain in a short-circuit state, rather than being connected only when the control terminal is in a high-level state. This simplifies the control process of the driver IC without affecting the transmission of the Vcom signal.

[0058] In some embodiments, please refer to Figure 6 and Figure 8 The control terminal of the first transistor M1 is disconnected from the pull-up node PU, and the second terminal is disconnected from the second transistor M2. This ensures that only the CLK trace and the signal output line Gout in the first transistor M1 are connected, while other lines are disconnected, guaranteeing that the Vcom signal is transmitted only along the Gout trace.

[0059] In some embodiments, please refer to Figure 7 and Figure 8 The signal output line Gout of the second pole is connected to the second common voltage line Vcom AA via a fourth connection mechanism 14. The fourth connection mechanism 14 is located in the overlapping area of ​​the signal output line Gout and the second common voltage line Vcom AA. Specifically, the fourth connection mechanism 14 connects the Gout trace and the Vcom AA trace in the overlapping area, keeping them short-circuited. This allows the Vcom signal to be transmitted to the common voltage line in the plane without loss, thereby further improving the uniformity of the Vcom signal in the plane.

[0060] In some embodiments, please refer to Figure 7 and Figure 8 Connect the second common voltage line Vcom AA and the thin-film transistor in the display area ( Figure 7 and 8 The signal output line Gout (not shown) is in the off state, which can avoid short circuit problems in the plane and improve the uniformity and display effect of the Vcom signal in the plane.

[0061] In some embodiments, please refer to Figure 3 The clock signal line includes multiple clock signal sub-lines arranged in parallel, such as CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6. The first common voltage line Vcom can be connected to at least one of the clock signal sub-lines through the second connection mechanism 12. Figure 3The diagram shows the Vcom line being connected to the adjacent CLK1 line via the second connection mechanism 12, which has a relatively low manufacturing cost. However, in some cases, the Vcom line can also be connected to a non-adjacent CLKi line via the second connection mechanism 12. That is, the second connection mechanism 12 spans the CLK1 to CLK(i-1) lines and connects to the CLKi line, where i is an integer from 2 to 6. Through a transistor connected to the CLKi line, the Vcom signal can also be transmitted in-plane, achieving the technical effect of compensating for the in-plane uniformity of Vcom.

[0062] In summary, the array substrate provided in this embodiment enhances the in-plane Vcom uniformity and improves the stability of the in-plane Vcom signal by forming a complete Vcom compensation loop on the DPO side. Moreover, it does not require additional masking processes during manufacturing; only the routing design of the peripheral clock signal CLK needs to be changed. This can be achieved by forming connection mechanisms or cutting points to disconnect the lines at certain locations. Therefore, it will not adversely affect the production efficiency of the array substrate or display panel.

[0063] The array substrate provided in this embodiment is suitable for various types of display panels, especially for manufacturing medium and large-sized display panels, where medium and large size refers to a size of not less than 7.9 inches.

[0064] Secondly, based on the same inventive concept, in another alternative embodiment, a gate driving circuit is provided, which can be referred to... Figure 8 The gate driving circuit includes at least one shift register 20 disposed in the non-display area of ​​the array substrate, a common voltage feedback line Vcom FB, a first common voltage line Vcom and a clock signal line CLK1 located on one side of the shift register 20, and a second common voltage line Vcom AA located on the other side of the shift register 20; the non-display area also includes a virtual area Dummy located on the DPO side of the array substrate, in which the common voltage feedback line Vcom FB and the first common voltage line Vcom are connected through a first connection mechanism 11, the first common voltage line Vcom and the clock signal line CLK1 are connected through a second connection mechanism 12, and the shift register 20 is connected between the clock signal line CLK1 and the second common voltage line Vcom AA.

[0065] Specifically, the Vcom compensation signal from the Vcom FB line is transmitted to the Vcom AA line through the first connection mechanism 11, the second connection mechanism 12, the via 10 of the CLK1 line, the third connection mechanism 13 connecting the first and second poles of the first transistor M1, and the fourth connection mechanism 14 connecting the Gout line and the Vcom AA line, thereby achieving compensation for the Vcom signal in the plane and improving the uniformity of the Vcom signal in the plane.

[0066] Thirdly, in some alternative embodiments, a display panel is provided, the display panel including any of the array substrates provided in the first aspect embodiments.

[0067] Fourthly, in some optional embodiments, please refer to Figure 9 A display device is provided, including a second aspect, a display panel. The display device can be a display product such as an LCD TV or an all-in-one conference machine.

[0068] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0069] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An array substrate, characterized in that, The array substrate includes a non-display area, in which at least one shift register is provided, a common voltage feedback line, a first common voltage line and a clock signal line are located on one side of the shift register, and a second common voltage line is located on the other side of the shift register; The non-display area also includes a virtual area located opposite the data binding area of ​​the array substrate. In the virtual area, the common voltage feedback line and the first common voltage line are connected through a first connection mechanism, the first common voltage line and the clock signal line are connected through a second connection mechanism, and the shift register is connected between the clock signal line and the second common voltage line. The clock signal line has a disconnected cut segment, the cut segment includes a via, the via is connected to the shift register through a CLK trace, and the second connection mechanism is connected to the cut segment.

2. The array substrate as described in claim 1, characterized in that, The shift register includes a first transistor, the first terminal of which is connected to the via through the CLK trace, and the second terminal is connected to the second common voltage line. The first terminal and the second terminal are connected by a third connection mechanism.

3. The array substrate as described in claim 2, characterized in that, The control terminal of the first transistor is disconnected from the pull-up node, and the second terminal is disconnected from the second transistor.

4. The array substrate as described in claim 2, characterized in that, The signal output line of the second pole is connected to the second common voltage line through a fourth connecting mechanism, which is located in the overlapping area of ​​the signal output line and the second common voltage line.

5. The array substrate as described in claim 1, characterized in that, The signal output line connecting the second common voltage line and the thin-film transistor in the display area is disconnected.

6. The array substrate as claimed in claim 1, characterized in that, The clock signal line includes multiple clock signal sub-lines arranged in parallel, and the first common voltage line is connected to at least one of the clock signal sub-lines through the second connection mechanism.

7. A gate driving circuit, characterized in that, It includes at least one shift register disposed in the non-display area of ​​the array substrate, a common voltage feedback line, a first common voltage line and a clock signal line located on one side of the shift register, and a second common voltage line located on the other side of the shift register; The non-display area also includes a virtual area located opposite the data binding area of ​​the array substrate. In the virtual area, the common voltage feedback line and the first common voltage line are connected through a first connection mechanism, the first common voltage line and the clock signal line are connected through a second connection mechanism, and the shift register is connected between the clock signal line and the second common voltage line. The clock signal line has a disconnected cut segment, the cut segment includes a via, the via is connected to the shift register through a CLK trace, and the second connection mechanism is connected to the cut segment.

8. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 6.

9. A display device, characterized in that, Includes the display panel as described in claim 8.

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