Method of forming a semiconductor structure
By employing multiple ion implantations and chemical rinsing methods, the removal of the inner sidewall material layer is precisely controlled, solving the problem of damage at the apex of the gate structure and improving the device performance of the fully enclosed gate structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-02-25
- Publication Date
- 2026-07-24
AI Technical Summary
During the formation of the inner wall of the fully enclosed gate structure, the apex corner of the gate structure is easily damaged, leading to a decrease in device performance.
The inner sidewall material layer is modified by multiple ion implantation processes to gradually remove excess material. Combined with chemical flushing technology, the removal process of the inner sidewall is precisely controlled to protect the apex corner of the gate structure from damage.
It effectively protects the apex corner of the gate structure, improves device performance, avoids the formation of mushroom-shaped defects, and ensures process precision.
Smart Images
Figure CN116705608B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] Gate-All-Around (GAA) is a novel structure for manufacturing metal-oxide-semiconductor field-effect transistors (MOSFETs) smaller than 5 nanometers. It offers superior control and device performance compared to FinFETs. Common GAA structures include nanosheets and nanowires.
[0003] In the fabrication of nanosheet structures, the fins are multilayer silicon-germanium / silicon. The silicon-germanium layer of the fin is removed after silicon-germanium epitaxial deposition, a process known as channel release, and the vacant gaps are then filled with a metal gate material. To prevent the silicon layer of the fin from collapsing, inner spacers are filled into the cavities on both sides of the silicon-germanium layer.
[0004] However, in current processes, the formation of the inner sidewalls can easily damage the apex corners of the gate structure, thereby damaging the gate layer. Therefore, it is necessary to provide a more efficient and reliable technical solution. Summary of the Invention
[0005] This application provides a method for forming a semiconductor structure that can protect the apex corner of the gate structure from damage during the formation of the inner sidewall, thereby improving device performance.
[0006] This application provides a method for forming a semiconductor structure, comprising: forming a semiconductor structure sequentially including a bottom, a fin, and a gate structure, wherein the fin includes a plurality of sequentially stacked sacrificial layers and a channel layer, and recesses are formed on both sides of the plurality of sacrificial layers; forming an inner sidewall material layer on the surface and sidewalls of the gate structure, the sidewalls of the fin, and the surface of the bottom, the inner sidewall material layer filling the recesses and the inner sidewall material layer of the gate structure sidewall protruding from the inner sidewall material layer of the fin sidewall; forming a protective layer on the top of the gate structure; performing a first ion implantation process to convert the inner sidewall material layer protruding from the sidewalls of the fin into a first modified layer, and then removing the first modified layer; performing a second ion implantation process to convert the recesses and the inner sidewall material layer other than the top of the gate structure into a second modified layer, and then removing the second modified layer; and removing the protective layer.
[0007] In some embodiments of this application, the first modified layer includes several first sub-modified layers. A first ion implantation process is performed to convert the inner sidewall material layer protruding from the fin sidewall of the gate structure into the first modified layer. The method for removing the first modified layer includes: performing the first ion implantation process to convert a portion of the inner sidewall material layer protruding from the fin sidewall of the gate structure into a first sub-modified layer, and then removing the first sub-modified layer; repeating the above steps until all the inner sidewall material layers protruding from the fin sidewall of the gate structure are removed.
[0008] In some embodiments of this application, the process parameters of the first ion implantation process include: the implanted ion is a hydrogen ion, the implantation angle is 60 to 80 degrees, the implantation depth is 10 to 20 angstroms, and the implantation energy is 3 to 20 eV.
[0009] In some embodiments of this application, the method for removing the first sub-modified layer includes chemical rinsing, wherein the process parameters of the chemical rinsing include: the rinsing reagent is DHF, the rinsing time is 60 to 180 seconds, and the rinsing flow rate is 5 to 35 L / min.
[0010] In some embodiments of this application, the protective layer is removed at the same time as the first sub-modification layer is removed each time, and a new protective layer is formed on top of the gate structure before each first ion implantation process is performed.
[0011] In some embodiments of this application, the second modified layer includes several second sub-modified layers. A second ion implantation process is performed to convert the inner sidewall material layer other than the recess and the top of the gate structure into the second modified layer. The method for removing the second modified layer includes: performing a second ion implantation process to convert a portion of the inner sidewall material layer other than the recess and the top of the gate structure into a second sub-modified layer, and then removing the second sub-modified layer; repeating the above steps until all the inner sidewall material layers other than the recess and the top of the gate structure are removed.
[0012] In some embodiments of this application, the process parameters of the second ion implantation process include: the implanted ion is a hydrogen ion, the implantation angle is 60 to 80 degrees, the implantation depth is 10 to 20 angstroms, and the implantation energy is 3 to 20 eV.
[0013] In some embodiments of this application, the protective layer is removed each time the second sub-modified layer is removed, and a new protective layer is formed on top of the gate structure before each second ion implantation process.
[0014] In some embodiments of this application, the method for removing the second sub-modified layer includes chemical rinsing, wherein the process parameters of the chemical rinsing include: the rinsing reagent is DHF, the rinsing time is 60 to 180 seconds, and the rinsing flow rate is 5 to 35 L / min.
[0015] In some embodiments of this application, the material of the protective layer is a carbon-containing compound, and the method for forming the protective layer is radio frequency control.
[0016] The semiconductor structure formation method described in this application involves removing excess inner sidewall material layers in multiple steps. Each time, a portion of the inner sidewall material layer is modified using an ion implantation process, and then this portion of the inner sidewall material layer is removed. The entire process can be precisely controlled, thus protecting the apex corner of the gate structure from damage during the formation of the inner sidewall and improving device performance. Attached Figure Description
[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein: Figures 1 to 3 These are schematic diagrams illustrating the steps involved in forming some semiconductor structures. Figure 4 A flowchart of the method for forming the semiconductor structure described in the application embodiment; Figures 5 to 12 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0018] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0019] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0020] Figures 1 to 3 This is a schematic diagram of the steps in some methods for forming semiconductor structures.
[0021] refer to Figure 1 As shown, a semiconductor structure is formed that sequentially includes a bottom 100, a fin 110 and a gate structure 120, wherein the fin 110 includes a plurality of sequentially stacked sacrificial layers 111 and channel layers 112, and recesses 113 are formed on both sides of the plurality of sacrificial layers 111.
[0022] refer to Figure 2 As shown, an inner sidewall material layer 130 is formed on the surface and sidewalls of the gate structure 120, the sidewalls of the fin 110, and the surface of the bottom 100. The inner sidewall material layer 130 fills the recess 113, and the inner sidewall material layer 130 of the gate structure 120 sidewalls protrudes beyond the inner sidewall material layer 130 of the fin 110 sidewalls. The method for forming the inner sidewall material layer 130 is generally FCVD. Due to the presence of the recess 113, a certain amount of inner sidewall material is required to fill the recess 113, thus causing the inner sidewall material layer 130 of the gate structure 120 sidewalls to protrude beyond the inner sidewall material layer 130 of the fin 110 sidewalls.
[0023] refer to Figure 3 As shown, the inner wall material layer 130 outside the recess 113 is removed by etching process, leaving only the inner wall material layer 130 in the recess 113 as the inner wall 140.
[0024] However, since the inner sidewall material layer 130 of the gate structure 120 protrudes from the inner sidewall material layer 130 of the fin 110, and the etching process generally etches from top to bottom, the inner sidewall material layer 130 of the gate structure 120 must be etched open before the inner sidewall material layer 130 of the fin 110 can be etched. Moreover, this large amount of etching makes it difficult to precisely control the etching amount, and it is easy to over-etch and damage the gate structure 120, especially the apex corner 150 of the gate structure 120. Figure 3 The area indicated by the dashed box is easily opened, forming a mushroom defect, which can damage the gate layer inside the gate structure.
[0025] To address the aforementioned issues, this application provides a method for forming a semiconductor structure, which involves removing excess inner sidewall material layers in multiple steps. Each step employs an ion implantation process to modify a portion of the inner sidewall material layer before removing that portion. The entire process can be precisely controlled, thus protecting the gate structure's apex from damage during the formation of the inner sidewalls and improving device performance.
[0026] Figure 4 This is a flowchart of the method for forming the semiconductor structure described in the application embodiment.
[0027] This application provides a method for forming a semiconductor structure, with reference to... Figure 4 As shown, it includes: Step S1: Form a semiconductor structure comprising a bottom, a fin and a gate structure in sequence, wherein the fin comprises a plurality of sacrificial layers and a channel layer stacked in sequence, and recesses are formed on both sides of the plurality of sacrificial layers; Step S2: An inner sidewall material layer is formed on the surface and sidewall of the gate structure, the sidewall of the fin, and the bottom surface. The inner sidewall material layer fills the recess and the inner sidewall material layer of the gate structure sidewall protrudes from the inner sidewall material layer of the fin sidewall. Step S3: Form a protective layer on top of the gate structure; Step S4: Perform a first ion implantation process to transform the inner wall material layer of the gate structure sidewall protruding from the fin sidewall into a first modified layer, and then remove the first modified layer; Step S5: Perform a second ion implantation process to convert the inner wall material layer outside the recess and the top of the gate structure into a second modified layer, and then remove the second modified layer; Step S6: Remove the protective layer.
[0028] Figures 5 to 12 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0029] refer to Figure 4 and Figure 5 As shown, in step S1, a semiconductor structure is formed that sequentially includes a bottom 200, a fin 210 and a gate structure 220. The fin 210 includes a plurality of sequentially stacked sacrificial layers 211 and channel layers 212, and recesses 213 are formed on both sides of the plurality of sacrificial layers 211.
[0030] In some embodiments of this application, the bottom 200 is a semiconductor substrate, the material of which includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.
[0031] In some embodiments of this application, a plurality of fins 210 may be formed on the bottom 200. For the purpose of simplicity, only one fin is used as an example in this embodiment.
[0032] In some embodiments of this application, the material of the sacrificial layer 211 is, for example, silicon-germanium, and the material of the channel layer 212 is, for example, silicon.
[0033] In some embodiments of this application, the number of sacrificial layers 211 and channel layers 212 is multiple. In this embodiment, only three sacrificial layers 211 and two channel layers 212 are used as examples. The top and bottom layers are both sacrificial layers 211.
[0034] The recess 213 is used to form an inner spacer, which supports the channel layer 212 to prevent it from collapsing when the sacrificial layer 211 is subsequently removed.
[0035] In some embodiments of this application, the gate structure 220 includes a gate oxide layer, a gate layer, a mask layer, and a sidewall layer located sequentially on the surface of the fin 210.
[0036] refer to Figure 4 and Figure 6 As shown, in step S2, an inner sidewall material layer 230 is formed on the surface and sidewall of the gate structure 220, the sidewall of the fin 210, and the surface of the bottom 200. The inner sidewall material layer 230 fills the recess 213, and the inner sidewall material layer 230 of the sidewall of the gate structure 220 protrudes from the inner sidewall material layer 230 of the sidewall of the fin 210.
[0037] The method for forming the inner sidewall material layer 230 is generally FCVD. Due to the presence of the recess 213, a certain amount of inner sidewall material is required to fill the recess 213, which causes the inner sidewall material layer 230 of the gate structure 220 sidewall to protrude from the inner sidewall material layer 230 of the fin 210 sidewall.
[0038] In some embodiments of this application, the material of the inner wall material layer 230 is silicon nitride.
[0039] refer to Figure 4 and Figure 7 As shown, in step S3, a protective layer 240 is formed on the surface of the inner wall material layer on top of the gate structure 220.
[0040] In some embodiments of this application, the protective layer 240 is made of a carbon-containing polymer, such as CH3F-X, and the protective layer 240 is formed by radio frequency control (RF control). The carbon-containing polymer is mainly generated by the dissociation of a -CH3-containing gas. If the plasma excitation voltage is not biased, it will easily deposit on top of the patterned structure. Because its dissociation reactants are relatively complex, they can generally be considered as complex compounds such as CxHxFx.
[0041] The protective layer 240 can protect the gate structure 220 and the inner sidewall material layer on top of the gate structure 220 during subsequent ion implantation processes. Furthermore, the protective layer 240 can be removed simultaneously with the modified inner sidewall material layer.
[0042] refer to Figure 4 and Figures 8 to 9 As shown, in step S4, a first ion implantation process is performed to transform the inner sidewall material layer 230 of the gate structure 220 sidewall protruding from the fin 210 sidewall into a first modified layer 250, and then the first modified layer 250 is removed. First, the inner sidewall material layer 230 of the gate structure 220 sidewall is opened to be flush with the inner sidewall material layer 230 of the fin 210 sidewall, facilitating subsequent removal of the inner sidewall material layer 230 of the fin 210 sidewall.
[0043] Specifically, refer to Figure 8 As shown, a first ion implantation process is performed to transform the inner sidewall material layer 230, which protrudes from the sidewall of the gate structure 220 beyond the sidewall of the fin 210, into a first modified layer 250. (Reference) Figure 9 As shown, the first modified layer 250 is then removed. During the removal of the first modified layer 250, the width of the protective layer 240 is made to match the width of the inner wall material layer at the top of the gate structure.
[0044] In the technical solution of this application, the inner wall material layer 230 is modified into an easily removable material by using ion implantation process before removal, which makes it easier to control and prevents excessive removal.
[0045] In some embodiments of this application, in addition to converting all the inner wall material layer 230 protruding from the sidewall of the gate structure 220 into the first modified layer 250 at once and then removing the first modified layer 250, in order to further improve accuracy, the protruding inner wall material layer 230 can also be removed in multiple steps.
[0046] For example, the first modified layer 250 includes several first sub-modified layers. A first ion implantation process is performed to convert a portion of the inner sidewall material layer 230 protruding from the sidewall of the gate structure 220 into a first sub-modified layer, and then the first sub-modified layer is removed. The above steps are repeated until all the inner sidewall material layers 230 protruding from the sidewall of the gate structure 220 are removed. That is, each time the first ion implantation process is performed, a small portion of the protruding inner sidewall material layer is modified and removed, and then this process is repeated multiple times until all the protruding inner sidewall material layers are removed.
[0047] In some embodiments of this application, the process parameters for each of the first ion implantation processes include: implanted ions are hydrogen ions, the implantation angle is 60 to 80 degrees, the implantation depth is 10 to 20 angstroms, and the implantation energy is 3 to 20 eV. Due to the high selectivity of hydrogen ion treatment (H2 treatment) for nitrogen and carbon atoms, only silicon nitride (i.e., the inner sidewall material layer) reacts with hydrogen atoms and is modified. This modification refers to altering the physical and chemical properties of the inner sidewall material layer, making it easier to wash away. On the one hand, H2 ion bombardment loosens the physical structure of SiN, making it easy to wash away; on the other hand, H2 ions react with SiN to form -NH4 ammonium salt, which is easily removed by DHF.
[0048] In some embodiments of this application, the method for removing the first sub-modified layer includes chemical rinsing, wherein the process parameters for chemical rinsing include: the rinsing reagent is DHF (diluted hydrofluoric acid), the rinsing time is 60 to 180 seconds, and the rinsing flow rate is 5 to 35 L / min.
[0049] In some embodiments of this application, the protective layer is removed simultaneously with each removal of the first sub-modified layer, and a new protective layer is formed on top of the gate structure before each execution of the first ion implantation process. Repeated execution of the first ion implantation process may damage the protective layer and affect its protective effect. Therefore, it is best to reform a new protective layer after each cycle (one cycle consists of one first ion implantation process plus one rinsing process).
[0050] refer to Figure 4 and Figures 10 to 11 As shown, in step S5, a second ion implantation process is performed to transform the inner sidewall material layer 230, excluding the top of the recess 213 and the gate structure 220, into a second modified layer 260, and then the second modified layer 260 is removed. The inner sidewall material layer in the recess 213 forms an inner sidewall 270.
[0051] Specifically, refer to Figure 10 As shown, a second ion implantation process is performed to transform the inner sidewall material layer 230, excluding the top of the recess 213 and the gate structure 220, into a second modified layer 260. (Reference) Figure 11 As shown, the second modified layer 260 is then removed.
[0052] In the technical solution of this application, the inner wall material layer 230 is modified into an easily removable material by using ion implantation process before removal, which makes it easier to control and prevents excessive removal.
[0053] In some embodiments of this application, in addition to converting the inner wall material layer 230 other than the top of the recess 213 and the gate structure 220 into the second modified layer 260 in one go, and then removing the second modified layer 260, in order to further improve accuracy, the inner wall material layer 230 other than the top of the recess 213 and the gate structure 220 can be removed in multiple steps.
[0054] For example, the second modified layer 260 includes several second sub-modified layers. A second ion implantation process is performed to convert a portion of the inner sidewall material layer 230 outside the top of the recess 213 and the gate structure 220 into a second sub-modified layer, and then the second sub-modified layer is removed. The above steps are repeated until all the inner sidewall material layers 230 outside the top of the recess 213 and the gate structure 220 are removed. That is, each time the second ion implantation process is performed, a small portion of the inner sidewall material layer 230 outside the top of the recess 213 and the gate structure 220 is modified and removed, and then this process is repeated multiple times until all the inner sidewall material layers 230 outside the top of the recess 213 and the gate structure 220 are removed.
[0055] In some embodiments of this application, the process parameters of the second ion implantation process include: the implanted ion is hydrogen ion, the implantation angle is 60 to 80 degrees, the implantation depth is 10 to 20 angstroms, and the implantation energy is 3 to 20 eV. The modification principle of the second modified layer is the same as that of the first modified layer.
[0056] In some embodiments of this application, the protective layer is removed simultaneously with each removal of the second sub-modified layer, and a new protective layer is formed on top of the gate structure before each second ion implantation process. Repeated execution of the second ion implantation process may damage the protective layer and affect its protective effect; therefore, it is preferable to reform a new protective layer after each cycle.
[0057] In some embodiments of this application, the method for removing the second sub-modified layer includes chemical rinsing, wherein the process parameters of the chemical rinsing include: the rinsing reagent is DHF, the rinsing time is 60 to 180 seconds, and the rinsing flow rate is 5 to 35 L / min.
[0058] refer to Figure 4 and Figure 12 As shown, in step S6, the protective layer 260 is removed.
[0059] In some embodiments of this application, the protective layer 260 may be removed simultaneously with the second modified layer.
[0060] In the technical solution of this application, the method of partially modifying and then removing the inner sidewall material layer is easy to control precisely and will not remove too much material, thus not damaging the gate structure.
[0061] In some embodiments of this application, the method further includes: removing the inner wall material layer 230.
[0062] In some embodiments of this application, a source electrode and a drain electrode are formed on the bottom 200 on both sides of the fin 210.
[0063] The semiconductor structure formation method described in this application involves removing excess inner sidewall material layers in multiple steps. Each time, a portion of the inner sidewall material layer is modified using an ion implantation process, and then this portion of the inner sidewall material layer is removed. The entire process can be precisely controlled, thus protecting the apex corner of the gate structure from damage during the formation of the inner sidewall and improving device performance.
[0064] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0065] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0066] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0067] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0068] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor structure is formed comprising a bottom, a fin, and a gate structure in sequence, wherein the fin comprises a plurality of sequentially stacked sacrificial layers and a channel layer, and recesses are formed on both sides of the plurality of sacrificial layers; An inner sidewall material layer is formed on the surface and sidewall of the gate structure, the sidewall of the fin, and the bottom surface. The inner sidewall material layer fills the recess, and the inner sidewall material layer of the gate structure sidewall protrudes from the inner sidewall material layer of the fin sidewall. A protective layer is formed on top of the gate structure; The method of performing a first ion implantation process to convert the inner sidewall material layer of the gate structure sidewall protruding from the fin sidewall into a first modified layer, and then removing the first modified layer, wherein the first modified layer comprises a plurality of first sub-modified layers, includes: performing a first ion implantation process to convert a portion of the inner sidewall material layer of the gate structure sidewall protruding from the fin sidewall into a first sub-modified layer, and then removing the first sub-modified layer; repeating the above steps until all the inner sidewall material layers of the gate structure sidewall protruding from the fin sidewall are removed; The method of performing a second ion implantation process to convert the inner sidewall material layer outside the recess and the top of the gate structure into a second modified layer, and then removing the second modified layer, wherein the second modified layer comprises a plurality of second sub-modified layers, includes: performing a second ion implantation process to convert a portion of the inner sidewall material layer outside the recess and the top of the gate structure into a second sub-modified layer, and then removing the second sub-modified layer; repeating the above steps until all the inner sidewall material layers outside the recess and the top of the gate structure are removed; Remove the protective layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters of the first ion implantation process include: the implanted ion is hydrogen ion, the implantation angle is 60 to 80 degrees, the implantation depth is 10 to 20 angstroms, and the implantation energy is 3 to 20 eV.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for removing the first sub-modified layer includes chemical rinsing, wherein the process parameters for chemical rinsing include: rinsing reagent is DHF, rinsing time is 60 to 180 seconds, and rinsing flow rate is 5 to 35 L / min.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective layer is removed at the same time as the first sub-modified layer is removed each time, and a new protective layer is formed on top of the gate structure before each first ion implantation process.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters of the second ion implantation process include: the implanted ion is hydrogen ion, the implantation angle is 60 to 80 degrees, the implantation depth is 10 to 20 angstroms, and the implantation energy is 3 to 20 eV.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective layer is removed at the same time as the second sub-modified layer is removed each time, and a new protective layer is formed on top of the gate structure before each second ion implantation process.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for removing the second sub-modified layer includes chemical rinsing, wherein the process parameters for chemical rinsing include: the rinsing reagent is DHF, the rinsing time is 60 to 180 seconds, and the rinsing flow rate is 5 to 35 L / min.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective layer is made of a carbon-containing compound, and the protective layer is formed by radio frequency control.