FPGA-based system and method for LTE-V receiver CCH channel de-rate matching

Abstract

A system and method for LTE-V receiving end CCH channel rate dematching based on FPGA, comprising: a state machine control unit, an input control unit, a block random memory unit and an output control unit, wherein: the state machine control unit transmits information of data count to the input control unit and the output control unit respectively according to a start signal to control the input and output of data; the input control unit receives and fills the descrambled data to 432 bits and then outputs to the BRAM unit; the output control unit reads the data in the BRAM unit by generating a read address and a read enable signal, and outputs the data after bit rearrangement while reading the data from the BRAM unit. The application utilizes the same rule of bit transformation of CCH channel rate dematching each time to avoid the calculation of interleaving and deinterleaving and significantly simplify the system structure.

Description

Technical Field

[0001] This invention relates to a technology in the field of wireless communication, specifically a system and method for rate matching of the LTE-V receiver CCH channel based on FPGA. Background Technology

[0002] Rate matching and de-rate matching are crucial technologies in LTE-V systems. Improving the processing speed of the de-rate matching module to reduce latency, and lowering algorithm complexity to reduce resource consumption are the main goals of the hardware implementation of the de-rate matching algorithm. Current technologies often require the implementation of interleaving and de-interleaving calculations in hardware, but in the LTE-V CCH channel (control channel), the bit rearrangement rules are consistent for each transmission; therefore, it is possible to avoid the specific calculations for interleaving and de-interleaving.

[0003] Existing improved techniques employ multi-path parallel processing to increase the speed of rate matching, with each path performing interleaving and deinterleaving operations separately. This results in complex structures and high algorithm implementation complexity, and the parallel processing also increases resource consumption. Even when the channel configuration remains unchanged, the bit rearrangement rules for rate matching are the same each time, but the same interleaving and deinterleaving calculations must be repeated each time. Summary of the Invention

[0004] This invention addresses the problems of long processing delays in rate matching and high resource consumption caused by interleaving and deinterleaving calculations in each rate matching operation in existing technologies. It proposes a system and method for rate matching of the LTE-V receiver CCH channel based on FPGA. By utilizing the fact that the bit transformation rules are the same for each rate matching operation of the CCH channel, the calculations of interleaving and deinterleaving are avoided and the system structure is significantly simplified.

[0005] This invention is achieved through the following technical solution:

[0006] This invention relates to an FPGA-based LTE-V receiver CCH channel rate matching system, comprising: a state machine control unit, an input control unit, a block random access memory (BRAM) unit, and an output control unit. The state machine control unit transmits data counting information to the input control unit and the output control unit respectively based on a start signal to control data input and output. The input control unit receives descrambled data, pads it to 432 bits, and outputs it to the BRAM unit. The output control unit reads data from the BRAM unit by generating a read address and a read enable signal, and simultaneously performs bit rearrangement before outputting the data.

[0007] The output control unit preferably includes a ROM for pre-storing interleaving addresses.

[0008] The output unit outputs rearranged data after handshaking with the subsequent decoding module, and performs decoding operation after rate matching.

[0009] This invention relates to an FPGA-based LTE-V receiver CCH channel rate matching solution method based on the above-mentioned system, comprising the following steps:

[0010] Step 1: The state machine is in the idle state (IDLE), that is, the registers of the read and write signals of the input BRAM unit are all cleared. When the external start signal is received, it jumps to the input data storage (S1) state and starts data processing.

[0011] Step 2: In state S1, the input data with a total length of 432 is divided into three segments of 144 each and the three segments are superimposed to obtain a total data length of 144. The data is stored into the BRAM unit in sequence according to the addresses from 0 to 143. When the storage is complete, a trigger signal (totalBits_finish) is generated and the process jumps to the data control output (S2) state.

[0012] Step 3: In state S2, the state machine stores the calculated bit interleaving transformation mapping relationship of CCH de-rate matching as address data in ROM. In state S2, it controls the reading of the ROM containing the address data of the mapping relationship, uses the read address data as the address to read the BRAM cell, reads the input data stored in state S1, completes CCH de-rate matching, and then jumps back to state IDLE.

[0013] Technical effect

[0014] Compared to existing methods that use hardware to implement each step of bit interleaving and deinterleaving, this invention utilizes the rule that the bit transformation rules are the same for each CCH channel de-rate matching. The calculated bit address transformation mapping relationship directly completes the bit rearrangement, avoiding the specific calculations of interleaving and deinterleaving, reducing the complexity of the hardware algorithm, improving the processing speed, and reducing resource consumption. At the same time, the algorithm of two superpositions utilizes every bit received, improving the information utilization rate and further improving the success rate of subsequent decoding. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the CCH solution rate matching (rdm) system of the present invention;

[0016] Figure 2 This is the CCH rdm state transition diagram of the present invention;

[0017] Figure 3 This is a flowchart of the superposition algorithm of the present invention;

[0018] Figure 4 This is a schematic diagram of bit transformation;

[0019] Figure 5 The following are simulation results of CCH channel rate matching (RDM) for the example implementation.

[0020] Figure 6 A flowchart illustrating the specific implementation process of CCH channel rate matching (RDM);

[0021] Figure 7 This is a schematic diagram of the system in the embodiment. Detailed Implementation

[0022] like Figure 1 As shown in the figure, this embodiment relates to a CCH channel de-rate matching system, including: a state machine control unit, an input control unit, a BRAM unit, and an output control unit. The state machine control unit transmits data counting information to the input control unit and the output control unit respectively according to the start signal (start) to control the data input and output. The input control unit receives the descrambled data (data_descr_i), pads it to 432 bits, and outputs it to the BRAM unit. The output control unit reads the interleaved address data from the ROM and sends the read address as the read address control to the BRAM unit. After completing the reading of three data segments, the system performs bit rearrangement and outputs the CCH channel de-rate matching output data to the decoding unit.

[0023] The state machine control unit uses a three-stage state machine to control data input and output, including: IDLE state, input data storage state S1, and data control output state S2. In IDLE state, all registers for read / write signals output to the BRAM are cleared. Upon receiving the start signal, it jumps to state S1 to begin data processing. In state S1, the input data, totaling 432 bytes, is divided into three segments of 144 bytes each and superimposed to obtain a superimposed data of 144 bytes. This superimposed data is then output sequentially to BRAM cells at addresses 0 to 143, and a totalBits_finish signal is generated after storage, triggering a jump to state S2. In state S2, the bit interleaving transformation mapping relationship calculated by MATLAB for CCH rate matching is stored as address data in the ROM. In state S2, the ROM containing the mapping relationship address data is read, and the read address data is used as the address to read the BRAM, retrieving the input data stored in state S1, completing the CCH rate matching, and then jumping back to the IDLE state.

[0024] like Figure 1As shown, the input control unit includes an input handshake module, a zero-padding module, and an input counter. The input handshake module receives start and end reception information from the state machine control unit, and receives the descrambled output data_descr_i from the preceding descrambling module. It inputs a valid signal to the counter to count the data. The zero-padding module performs zero-padding based on the number of descrambled output data bits. When the descrambled data_descr_i is less than 432 bits, it pads the end of the input data with zeros to fill the 432 bits and outputs it to the BRAM unit. The input counter counts the number of input data bits and outputs the count result to the state machine control unit as state transition information.

[0025] like Figure 1 As shown, the BRAM unit stores three segments of bit data S_Int, P1_Int, and P2_Int, and outputs data at the corresponding read address or write address according to the read / write address signal and read / write enable signal. Specifically, the input control unit outputs the write instruction and write address to the BRAM unit, and the output control unit controls the input of the read instruction and read address to the BRAM unit.

[0026] like Figure 3 As shown, according to the current LTE-V configuration, each of the three data segments v0, v1, and v2 is 48 bits long, for a total of 144 bits. Since the input control unit needs to superimpose the three 8-bit data segments, requiring two additions, the bit width is extended to 10 bits. Considering these two points, the BRAM unit in this embodiment uses the BRAM IP core provided by VIVADO. This BRAM unit is configured with a bit width of 10 bits and a depth of 144. When the input data is x(n), the data stored in the BRAM after superposition is... Where: t∈[1, 432], t∈Z. n∈[1, 144], n∈Z, M is the number of segments.

[0027] like Figure 4 As shown, the input control unit stores data in BRAM cells sequentially by incrementing the control address. The output control unit then reads the data using a lookup table. Figure 1 The S_Int, P1_Int, and P2_Int RAM data shown are each 48 bits long. When looking up the table, these three data paths can be selected by controlling the read address. Therefore, only one BRAM cell is needed to sequentially store 144 data.

[0028] Since the data length from the descrambling module to the rate matching module exceeds 144, in order to improve information utilization, after the first data is stored, the data is read out sequentially and added to the new data. Then, the data after the first superposition is stored back into the BRAM to overwrite the original data. Repeating the superposition process twice can complete the superposition and storage of the three data segments.

[0029] The output control unit includes a read RAM module, an output handshake module, and an output counter. The read RAM module inputs read instructions and read addresses to the BRAM cells and controls the data output rate according to the speed of the read address change. The output handshake module controls the handshake output data with the subsequent decoding module. When the subsequent decoding module is ready to receive data, it sends a ready signal to the de-decoding rate matching module to start reading the BRAM cells in the de-decoding rate matching module and outputs the data. The output counter calculates the count information of the output data based on the number of valid output data signals and outputs it to the state machine control unit to trigger a state transition.

[0030] The read address refers to: using the address mapping relationship calculated by MATLAB, reading out the address data sequentially, and then using this data as the read address of the BRAM, thereby realizing the calculation of interleaving and deinterleaving in CCH channel rate matching and avoiding complex calculation structures.

[0031] Preferably, since the rules and mapping relationships of bit rearrangement in CCH rate matching are fixed under the current protocol, the interleaving mapping algorithm in the rate matching method does not need to be implemented in the FPGA implementation. Instead, the address mapping relationship is stored in the ROM of the output control unit. The output control unit reads the address data in the address ROM and uses it as the address to read the BRAM unit. Finally, the output handshake module and the subsequent decoding module handshake the output, thus realizing the function of CCH rate matching.

[0032] In this embodiment, the address mapping relationship of bit transformation is pre-calculated using MATLAB and stored in the ROM of the output control unit. During hardware implementation, the bit transformation in rate matching can be directly completed using a lookup table-like method, thereby avoiding the need for specific interleaving and deinterleaving calculations. This not only reduces processing latency but also significantly reduces hardware design complexity, resource consumption, and power consumption. As shown in Table 1.

[0033]

[0034]

[0035] like Figure 6As shown, for the LTE-V scenario, its physical layer design has been completed based on FPGA. In the VIVADO project, it is applied to the CCH channel at the receiving end. At the decoding end, after restoring the original digital signal from the scrambled digital signal after QPSK demodulation, the bit rearranged de-rate matching data is obtained by the above-mentioned FPGA-based LTE-V receiving end CCH channel de-rate matching method. The information output by the de-rate matching is further processed by the decoding module to obtain the decoded original information.

[0036] In the diagram, data_descr represents the input data of the rate matching module, and data_viterbi_o represents the output data of the rate matching module. After receiving data from the front-end descrambling module, the bit rearrangement can be completed while storing the data. After receiving the data, it can be output to the back-end dechannel coding module. It works stably in multiple onboard tests, and the success rate of the back-end CCH channel is 100%.

[0037] Through specific experiments, in an LTE-V scenario with an operating frequency of 307.2MHz, using Figure 7 The MINITRX-Z (Hejiaxing) development board programming project shown can be configured by changing the values ​​of RB (the resource unit for service channel resource allocation in the LTE protocol, which is one time slot in the time domain and 12 subcarriers in the frequency domain) and MCS (modulation and coding strategy in the LTE protocol) of the system. Under the conditions of single-board self-transmission and self-reception and two-board air interface communication, according to the statistical results of decoding success rate, the success rate of CCH channel de-rate matching of 382 different RB and IMCS configurations is 100%, as shown in Table 2.

[0038]

[0039]

[0040] The table above shows a partial statistical analysis of the board test results for different RBs and MCSs, totaling 382 groups.

[0041] Compared with existing technologies, this invention utilizes the consistent bit transformation rules of CCH channel de-rate matching to directly complete bit rearrangement using the bit address transformation mapping relationship calculated by MATLAB, avoiding the specific calculations of interleaving and deinterleaving. This reduces the number of multipliers and control registers required for interleaving and deinterleaving.

[0042] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A system for rate matching of the LTE-V receiver CCH channel based on FPGA, characterized in that, include: The system comprises a state machine control unit, an input control unit, a BRAM unit, and an output control unit. The state machine control unit transmits data counting information to the input control unit and the output control unit respectively, based on a start signal, to control data input and output. The input control unit receives descrambled data, pads it to 432 bits, and outputs it to the BRAM unit. The output control unit reads data from the BRAM unit by generating a read address and a read enable signal, and simultaneously performs bit rearrangement before outputting the data. The output control unit is equipped with a ROM for pre-storing interleaving addresses; The state machine control unit uses a three-stage state machine to control data input and output, including: idle state, input data storage state, and data control output state. In the idle state, all registers for read / write signals output to the BRAM are cleared. Upon receiving the start signal, it jumps to the input data storage state to begin data processing. In the input data storage state, the total length of the input data (432) is divided into three segments of 144 each, and these segments are superimposed to obtain a total length of 144 superimposed data. This superimposed data is then output sequentially to BRAM cells according to addresses 0 to 143, and a totalBits_finish signal is generated after storage, triggering a jump to the data control output state. In the data control output state, the bit interleaving transformation mapping relationship calculated by MATLAB for CCH rate matching is stored as address data in the ROM. The ROM containing the mapping relationship address data is read in the data control output state, and the read address data is used as the address to read the BRAM, reading the input data stored in the input data storage state, completing the CCH rate matching, and then jumping back to the idle state. The output control unit includes: a read RAM module, an output handshake module, and an output counter. The read RAM module inputs read instructions and read addresses to the BRAM cells and controls the data output rate according to the speed of the read address change. The output handshake module controls the handshake output data with the subsequent decoding module. When the subsequent decoding module is ready to receive data, it sends a ready signal to the de-decoding rate matching module to start reading the BRAM cells in the de-decoding rate matching module and outputs the data. The output counter calculates the count information of the number of output data valid signals based on the number of valid output data signals and outputs it to the state machine control unit to trigger a state transition. The read address refers to: using the address mapping relationship calculated by MATLAB, sequentially reading out the address data, and then using this data as the read address of the BRAM, thereby realizing the calculation of interleaving and deinterleaving in CCH channel rate matching and avoiding complex calculation structures; In the current protocol, the rules and mapping relationships for bit rearrangement in CCH rate matching are stored in the ROM of the output control unit. The output control unit reads the address data from the address ROM and uses it as the address to read the BRAM unit. Finally, the output handshake module and the subsequent decoding module handshake the output, thus realizing the function of CCH rate matching.

2. The FPGA-based LTE-V receiver CCH channel rate matching system according to claim 1, characterized in that, The output control unit outputs rearranged data after handshaking with the subsequent decoding module, and performs decoding operation after rate matching.

3. The FPGA-based LTE-V receiver CCH channel rate matching system according to claim 1, characterized in that, The input control unit includes an input handshake module, a zero-padding module, and an input counter. The input handshake module receives start and end reception information from the state machine control unit, and receives the descrambled output data (data_descr_i) from the preceding descrambling module. It inputs a valid signal to the counter to count the data. The zero-padding module pads the data with zeros based on the number of descrambled output data bits. When the descrambled data (data_descr_i) is less than 432 bits, it pads the input data with zeros to fill the 432 bits and outputs it to the BRAM unit. The input counter counts the number of input data bits and outputs the count result to the state machine control unit as state transition information.

4. The FPGA-based LTE-V receiver CCH channel rate matching system according to claim 1 or 3, characterized in that, The BRAM unit stores three segments of bit data S_Int, P1_Int and P2_Int, and outputs the data to be read or written to the corresponding address according to the read / write address signal and the read / write enable signal. The input control unit outputs the write instruction and write address to the BRAM unit, and the output control unit controls the input of the read instruction and read address to the BRAM unit. According to the current LTE-V configuration, each of the three data segments v0, v1, and v2 is 48 bits long, for a total of 144 bits. Since the input control unit needs to superimpose the three data segments with an 8-bit width, the input control unit is required to handle this. The BRAM cell uses the built-in BRAM IP core of VIVADO. This BRAM cell is configured with a bit width of 10 bits and a depth of 144. When the input data is x(n), the data stored in the BRAM after stacking is... ,in: M is the number of segments; The input control unit stores data in BRAM cells sequentially by incrementing the control address. Since the output control unit reads S_Int, P1_Int, and P2_Int RAM data using a lookup table, with each bit data segment being 48 bits long, and the three data paths are selected by customizing the read address during the lookup, only one BRAM cell is needed to sequentially store 144 data entries.

5. A method for rate matching of the LTE-V receiver CCH channel based on an FPGA, according to any one of the systems described in claims 1 to 4, characterized in that, Includes the following steps: Step 1: The state machine is in the idle state (IDLE), that is, the registers of the read and write signals of the input BRAM unit are all cleared. When the external start signal is received, it jumps to the input data storage (S1) state and starts data processing. Step 2: In state S1, the state machine divides the input data with a total length of 432 into three segments of 144 each and superimposes the three segments to obtain a total data length of 144. The data is then stored into the BRAM unit in sequence according to the addresses from 0 to 143. After storage, a trigger signal is generated and the machine jumps to the data control output (S2) state. Step 3: In state S2, the state machine stores the calculated bit interleaving transformation mapping relationship of CCH de-rate matching as address data in ROM. In state S2, it controls the reading of the ROM containing the address data of the mapping relationship, uses the read address data as the address to read the BRAM cell, reads the input data stored in state S1, completes CCH de-rate matching, and then jumps back to state IDLE.

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