Optical proximity correction for freeform shapes

Abstract

Aspects of the disclosed technology relate to techniques for applying optical proximity correction to freeform shapes. Each optical proximity correction iteration includes calculating edge adjustment values for straight line segments based on edge placement errors derived from an optical proximity correction iteration immediately preceding each of the plurality of optical proximity correction iterations, adjusting positions of the straight line segments based on the determined edge adjustment values, determining smoothed boundary lines for layout features based on the straight line segments in the adjusted positions, performing simulation processing on the layout features with the smoothed boundary lines to determine simulated images of the layout features, and deriving edge adjustment errors for the straight line segments based on comparing the simulated images of the layout features to target images of the layout features.

Description

Technical Field

[0001] The technology disclosed herein relates to the field of circuit design and fabrication. Various embodiments of the disclosed technology may be particularly useful for optical proximity correction of layout designs. Background Art

[0002] As designers and manufacturers continue to shrink the size of circuit components, the shapes reproduced on substrates by photolithography become smaller and placed closer together. This reduction in feature size and spacing increases the difficulty of faithfully reproducing the image intended by the design layout onto the substrate and can result in defects in the fabricated device. To address this problem, one or more resolution enhancement techniques are typically employed to improve the resolution of the image formed on the substrate by the mask during the photolithography process.

[0003] One of the resolution enhancement techniques, optical proximity correction or optical process correction (OPC), attempts to compensate for the effects of light diffraction. When light strikes a photomask, the transmitted light diffracts, and the higher the spatial frequency of the mask area, the larger the angle of light diffraction. The resolution limit of the lens in the lithography system causes the lens to effectively act as a low-pass filter for various spatial frequencies in a two-dimensional layout. This can lead to optical proximity effects, such as the pullback of line ends from their desired positions, corner rounding, and deviations between isolated structures and dense structures. Optical proximity correction adjusts the amplitude of light transmitted through the photomask by modifying the layout design data used to create the photomask. For example, the edges in the layout design can be adjusted to make certain parts of the geometric elements larger or smaller depending on how much extra exposure (or underexposure) is needed at certain points on the substrate. When these adjustments are properly calibrated, the overall pattern fidelity is greatly improved, thereby reducing optical proximity effects.

[0004] Typically, layout designs primarily consist of Manhattan shapes. For Manhattan shapes, the edges are parallel to the x-axis and y-axis. Traditional design rule checking (DRC) and OPC tools focus on handling Manhattan shapes. Silicon photonics combines large-scale photonic integration with large-scale electronic integration and can impact areas such as telecommunications, data centers, and high-performance computing. However, silicon photonics designs are often drawn with curved shapes. Curved patterns can also provide better lithography quality than Manhattan patterns. Memory chip manufacturing has begun to explore curved patterns. Due to the practical needs and advantages of using curved patterns, the mask making industry has made progress with the introduction of multi-beam mask writers for writing curved patterns on masks. However, there is still a need to improve OPC technology to better handle curved shapes. Summary of the Invention

[0005] Aspects of the disclosed technology relate to techniques for applying optical proximity correction to free form shapes. In one aspect, there is a method comprising: segmenting a boundary line of a layout feature in a layout design into straight line segments, the segmenting comprising using some of the straight line segments to represent curved boundary line segments of the layout feature; generating a modified layout feature based on a plurality of optical proximity correction iterations, each of the plurality of optical proximity correction iterations comprising: calculating edge adjustment values ​​for the straight line segments based on edge placement errors derived from an optical proximity correction iteration immediately preceding each of the plurality of optical proximity correction iterations, adjusting positions of the straight line segments based on the determined edge adjustment values, determining a smooth boundary line of the layout feature based on the straight line segments at the adjusted positions, performing a simulation process on the layout feature having the smooth boundary line to determine a simulated image of the layout feature, and deriving edge adjustment errors for the straight line segments based on comparing the simulated image of the layout feature with a target image of the layout feature.

[0006] The method may further include processing the modified layout features to generate mask data for a mask writing tool to make a photomask. The method may further include applying the mask data to the mask writing tool to create a photomask.

[0007] Determining the smoothed boundary line can be based on a Gaussian convolution technique. The length of the straight line segment can be greater than or equal to one-quarter of the minimum feature size of the layout design. Each of the straight line segments can be parallel to the x-axis or y-axis of the layout design. Calculating the edge adjustment value can include multiplying the edge placement error by a matrix including a cross-mask error enhancement factor.

[0008] The plurality of optical proximity correction iterations may be terminated when the edge adjustment error is within a predetermined range or the number of the plurality of optical proximity correction iterations is equal to a predetermined number.

[0009] In another aspect, there is one or more computer-readable media storing computer-executable instructions for causing one or more processors to perform the above-described method.

[0010] In yet another aspect, there is a system comprising: one or more processors programmed to perform the above method.

[0011] Certain innovative aspects are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with features of the independent claim as appropriate, as well as with features of other dependent claims, and not just with features explicitly set out in the claims.

[0012] Certain objects and advantages of various innovative aspects have been described above. Of course, it should be understood that not all such objects or advantages need be achieved according to any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology can be embodied or implemented in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a computing system that can be used to implement various embodiments of the disclosed technology is shown.

[0014] Figure 2 An example of a multi-core processor unit that may be used to implement various embodiments of the disclosed technology is shown.

[0015] Figure 3A A mask feature 300 and a simulated image 302 of the mask feature are shown; Figure 3B An example of segmentation of the edge of a mask feature 300 is shown; Figure 3C Edge placement errors for some of these edge segments are shown; Figure 3D Shown are mask features 303 modified from mask features 300 by an OPC process and a corresponding simulated image 304 .

[0016] Figure 4 Two curved shapes are shown, whose boundary lines are segmented.

[0017] Figure 5 An example of waviness caused by approximating a curved boundary line using straight line segments is shown.

[0018] Figure 6 An example of an optical proximity correction tool that can be implemented according to various embodiments of the disclosed technology is shown.

[0019] Figure 7 A flow chart showing a process for optical proximity correction that can be implemented according to various examples of the disclosed technology is shown.

[0020] Figure 8 An example of a portion of a curved layout feature that is broken for OPC processing using two different methods is shown.

[0021] Figure 9 Examples of optical proximity iterations according to various examples of the disclosed technology are shown.

[0022] Figure 10A An example of the smoothed result of the Gaussian convolution of layout features during OPC iterations is shown.

[0023] Figure 10B Various examples of the disclosed technology are shown. Figure 10A An example of a modified layout feature obtained by performing OPC processing on the layout feature shown in . DETAILED DESCRIPTION

[0024] Overview

[0025] Various aspects of the presently disclosed technology relate to techniques for applying optical proximity correction to freeform shapes. In the following description, numerous details are set forth for purposes of explanation. However, those skilled in the art will recognize that the disclosed technology can be implemented without these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the presently disclosed technology.

[0026] Some of the techniques described herein can be implemented as software instructions stored on a computer-readable medium, as software instructions executed on a computer, or as some combination of the two. For example, some of the disclosed techniques can be implemented as part of an electronic design automation (EDA) tool. This method can be performed on a single computer or on a network of computers.

[0027] Although the operations of the disclosed methods are described in a particular order for ease of presentation, it should be understood that unless the specific language set forth below requires a particular order, this description includes rearrangement. For example, in some cases, the operations described sequentially can be rearranged or performed simultaneously. In addition, for the sake of simplicity, the disclosed flowcharts and block diagrams generally do not show the various ways in which a particular method can be used in conjunction with other methods. In addition, the detailed description sometimes uses terms such as "perform," "derive," and "determine" to describe the disclosed methods. These terms are high-level abstractions of the actual operations performed. The actual operations corresponding to these terms will vary depending on the specific implementation, and those of ordinary skill in the art will readily recognize these actual operations.

[0028] Furthermore, as used herein, the term "design" is intended to encompass data that describes an entire integrated circuit device. The term is also intended to encompass smaller sets of data that describe one or more components of the entire device (however, for example, a portion of an integrated circuit device). Furthermore, the term "design" is also intended to encompass data that describes more than one microdevice, such as data used to form multiple microdevices on a single wafer.

[0029] Illustrative operating environment

[0030] The execution of various electronic design automation processes according to embodiments of the disclosed technology can be implemented using computer-executable software instructions executed by one or more programmable computing devices. Because these embodiments of the disclosed technology can be implemented using software instructions, the components and operation of a general-purpose programmable computer system on which various embodiments of the disclosed technology can be employed will first be described. In addition, due to the complexity of some electronic design automation processes and the large size of many circuit designs, various electronic design automation tools are configured to operate on computing systems capable of running multiple processing threads simultaneously. Therefore, reference will be made to Figure 1 The components and operations of a computer network having a host or master computer and one or more remote or slave computers are described. However, this operating environment is only one example of a suitable operating environment and is not intended to suggest any limitation on the scope of use or functionality of the disclosed technology.

[0031] exist Figure 1 , computer network 101 includes a host computer 103. In the example shown, host computer 103 is a multiprocessor computer that includes multiple input and output devices 105 and memory 107. Input and output devices 105 may include any device for receiving input data from a user or providing output data to a user. Input devices may include, for example, a keyboard, microphone, scanner, or pointing device for receiving input from a user. Output devices may then include a display monitor, speakers, printer, or tactile feedback device. These devices and their connections are known in the art and will not be discussed in detail here.

[0032] Memory 107 may similarly be implemented using any combination of computer-readable media accessible by host computer 103. Computer-readable media may include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVDs), or other optical storage devices. Computer-readable media may also include magnetic cassettes, magnetic tape, disks or other magnetic storage devices, perforated media, holographic storage devices, or any other medium that can be used to store the desired information.

[0033] As will be discussed in detail below, the host computer 103 runs a software application for performing one or more operations according to various examples of the disclosed technology. Accordingly, the memory 107 stores software instructions 109A that, when executed, implement the software application for performing the one or more operations. The memory 107 also stores data 109B for use with the software application. In the illustrated embodiment, the data 109B comprises processed data used by the software application to perform operations, at least some of which may be performed in parallel.

[0034] The host computer 103 also includes a plurality of processor units 111 and an interface device 113. The processor units 111 may be any type of processor device that can be programmed to execute the software instructions 109A, but are typically microprocessor devices. For example, one or more of the processor units 111 may be a commercially available programmable microprocessor, such as (Intel Corporation) or Xeon TM Microprocessor, Advanced Micro Devices (AMD) Athlon TM Microprocessor, or Motorola Microprocessor. Alternatively or additionally, one or more of the processor units 111 may be custom-made processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Interface device 113, processor unit 111, memory 107, and input / output device 105 are connected together via bus 115.

[0035] For some implementations of the disclosed technology, the host computing device 103 may employ one or more processing units 111 having more than one processor core. Figure 2 An example of a multi-core processor unit 111 that can be used with various embodiments of the disclosed technology is shown. As shown in the figure, the processor unit 111 includes multiple processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those of ordinary skill in the art, a computing engine contains logic devices for performing various computing functions (e.g., obtaining software instructions) and then executing the actions specified in the obtained instructions. These actions can include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR, and XOR, and retrieving data. Each computing engine 203 can then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0036] Each processor core 201 is connected to an interconnect 207. The specific structure of the interconnect 207 may vary depending on the architecture of the processor unit 111. For some processor cores 201, such as the unit microprocessors created by Sony, Toshiba, and IBM, the interconnect 207 may be implemented as an interconnect bus. However, for other processor units 111, such as the Opteron microprocessors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as an interconnect bus. TM and AthlonTM For dual-core processors, interconnect 207 may be implemented as a system request interface device. In any case, processor core 201 communicates with input / output interface 209 and memory controller 210 via interconnect 207. Input / output interface 209 provides a communication interface between processor unit 111 and bus 115. Similarly, memory controller 210 controls the exchange of information between processor unit 111 and system memory 107. For some embodiments of the disclosed technology, processor unit 111 may include additional components, such as a high-level cache memory that is accessible to all processor cores 201.

[0037] Although Figure 2 A diagram of a processor unit 111 that may be employed by some embodiments of the disclosed technology is shown, but it should be understood that the diagram is representative only and not limiting. Furthermore, for some embodiments, a multi-core processor unit 111 may be used in place of multiple individual processor units 111. For example, instead of employing six individual processor units 111, alternative embodiments of the disclosed technology may employ a single processor unit 111 with six cores, two multi-core processor units with three cores each, a multi-core processor unit 111 with four cores, two individual single-core processor units 111, and so on.

[0038] Now back Figure 1 , the interface device 113 allows the master computer 103 to communicate with the slave computers 117A, 117B, 117C ... 117x through a communication interface. The communication interface can be any suitable type of interface, including, for example, a conventional wired network connection or a wired network connection for optical transmission. The communication interface can also be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. The interface device 113 converts data and control signals from the master computer 103 and each slave computer 117 into network messages according to one or more communication protocols (such as the Transmission Control Protocol (TCP), the User Datagram Protocol (UDP), and the Internet Protocol (IP)). These and other conventional communication protocols are well known in the art and are therefore not discussed in detail herein.

[0039] Each slave computer 117 may include a memory 119, a processor unit 121, an interface device 123, and optionally one or more input / output devices 125, connected together via a system bus 127. As with the master computer 103, the optional input / output devices 125 for the slave computers 117 may include any conventional input or output devices, such as a keyboard, pointing device, microphone, display monitor, speakers, and printer. Similarly, the processor unit 121 may be any type of conventional or custom-made programmable processor device. For example, one or more of the processor units 121 may be a commercially available programmable microprocessor, such as a of or Xeon TM Microprocessor, Advanced MicroDevices Athlon TM Microprocessor, or Motorola Alternatively, one or more of the processor units 121 may be custom-made processors, such as microprocessors designed to optimally perform specific types of mathematical operations. In addition, one or more of the processor units 121 may have more than one core, as described above with reference to FIG. Figure 2 As described above. For example, for some embodiments of the disclosed technology, one or more of the processor units 121 can be a cell processor. The memory 119 can then be implemented using any combination of the computer-readable media discussed above. Similar to the interface device 113, the interface device 123 allows the slave computer 117 to communicate with the master computer 103 via a communication interface.

[0040] In the example shown, the master computer 103 is a multi-processor unit computer having multiple processor units 111, while each of the slave computers 117 has a single processor unit 121. However, it should be noted that alternative implementations of the disclosed technology may employ a master computer having a single processor unit 111. Furthermore, one or more of the slave computers 117 may have multiple processor units 121, depending on their intended use, as previously discussed. Furthermore, while only a single interface device 113 or 123 is shown for both the master computer 103 and the slave computers, it should be noted that for alternative implementations of the disclosed technology, the computer 103, one or more of the slave computers 117, or some combination thereof may use two or more different interface devices 113 or 123 to communicate over multiple communication interfaces.

[0041] For various examples of the disclosed technology, the master computer 103 can be connected to one or more external data storage devices. These external data storage devices can be implemented using any combination of computer-readable media that can be accessed by the master computer 103. Computer-readable media can include, for example, microcircuit memory devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVDs), or other optical storage devices. Computer-readable media can also include magnetic cassettes, magnetic tapes, disks or other magnetic storage devices, perforated media, holographic storage devices, or any other media that can be used to store the required information. According to some embodiments of the disclosed technology, one or more of the slave computers 117 can be alternatively or additionally connected to one or more external data storage devices. Typically, these external data storage devices will include data storage devices that are also connected to the master computer 103, but they can also be different from any data storage devices accessible to the master computer 103.

[0042] It should also be understood that Figure 1 and Figure 2 The description of the computer network shown in is provided by way of example only and is not intended to suggest any limitation as to the scope of use or functionality of alternative embodiments of the disclosed technology.

[0043] Circuit Design Flow and Optical Proximity Correction

[0044] Electronic circuits, such as integrated microcircuits, are used in a wide variety of products, from automobiles to microwaves to personal computers. Designing and manufacturing integrated circuit devices typically involves many steps, sometimes referred to as the "design flow." The specific steps in the design flow often depend on the type of integrated circuit, its complexity, the design team, and the integrated circuit manufacturer or foundry that will manufacture the microcircuit. Software and hardware "tools" typically verify the design at various stages of the design flow by running software simulators and / or hardware emulators. These steps help identify errors in the design and allow designers and engineers to correct or improve it.

[0045] For most design flows, several steps are common. Initially, the specification for the new circuit is converted into a logic design, sometimes called a register transfer level (RTL) description of the circuit. Using this logic design, the circuit is described in terms of the exchange of signals between hardware registers and the logical operations performed on those signals. The logic design is typically written in a hardware design language (HDL), such as Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed to confirm that the logic will accurately perform the functions required of the circuit. This analysis is sometimes called "functional verification."

[0046] After the accuracy of the logic design is confirmed, the logic design is converted into a device design by synthesis software. The device design, usually in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors and capacitors) and their interconnections that will be used in the circuit. The device design generally corresponds to the level of representation shown in a conventional circuit diagram. The relationship between the electronic devices is then analyzed to confirm that the circuit described by the device design will correctly perform the required function. This analysis is sometimes referred to as "formal verification". Additionally, at this stage, preliminary timing estimates are usually made for parts of the circuit using the assumed characteristic speed for each device and incorporated into the verification process.

[0047] Once the components and their interconnections are established, the design is converted again, this time into a physical design that describes specific geometric elements. This type of design is often referred to as a "layout" design. The geometric elements, typically polygons, define the shapes that will be created in the various material layers to make the circuit. Typically, automated placement and routing tools will be used to define the physical layout, in particular, to define the wires that will be used to interconnect the circuit devices. In the layout design, each layer of the microcircuit will have a corresponding layer representation, and the geometric shapes described in the layer representation will define the relative positions of the circuit elements that make up the circuit devices. For example, the shape in the layer representation of the metal layer will define the position of the metal wires used to connect the circuit devices. Custom layout editors such as Mentor Graphics' IC Station or Cadence's Virtuoso allow designers to customize the design layout, which is mainly used for analog, mixed-signal, RF, and standard cell designs.

[0048] Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transmitting and archiving two-dimensional graphical IC layout data. Among other features, it contains a hierarchy of structures, each of which contains layout elements (e.g., polygons, paths or polylines, circles, and text boxes). Other formats include an open source format called Open Access, Milkyway provided by Synopsys, Inc., EDDM provided by Mentor Graphics, and the Open Artwork System Interchange Standard (OASIS) recently proposed by Semiconductor Devices and Materials International (SEMI). These various industry formats are used to define geometric information in IC layout designs, which are used to manufacture integrated circuits. Once a microcircuit device design is completed, the layout portion of the design can be used by manufacturing tools to manufacture the device using a photolithography process.

[0049] Typically, designers will perform multiple verification processes on their layout designs. For example, the layout design can be analyzed to confirm that it accurately represents the circuit components and their relationships as described in the device design. In this process, LVS (Layout Versus Schematic) tools extract a netlist from the layout design and compare it to a netlist taken from the circuit schematic. LVS can be enhanced with formal equivalence checking, which verifies that two circuits perform exactly the same function without requiring isomorphism.

[0050] The layout design can also be analyzed to confirm that it meets various design requirements, such as the minimum spacing between geometric elements and the minimum line width of geometric elements. In this process, the DRC (design rule checking) tool takes as input a layout in the GDSII standard format and a list of rules specific to the semiconductor process selected for manufacturing. A set of rules for a particular process is called a run group, a rule set (deck), or just a set. An example of a rule set format is Mentor Graphics' Standard Verification Rule Format (SVRF).

[0051] There are many different manufacturing processes for making circuits, but most processes involve a series of steps that deposit different material layers on a substrate, expose specific portions of each layer to radiation, and then etch away the exposed (or non-exposed) portions of the layer. For example, a simple semiconductor device component can be made by the following steps. First, a positive epitaxial layer is grown on a silicon substrate by chemical vapor deposition. Next, a nitride layer is deposited on the epitaxial layer. Specific areas of the nitride layer are then exposed to radiation, and the exposed areas are etched away to leave exposed areas on the epitaxial layer (i.e., areas no longer covered by the nitride layer). The exposed areas are then subjected to a diffusion or ion implantation process that introduces dopants (e.g., phosphorus) into the exposed epitaxial layer and forms charged wells. This process of depositing material layers on a substrate or subsequent material layers, then exposing specific patterns to radiation, etching, and dopants or other diffused materials is repeated multiple times, allowing for the manufacture of different physical layers of a circuit.

[0052] Each time a material layer is exposed to radiation, a mask must be created to expose only the desired areas to the radiation and protect other areas from exposure. The mask is created based on the circuit layout data. That is, the geometric elements described in the design layout define the relative positions or areas of the circuit that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based on the design layout, after which the mask can be used in the photolithography process.

[0053] As previously discussed, one or more resolution enhancement techniques (RETs) are often used to improve the resolution of the image formed by the mask on the substrate during the lithography process. One of these techniques is optical proximity correction (OPC). OPC can be rule-based, model-based, or both. In rule-based OPC, proximity effects are characterized and specific solutions are designed for specific geometric configurations. DRC tools or geometry-based software engines are then used to search the layout design to find these geometric configurations. Once the geometric configuration is found, a specific solution is applied.

[0054] Rule-based OPC methods are suitable for simple situations. However, for complex layout features, model-based OPC methods must be used to achieve the desired results. Model-based OPC performs simulations to predict the printed image, thereby guiding layout modifications. In a typical model-based OPC process, polygons in the layout design are divided into edge segments to allow for the desired fine-scale movement of the edge segments. Figures 3A-3D An example is shown. Figure 3A The edge 301 of the layout feature 300 in FIG. Figure 3BEdge segments 301A-301F are shown. In a given layout design, the size of the edge segments and which specific edges will be segmented depends on the OPC process parameters, often referred to as the OPC recipe. Although not all edges in a layout design are segmented in every OPC process, these edges can also be referred to as edge segments. Simulations are performed to obtain Figure 3A The predicted printed image 302 of the layout feature 300 shown in FIG. This simulated image is compared with the target image. Typically, this comparison is performed on each edge segment. For example, Figure 3C As shown, the target image is at a distance d1 from the simulated image at edge segment 301A, the target image is at a distance d2 from the simulated image at edge segment 301C, and the target image intersects the simulated image at edge segment 301B. The distance between the target image and the simulated image is generally referred to as the edge placement error (EPE).

[0055] Next, the edge segments are moved or adjusted respectively so that the simulated image of the resulting mask can reproduce the target image as closely as possible. Figure 3D As shown, edge segments 301A and 301F are shifted in a direction away from layout feature 300 in an effort to widen corresponding portions of the image to be produced by the resulting mask. Similarly, edge segments 301C and 301D are shifted in a direction toward layout feature 300 in an effort to narrow corresponding portions of the image to be produced by the resulting mask. Next, an image to be produced by the mask using the shifted edge segments is simulated, the new simulated image is compared to the target image, and the edge placement error for each edge segment is calculated.

[0056] This process of moving edge segments, simulating an image that would be produced using the moved edge segments, and comparing the simulated image to the target image can be repeated multiple times. Each cycle of moving edge segments and comparing the new simulated image to the target image is called an iteration of the OPC process. Typically, the edge segments that are moved during a given iteration and the distance that the edge segments are displaced are determined based on the edge placement error. For example, because Figure 3C Where d1 is greater than d2, subsequent iterations of the optical proximity correction process may cause edge segment 301A to move by a greater amount than edge segment 301C.

[0057] The shift value for each edge segment (often referred to as an edge adjustment value or edge displacement value) can be the edge placement error multiplied by a constant factor (feedback factor). Depending on the OPC procedure, this feedback factor can be position-dependent or edge-type-dependent. Methods that consider the correlation between adjacent edge segments, such as those described in U.S. Patents Nos. 8,910,098 and 8,881,070 (incorporated herein by reference), can also be used to derive the shift value (referred to as cross-MEEF (Mask Error Enhancement Factor)-based methods).

[0058] The OPC iteration process continues until the simulated image is sufficiently similar to the target image (e.g., both d1 and d2 are less than a threshold), or until it is determined that the displacement of the edge segment has converged to a position where no further movement of the edge segment will improve the simulated image. Once the final position of the edge segment is determined in the layout design data, such as Figure 3D , a modified mask feature 303 can be created from the corrected layout design data. Figure 3D , the image 304 produced by the modified mask features 303 should correspond more closely to the target image.

[0059] While geometry-based OPC can certainly correct for many proximity effects, it cannot address one: isodensity deviations caused by focus differences. Focus differences become significant when off-axis illumination schemes (one of the three primary resolution enhancement techniques) are optimized to maximize the depth of focus for densely placed features. Sub-resolution assist features (SRAFs) can be inserted into the layout design to provide a similarly dense environment for individual features. SRAFs (sometimes also called "scatter bars") are sub-resolution features that are not intended to be printed. Their size and position must be carefully adjusted so that they do not print within the desired process window. This determines the most important trade-off in SRAF generation and placement: making the assist features as large and dense as possible to create a denser mask pattern, but not so large or dense that they are printed. Just as with edge-adjustment-based OPC methods, there are rule-based and model-based SRAF methods. SRAF insertion is typically performed before or during the edge-adjustment-based OPC process.

[0060] Optical Proximity Correction Tool

[0061] Inverse lithography, sometimes also referred to as extreme OPC, inverse OPC, or pixOPC, has been explored for optical proximity correction. Unlike traditional OPC techniques, an inverse calculation is performed to obtain a mask pattern that will provide the desired wafer image and process window given the target wafer shape and model of the lithography optics. Inverse lithography treats optical proximity correction as a constrained optimization problem over the pixelated mask domain. The constrained optimization problem can be formulated as finding a mask m = m(x, y) that will represent the image intensity I(x, y) along the target profile C of the frame. i The objective function G is minimized, which is the deviation from a threshold constant T. An analytical representation of the objective function gradient can be found, and the Fast Fourier Transform can be used to quickly compute the objective function gradient.

[0062] Because lithography optics are band-limited, patterns derived from inverse lithography are often curved. However, inverse lithography is a relatively computationally rigorous method used to determine the mask shape that will produce the desired on-chip result. Therefore, inverse lithography is often computationally intensive. Using current inverse lithography techniques, the cost of full-chip design can be uneconomical, except for processing small patterns such as hotspot repair and OPC of shapes in memory cells.

[0063] Another potential approach to perform operational control on curved patterns is to approximate the curved boundary lines using short straight line segments. Figure 4 Two curved shapes 410 and 420 are shown in the figure, in which the boundary lines are fragmented. The fragment points on the boundary lines are represented by points in the figure. The straight line segments connecting adjacent points are used to approximate the boundary lines. As can be seen in the figure, the straight line segments associated with the boundary lines with large curvature are significantly shorter than the straight line segments associated with the boundary lines with small curvature (for example, those straight line segments in position 430 are compared with those straight line segments in position 440). This poses a problem for traditional OPC technology because, in the OPC process, the short straight line segments in those positions with large curvature have a strong correlation. Adjusting one short straight line segment will affect the adjustment of many other adjacent straight line segments. This is because when the feature scale is much smaller than the wavelength of light, the optical proximity effect will increase significantly. Strong correlation may lead to undesirable results, such as the spike feature 450 of the modified layout feature of the curved shape 420.

[0064] Silicon photonics features are typically not very small compared to the wavelength of light. Therefore, correlation issues may not be significant. However, using straight line segments (parallel to the x-axis or y-axis of the layout design, or at a 45-degree angle to the x-axis) to approximate curved boundary lines can lead to a different problem: waviness. Figure 5An example of waviness caused by using straight line segments to approximate curved boundary lines is shown. The figure shows target images of two waveguides 510 and 520. The boundary lines for waveguides 510 and 520 are curved to propagate signal-carrying light. A magnified image 530 of a portion of waveguide 510 shows the target boundary line 540 and a simulated boundary line 550 obtained after OPC processing. The apparent waviness of simulated boundary line 550 can be a problem for waveguides.

[0065] Figure 6 An example of an optical proximity correction tool 600 that can be implemented according to various embodiments of the disclosed technology is shown. The optical proximity correction tool 600 can be used to efficiently perform OPC on a full-chip layout design with a curved pattern without introducing ripples or other undesirable features. As shown, the optical proximity correction tool 600 includes a segmentation unit 610, an edge segment smoothing unit 620, a simulation unit 630, and an edge segment adjustment unit 640. Some embodiments of the optical proximity correction tool 600 can cooperate with (or be combined with) one or more of a mask data preparation tool 650, a mask writing tool 660, an input database 605, and an output database 655.

[0066] As will be discussed in more detail below, the optical proximity correction tool 600 can receive a layout design from an input database 605. A segmentation unit 610 can segment the boundary lines of layout features in the layout design into straight line segments, including using some of the straight line segments to represent curved boundary line segments of the layout feature. The optical proximity correction tool 600 can then generate modified layout features based on multiple optical proximity correction iterations. Each of the multiple optical proximity correction iterations includes the following operations performed by an edge segment smoothing unit 620, a simulation unit 630, and an edge segment adjustment unit 640, respectively. The edge segment adjustment unit 640 can calculate edge adjustment values ​​for the straight line segments based on edge placement errors derived from the optical proximity correction iteration immediately preceding the current optical proximity correction iteration. The edge segment adjustment unit 640 can then adjust the positions of the straight line segments based on the determined edge adjustment values. Based on the straight line segments at the adjusted positions, the edge segment smoothing unit 620 can determine smoothed boundary lines of the layout features. The simulation unit 630 can perform a simulation process on the layout features having smoothed boundary lines to determine a simulated image of the layout features. The edge segment adjustment unit 640 can derive an edge adjustment error for the straight line segment based on comparing the simulated image of the layout feature with the target image of the layout feature. The optical proximity correction tool 600 can determine whether to terminate the iteration based on whether the edge adjustment error is within a predetermined range or whether the number of optical proximity correction iterations is equal to a predetermined number.

[0067] After generating the modified layout features, the optical proximity correction tool 600 can store information about the modified layout features in an output database 655. Optionally, the mask writing tool 660 can process the modified layout features to generate mask data for the mask writing tool to make a photomask. The mask writing tool 660 can use the mask data to create a photomask.

[0068] As previously mentioned, various examples of the disclosed technology can be implemented by one or more computing systems (e.g. Figure 1 and Figure 2 Thus, the system can be implemented by using one or more computing systems (e.g. Figure 1 and Figure 2 6. The segmentation unit 610, the edge segment smoothing unit 620, the simulation unit 630, the edge segment adjustment unit 640, and the mask data preparation tool 650 are implemented by executing programmed instructions on one or more processors in a computer system (such as a computing system shown in FIG. 1 ). Accordingly, some other embodiments of the disclosed technology may be implemented by software instructions stored on a non-transitory computer-readable medium for instructing one or more programmable computers / computer systems to perform the functions of one or more of the segmentation unit 610, the edge segment smoothing unit 620, the simulation unit 630, the edge segment adjustment unit 640, and the mask data preparation tool 650. As used herein, a "non-transitory computer-readable medium" refers to a computer-readable medium that can store data for future retrieval without transmitting electromagnetic waves. A non-transitory computer-readable medium may be, for example, a magnetic storage device, an optical storage device, or a solid-state storage device.

[0069] It should also be understood that although Figure 6 The segmentation unit 610, edge segment smoothing unit 620, simulation unit 630, edge segment adjustment unit 640, and mask data preparation tool 650 are shown as separate units, but a single computer (or a single processor within a host computer) or a single computer system can be used to implement some or all of these units, or components of these units, at different times.

[0070] Utilizing various examples of the disclosed technology, the input database 605 and the output database 655 may be implemented using any suitable computer-readable storage device. That is, either of the input database 605 and the output database 655 may be implemented using any combination of computer-readable storage devices, including, for example, microcircuit storage devices such as read-write memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory or (EEPROM) or flash microcircuit devices, CD-ROM disks, digital video disks (DVDs), or other optical storage devices. Computer-readable storage devices may also include magnetic cassettes, magnetic tape, magnetic disks, or other magnetic storage devices, holographic storage devices, or any other non-transitory storage medium that can be used to store the desired information. Although the input database 605 and the output database 655 may be implemented in Figure 6 are shown as separate units, but some or all of these databases may be implemented using a single data storage medium.

[0071] Process for optical proximity correction of free-form shapes

[0072] Figure 7 A flowchart 700 is shown showing a process for optical proximity correction that may be implemented according to various examples of the disclosed technology. Figure 6 The optical proximity correction tool 600 and Figure 7 700 is used to describe a method of optical proximity correction that can be used in accordance with various embodiments of the disclosed technology. However, it should be understood that, in accordance with various embodiments of the disclosed technology, alternative implementations of the optical proximity correction tool can be used to perform the method of optical proximity correction illustrated by flowchart 700. Similarly, the optical proximity correction tool 600 can be used to perform other methods of optical proximity correction in accordance with various embodiments of the disclosed technology.

[0073] In operation 710 of flowchart 700, optical proximity correction tool 400 receives a layout design from input database 705. The layout design derived from the circuit design may be in a GDSII standard format. The layout design may be a layout design for the entire chip or a portion of a full chip layout design. The layout design may include layout features having curved border lines or curved line segments. Figure 8 An example of a portion of a curved layout feature 800 is shown. Layout feature 800 includes two straight boundary segments: one between endpoint 810 and endpoint 820, and another between endpoint 830 and endpoint 840. Layout feature 800 also includes a curved boundary segment between endpoint 820 and endpoint 830.

[0074] In operation 720, the segmentation unit 610 of the optical proximity correction tool 400 segments the boundary lines of the layout features in the layout design into straight line segments. Straight boundary line segments can be divided into straight line segments, while curved boundary line segments are represented by straight line segments. The size of the straight line segments may depend on some factors, such as the minimum feature size of the layout design. The minimum feature size can be the gate length or the M1 (first metal layer) half pitch of the technology node to be used for the layout design. In some embodiments of the disclosed technology, the length of the straight line segment is greater than or equal to one-quarter of the minimum feature size of the layout design.

[0075] For some embodiments of the disclosed technology, the segmentation unit 610 uses only straight line segments parallel to the x-axis or y-axis of the layout design. For some other embodiments of the disclosed technology, the segmentation unit 610 may additionally use straight line segments with angles of 45 degrees and 135 degrees to the x-axis.

[0076] exist Figure 8 In the example of the segmentation results obtained according to various embodiments of the disclosed technology are compared with the segmentation results obtained by using short straight line segments to approximate the curved boundary line (similar to Figure 4 ) are compared. The two methods produce almost identical results for the two straight boundary segments 810-820 and 830-840, because the endpoints almost overlap. However, for the curved boundary segment 820-830, the segmentation performed by the segmentation unit 610 results in 10 straight line segments 851-860, while the other method results in 30 straight line segments. The endpoints of the latter are clustered in the region where the boundary segment has a large curvature.

[0077] Reference is made back to flowchart 700. In operation 730, the optical proximity correction tool 600 generates modified layout features based on the plurality of optical proximity correction iterations. Figure 9 An example of multiple optical proximity correction iterations according to various embodiments of the disclosed technology is shown. In operation 910, the edge segment adjustment unit 640 calculates an edge adjustment value for a straight line segment based on the edge placement error derived from the optical proximity correction iteration immediately before the current optical proximity correction iteration. The edge adjustment value can be obtained by multiplying the edge placement error by a feedback factor. The feedback factor can be a constant. Alternatively, the feedback factor can be represented by a matrix including a cross-MEEF to account for correlation between adjacent straight line segments. In operation 920, the edge segment adjustment unit 640 can then adjust the position of the straight line segment based on the determined edge adjustment value. The new position information of the straight line segment can be stored.

[0078] In operation 930, edge segment smoothing unit 620 determines a smoothed boundary line for the layout feature based on the adjusted position of the straight line segments. Various smoothing techniques can be used. In some embodiments of the disclosed technology, edge segment smoothing unit 620 employs a Gaussian convolution technique. A function representing a stair-step contour formed by straight line segments can be convolved with a Gaussian weighting function. The Gaussian weighting function acts like a spatial filter, replacing the stair-step contour with a smoothed curve. The parameters of the Gaussian weighting function can be selected by the user. Figure 10A An example of the smoothing result of layout feature 1000 obtained by Gaussian convolution during OPC iteration is shown. In the figure, line 1005 represents the boundary line of the target image of layout feature 1000; line 1010 represents the straight line segment obtained by segmenting the boundary line of layout feature 1000; and line 1020 is the smoothed line obtained by applying the Gaussian convolution technique to line 1010. In addition to Gaussian convolution, techniques based on moving average, spline, Bezier curve, least squares filtering, local regression, or other curve fitting / filtering methods can also be used.

[0079] In operation 940, the simulation unit 630 then performs a simulation process on the layout feature having the smooth boundary line to determine a simulated image of the layout feature. The simulation can be based on an optical model and a photoresist model of the lithography system. Other models, such as an etching model, can also be used. One or more of the simulation unit 630, the segmentation unit 610, and the edge segment adjustment unit 640 can be implemented based on an engine in a commercial OPC tool, such as an engine in the Calibre series of software tools available from Mentor Graphics Corporation of Wilsonville, Oregon. Figure 10A , line 1030 is a boundary line of a simulated image of feature 1000 derived based on smoothed line 1020 as a boundary line of layout feature 1000 .

[0080] In operation 950, the edge segment adjustment unit 640 derives edge adjustment errors of the straight line segments based on comparing the simulated image of the layout feature with the target image of the layout feature. Figure 10A In FIG. 1 , line 1030 can be compared with line 1005 to obtain the edge adjustment error of each straight line segment on line 1010 .

[0081] In operation 960, the optical proximity correction tool 600 may determine whether to terminate the iteration based on whether the edge adjustment error is within a predetermined range or whether the number of optical proximity correction iterations is equal to a predetermined number. If the answer to both questions is no, the optical proximity correction tool 600 may start the next iteration. If the answer to either question is yes, the optical proximity correction tool 600 may exit the iteration and store information about the modified layout features in the output database 655. This information may include information about the smoothed boundary lines of the modified layout features. Figure 10B An example of a modified layout feature for mask preparation obtained by performing an OPC process on a layout feature 1000 according to various examples of the disclosed technology is shown. The figure shows a line 1005 of a target image for the layout feature 1000, a final smoothed line 1025 for the layout feature 1000, and a line 1035 of a simulated wafer image for the layout feature 1000 calculated based on the final smoothed line 1025, where the final smoothed line 1025 is derived from multiple OPC iterations and can be used as a basis for mask writing. As can be seen, the line 1035 is not only very close to the target line 1005, but also has no ripples or other undesirable features, such as Figure 4 Feature 450. In addition, Figure 9 The OPC iterations represented by the flowchart in do not include operations that are as computationally intensive as the inverse lithography process.

[0082] The optical proximity correction tool 600 can also determine processing window information for layout features that have been modified after multiple optical proximity correction iterations. The simulated image obtained in operation 940 is typically an image simulated under nominal conditions. The processing window information can be obtained by performing simulations under conditions that deviate from the nominal conditions. The optical proximity correction tool 600 can use the processing window information to find hot spots, i.e., layout patterns that may cause printability problems during the lithography process. Pinching-type hot spots may cause open circuits or pinch-off defects, and bridging-type hot spots may cause bridging defects. The optical proximity correction tool 600 can perform repair operations to repair some or all of the hot spots.

[0083] Referring back to flowchart 700. In operation 740, the mask data preparation tool 650 may optionally process the modified layout features to generate mask data for a mask writing tool to make a photomask. The mask writing tool may be raster scan based - an electron beam or laser beam is continuously scanned in a predetermined pattern. In this approach, the mask data preparation tool 650 converts the layout data into a primitive shape, which is sometimes referred to as mask data fracturing. Alternatively, the mask writing tool may use a variable shape beam - a larger beam is shaped into the primitive shape by an aperture, and the image of the aperture is projected at multiple suitable locations in the form of separate "flashes of light". For this approach, the mask data preparation tool 650 fracturs the layout design into multiple exposure areas (shots) of acceptable size and appropriate stage motion instructions to create the pattern. In addition, the mask data preparation tool 650 may perform mask process correction. While photomask features are typically fabricated on a 4x scale-down system, so that the feature size is 4x larger than on the wafer, the SRAF and other significantly smaller OPC jogs and structures still need to be accurately fabricated. Mask process correction attempts to correct for charged particle proximity effects.

[0084] In operation 750, the mask writing tool 660 creates a photomask using the mask data. The photomask can be used to manufacture chips through photolithography.

[0085] in conclusion

[0086] While the disclosed technology has been described with respect to specific examples, including presently preferred modes of implementing the disclosed technology, those skilled in the art will appreciate that many variations and permutations of the above-described systems and technologies fall within the spirit and scope of the disclosed technology as set forth in the appended claims. For example, while specific terminology has been used above to refer to electronic design automation processes, it should be understood that the various examples of the disclosed technology can be implemented using any desired combination of electronic design automation processes.

Claims

1. A method for optical proximity correction of free-form shapes, performed by at least one processor of a computer, comprising: Segmenting a boundary line of a layout feature in a layout design into straight line segments, the segmenting comprising using some of the straight line segments to represent curved boundary line segments of the layout feature; as well as Generating modified layout features based on a plurality of optical proximity correction iterations, each of the plurality of optical proximity correction iterations comprising: calculating an edge adjustment value for the line segment based on an edge placement error derived from an optical proximity correction iteration immediately preceding each of the plurality of optical proximity correction iterations, adjusting the position of the straight line segment based on the determined edge adjustment value, determining a smooth boundary line of the layout feature based on the straight line segment at the adjusted position, performing a simulation process on the layout feature having the smooth boundary line to determine a simulated image of the layout feature, and An edge adjustment error of the straight line segment is derived based on comparing the simulated image of the layout feature with a target image of the layout feature.

2. The method according to claim 1, further comprising: The modified layout features are processed to generate mask data for a mask writing tool to fabricate a photomask.

3. The method according to claim 2, further comprising: The mask data is applied to the mask writing tool to create a photomask.

4. The method according to claim 1, wherein Determining the smooth boundary line is based on the Gaussian convolution technique.

5. The method according to claim 1, wherein The length of the straight line segment is greater than or equal to one quarter of the minimum feature size of the layout design.

6. The method according to claim 1, wherein Each of the straight line segments is parallel to the x-axis or the y-axis of the layout design.

7. The method according to claim 1, wherein Calculating the edge adjustment value includes multiplying the edge placement error by a matrix including a cross-mask error enhancement factor.

8. The method according to claim 1, wherein When the edge adjustment error is within a predetermined range or the number of the plurality of optical proximity correction iterations is equal to a predetermined number, the plurality of optical proximity correction iterations are terminated.

9. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method comprising: Segmenting a boundary line of a layout feature in a layout design into straight line segments, the segmenting comprising using some of the straight line segments to represent curved boundary line segments of the layout feature; as well as Generating modified layout features based on a plurality of optical proximity correction iterations, each of the plurality of optical proximity correction iterations comprising: calculating an edge adjustment value for the line segment based on an edge placement error derived from an optical proximity correction iteration immediately preceding each of the plurality of optical proximity correction iterations, adjusting the position of the straight line segment based on the determined edge adjustment value, determining a smooth boundary line of the layout feature based on the straight line segment at the adjusted position, performing a simulation process on the layout feature having the smooth boundary line to determine a simulated image of the layout feature, and An edge adjustment error of the straight line segment is derived based on comparing the simulated image of the layout feature with a target image of the layout feature.

10. The one or more non-transitory computer-readable media of claim 9, wherein: The method also includes processing the modified layout features to generate mask data for a mask writing tool to fabricate a photomask.

11. The one or more non-transitory computer-readable media of claim 10, wherein: The method also includes applying the mask data to the mask writing tool to create a photomask.

12. The one or more non-transitory computer-readable media of claim 9, wherein: Determining the smooth boundary line is based on the Gaussian convolution technique.

13. The one or more non-transitory computer-readable media of claim 9, wherein: The length of the straight line segment is greater than or equal to one quarter of the minimum feature size of the layout design.

14. The one or more non-transitory computer-readable media of claim 9, wherein: Each of the straight line segments is parallel to the x-axis or the y-axis of the layout design.

15. The one or more non-transitory computer-readable media of claim 9, wherein: When the edge adjustment error is within a predetermined range or the number of the plurality of optical proximity correction iterations is equal to a predetermined number, the plurality of optical proximity correction iterations are terminated.

16. A system for free-form optical proximity correction, comprising: One or more processors programmed to perform a method comprising: Segmenting a boundary line of a layout feature in a layout design into straight line segments, the segmenting comprising using some of the straight line segments to represent curved boundary line segments of the layout feature; and Generating modified layout features based on a plurality of optical proximity correction iterations, each of the plurality of optical proximity correction iterations comprising: calculating an edge adjustment value for the line segment based on an edge placement error derived from an optical proximity correction iteration immediately preceding each of the plurality of optical proximity correction iterations, adjusting the position of the straight line segment based on the determined edge adjustment value, determining a smooth boundary line of the layout feature based on the straight line segment at the adjusted position, performing a simulation process on the layout feature having the smooth boundary line to determine a simulated image of the layout feature, and An edge adjustment error of the straight line segment is derived based on comparing the simulated image of the layout feature with a target image of the layout feature.

17. The system according to claim 16, wherein: The method also includes processing the modified layout features to generate mask data for a mask writing tool to fabricate a photomask.

18. The system according to claim 16, wherein: Determining the smooth boundary line is based on the Gaussian convolution technique.

19. The system according to claim 16, wherein: The length of the straight line segment is greater than or equal to one quarter of the minimum feature size of the layout design.

20. The system of claim 16, wherein: Each of the straight line segments is parallel to the x-axis or the y-axis of the layout design.

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