Monise device synapse element biasing scheme

Abstract

A neuromorphic synapse array comprising: a plurality of synapse array cells connected by circuitry such that the synapse array cells are assigned to rows and columns of the array, the synapse array cells each having a unipolar synapse weight, the rows each connected to a respective input of the synapse array cells, the columns each connected to a respective output of the synapse array cells, the synapse array cells arranged in columns of the array defined as operating column arrays; and a current mirror array, each current mirror exhibiting a mirror ratio of N:1, where N is the number of columns of the synapse array cells, each connected to a respective row such that the weights corresponding to all the current mirrors are set to the average weight of all the synapse array cells updated during a learning phase.

Description

BACKGROUND

[0001] The present invention relates generally to neuromorphic and synaptronic computing, and more specifically, to a biasing scheme for single-device synapse elements.

[0002] Neuromorphic and synaptronic computing, also known as artificial neural networks, are computing systems that allow electronic systems to function in a manner substantially similar to the biological brain. Neuromorphic and synaptronic computing generally does not utilize the traditional digital model of manipulating 0s and Is. Instead, neuromorphic and synaptronic computing creates connections between processing elements that are functionally equivalent to neurons of the biological brain. Neuromorphic and synaptronic computing can include various electronic circuits modeled on biological neurons.

[0003] In biological systems, the point of contact between the axon of a neuron and the dendrite on another neuron is called a synapse, and for a synapse, the two neurons are called presynaptic and postsynaptic, respectively. The essence of individual experience is stored in the conductance of the synapse. The synapse conductance changes over time according to the relative spike times of the presynaptic and postsynaptic neurons, as per spike-timing dependent plasticity (STDP).

[0004] Deep neural networks (DNNs) are a family of neuromorphic computing architectures that have made substantial progress on difficult machine learning problems such as image or object recognition, speech recognition, and machine language translation. The computation of DNNs includes training and forward inference, during which the weights of the network are optimized on a training dataset, and during which the network has learned is leveraged to classify, predict, or other useful tasks on new, previously unseen test data. These networks are well suited for computation via large and dense matrix-matrix multiplications that can be highly parallelized.

[0005] Conventional von Neumann hardware is constrained by the time and energy spent moving data back and forth between memory and processor ("von Neumann bottleneck"). In contrast, in a non-von Neumann scheme, computation is performed at the data location, with the strength of the synapse connection (weight) stored and adjusted directly in memory. However, for efficient on-chip training, it would be preferable to replace digital synapse weights stored in static random access memory arrays with high-density analog devices that directly encode the synapse weights in their conductance. Such an analog system can enable significant speedup and power reduction for both forward inference and training. Desirable properties for the analog devices used for training include fast, low-power programming of multiple analog levels, size scalability, reasonable retention, high durability, and most importantly, gradual and symmetric conductance update characteristics.

[0006] To date, experimental demonstrations of DNN training based on analog memory suffer from reduced classification accuracy due to substantial non-idealities exhibited by existing devices. These demonstrations have featured characterized filamentary resistive RAM (RRAM), non-filamentary resistive RAM, phase change memory (PCM), conductive-bridge RAM (CBRAM), ferroelectric RAM, and hybrid digital non-volatile memory (NVM) architectures. Thus, new means are needed to use synaptic weights as single devices. SUMMARY

[0007] According to one embodiment, there is provided a neuromorphic synapse array. The neuromorphic synapse array comprises a plurality of synapse array cells connected by circuitry such that the synapse array cells are assigned to rows and columns of the array, the synapse array cells each having unipolar synaptic weights, the rows are each connected to respective input terminals of the synapse array cells, the columns are each connected to respective output terminals of the synapse array cells, the synapse array cells arranged in columns of the array are defined as an operational column array, and a current mirror array, each current mirror exhibiting a mirror ratio of N: 1, where N is the number of columns of the synapse array cells, are each connected to respective rows such that the weights corresponding to all of the current mirrors are set to an average weight of all of the synapse array cells updated during a learning phase.

[0008] According to another embodiment, there is provided a computer-implemented method. The computer-implemented method comprises connecting, by circuitry, a plurality of synapse array cells such that the synapse array cells are assigned to rows and columns of the array, the synapse array cells each having unipolar synaptic weights, the rows are each connected to respective input terminals of the synapse array cells, the columns are each connected to respective output terminals of the synapse array cells, the synapse array cells arranged in columns of the array are defined as an operational column array, and connecting a current mirror array to the array, each current mirror exhibiting a mirror ratio of N: 1, where N is the number of columns of the synapse array cells, are each connected to respective rows such that the weights corresponding to all of the current mirrors are set to an average weight of all of the synapse array cells updated during a learning phase.

[0009] According to yet another embodiment, a neuromorphic synaptronic array is provided. The neuromorphic synaptronic array comprises: a plurality of synaptronic array cells connected by circuitry such that the synaptronic array cells are assigned to rows and columns of an array, the synaptronic array cells each having unipolar synaptronic weights, the rows each connected to a respective input of the synaptronic array cells, the columns each connected to a respective output of the synaptronic array cells, the synaptronic array cells arranged in columns of the array defined as operational column arrays; an array of current mirrors, each current mirror exhibiting a mirror ratio of N: 1, where N is a number of columns of the synaptronic array cells, each connected to a respective row such that weights corresponding to all of the current mirrors are set to an average weight of all of the synaptronic array cells updated during a learning phase; and an array of current integrators, each connected to a respective column of the array, and each comprising an integration capacitor to receive a collected mirror current, replicate the collected mirror current, and discharge the collected mirror current.

[0010] According to yet another embodiment, a computer-implemented method is provided. The computer-implemented method comprises: connecting a plurality of synaptronic array cells by circuitry such that the synaptronic array cells are assigned to rows and columns of an array, the synaptronic array cells each having unipolar synaptronic weights, the rows each connected to a respective input of the synaptronic array cells, the columns each connected to a respective output of the synaptronic array cells, the synaptronic array cells arranged in columns of the array defined as operational column arrays; connecting an array of current mirrors to the array, each current mirror exhibiting a mirror ratio of N: 1, where N is a number of columns of the synaptronic array cells, each connected to a respective row such that weights corresponding to all of the current mirrors are set to an average weight of all of the synaptronic array cells updated during a learning phase; and connecting an array of current integrators to the array, each connected to a respective column of the array, and each comprising an integration capacitor to receive a collected mirror current, replicate the collected mirror current, and discharge the collected mirror current.

[0011] According to yet another embodiment, a neuromorphic synapse array is provided. The neuromorphic synapse array comprises: a plurality of electrically connected synapse array cells such that the synapse array cells are assigned to rows and columns of the array, the synapse array cells each having a unipolar synapse weight; a current mirror array, each current mirror exhibiting an N: 1 mirror ratio, where N is a number of columns of the synapse array cells, connected to a respective row such that weights corresponding to all of the current mirrors are set to an average weight of all of the synapse array cells updated during a learning phase; and a current integrator array, each current integrator connected to a respective column of the array, and each current integrator comprising an integration capacitor for receiving a collected mirror current, replicating the collected mirror current, and discharging the collected mirror current to accelerate multiply-accumulate (MAC) operations in an artificial neural network accelerator chip.

[0012] In a preferred aspect, at least a portion of the plurality of synapse array cells comprises a resistive memory.

[0013] In another preferred aspect, at least a portion of the plurality of synapse array cells comprises a current integrator.

[0014] In another preferred aspect, the current mirror array comprises different current mirror configurations for one or more rows of the array.

[0015] In yet another preferred aspect, one current mirror configuration comprises two n-type field effect transistors (NFETs).

[0016] In yet another preferred aspect, one current mirror configuration comprises two p-type field effect transistors (PFETs) and a single NFET.

[0017] In yet another preferred aspect, one current mirror configuration comprises two NFETs and a single operational amplifier (op-amp).

[0018] In yet another preferred aspect, one current mirror configuration comprises two PFETs, a single NFET, and two operational amplifiers.

[0019] In yet another preferred aspect, the current integrator comprises different configurations for one or more rows of the array.

[0020] In yet another preferred aspect, one current integrator configuration comprises two PFETs, a single NFET, and an integrated capacitor.

[0021] In yet another preferred aspect, one current integrator configuration comprises two PFETs, a single NFET, an operational amplifier, and an integration capacitor.

[0022] In yet another preferred aspect, the integration capacitor receives the collected mirror current, replicates the collected mirror current, and discharges the collected mirror current.

[0023] In yet another preferred aspect, the neuromorphic synapse array accelerates multiply-accumulate (MAC) operations in an artificial neural network accelerator chip.

[0024] Advantages of the present invention include removing processing time overhead for programming the synapse cells, such that "read", "write", and "average" operations are not necessary. Further advantages include reducing the circuit layout area for each operation. Another advantage includes reducing the energy consumption per operation. In addition, another advantage includes reducing or eliminating read quantization error, average calculation error, and write quantization error. This results in higher storage capacity, faster processing, and better data transfer speed. Further advantages include higher quality, reduced cost, clearer range, faster performance, fewer application errors, and fewer data errors.

[0025] It should be noted that the example embodiments are described with reference to different subject matters. In particular, some embodiments are described with reference to method type claims whereas other embodiments are described with reference to device type claims. However, a person skilled in the art will gather from the above and the following description that, unless otherwise indicated, any aspect or feature described as pertaining to a particular subject matter can be implemented with a different subject matter, in particular a method type claim with a device type claim or vice versa. Thus, a skilled person will appreciate that an aspect or feature described with reference to one type of subject matter can equally well be implemented with a different type of subject matter.

[0026] These and other features and advantages will be apparent from a reading of the following detailed description of illustrative embodiments of the application, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] The application will be described with reference to the following drawings, in which:

[0028] Figure 1 An exemplary neuron excitation of multiply-accumulate (MAC) operations on inputs from multiple pre-neurons by a synapse of a neuron is shown;

[0029] Figure 2 A synapse array cell including a current mirror in each row, in accordance with an embodiment of the present invention;

[0030] Figure 3 Another embodiment of a synapse array cell including a current mirror in each row, in accordance with an embodiment of the present invention, in which the current mirror includes a combination of transistors;

[0031] Figure 4is another embodiment of a synaptic array cell including a current mirror in each row, wherein the current mirror includes a combination of a transistor and an operational amplifier, according to embodiments of the present application;

[0032] Figure 5 is a block diagram / flowchart of a method to accelerate multiply-accumulate (MAC) operations using a current mirror, according to embodiments of the present application;

[0033] Figure 6 is an exemplary neuromorphic and synaptic electronics network of a crossbar of electronic synapses including interconnected electronic neurons and axons, according to an embodiment of the present application;

[0034] Figure 7 is a block diagram of components of a computing system including a computing device and a neuromorphic chip capable of employing a current mirror to accelerate MAC operations, according to embodiments of the present application;

[0035] Figure 8 is a block diagram / flowchart of an exemplary cloud computing environment, according to embodiments of the present application;

[0036] Figure 9 is a schematic diagram of an exemplary abstraction model layer, according to embodiments of the present application;

[0037] Figure 10 shows a practical application of using a current mirror to accelerate MAC operations, according to embodiments of the present application;

[0038] Figure 11 is a block diagram / flowchart of a method to employ a current mirror to accelerate MAC operations with Internet of Things (IoT) systems / devices / infrastructure, according to embodiments of the present application; and

[0039] Figure 12 is a block diagram / flowchart of an exemplary IoT sensor to collect data / information related to a current mirror for accelerating MAC operations, according to embodiments of the present application.

[0040] In all drawings, like or similar elements are referred to by like or similar reference numerals. DETAILED DESCRIPTION

[0041] Embodiments according to the present application provide methods and apparatus for advantageously moving the accumulated (multiply-accumulate) value in a neuron close to a zero value (where the activation function has the most sensitive region) by employing a current mirror circuit instead of a physical reference cell. Thus, each single apparatus advantageously represents one synaptic weight.

[0042] Recently, deep learning has revolutionized the field of machine learning by providing human-like performance in areas such as computer vision, speech recognition, and complex strategic games. However, current hardware implementations of deep neural networks still fall far short of competing with biological neural systems in terms of real-time information processing capabilities and comparable energy consumption. Most neural networks are implemented on computing systems based on the Von Neumann architecture, which have separate memory and processing units or devices. These devices store information in their resistance / conductance states and exhibit conductance modulation based on programmed history. The core idea behind building devices based on cognitive hardware is to store synaptic weights as their conductance states and perform the relevant computational tasks in situ. Two fundamental synaptic properties that need to be emulated by such devices are synaptic efficacy and plasticity. Synaptic efficacy refers to the generation of synaptic output based on incoming neuronal activation. In contrast, synaptic plasticity is the ability of a synapse to change its weight, typically during the execution of a learning algorithm. Synaptic weights are increased, referred to as potentiation, and decreased, referred to as depression. In ANNs, the weights are typically changed according to a backpropagation algorithm.

[0043] In computing, a multiply-accumulate operation is the task of computing the product of two numbers and adding the product to an accumulator. The hardware unit that performs this operation is called a multiplier-accumulator (MAC, or MAC unit). The operation itself is often referred to as a MAC or MAC operation. MAC techniques using resistive devices such as resistive random access memory (RRAM), phase change memory (PCM), and magnetic random access memory (MRAM) are gaining interest for neural network accelerator chips. Using a pair of positive (G + ) and negative (G - ) resistive devices is a widely used technique for expressing signed synaptic weights. However, previous uses of synaptic weights utilize a single device with a reference cell, rather than a pair of G + and G - resistive devices. Exemplary embodiments of the present invention advantageously employ a current mirror rather than a reference cell to represent synaptic weights. Methods and devices are provided that advantageously mitigate the complex programming (write) process by minimizing or eliminating read quantization error, average computation error, and programming (write) quantization error, according to embodiments of the present invention. Performance overhead and energy consumption are advantageously minimized, and additional layout area for certain circuit blocks can advantageously be removed.

[0044] It should be appreciated that the present application will be described in connection with a given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps / blocks can be varied within the scope of the present application. It should be noted that for clarity's sake, certain features can not be shown in all of the figures. This should not be interpreted as a limitation on the scope or spirit of any particular embodiment or claim.

[0045] Figure 1 An exemplary neuron excitation of a multiply-accumulate operation (MAC) of inputs from multiple pre-synaptic neurons is shown. The multiply-accumulate operation (MAC) can be referred to as a "sum of products". A neuromorphic array utilizes a MAC operation of a biological neuron activation potential model. By adding (sum of products) the multiplication results of the input values and the weights of the synapses connected between the input ports and the neuron, a neuron membrane potential called "neuron action potential" is calculated.

[0046] Figure 2 A synapse array cell including a current mirror in each row according to an embodiment of the present application.

[0047] The synapse array cell 10 includes a bit line 12 and a plurality of word lines 14, and a plurality of return lines 11 for collecting current from each cell element in a row. A first row includes a plurality of resistive memory elements. For purposes of illustration, a first resistive memory 30 and a second resistive memory 32 are depicted. Advantageously, the first row is provided with a current mirror 20. The current mirror 20 is connected in series with the first and second resistive memories 30, 32. An input pulse 16 is applied to the first row resistive memory elements.

[0048] A second row also includes a plurality of resistive memory elements. For purposes of illustration, a first resistive memory 30' and a second resistive memory 32' are depicted for the second row. Advantageously, the second row is provided with a current mirror 22. The current mirror 22 is connected in series with the first and second resistive memories 30', 32'. An input pulse is applied to the second row resistive memory elements. Element 23 is a leg of the current mirror for sensing current. Each current mirror 20, 22 has two legs, one for sensing a reference current and one for replicating the current by amplification, e.g., 1 / N, and in addition, a plurality of pairs of legs 24, 26 are shown at each column N of the array 10, each leg including an integration capacitor 25, 27.

[0049] Current mirrors 20, 22 are circuits designed to replicate the current through one active device by controlling the current in another active device, thereby keeping the output current constant independent of the load. The current being "replicated" can be and sometimes is a varying signal current. In other words, a current mirror is a circuit block that is used to produce a copy of the current flowing into or out of the input terminal by replicating the current in the output terminal. One advantageous feature of a current mirror is a relatively high output resistance, which helps to keep the output current constant independent of the load conditions. Another advantageous feature of a current mirror is a relatively low input resistance, which helps to keep the input current constant independent of the driving conditions.

[0050] Conceptually, an ideal current mirror is simply an ideal negative current amplifier that also reverses the current direction, or it can include a current-controlled current source (CCCS). Current mirrors 20, 22 can be advantageously used to provide bias currents and active loads to circuits. Current mirrors 20, 22 can also be advantageously used to model more practical current sources. There are certain main specifications that characterize a current mirror. One is the transconductance (in the case of a current amplifier) or the output current magnitude (in the case of a constant current source, CCS). Another is its AC output resistance, which determines the degree to which the output current varies with the voltage applied to the current mirror. Yet another specification is the minimum voltage drop across the output part of the current mirror needed for it to function properly. This minimum voltage is dictated by the need to keep the output transistor of the current mirror in the active mode. The voltage range over which the current mirror operates is called the compliance range, and the voltage that marks the boundary between good and bad behavior is called the compliance voltage.

[0051] Figure 3 Another embodiment of a synapse array cell including a current mirror in each row, where the current mirror includes a combination of transistors, in accordance with an embodiment of the present invention.

[0052] The synapse array cell includes a bit line 12 and a plurality of word lines 14, as well as a plurality of return lines 11 for collecting current from each of the cell elements in a row. A first row includes a plurality of resistive memory elements. For purposes of illustration, a first resistive memory 30 and a second resistive memory 32 are depicted. A current mirror 40 is advantageously provided for the first row. The current mirror 40 is connected in series with the first and second resistive memories 30, 32. An input pulse 16 is applied to the resistive memory elements of the first row.

[0053] The current mirror 40 includes two n-type field effect transistors (NFETs) 41, 42.

[0054] A second row includes a plurality of current integrators. For purposes of illustration, a first current integrator 50 and a second integrator 60 are depicted. A current mirror 44 is advantageously provided for the second row. The current mirror 44 is connected in series with the first and second current integrators 50, 60.

[0055] Current mirror 44 includes two p-type field effect transistors (PFETs) 45, 47 and a single NFET 49.

[0056] If input pulse 16 enters the array, current flows from the left leg of element 50 and element 60 through resistive memories 30, 32 to the right leg of element 40. Current is then mirrored into the left leg of element 40 and is amplified by a factor of 1 / N. Advantageously, these behaviors occur in every row and column. The mirrored current is collected in the left-most line and the collected current is sourced from the left leg of element 44. Thereafter, the collected current is also mirrored into the right leg of element 44 and is then advantageously replicated and discharged from the column N integration capacitors 58, 68. As a result, current mirrors 40, 44 are provided with a mirror ratio of N: 1, where N is the number of columns of operation-synapse cells. The mirrored current is advantageously summed together and mirrored to the integration capacitors 58, 68 on each column to shift the MAC result without the need for reference synapse cells.

[0057] Elements 50, 60 are current integrators that include two current mirrors and an integration capacitor. Current integrator 50 includes two PFETs 52, 54 and a single NFET 56, and integration capacitor 58. Similarly, integrator 60 includes two PFETs 62, 64 and a single NFET 66, and integration capacitor 68.

[0058] The NFET current mirror has only one leg. A pair of common sense legs exist in the right leg of element 44. Elements 50, 60 can also be referred to as “neuron circuits.” The voltage on integration capacitors 58, 68 is typically converted to digital bits by an analog-to-digital converter (ADC) so that the connected system can use the output data as digital data.

[0059] Figure 4 is another embodiment of a synapse array cell including a current mirror in each row according to an embodiment of the invention, wherein the current mirror includes a combination of transistors and operational amplifiers.

[0060] The synapse array cell includes bit line 12 and a plurality of word lines 14, and a plurality of return lines 11 for collecting current from each cell element in a row. A first row includes a plurality of resistive memory elements. For purposes of illustration, a first resistive memory 30 and a second resistive memory 32 are depicted. Advantageously, a current mirror 70 is provided for the first row. Current mirror 70 is in series with the first and second resistive memories 30, 32, and input pulse 16 is applied to the first row resistive memory elements.

[0061] Current mirror 70 includes two n-type field effect transistors (NFETs) 71, 72 and an operational amplifier (or op-amp) 73.

[0062] The second row includes multiple current integrators. For purposes of illustration, a first current integrator 80 and a second integrator 86 are depicted. Advantageously, a current mirror 74 is provided for the second row. Current mirror 74 is connected in series with the first and second current integrators 80, 86.

[0063] Current mirror 74 includes two PFETs 75, 76, a single NFET 78, and two operational amplifiers 77, 79.

[0064] If an input pulse 16 enters the array, current flows from element 86 and the left leg of element 80 through resistive memories 30, 32 to the right leg of element 70. The current is then advantageously amplified by 1 / N and mirrored into the left leg of element 70. Advantageously, these behaviors occur in every row and column. The mirrored current is collected in the left-most line and the collected current is sourced from the left leg of element 74. The collected current is then also mirrored into the right leg of element 74, which is then advantageously replicated and discharged from the integrator capacitors 85, 92 of each column N.

[0065] Elements 80, 86 are current integrators that include two current mirrors and one integrator capacitor. Current integrator 80 includes two PFETs 81, 82 and a single NFET 84, as well as integrator capacitor 85. Current integrator 80 also includes operational amplifier 83. Similarly, integrator 86 includes two PFETs 87, 88 and a single NFET 90, as well as integrator capacitor 92. Current integrator 86 also includes operational amplifier 89.

[0066] The NFET current mirror has only one leg. A pair of common sense legs exist in the right leg of element 74. Elements 80, 86 can also be referred to as “neuron circuits.” The voltage on integrator capacitors 85, 92 is typically converted to digital bits by an analog-to-digital converter (ADC) so that the connected system can use the output data as digital data.

[0067] Figures 2-4 Each of the circuit diagrams in FIGS. 1-4 can advantageously be implemented by an artificial intelligence (AI) accelerator chip, as shown below with reference to FIG. 5. Figure 10

[0068] Figure 5 is a block diagram / flowchart of a method of advantageously using current mirrors to accelerate multiply-accumulate (MAC) operations according to embodiments of the present invention.

[0069] ​At block 96, a plurality of synapse array cells are connected by circuitry such that the synapse array cells are assigned to rows and columns of an array, the synapse array cells respectively having unipolar synapse weights, the rows respectively connected to respective inputs of the synapse array cells, the columns respectively connected to respective outputs of the synapse array cells, the synapse array cells arranged in the columns of the array being defined as an operational column array.

[0070] At block 98, a current mirror array is employed, each current mirror exhibiting a mirror ratio of N: 1, where N is the number of columns of synapse cells, respectively connected to respective rows, configured such that the weights corresponding to all mirrored currents are set to the average weight of all synapse cells that are advantageously updated during a learning phase.

[0071] Figure 6 An exemplary neuromorphic and synapticonic network including crossbars of electronic synapses interconnecting electronic neurons and axons according to an embodiment of the present invention.

[0072] According to embodiments of the present invention, an exemplary tile circuit 100 has a crossbar 112. In one example, the entire circuit can include a "hyper-dense crossbar array" that can have a pitch in the range of about 10 nm to 500 nm. However, smaller and larger pitches can also be contemplated by those skilled in the art. The neuromorphic and synapticonic circuit 100 includes a crossbar 112 that interconnects a plurality of digital neurons 111 including neurons 114, 116, 118, and 120. These neurons 111 are also referred to herein as "electronic neurons." For illustrative purposes, the example circuit 100 provides symmetric connections between two pairs of neurons (e.g., N1 and N3). However, embodiments of the present invention can be used for asymmetric connections of neurons as well (neurons N1 and N3 need not be connected with the same connections). The crossbar in the tile accommodates the appropriate ratio of synapses to neurons, and thus need not be square.

[0073] In the example circuit 100, the neurons 111 are connected to the crossbar 112 via dendrite paths / lines (dendrites) 113 such as dendrites 126 and 128. The neurons 111 are also connected to the crossbar 112 via axon paths / lines (axons) 115 such as axons 134 and 136. Neurons 114 and 116 are dendrite neurons, and neurons 118 and 120 are axon neurons connected with axons 113. Specifically, neurons 114 and 116 are shown as having outputs 122 and 124 connected to dendrites (e.g., bit lines) 126 and 128, respectively. Axon neurons 118 and 120 are shown as having outputs 130 and 132 connected to axons (e.g., word lines or access lines) 134 and 136, respectively.

[0074] When any of the neurons 114, 116, 118, and 120 fire, they will send out a pulse to their axonal connections and to their dendritic connections. Each synapse provides contact between the axon of one neuron and the dendrite on another neuron, and the two neurons are referred to as pre- and post-synaptic, respectively, with respect to the synapse.

[0075] Each connection between a dendrite 126, 128 and an axon 134, 136 is made through a digital synapse device 131 (synapse). The junction at which the synapse device is located can be referred to herein as a "crosspoint junction." Typically, in accordance with embodiments of the application, the neurons 114 and 116 will "fire" (send out a pulse) in response to input received from their axonal input connections (not shown) exceeding a threshold value.

[0076] The synapses 131 can include resistive memories 30, 32. The synapses 131 can include current integrators 50, 60 of Figure 3 or current integrators 80, 86 of Figure 4 Any of the types of current mirrors described herein can also be included in the synapses 131. Thus, one of skill in the art can envision Figures 2-4 all of the circuit elements of the synapses 131 of the circuit 100 being advantageously incorporated or embedded.

[0077] The neurons 118 and 120 will "fire" (send out a pulse) in response to input received from their external input connections (not shown), typically from other neurons, exceeding a threshold value. In one embodiment, when the neurons 114 and 116 fire, they maintain a decaying post-synaptic spike-time-dependent plasticity (STDP) (STDP post) variable. For example, in one implementation, the decay period can be 50 μβ (1000 times shorter than the decay period of actual biological systems, equivalent to an operational speed 1000 times higher). STDP is implemented using the STDP post variable by encoding the time since the last firing of the associated neuron. This STDP is used to control long-term potentiation or "potentiation," which is defined herein as increasing the synaptic conductance. When the neurons 118, 120 fire, they maintain a pre-STDP (pre-synaptic STDP) variable that decays in a similar manner to the variable of the neurons 114 and 116.

[0078] For example, the pre-STDP variable and the post-STDP variable can decay according to an exponential, linear, polynomial, or quadratic function. In another embodiment of the invention, the variable can increase over time rather than decrease. In any case, the variable can be used to implement STDP by encoding the time since the last spike from the associated neuron. STDP is used to control long-term depression or "depression," defined herein as a reduction in synaptic conductance. Note that the roles of the pre-STDP variable and the post-STDP variable can be reversed with pre-STDP implementing potentiation and post-STDP implementing depression.

[0079] The external bidirectional communication environment can provide sensory input and consume motor output. Digital neurons 111 implemented using complementary metal-oxide-semiconductor (CMOS) logic gates receive spike inputs and integrate them. In one embodiment, the neurons 111 include comparator circuits that generate spikes when the integrated input exceeds a threshold. In one embodiment, synapses are implemented using flash memory cells, where each neuron 111 can be an excitatory or inhibitory neuron (or both). As described below, each learning rule on each neuron axon and dendrite is reconfigurable. This assumes transposable access to the crossbar memory array. The neurons that select spikes one at a time send spike events to corresponding axons, which can reside on a core or somewhere else in a larger system with many cores.

[0080] The term electronic neuron as used herein refers to an architecture configured to mimic a biological neuron. Electronic neurons create connections between processing elements that are roughly equivalent in function to neurons of a biological brain. Thus, neuromorphic and synaptodrionic systems including electronic neurons according to embodiments of the invention can include various electronic circuits modeled after biological neurons, however in many useful embodiments they can operate on a faster timescale (e.g., 1000X) than their biological counterparts. Furthermore, neuromorphic and synaptodrionic systems including electronic neurons according to embodiments of the invention can include various processing elements modeled after biological neurons, including computer simulations. Although certain illustrative embodiments of the invention are described herein using electronic neurons including electronic circuits, the invention is not limited to electronic circuits. Neuromorphic and synaptodrionic systems according to embodiments of the invention can be implemented as neuromorphic and synaptodrionic architectures including circuits, additionally as computer simulations. Indeed, embodiments of the invention can take the form of a purely hardware embodiment, a purely software embodiment or an embodiment including both hardware and software elements.

[0081] Figure 7is a block diagram of components of a computing system including a computing device and a neuromorphic chip capable of employing unit cells and / or synaptic weights according to embodiments of the present invention.

[0082] Figure 7 A block diagram depicting components of system 200 including computing device 205 is depicted. It should be understood that Figure 7 The example illustration of an implementation is provided for simplicity only and is not intended to suggest any limitation as to the environment in which different embodiments can be implemented. Numerous modifications can be made to the described environment.

[0083] Computing device 205 includes a communication structure 202 that provides for communication between computer processor(s) 204, memory 206, persistent storage 208, communication unit 210, and input / output (I / O) interface(s) 212. Communication structure 202 can be implemented with any architecture designed for the communication of data and / or control information between processors, such as microprocessors, communication and network processors, system memory, peripheral devices, and any other hardware components within a system. For example, communication structure 202 can be implemented with one or more buses.

[0084] Memory 206, cache memory 216, and persistent storage 208 are computer readable storage media. In this embodiment, memory 206 includes random access memory (RAM) 214. In another embodiment, memory 206 can be flash memory. In general, memory 206 can include any suitable volatile or non-volatile computer readable storage media.

[0085] In some embodiments of the present invention, deep learning program 225 is included and operated by neuromorphic chip 222 as a component of computing device 205. In other embodiments, deep learning program 225 is stored in persistent storage 208 for execution by neuromorphic chip 222 in conjunction with one or more of the respective computer processors 204 via one or more memories of memory 206. In this embodiment, persistent storage 208 includes a magnetic hard disk drive. Alternatively, or in addition to the magnetic hard disk drive, persistent storage 208 can also include a solid state hard drive, semiconductor storage, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, or any other computer readable storage media that is capable of storing program instructions or digital information.

[0086] The media used by persistent storage 208 can also be removable. For example, a removable hard drive can be used for persistent storage 208. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive, port or otherwise connected, such as to encompass another computer-readable storage medium of a

[0087] In these examples, communication unit 210 provides communication through the use of either or both physical and wireless communications links. Deep learning program 225 can be downloaded to persistent memory 208 through communication unit 210.

[0088] I / O interface 212 allows for input and output of data with other devices that can be connected to the computing system 200. For example, I / O interface 212 can provide a connection to external devices 218 such as a keyboard, a keypad, a touch screen, and / or some other suitable input device. External devices 218 can also include portable computer readable storage media such as, for example, thumb drives, portable optical or magnetic disks, and memory cards.

[0089] Display 220 provides a mechanism to display data to a user, and can be, for example, a computer monitor.

[0090] Figure 8 is a block diagram / flow diagram of an example cloud computing environment in accordance with an embodiment of the present application.

[0091] It should be understood that, although the present application includes detailed descriptions of cloud computing, implementation of the teachings described herein are not limited to a cloud computing environment. Rather, embodiments of the present application are capable of being implemented in conjunction with any other type of computing environment now known or later developed.

[0092] Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0093] The characteristics are as follows:

[0094] On-demand self-service: cloud consumers can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically without requiring human interaction with the service's provider.

[0095] Broad network access: capabilities are available over the network, and users need not be bound to any specific devices, locations or networks. Users can access the Cloud through a variety of thin or thick client platforms (e.g., mobile phones, laptops, PDAs).

[0096] Resource pooling: the provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to consumer demand. There is a sense of location independence in that the consumer generally has no control or knowledge over the exact location of the provided resources but can be able to specify location at a higher level of abstraction (e.g., country, state, or datacenter).

[0097] Rapid elasticity: capabilities can be provisioned and released in a very short period of time, in order to quickly scale out and rapidly release to quickly scale in. To the consumer, the capabilities available for provisioning appear to be almost unlimited and can be purchased in any quantity at any time.

[0098] Measured service: cloud systems automatically control and optimize resource use by leveraging utilization of resources in an efficient manner, such as in the form of tenancy in an application server, web server or data storage area that are not directly observable by the consumer.

[0099] Service models are as follows:

[0100] Software as a Service (SaaS): the capability provided to the consumer is to use the provider's applications running on a cloud infrastructure. The applications are accessible from various client devices through a thin client interface such as a web browser (e.g., web-based e-mail). The consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0101] Platform as a Service (PaaS): the capability provided to the consumer is to deploy onto the cloud infrastructure consumer-created or acquired applications created using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

[0102] Infrastructure as a Service (laaS): the capability provided to the consumer is to provision processing, storage, networks, and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).

[0103] Deployment models are as follows:

[0104] Private cloud: the cloud infrastructure is operated solely for an organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0105] Community cloud: the cloud infrastructure is shared by several organizations and supports mission-critical enterprise resources. It can be managed by the organizations or a third party and can exist on-premises or off-premises.

[0106] Public cloud: the cloud infrastructure is made available to general public or a large industry group and is owned by an organization selling cloud services.

[0107] Hybrid cloud: the cloud infrastructure is a composition of two or more types of cloud (private, community, or public) that remain unique entities but are bound together, using standard technologies or private technologies to enable data and application portability.

[0108] A cloud computing environment is service-oriented, with a focus on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure of interconnected nodes, including end-points of data transfer.

[0109] Referring now to the drawing Figure 8 , an illustrative cloud computing environment 350 is described for implementing a use case of the present application. As shown, cloud computing environment 350 comprises one or more cloud computing nodes 310 with which a cloud consumer can communicate via a network 360. Although cloud computing nodes 310 are shown with the cloud computing environment 350, it should be understood that other nodes can exist with some of the components illustrated in cloud computing environment 350 (not shown), and each of nodes 310 can be in communication with one another. Figure 8 The types of computing devices 354A-N shown in FIG. 11 are intended to be illustrative only and that computing nodes 310 and cloud computing environment 350 can communicate with any type of computerized devices over any type of network and / or network addressable connection (e.g., using a web browser).

[0110] Figure 9 is a schematic diagram of exemplary abstraction model layers according to an embodiment of the present application. It should be appreciated that Figure 9The components, layers, and functions shown in the middle are intended as examples only; embodiments of the application are not limited to these.

[0111] As depicted, the following layers and corresponding functionality are provided:

[0112] Hardware and software layer 460 includes hardware and software components. Examples of hardware components include: mainframes 461; RISC (Reduced Instruction Set Computer) architecture based servers 462; servers 463; blade servers 464; storage devices 465; and networks and networking components 466. In some embodiments, software components include network application server software 467 and database software 468.

[0113] Virtualization layer 470 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 471; virtual storage 472; virtual networks 473, including virtual private networks; virtual applications and operating systems 474; and virtual clients 475.

[0114] In one example, management layer 480 can provide the functions described below. Resource provisioning 481 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing 482 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources can include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 483 provides access to the cloud computing environment for consumers and system administrators. Service level management 484 provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment 485 provide pre-arrangement for, and procurement of, cloud computing resources for which future utilization is anticipated in accordance with an SLA.

[0115] Workloads layer 490 provides examples of functionality for which the cloud computing environment can be utilized. Examples of workloads and functions which can be provided from this layer include: mapping and navigation 441; software development and lifecycle management 492; virtual classroom education delivery 493; data analytics processing 494; transaction processing 495; and single device for synaptic weight 496.

[0116] Figure 10 A practical application of using a current mirror to speed up MAC operations is shown in accordance with embodiments of the present application.

[0117] Artificial intelligence (AI) accelerator chips 501 can be used in a variety of practical applications, including but not limited to robotics 510, industrial applications 512, mobile or Internet of Things (loT) 514, personal computing 516, consumer electronics 518, server data centers 520, physical and chemical applications 522, medical health applications 524, and financial applications 526. AI accelerator chips 501 can employ Figures 2-4 circuitry in FIG. 1, including the current mirror and current integrator described.

[0118] For example, robotic process automation or RPA 510 enables organizations to automate tasks, streamline processes, improve employee productivity, and ultimately deliver a satisfying customer experience. By using RPA 510, robots can perform a large number of repetitive tasks, freeing up a company’s resources to work on higher-value activities. RPA robots 510 mimic human actions to perform manual repetitive tasks, make decisions based on a defined rules set, and integrate with existing applications. All of this while maintaining compliance, reducing errors, and improving customer experience and employee engagement. AI accelerator chips 510 employing circuitry of FIG. 1 can enhance RPA 510. Figures 2-4

[0119] Figure 11 is a block diagram / flowchart of a method for advantageously employing a current mirror to accelerate MAC operations with Internet of Things (loT) systems / devices / infrastructure, in accordance with embodiments of the present invention.

[0120] According to some embodiments of the present invention, networks are implemented using loT methods. For example, AI accelerator chips 501 can be incorporated into, for example, wearable, implantable, or ingestible electronic devices and loT sensors. Wearable, implantable, or ingestible devices can include at least health and wellness monitoring devices and fitness devices. Wearable, implantable, or ingestible devices can also include at least implantable devices, smart watches, head-mounted devices, safety and security devices, and gaming and lifestyle devices. loT sensors can be incorporated into, for example, at least home automation applications, automotive applications, user interface applications, lifestyle and / or entertainment applications, city and / or infrastructure applications, toys, medical health, fitness, retail tags and / or trackers, platforms and components, and the like. AI accelerator chips 501 described herein can be incorporated into any type of electronic device for any type of use or application or operation.

[0121] ​IoT systems allow users to implement deeper automation, analytics, and integration within the system. IoT improves the range and accuracy of these areas. IoT utilizes existing and emerging technologies for sensing, networking, and robotics. Features of IoT include artificial intelligence, connectivity, sensors, active engagement, and small device usage. In various embodiments, the AI accelerator chip 501 of the present invention can be incorporated into a variety of different devices and / or systems. For example, the AI accelerator chip 501 can be incorporated into a wearable or portable electronic device 904. The wearable / portable electronic device 904 can include an implantable device 940, such as a smart clothing 943. The wearable / portable device 904 can include a smart watch 942 and smart jewelry 945. The wearable / portable device 904 can also include a fitness monitoring device 944, a medical and health monitoring device 946, a head mounted device 948 (e.g., smart glasses 949), a safety and security system 950, a gaming and life device 952, a smart phone / tablet 954, a media player 956, and / or a computer / computing device 958.

[0122] The AI accelerator chip 501 of the present invention can further be incorporated into an Internet of Things (IoT) sensor 906 for a variety of applications, such as home automation 920, automotive 922, user interface 924, life and / or entertainment 926, city and / or infrastructure 928, retail 910, tags and / or trackers 912, platforms and components 914, toys 930, and / or medical health 932 and fitness 934. The IoT sensor 906 can employ the AI accelerator chip 501. Of course, one of skill in the art can contemplate incorporating such AI accelerator chip 501 into any type of electronic device for any type of application, without being limited to those described herein.

[0123] Figure 12 is a block diagram / flow diagram of an exemplary IoT sensor for advantageously collecting data / information related to a current mirror for accelerating MAC operations, in accordance with embodiments of the present invention.

[0124] IoT loses its distinction without sensors. IoT sensors serve as the deciding equipment that transforms IoT from a standard passive device network into an active system capable of real-world integration.

[0125] The IoT sensors 906 can employ the Al accelerator chip 501 to continuously and in real-time transmit information or data to any type of distributed system via the network 908. Exemplary IoT sensors 906 can include, but are not limited to, a location / presence / proximity sensor 1002, a motion / speed sensor 1004, a displacement sensor 1006 such as an acceleration / tilt sensor 1007, a temperature sensor 1008, a humidity / moisture sensor 1010, and a flow sensor 1011, an acoustic / sound / vibration sensor 1012, a chemical / gas sensor 1014, a force / load / torque / strain / pressure sensor 1016, and / or an electric / magnetic sensor 1018. Those skilled in the art can envision using any combination of these sensors to collect data / information of a distributed system for further processing. Those skilled in the art can envision using other types of IoT sensors such as, but not limited to, a magnetometer, a gyroscope, an image sensor, a light sensor, a radio frequency identification (RFID) sensor, and / or a microfluidic sensor. The IoT sensors can also include energy modules, power management modules, RF modules, and sensing modules. The RF modules manage communications through their signal processing, WiFi, wireless transceivers, duplexers, etc.

[0126] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0127] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0128] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adaptation card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to storage media within the respective computing / processing device for execution.

[0129] Computer readable program instructions for carrying out operations of the present application can be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0130] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0131] These computer readable program instructions can be provided to at least one processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks or modules. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other

[0132] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks or modules.

[0133] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks or modules.

[0134] Reference throughout this specification to "an embodiment" or "the embodiment" or similar language means that a particular feature, structure, characteristic, and so forth being described is included in at least one embodiment of the present concept. Accordingly, appearances of the phrase "in one embodiment" or "in an embodiment" or similar language in various places throughout this specification do not necessarily all refer to the same embodiment.

[0135] It is to be appreciated that the use of any of the following“ / ”,“and / or”, and“at least one of”, for example, in the cases of“A / B”,“A and / or B” and“at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of“A, B, and / or C” and“at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are chosen in a similar manner.

[0136] Having described preferred embodiments for scalable and transient biasing schemes for single device synaptic elements (which are intended to be illustrative and not limiting), it is noted that modifications and variations from the embodiments already described are possible in light of the above teachings. It is therefore to be understood that changes can be made in the particular embodiments described, which will be apparent to those of ordinary skill in the art. These changes, while not exhaustive of the scope of this application, reside within the scope of the application as defined by the following claims. Accordingly, it is intended that the application not be limited by the particular embodiments described, but that the application should be construed in accordance with the appended claims and their equivalents.

Claims

1. A neuromorphic synapse array, comprising: a plurality of synapse array cells connected by circuitry such that the synapse array cells are assigned to rows and columns of an array, the synapse array cells each having unipolar synapse weights, the rows each connected to a respective input of the synapse array cells, the columns each connected to a respective output of the synapse array cells, the synapse array cells arranged in columns of the array defined as operational column arrays; and a current mirror array connected to the array, the current mirrors each connected to a respective row such that during a learning phase, weights corresponding to the current mirrors are set to an average weight of the synapse array cells being updated, each current mirror exhibiting a mirror ratio of N: 1, where N is a number of columns of the synapse array cells.

2. The neuromorphic synaptronic array of claim 1, wherein, At least a portion of the plurality of synapse array cells comprises resistive memory.

3. The neuromorphic synaptronic array of claim 2, wherein, At least a portion of the plurality of synapse array cells comprises a current integrator.

4. The neuromorphic synaptronic array of claim 3, wherein, The current mirror array comprises different current mirror configurations for one or more rows of the array.

5. The neuromorphic synaptronic array of claim 4, wherein, One current mirror configuration comprises two n-type field effect transistors.

6. The neuromorphic synaptronic array of claim 4, wherein, One current mirror configuration comprises two p-type field effect transistors and a single n-type field effect transistor.

7. The neuromorphic synaptronic array of claim 4, wherein, One current mirror configuration comprises two n-type field effect transistors and a single operational amplifier.

8. The neuromorphic synaptronic array of claim 4, wherein, One current mirror configuration comprises two p-type field effect transistors, a single n-type field effect transistor, and two operational amplifiers.

9. The neuromorphic synaptral array of claim 3, wherein, The current integrator comprises different configurations for one or more rows of the array.

10. The neuromorphic synaptronic array of claim 9, wherein, One current integrator configuration comprises two p-type field effect transistors, a single n-type field effect transistor, and an integration capacitor.

11. The neuromorphic synaptronic array of claim 10, wherein, The integration capacitor receives a collected mirror current, replicates the collected mirror current, and discharges the collected mirror current.

12. The neuromorphic synaptronic array of claim 9, wherein, One current integrator configuration comprises two p-type field effect transistors, a single n-type field effect transistor, an operational amplifier, and an integration capacitor.

13. The neuromorphic synaptronic array of claim 12, wherein, The integration capacitor receives a collected mirror current, replicates the collected mirror current, and discharges the collected mirror current.

14. The neuromorphic synaptrc array of claim 1, wherein, The neuromorphic synapse array accelerates multiply-accumulate operations in an artificial neural network accelerator chip.

15. A computer-implemented method, comprising: connecting a plurality of synapse array cells by circuitry such that the synapse array cells are assigned to rows and columns of an array, the synapse array cells each having unipolar synapse weights, the rows each connected to a respective input of the synapse array cells, the columns each connected to a respective output of the synapse array cells, the synapse array cells arranged in columns of the array defined as operational column arrays; and connecting a current mirror array to the array, the current mirrors each connected to a respective row such that during a learning phase, weights corresponding to the current mirrors are set to an average weight of the synapse array cells being updated, each current mirror exhibiting a mirror ratio of N: 1, where N is a number of columns of the synapse array cells.

16. The computer-implemented method of claim 15, wherein at least a portion of the plurality of synapse array cells comprises resistive memory.

17. The computer-implemented method of claim 16, wherein, At least a portion of the plurality of synapse array cells comprises a current integrator.

18. The computer-implemented method of claim 17, wherein the array of current mirrors includes different current mirror configurations for one or more rows of the array.

19. The computer-implemented method of claim 18, wherein one current mirror configuration includes two p-type field effect transistors and a single n-type field effect transistor.

20. The computer-implemented method of claim 18, wherein one current mirror configuration includes two n-type field effect transistors and a single operational amplifier.

21. The computer-implemented method of claim 18, wherein one current mirror configuration includes two p-type field effect transistors, a single n-type field effect transistor, and two operational amplifiers.

22. A neuromorphic synapse array, comprising: a plurality of synapse array cells connected by circuitry such that the synapse array cells are assigned to rows and columns of an array, the synapse array cells each having a single polarity synapse weight, the rows each connected to a respective input of the synapse array cells, the columns each connected to a respective output of the synapse array cells, the synapse array cells arranged in columns of the array defined as operational column arrays; an array of current mirrors each connected to a respective row such that during a learning phase, weights corresponding to the current mirrors are set to an average weight of the synapse array cells being updated, each current mirror exhibiting a mirror ratio of N: 1, where N is a number of columns of the synapse array cells; and an array of current integrators each connected to a respective column of the array, and each current integrator including an integration capacitor to receive, replicate, and discharge a collected mirror current.

23. A computer-implemented method, comprising: connecting a plurality of synapse array cells by circuitry such that the synapse array cells are assigned to rows and columns of an array, the synapse array cells each having a single polarity synapse weight, the rows each connected to a respective input of the synapse array cells, the columns each connected to a respective output of the synapse array cells, the synapse array cells arranged in columns of the array defined as operational column arrays; connecting an array of current mirrors to the array, the current mirrors each connected to a respective row such that during a learning phase, weights corresponding to the current mirrors are set to an average weight of the synapse array cells being updated, each current mirror exhibiting a mirror ratio of N: 1, where N is a number of columns of the synapse array cells; and connecting an array of current integrators to the array, each current integrator connected to a respective column of the array, and each current integrator including an integration capacitor to receive, replicate, and discharge a collected mirror current.

24. A neuromorphic synapse array, comprising: a plurality of synapse array cells connected by circuitry such that the synapse array cells are assigned to rows and columns of an array, the synapse array cells each having a single polarity synapse weight; a current mirror array, the current mirror array connected to respective rows of the array of synaptic array cells, such that during a learning phase, weights corresponding to the current mirror array are set to an average weight of the synaptic array cells being updated, each current mirror exhibiting a mirror ratio of N:1, where N is a number of columns of the synaptic array cells; and a current integrator array, each current integrator connected to a respective column of the array, and each current integrator including an integration capacitor for receiving a collected mirror current, replicating the collected mirror current, and discharging the collected mirror current to accelerate multiply-accumulate operations in an artificial neural network accelerator chip.

25. The neuromorphic synaptral array of claim 24, wherein, the current mirror array includes different current mirror configurations for one or more rows of the array.

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