Electrode array structure and preparation method thereof, and signal acquisition device

Abstract

This disclosure provides an electrode array structure, its fabrication method, and a signal acquisition device. The electrode array structure includes multiple repeating units arranged in an array and multiple row control signal lines and multiple column control signal lines connected to the repeating units. At least one repeating unit includes an electrode unit and a circuit unit. The electrode unit includes at least one of a first electrode and a second electrode. The circuit unit includes at least one of a first control circuit connected to the first electrode and a second control circuit connected to the second electrode. The first control circuit is configured to control the first electrode to output a stimulation signal to a target object under the control of the corresponding row control signal lines and column control signal lines. The second control circuit is configured to acquire the electroencephalogram (EEG) signal of the target object through the second electrode under the control of the corresponding row control signal lines and column control signal lines.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of artificial intelligence, and particularly to an electrode array structure and its fabrication method, and a signal acquisition device. Background Technology

[0002] Brain-computer interface (BCI) is an information exchange pathway established between the brain (or a culture of brain cells) of a human or animal and an external device, independent of conventional brain information output pathways (such as the peripheral nervous system and muscle tissue). It can monitor, replace, improve, restore, enhance, and supplement the overall function of the brain and body. BCI is typically implemented by acquiring electroencephalogram (EEG) signals from the cerebral cortex and other areas using signal acquisition devices. These signals are then processed through pre-screening, amplification, and filtering to convert them into computer-recognizable signals. Finally, through pre-processing, feature extraction, and feature classification, these computer-recognizable signals are converted into commands that control external devices, enabling the brain to control external devices (such as robotic arms, wheelchairs, and prostheses).

[0003] Currently, most signal acquisition devices use sensors (such as EEG caps, retinal nerve electrodes, electrocorticography (ECoG) electrodes, silicon needle tip electrode arrays, and substrate silicon microneedle electrode arrays) to collect EEG signals from the cerebral cortex and other areas. During acquisition, the electrode contacts are evenly distributed in the brain region, resulting in a large invasive area and low resolution. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide an electrode array structure applied to a brain-computer interface system. The electrode array structure includes: a plurality of repeating units arranged in an array and a plurality of row control signal lines and a plurality of column control signal lines connected to the plurality of repeating units; at least one repeating unit includes: an electrode unit and a circuit unit, the electrode unit including at least one of a first electrode and a second electrode, the circuit unit including at least one of a first control circuit connected to the first electrode and a second control circuit connected to the second electrode, the first control circuit being configured to control the first electrode to output a stimulation signal to a target object under the control of the corresponding row control signal lines and column control signal lines; the second control circuit being configured to acquire the electroencephalogram (EEG) signal of the target object through the second electrode under the control of the corresponding row control signal lines and column control signal lines.

[0006] In one exemplary embodiment, the first control circuit includes: a first transistor, the control electrode of the first transistor being connected to a row control signal line, a first electrode of the first transistor being connected to a column control signal line, and a second electrode of the first transistor being connected to the first electrode.

[0007] In one exemplary embodiment, the second control circuit includes: a first sub-circuit, a second sub-circuit, and a third sub-circuit;

[0008] The first sub-circuit is connected to the row control signal line, the column control signal line and the first node respectively, and is configured to provide the column control signal line signal to the first node under the control of the signal of the row control signal line.

[0009] The second sub-circuit is connected to the first power supply terminal, the first node, and the second node, respectively, and is configured to provide the signal from the first power supply terminal to the first node under the control of the second node.

[0010] The third sub-circuit is connected to the reset signal terminal, the second power supply terminal, and the second node, respectively, and is configured to provide the second power supply terminal signal to the second node under the control of the reset signal terminal signal.

[0011] The second electrode, connected to the second node, is configured to acquire electroencephalogram (EEG) signals.

[0012] In one exemplary embodiment, the first sub-circuit includes: a second transistor, the first terminal of the second transistor being connected to the first node, the second terminal of the second transistor being connected to the column control signal line, and the control terminal of the second transistor being connected to the row control signal line;

[0013] The second sub-circuit includes: a third transistor, wherein the control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first power supply terminal, and the second electrode of the third transistor is connected to the first node;

[0014] The third sub-circuit includes: a fourth transistor, the control electrode of the fourth transistor being connected to the reset signal terminal, the first electrode of the fourth transistor being connected to the second power supply terminal, and the second electrode of the fourth transistor being connected to the second node.

[0015] In one exemplary embodiment, the second control circuit includes: a second transistor, a first terminal of the second transistor connected to a second electrode, a second terminal of the second transistor connected to the column control signal line, and a control terminal of the second transistor connected to the row control signal line.

[0016] In one exemplary embodiment, in a direction perpendicular to the electrode array structure, the electrode array structure includes: a substrate, a circuit structure layer disposed on one side of the substrate, and an electrode structure layer disposed on the side of the circuit structure layer away from the substrate; wherein,

[0017] The circuit structure layer includes: multiple circuit units, multiple row control signal lines, and multiple column control signal lines;

[0018] The electrode structure layer includes: a plurality of electrode units, wherein at least one of the first electrode and the second electrode is a single-layer metal structure or a multi-layer metal structure, wherein the multi-layer metal structure includes: a first metal layer and a second metal layer stacked sequentially, wherein the orthogonal projection of the first metal layer on the substrate is located within the orthogonal projection of the second metal layer on the substrate.

[0019] In one exemplary embodiment, at least one of the first electrode and the second electrode includes: a first region and a second region, the second region having a cavity, the first metal layer being located in the first region, and the second metal layer including: a support portion located in the first region and a suspended portion located in the second region connected in sequence, the support portion overlapping the first metal layer, and the suspended portion being suspended in the cavity.

[0020] In one exemplary embodiment, at least one of the first electrode and the second electrode further includes a microneedle electrode disposed on the side of the suspended portion away from the substrate.

[0021] In one exemplary embodiment, the microneedle electrode is tapered.

[0022] In one exemplary embodiment, the second metal layer is either a comb-like structure or a hollow structure.

[0023] In one exemplary embodiment, in a plane parallel to the electrode array structure, the comb-like structure includes: a first region extending along a first direction and a second region located on one side of the first region along the first direction. The second region includes: protrusions and first intervals alternately arranged along a second direction. The size of the protrusions gradually decreases along the first direction, and the size of the first intervals gradually increases along the first direction. The second direction intersects the first direction.

[0024] In one exemplary embodiment, in a plane parallel to the electrode array structure, the hollow structure includes: a spiral-shaped hollow region and a spiral-shaped non-hollow region spaced apart.

[0025] In an exemplary embodiment, in a plane parallel to the electrode array structure, the hollow structure includes: a plurality of main body portions extending along a first direction, a plurality of second spacing portions extending along the first direction, a plurality of first connecting portions extending along a second direction, and a plurality of second connecting portions extending along the second direction. The main body portions and the second spacing portions are alternately arranged along the second direction, and the first connecting portions and the second connecting portions are alternately arranged along the second direction. The second end of the i-th main body portion is connected to the first end of the i-th first connecting portion, the second end of the i-th first connecting portion is connected to the second end of the (i+1)-th main body portion, the first end of the (i+1)-th main body portion is connected to the first end of the i-th second connecting portion, and the second end of the i-th second connecting portion is connected to the first end of the (i+2)-th main body portion. i is a positive integer greater than or equal to 1, and the second direction intersects the first direction.

[0026] In one exemplary embodiment, the dimensions of the plurality of main body portions along the first direction are all the same and the dimensions of the plurality of second spacing portions along the first direction are all the same; or, the dimensions of the plurality of main body portions along the first direction increase sequentially in the second direction and the dimensions of the plurality of second spacing portions along the first direction increase sequentially.

[0027] Secondly, this disclosure also provides a method for fabricating an electrode array structure, wherein the electrode array structure is the electrode array structure described in one or more exemplary embodiments above, and the fabrication method includes:

[0028] A circuit structure layer is formed on one side of a substrate. The circuit structure layer includes: multiple circuit units, multiple row control signal lines, and multiple column control signal lines. Each circuit unit includes: at least one of the first control circuit and the second control circuit.

[0029] An electrode structure layer is formed on the side of the circuit structure layer away from the substrate. The electrode structure layer includes a plurality of electrode units, each electrode unit including at least one of a first electrode and a second electrode. At least one of the first electrode and the second electrode is a single metal structure or a multi-layer metal structure. The multi-layer metal structure includes a first metal layer and a second metal layer stacked sequentially. The orthogonal projection of the first metal layer on the substrate is located within the orthogonal projection of the second metal layer on the substrate.

[0030] In one exemplary embodiment, forming the electrode structure layer on the side of the circuit structure layer away from the substrate includes:

[0031] A first metal layer is formed on the side of the circuit structure layer away from the substrate.

[0032] Photoresist is coated on the area of ​​the electrode structure layer not covered by the first metal layer, and the photoresist is exposed using a mask to form a first photoresist pattern layer.

[0033] A second metal layer is formed on the first metal layer and the first photoresist pattern layer;

[0034] Photoresist is coated on the area of ​​the first photoresist pattern layer that is not covered by the second metal layer, and the photoresist is exposed using a mask to form the second photoresist pattern layer.

[0035] The second photoresist pattern layer and the first photoresist pattern layer are developed to remove the photoresist below the area of ​​the second metal layer that is not covered by the first metal layer, forming a cavity, such that at least one of the first electrode and the second electrode includes: a first region and a second region, the second region having a cavity, the first metal layer being located in the first region, and the second metal layer including: a support portion located in the first region and a suspended portion located in the second region connected in sequence, the support portion overlapping the first metal layer, and the suspended portion being suspended in the cavity.

[0036] In one exemplary embodiment, the method further includes forming a microneedle electrode on the side of the suspended portion away from the substrate.

[0037] Thirdly, this disclosure also provides a signal acquisition device for use in a brain-computer interface system. The signal acquisition device includes: a row control circuit, a column control circuit, and an electrode array structure as described in one or more exemplary embodiments above. The column control circuit is connected to a plurality of column control signal lines, and the row control circuit is connected to a plurality of row control signal lines.

[0038] The electrode array structure, its fabrication method, and signal acquisition device provided in this disclosure integrate electrode units and corresponding circuit units within repeating units, and arrange multiple repeating units in an array. This results in an electrode array structure with high integration, high throughput, high resolution, and minimal invasiveness. Furthermore, integrating electrode units and corresponding circuit units within repeating units reduces the use of back-end processing circuitry and minimizes the introduction of noise signals during signal transmission.

[0039] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0040] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects will become clear. Attached Figure Description

[0041] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0042] Figure 1 This is a schematic diagram of the structure of a brain-computer interface system according to an exemplary embodiment of the present disclosure;

[0043] Figure 2 This is a schematic diagram of the structure of a signal acquisition device according to an exemplary embodiment of the present disclosure;

[0044] Figure 3 This is a schematic diagram of an electrode array structure according to an exemplary embodiment of the present disclosure;

[0045] Figure 4 This is a schematic diagram of another electrode array structure in an exemplary embodiment of the present disclosure;

[0046] Figure 5 This is an equivalent circuit diagram of a first control circuit in an exemplary embodiment of the present disclosure;

[0047] Figure 6 This is an equivalent circuit diagram of a second control circuit in an exemplary embodiment of the present disclosure;

[0048] Figure 7 This is a schematic diagram of an equivalent circuit for another second control circuit in an exemplary embodiment of the present disclosure;

[0049] Figure 8 A signal timing diagram of the first and second control circuits in an exemplary embodiment of this disclosure;

[0050] Figure 9 This is a cross-sectional schematic diagram of an electrode array structure according to an exemplary embodiment of the present disclosure;

[0051] Figure 10A This is a schematic diagram of a first structure of the second metal layer in an exemplary embodiment of the present disclosure;

[0052] Figure 10B This is a schematic diagram of a second structure of the second metal layer in an exemplary embodiment of this disclosure;

[0053] Figure 10C This is a schematic diagram of a third structure of the second metal layer in an exemplary embodiment of this disclosure;

[0054] Figure 10D This is a schematic diagram of a fourth structure of the second metal layer in an exemplary embodiment of this disclosure;

[0055] Figure 11 This is a schematic diagram of the structure after the circuit structure layer is formed in an exemplary embodiment of this disclosure;

[0056] Figure 12 This is a schematic diagram of the structure after the first metal layer is formed in an exemplary embodiment of this disclosure;

[0057] Figure 13 This is a schematic diagram of the structure after the first photoresist pattern layer is formed in an exemplary embodiment of this disclosure;

[0058] Figure 14 This is a schematic diagram of the structure after the formation of the second metal layer and the second photoresist pattern layer in an exemplary embodiment of this disclosure;

[0059] Figure 15 This is a schematic diagram of the structure after the electrodes are formed in an exemplary embodiment of this disclosure;

[0060] Figure 16 This is a schematic diagram of the structure after the third photoresist pattern layer is formed in an exemplary embodiment of this disclosure;

[0061] Figure 17 This is a schematic diagram of the structure after the microneedle electrode is formed in an exemplary embodiment of this disclosure;

[0062] Figure 18 This is a schematic diagram of an equivalent circuit of a signal acquisition device according to an exemplary embodiment of the present disclosure;

[0063] Figure 19 This is a schematic diagram of an equivalent circuit for another signal acquisition device in an exemplary embodiment of the present disclosure. Detailed Implementation

[0064] This document describes several embodiments, but these descriptions are exemplary and not limiting. Many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the accompanying drawings and discussed in exemplary embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or substitute for, any feature or element of any other embodiment.

[0065] In describing representative embodiments, the specification may have presented a method or process as a specific sequence of steps. However, the method or process should not be limited to a specific order of steps to the extent that it is independent of this specific order. Other sequences of steps are possible, as will be understood by those skilled in the art. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Furthermore, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders may be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0066] In the accompanying drawings, the size of each component, the thickness of a layer, or the area are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of each part in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0067] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0068] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0069] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0070] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission and reception of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include electrodes or wiring, switching elements such as transistors, or other functional elements such as resistors, inductors, or capacitors.

[0071] In this specification, a transistor is a device comprising at least three terminals: a gate electrode (also called a gate or control electrode), a drain electrode (also called a drain terminal, drain region, or drain), and a source electrode (also called a source terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0072] In this specification, to distinguish the two terminals of a transistor other than the gate electrode, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0073] The transistors used in this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, the thin-film transistors used in this disclosure can include, but are not limited to, amorphous silicon TFTs, oxide TFTs, or low-temperature polysilicon TFTs (LTPSTFTs). For instance, the thin-film transistor can be either a bottom-gate structure or a top-gate structure, as long as it can perform a switching function. This disclosure does not limit the specific implementation of these features.

[0074] Figure 1 This is a schematic diagram of the structure of a brain-computer interface system according to an exemplary embodiment of this disclosure. Figure 1 As shown, the brain-computer interface system may include: the brain of the target object 10, a signal acquisition device 11, a signal processing device 12, and an external device 13.

[0075] In one exemplary embodiment, the signal processing device 12 can generate corresponding control commands based on the acquired electroencephalogram (EEG) signals to control external devices. For example, the signal processing device 12 can convert the EEG signals into signals that can be recognized by a computer through pre-screening, amplification, filtering, A / D (analog-to-digital) conversion, and then convert the computer-recognizable signals into control commands that can control external devices 13 through pre-processing, feature extraction, feature classification, and other processes, so as to realize the brain 10 of the target object controlling the external devices 13.

[0076] In one exemplary embodiment, the external device 13 may be an electronic device such as a laptop, television, or cursor, or a medical device such as a brain pacemaker, wheelchair, prosthesis, or robotic arm. Of course, it may also be other medical devices, but this embodiment does not limit the scope of the invention.

[0077] In one exemplary embodiment, the signal acquisition device 11 can collect and process electroencephalogram (EEG) signals from areas such as the cerebral cortex or gray matter layer of the target object's brain 10 using sensors. For example, the signal acquisition device 11 can collect EEG signals from areas such as the cerebral cortex.

[0078] Figure 2 This is a schematic diagram of the structure of a signal acquisition device according to an exemplary embodiment of this disclosure. Figure 2 As shown, the signal acquisition device may include: a row control circuit 21, a column control circuit 22, and an electrode array structure 23. The row control circuit 21 is connected to multiple row control signal lines (row control signal lines SCAN1 to SCAN2). m The column control circuit 22 is connected to multiple column control signal lines (column control signal lines Source1 to Source2). n Connect m and n, where m and n can be natural numbers.

[0079] In one exemplary embodiment, the line control circuit 21 can generate signals to be provided to the line control signal lines SCAN1, SCAN2, ... and SCAN3 by receiving a clock signal, a scan start signal, etc. m The horizontal control signal. For example, the horizontal control circuit 21 can sequentially provide horizontal control signals with on-level pulses to the horizontal control signal lines SCAN1 to SCAN2. m For example, the row control circuit 21 can be configured as a shift register and can generate row control signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. For example, the row control circuit 21 may include multiple cascaded shift registers.

[0080] In one exemplary embodiment, column control circuit 22 may generate signals to be provided to column control signal lines Source1, Source2, ... and Source... n The column control signal. For example, the column control circuit 22 can be configured as a data selector. For example, the column control circuit 22 may include: a plurality of data selectors MUX (MUX1 to MUXn).

[0081] This exemplary embodiment provides an electrode array structure that can be applied to a brain-computer interface system. The electrode array structure may include: multiple repeating units Pxij arranged in an array, and multiple row control signal lines SCAN (row control signal lines SCAN1 to SCAN) connected to the multiple repeating units Pxij. m ) and multiple column control signal lines Source (column control signal lines Source1 to Source n ), i and j can be natural numbers, m and n can be natural numbers; at least one repeating unit Pxij can include: an electrode unit and a circuit unit, the electrode unit can include: at least one of a first electrode ED and a second electrode ES, the circuit unit 30 can include: at least one of a first control circuit 31 connected to the first electrode ED and a second control circuit 32 connected to the second electrode ES, the first control circuit 31 is configured to control the first electrode ED to output a stimulation signal to the target object under the control of the corresponding row control signal line SCAN and column control signal line Source; the second control circuit 32 is configured to acquire the EEG signal of the target object through the second electrode ES under the control of the corresponding row control signal line SCAN and column control signal line Source.

[0082] Here, the first electrode ED can also be called the signal feedback electrode. The second electrode ES can also be called the signal acquisition electrode.

[0083] Thus, in the electrode array structure provided by the exemplary embodiments of this disclosure, by integrating the electrode units and corresponding circuit units into the repeating units, and by arranging multiple repeating units in an array, an electrode array structure with high integration, high throughput, high resolution, and low invasiveness can be formed. Furthermore, by integrating the electrode units and corresponding circuit units into the repeating units, the use of back-end processing circuitry for the electrodes can be reduced, and noise signals introduced during signal transmission can be reduced.

[0084] Here, the number of channels can refer to the number of neurons acquired and recorded by the electrode array structure, and generally refers to the number of electrodes. Resolution accuracy refers to the level of detail in the EEG signals received by the electrode array structure. Resolution accuracy can include spatial resolution and temporal resolution. Spatial resolution refers to the detection and recording of the EEG signals generated by the triggering of individual neurons, while temporal resolution refers to the exact time of occurrence of the recorded EEG signals.

[0085] In one exemplary embodiment, Figure 3 This is a schematic diagram of an electrode array structure according to an exemplary embodiment of the present disclosure, as shown below. Figure 3 As shown, the electrode array structure 23 may include: multiple row control signal lines SCAN (SCAN1 to SCAN2). m ) and multiple columns of control signal lines Source (Source1 to Source) n The multiple repeating units Pxij are defined and can be arranged in an array. Each repeating unit Pxij may include: a first electrode ED and a first control circuit 31 connected to the first electrode ED. The first control circuit 31 is configured to control the first electrode ED to output a stimulation signal to the target object under the control of the corresponding row control signal line SCAN and column control signal line Source.

[0086] In another exemplary embodiment, the electrode array structure 23 may include: multiple row control signal lines SCAN (SCAN1 to SCAN2). m ) and multiple columns of control signal lines Source (Source1 to Source) n The multiple repeating units Pxij are defined and can be arranged in an array. Each repeating unit Pxij may include a second electrode ES and a second control circuit 32 connected to the second electrode ES. The second control circuit 32 is configured to acquire the EEG signal of the target object through the second electrode ES under the control of the corresponding row control signal line SCAN and column control signal line Source.

[0087] In yet another exemplary embodiment, Figure 4 This is a schematic diagram of another electrode array structure in an exemplary embodiment of the present disclosure, as shown below. Figure 4 As shown, the electrode array structure 23 may include: multiple row control signal lines SCAN (SCAN1 to SCAN2). m ) and multiple columns of control signal lines Source (Source1 to Source) nThe system defines multiple repeating units Pxij, which are arranged in an array. Each repeating unit Pxij may include: a first electrode ED, a first control circuit 31 connected to the first electrode ED, a second electrode ES, and a second control circuit 32 connected to the second electrode ES. The first control circuit 31 is configured to control the first electrode ED to output stimulation signals to the target object under the control of the corresponding row control signal line SCAN and column control signal line Source. The second control circuit 32 is configured to acquire the EEG signals of the target object through the second electrode ES under the control of the corresponding row control signal line SCAN and column control signal line Source.

[0088] In one exemplary embodiment, Figure 5 This is an equivalent circuit diagram of a first control circuit in an exemplary embodiment of the present disclosure. Figure 5 The diagram illustrates the first control circuit 31, which includes one transistor. Figure 5 As shown, in at least one repeating unit, the first control circuit 31 may include: a first transistor Med, the control electrode of the first transistor Med being connected to the row control signal terminal SCAN, the first electrode of the first transistor Med being connected to the column control signal terminal Source, and the second electrode of the first transistor Med being connected to a first electrode ED. The first electrode ED is configured to output a stimulation signal to the target object.

[0089] In one exemplary embodiment, Figure 6 This is an equivalent circuit diagram of a second control circuit in an exemplary embodiment of the present disclosure. Figure 6 The second control circuit 32, comprising one transistor, is illustrated in the example. Figure 6 As shown, the second control circuit 32 may include: a second transistor Mse, the first electrode of which is connected to the second electrode ES, the second electrode of which is connected to the column control signal line Source, and the control electrode of which is connected to the row control signal line SCAN. The second electrode ES is configured to acquire electroencephalogram (EEG) signals.

[0090] In one exemplary embodiment, Figure 7 This is an equivalent circuit diagram of another second control circuit in an exemplary embodiment of the present disclosure, such as... Figure 7As shown, the second control circuit 32 may include: a first sub-circuit 321, a second sub-circuit 322, and a third sub-circuit 323; the first sub-circuit 321 is connected to the row control signal line SCAN, the column control signal line Source, and the first node N1, and is configured to provide the column control signal line Source to the first node N1 under the control of the signal from the row control signal line SCAN; the second sub-circuit 322 is connected to the first power supply terminal VDD, the first node N1, and the second node N2, and is configured to provide the first power supply terminal VDD to the first node N1 under the control of the second node N2; the third sub-circuit 323 is connected to the reset signal terminal RST, the second power supply terminal Vrst, and the second node N2, and is configured to provide the second power supply terminal Vrst to the second node N2 under the control of the signal from the reset signal terminal RST; the second electrode ES is connected to the second node N2 and is configured to acquire EEG signals. The second node N2 and the first node N1 represent the junction of related electrical connections in the circuit diagram.

[0091] In one exemplary embodiment, such as Figure 7 As shown, the first sub-circuit 321 may include: a second transistor Mse, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the column control signal line Source, and the control terminal of which is connected to the row control signal line SCAN; the second sub-circuit 322 may include: a third transistor Msf, the control terminal of which is connected to the second node N2, the first terminal of which is connected to the first power supply terminal VDD, and the second terminal of which is connected to the first node N1; the third sub-circuit 323 may include: a fourth transistor Mrst, the control terminal of which is connected to the reset signal terminal RST, the first terminal of which is connected to the second power supply terminal Vrst, and the second terminal of which is connected to the second node N2. Figure 7 The second control circuit 32, which includes three transistors, is illustrated in the example.

[0092] In one exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0093] In one exemplary embodiment, the first transistor Med, the second transistor Mse, the third transistor Msf, and the fourth transistor Mrst can be either P-type transistors or N-type transistors. Using the same type of transistor in the circuit unit simplifies the process flow, reduces the technological complexity of the electrode array structure, and improves product yield. In some possible implementations, the first transistor Med, the second transistor Mse, the third transistor Msf, and the fourth transistor Mrst can include both P-type and N-type transistors.

[0094] In one exemplary embodiment, the first transistor Med, the second transistor Mse, the third transistor Msf, and the fourth transistor Mrst can be low-temperature polysilicon (LTPS) thin-film transistors, or they can be oxide thin-film transistors, or a combination of LTPS and oxide thin-film transistors. The active layer of the LTPS thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor.

[0095] In one exemplary embodiment, the row control signal lines SCAN (SCAN1 to SCAN2) m It can extend horizontally, column control signal lines Source (Source1 to Source2). n It can extend vertically. Multiple row control signal lines SCAN (SCAN1 to SCAN2) m ) and multiple column control signal lines Source (Source1 to Source) n () Cross-definition defines multiple repeating units.

[0096] In one exemplary embodiment, Figure 8 A signal timing diagram of the first control circuit and the second control circuit provided for exemplary embodiments of this disclosure is shown below. Figure 5 The first control circuit shown and Figure 7 The circuit structure of the second control circuit shown is used as a reference, combined with... Figure 8 The signal timing diagram shown illustrates the operation of the electrode array structure provided in the exemplary embodiments of this disclosure. Figure 5 The first control circuit 31 includes one transistor (first transistor Med). Figure 7 The second control circuit 32 includes three transistors (second transistor Mse, third transistor Msf and fourth transistor Mrst), all of which are N-type transistors. Figure 8 The timing waveforms of the control signal line SCAN, column control signal line Source, reset signal terminal RST, and second power supply terminal Vrst are shown in the figure. Figure 8 The timing waveforms VNAN1 to VNANn-1 show the row control signal lines SCAN (SCAN1 to SCAN2). m The timing waveforms VN[1] to VN[n] show the column control signal lines Source (Source1 to Source2). n The timing waveforms of the reset signal terminal RST are shown in RST[1] to RST[n], and the timing waveforms of the second power supply terminal Vrst[1] to Vrst[n] are shown in Vrst[n]. Figure 8 The high and low potentials in the signal timing diagram shown are only schematic and do not represent actual potential values ​​or relative proportions. Corresponding to the embodiments of this disclosure, a high-level signal corresponds to the turn-on signal of an N-type transistor, while a low-level signal corresponds to the turn-off signal of an N-type transistor.

[0097] In one exemplary embodiment, the operation of the electrode array structure in this disclosure may include:

[0098] The first process can be called the stimulus signal output process.

[0099] For example, such as Figure 8 As shown, during this process, the row control signal lines SCAN (SCAN1 to SCAN2) are... m The control signal can be activated row by row from row 1 to row m in a cyclical manner according to a certain time and rhythm. When the row control signal line SCAN of the current row is high, the first transistor Med of the N-type transistor is turned on, the current stage VN control signal is turned on, and the column control signal lines Source (Source1 to Source...) are activated. n The electrodes are turned on sequentially, and the column control signal line Source is provided to the repeating cells in all columns (column 1 to n) in a row-by-row and cyclic manner from row 1 to row m in the electrode array structure. The signal of column control signal line Source is provided to the first electrode ED through the first transistor Med, so as to output a stimulation signal to the target object through the first electrode ED.

[0100] The second process can be called the electroencephalogram (EEG) signal acquisition process.

[0101] For example, such as Figure 8 As shown, during this process, the row control signal lines SCAN (SCAN1 to SCAN2) are... mThe system is activated row by row, from row 1 to row m, in a cyclical manner according to a set time and rhythm. When the row control signal line SCAN of the current row is high, the reset control signal RST provided by the reset signal terminal RST is also high, causing the fourth transistor Mrst of the N-type transistor to conduct. The reset signal Vrst provided by the second power supply terminal Vrst is then supplied to the second node N2 to reset the second electrode ES. This clears accumulated charges in the electrode's coupling capacitor, storage capacitor, or parasitic capacitor, effectively resetting and clearing the repeating unit where the current row is located, ensuring that the subsequent acquisition of EEG signals is not interfered with by other accumulated signals from the circuit, repeating unit, or other nodes. Next, the current stage VN control signal is activated, and the column control signal lines Source (Source1 to Source...) are activated. n When the electrodes are opened sequentially, the EEG signals collected by the second electrode in the repeating units of all columns (column 1 to column n) can be read (sampled) row by row and cyclically from row 1 to row m in the electrode array structure.

[0102] For example, external circuitry (such as an electronic engineering system board, driver integrated circuit, etc.) can generate a reset control signal that will be provided to the reset signal terminal RST and a reset signal that will be provided to the second power supply terminal Vrst.

[0103] For example, an analog-to-digital converter (ADC) chip can read the electroencephalogram (EEG) signals (analog acquisition signals) of a target object through an electrode array structure, and perform processing such as integration, amplification, digital quantization, and readout on the signals.

[0104] Of course, in addition to the exemplary working sequence described above, other working sequences can be set according to the actual circuit structure of the first control circuit and the second control circuit to realize the output of stimulation signals and the acquisition of EEG signals. Here, this disclosure does not limit this.

[0105] In one exemplary embodiment, the first direction D1 may be the extension direction of the row control signal line SCAN (row direction), and the second direction D2 may be the extension direction of the column control signal line Source (column direction). The first direction D1 and the second direction D2 may be perpendicular to each other.

[0106] Thus, in the electrode array structure of the exemplary embodiments of this disclosure, multiple repeating units Pxij are constructed in an array arrangement, and multiple row control signal lines SCAN (row control signal lines SCAN1 to SCAN) are connected to the multiple repeating units Pxij. m ) and multiple column control signal lines Source (column control signal lines Source1 to Source nThe system constructs a first electrode ED (signal acquisition electrode), a first control circuit composed of transistors, a second electrode ES (signal acquisition electrode), and a second control circuit composed of transistors within each repeating unit. The first control circuit may include addressing and writing control circuits for the signal feedback electrode composed of transistors, and the second control circuit may include addressing and reading control circuits for the signal acquisition electrode composed of transistors. The signals of the column control signal line Source within the repeating unit may include reading signals and writing signals, and the signals of the row control signal line SCAN within the repeating unit may include addressing signals and control signals. In this way, the system can complete the output of stimulation signals from the signal feedback electrode within the repeating unit, the sampling, pre-judgment, and reading of the EEG signals collected by the signal acquisition electrode within the repeating unit according to a specific timing sequence, and the writing of necessary external clock signals and control signals according to a specific timing sequence.

[0107] In one exemplary embodiment, Figure 9 This is a cross-sectional schematic diagram of an electrode array structure according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit in the electrode array structure. For example... Figure 9 As shown, on a plane perpendicular to the electrode array structure, the electrode array structure may include: a substrate 101, a circuit structure layer 102 disposed on the substrate 101, and an electrode structure layer 103 disposed on the side of the circuit structure layer 102 away from the substrate 101. In some possible implementations, the electrode array structure may include other film layers, such as encapsulation structure layers, etc., which are not limited in the embodiments disclosed herein.

[0108] In one exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate.

[0109] In one exemplary embodiment, the circuit structure layer 102 may include: a plurality of circuit units, each circuit unit may include: at least one of a transistor constituting the first control circuit 31 and a transistor constituting the second control circuit 32; the circuit structure layer 102 may also include: a plurality of row control signal lines SCAN (SCAN1 to SCAN2). m ), multiple control signal lines Source (Source1 to Source) n Various traces, such as... The electrode structure layer 103 may include: multiple electrode units, each electrode unit may include: at least one of a first electrode and a second electrode, etc. Figure 9 The example only uses one transistor in the circuit unit and one electrode in the electrode unit.

[0110] In one exemplary embodiment, such as Figure 9As shown, the electrode structure layer 103 may include: a first conductive layer, an insulating layer 301, a semiconductor layer, a second conductive layer, and a passivation layer 302 sequentially stacked on the substrate 101. The first conductive layer may include: a control electrode 201 of a transistor. The semiconductor layer may include: an active layer 202 of a transistor. The second conductive layer may include: a first electrode 203 and a second electrode 204 of a transistor. The passivation layer 302 is provided with vias, which are configured to expose the surface of the first electrode 203 of the transistor so that the subsequently formed first electrode or second electrode can be connected to the first electrode of the transistor.

[0111] In one exemplary embodiment, both the first electrode and the second electrode can be a single-layer metal structure, or both the first electrode and the second electrode can be a multi-layer metal structure. This disclosure does not limit the scope of the embodiments.

[0112] In one exemplary embodiment, such as Figure 9 As shown, taking the first electrode and the second electrode as an example of a multilayer metal structure, both the first electrode and the second electrode may include: a first metal layer 401 and a second metal layer 402 stacked sequentially, wherein the orthographic projection of the first metal layer 401 on the substrate 101 is located within the orthographic projection of the second metal layer 402 on the substrate 101.

[0113] In one exemplary embodiment, such as Figure 9 As shown, taking a multilayer metal structure as an example, the first and second electrodes may include at least one of the following: a first region 601 and a second region 602. The second region 602 has a cavity. A first metal layer 401 is located in the first region 601. The second metal layer 402 includes a support portion 402A located in the first region 601 and a suspended portion 402B located in the second region, which are connected in sequence. The support portion 402A overlaps the first metal layer 401, and the suspended portion 402B is suspended in the cavity. Thus, because the suspended portion is suspended in the cavity, it is not attached to the passivation layer (or other components in the circuit structure layer). The suspended portion of the first or second electrode can move or float within the cavity, thereby forming an electrode array structure whose spatial position is variable or controllable. Furthermore, in practical brain-computer interface applications, electrodes at specific sites in the cerebral cortex or gray matter layer can be implanted as needed. For example, in invasive or non-invasive brain-computer interface applications, electrodes can be placed at locations in the nerves (or tissues) of the target subject according to the actual situation, which is more flexible.

[0114] In one exemplary embodiment, such as Figure 9As shown, taking a multilayer metal structure as an example, the first and second electrodes may further include a microneedle electrode 501 disposed on the side of the suspended portion 404B away from the substrate 101. The microneedle electrode refers to a miniature needle-like electrode, such as a needle-like electrode in a Utah electrode array or a Michigan electrode array. Thus, since the microneedle electrode 501 is disposed on the suspended portion 404B of the first or second electrode, a movable or floating microneedle electrode 501 that does not adhere to the passivation layer 302 or other components can be obtained. Furthermore, in the electrode array structure, the array composed of microneedle electrodes in multiple repeating units can be similar to a Utah electrode array or a Michigan electrode array.

[0115] In one exemplary embodiment, such as Figure 9 As shown, the shape of the microneedle electrode can be conical. For example, the shape of the microneedle electrode can be conical.

[0116] In one exemplary embodiment, the second metal layer can be either a comb-like structure or a hollow structure.

[0117] In one exemplary embodiment, Figure 10A This is a schematic diagram of a first structure of the second metal layer of the electrode in an exemplary embodiment of this disclosure, as shown below. Figure 10A As shown, in a plane parallel to the electrode array structure, the comb-like structure may include: a first region 701 extending along the first direction D1 and a second region 702 located on one side of the first region along the first direction. The second region may include: protrusions 703 and first intervals 704 alternately arranged along the second direction D2. The size of the protrusions 703 gradually decreases along the first direction D1, and the size of the first intervals 704 gradually increases along the first direction D1. The second direction D2 intersects the first direction D1.

[0118] In one exemplary embodiment, Figure 10B This is a schematic diagram of a second structure of the second metal layer of the electrode in an exemplary embodiment of this disclosure. Figure 10B Taking the second metal layer as an example, which uses a hollow structure, as an example. Figure 10B As shown, in a plane parallel to the electrode array structure, the hollow structure may include: a spiral-shaped hollow region 801 and a spiral-shaped non-hollow region 802 spaced apart.

[0119] In one exemplary embodiment, Figure 10C This is a schematic diagram of a third structure of the second metal layer of the electrode in an exemplary embodiment of this disclosure. Figure 10DThis is a schematic diagram of a fourth structure of the second metal layer of the electrode in an exemplary embodiment of this disclosure. Figure 10C and Figure 10D Taking the second metal layer as an example, which uses a hollow structure, for instance... Figure 10C and Figure 10D As shown, in a plane parallel to the electrode array structure, the hollow structure may include: multiple main body portions 901 extending along the first direction D1, multiple second spacing portions 902 extending along the first direction D1, multiple first connecting portions 903 extending along the second direction D2, and multiple second connecting portions 904 extending along the second direction. The main body portions 901 and the second spacing portions 902 are alternately arranged along the second direction D2, and the first connecting portions 903 and the second connecting portions 904 are alternately arranged along the second direction D2. The second end of the i-th main body portion is connected to the first end of the i-th first connecting portion, the second end of the i-th first connecting portion is connected to the second end of the (i+1)-th main body portion, the first end of the (i+1)-th main body portion is connected to the first end of the i-th second connecting portion, and the second end of the i-th second connecting portion is connected to the first end of the (i+2)-th main body portion. i is a positive integer greater than or equal to 1, and the second direction intersects the first direction.

[0120] In one exemplary embodiment, such as Figure 10C As shown, the dimensions of the plurality of main body portions 901 are all the same along the first direction D1, and the dimensions of the plurality of second spacing portions 902 are all the same along the first direction D1, or, as... Figure 10D As shown, the dimensions of multiple main body portions 901 increase sequentially along the first direction D1 in the second direction D2, and the dimensions of multiple second spacing portions 902 increase sequentially along the first direction D1.

[0121] In one exemplary embodiment, the circuit unit mentioned in this disclosure is a region divided according to a circuit structure layer, and each circuit unit may include a control circuit. The repeating unit and electrode unit mentioned in this disclosure are regions divided according to an electrode structure layer, and each electrode unit may include an electrode. In one exemplary embodiment, the positions of the repeating unit, the electrode, and the circuit unit may be corresponding, or the positions of the repeating unit, the electrode, and the circuit unit may not be corresponding.

[0122] The technical solution of this embodiment is illustrated below through an example of the fabrication process of the electrode array structure. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are known and mature fabrication processes. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, which are not limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0123] The following description uses the second electrode and the second control circuit as examples, and the second control circuit includes the second transistor Mse as an example, to illustrate the electrode array structure provided in at least one embodiment of the present disclosure.

[0124] In one exemplary embodiment, the electrode array structure may include, in a direction perpendicular to the substrate, a substrate and a first conductive layer, an insulating layer, a semiconductor layer, a second conductive layer, a passivation layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate. Here, in this embodiment, "sequentially stacked" means that the first conductive layer, insulating layer, semiconductor layer, second conductive layer, passivation layer, third conductive layer, fourth conductive layer, and fifth conductive layer are stacked in a direction away from the substrate, but does not necessarily mean that these layers are necessarily bonded together in pairs.

[0125] Below Figure 9 Taking the electrode array structure shown as an example, the fabrication process of the electrode array structure provided in the exemplary embodiments of this disclosure will be described in conjunction with the accompanying drawings.

[0126] In one exemplary embodiment, the method for fabricating an electrode array structure may include the following steps:

[0127] (1) Provide a substrate.

[0128] In one exemplary embodiment, the substrate can be a rigid substrate, such as a glass substrate or a silicon substrate; or, the substrate can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), cellulose triacetate (TAC), cyclic olefin polymers (COP), or cyclic olefin copolymers (COC). The embodiments described herein all use a silicon substrate as an example; however, the embodiments of this disclosure are not limited thereto.

[0129] (2) A first conductive layer is formed on the substrate.

[0130] In one exemplary embodiment, a first conductive layer is formed on the substrate using a patterning process. For example, a first conductive material layer is formed on the substrate using chemical vapor deposition (PVD), and then the first conductive material layer is subjected to a photolithography process to form the first conductive layer. Figure 11 As shown, the first conductive layer may include: the control electrode 201 of the transistor.

[0131] In one exemplary embodiment, the first conductive layer may be referred to as the bottom gate electrode layer.

[0132] In one exemplary embodiment, the material of the first conductive layer can be a metallic material. In one exemplary embodiment, the first metal thin film can be a metallic material, such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or it can be a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum-doped zinc oxide (AlZnO), etc., and can be a single-layer structure or a multi-layer composite structure.

[0133] In one exemplary embodiment, the first conductive layer may include a control electrode 201 of a transistor constituting a control circuit in a circuit unit. The control circuit may include at least one of a first control circuit 31 connected to the first electrode and a second control circuit 32 connected to the second electrode. For example, if the control circuit may include a first control circuit 31 connected to the first electrode and a second control circuit 32 connected to the second electrode, and the first control circuit 31 includes a first transistor Med, and the second control circuit 32 includes a second transistor Mse, a third transistor Msf, and a fourth transistor Mrst, then the first conductive layer may include the gate electrode of the first transistor Med, the gate electrode of the second transistor Mse, the gate electrode of the third transistor Msf, and the gate electrode of the fourth transistor Mrst.

[0134] (3) An insulating layer, a semiconductor layer and a second conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed.

[0135] In one exemplary embodiment, an insulating material layer, a semiconductor material layer, and a second conductive material layer are formed on a first conductive layer. Then, a photolithography process is performed on the second conductive material layer to form an insulating layer 301, a semiconductor layer, and a second conductive layer, as shown below. Figure 11 As shown.

[0136] In one exemplary embodiment, the insulating layer may be referred to as the gate insulating layer, and the second conductive layer may be referred to as the source / drain metal layer.

[0137] In one exemplary embodiment, such as Figure 11 As shown, the semiconductor layer may include: an active layer 202 of a transistor constituting the control circuit in the circuit unit; the second conductive layer may include: a first electrode 203 and a second electrode 204 of the transistor constituting the control circuit in the circuit unit; and the control circuit may include at least one of a first control circuit connected to the first electrode and a second control circuit connected to the second electrode. For example, the semiconductor layer may include: an active layer of a first transistor Med, an active layer of a second transistor Mse, an active layer of a third transistor Msf, and an active layer of a fourth transistor Mrst. The second conductive layer may include: the first and second electrodes of the first transistor Med, the first and second electrodes of the second transistor Mse, the first and second electrodes of the third transistor Msf, and the first and second electrodes of the fourth transistor Mrst.

[0138] In one exemplary embodiment, the gate insulating material layer may be silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure, and may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0139] In one exemplary embodiment, the second conductive material layer can be one or more of the following metals: aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, chromium, etc. It can be a single-layer, double-layer, or multi-layer structure, and can be deposited using a radio frequency magnetron sputtering method.

[0140] (4) A passivation layer 302 is formed on the substrate on which the aforementioned structure is formed, and a via K is formed on the passivation layer 302 to expose the first electrode 203, such as Figure 11 As shown.

[0141] In one exemplary embodiment, a passivation material layer is deposited on a substrate forming the aforementioned structure; a photoresist layer is coated on the passivation material layer, and the photoresist is exposed and developed using a monochrome mask to form an exposed area without photoresist at the via location, while an unexposed area is formed at other locations, retaining the photoresist; the fully exposed area is etched by an etching process to etch away the second insulating material layer in that area, forming a passivation layer 302 with via K, exposing the first electrode 203 through the via.

[0142] In one exemplary embodiment, the passivation material layer can be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and can be a single-layer, double-layer, or multi-layer structure. It can be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0143] (5) A third conductive layer and a fourth conductive layer are sequentially formed on the substrate on which the aforementioned structure is formed. For example, the third conductive layer may be referred to as the first metal layer 401, and the fourth conductive layer may be referred to as the second metal layer 402.

[0144] In one exemplary embodiment, such as Figures 12 to 15As shown, a third conductive material layer is deposited on the substrate forming the aforementioned structure. A photolithography process is then performed on the third conductive material layer to form a third conductive layer (i.e., the first metal layer 401). The third conductive layer is connected to the first electrode 203 through vias K, allowing the subsequently formed first or second electrode to be connected to the transistor in the aforementioned structure. Next, a layer of photoresist is coated on the passivation layer 302 in the area not covered by the third conductive layer. The photoresist is exposed using a mask to form a first photoresist pattern layer 701. A fourth conductive material layer is deposited on the first photoresist pattern layer 701. A photolithography process is performed on four conductive material layers to form a fourth conductive layer (i.e., the second metal layer 402). A layer of photoresist is coated on the area of ​​the first photoresist pattern layer 701 not covered by the fourth conductive layer. The photoresist is exposed using a mask to form the second photoresist pattern layer 702. The second photoresist pattern layer 702 and the first photoresist pattern layer 701 are developed to remove the photoresist beneath the area of ​​the fourth conductive layer not covered by the third conductive layer, forming a cavity. A portion of the fourth conductive layer is suspended in the cavity, forming a suspended portion 402B, resulting in a first electrode or a second electrode comprising two metal structures. Thus, since a portion of the fourth conductive layer is not adhered to the passivation layer or other components in the circuit structure layer, a portion of the first electrode or second electrode can move or float within the cavity, thereby forming an electrode array structure whose spatial position is variable or controllable. Furthermore, in practical brain-computer interface applications, electrodes at specific sites in the cerebral cortex or gray matter can be implanted as needed. For example, in invasive or non-invasive brain-computer interface applications, electrodes can be placed at locations in the nerves (or tissues) of the target subject according to the actual situation, which is more flexible.

[0145] In one exemplary embodiment, the third and fourth conductive material layers can be one or more of the following metallic materials: aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, and chromium. For example, they can be single-layer, double-layer, or multi-layer structures. For example, they can be deposited using a radio frequency magnetron sputtering method.

[0146] (6) A fifth conductive layer is formed on the substrate on which the aforementioned structure is formed.

[0147] In one exemplary embodiment, such as Figures 16 to 17As shown, a fifth conductive material layer 5011 is deposited on the substrate forming the aforementioned structure; a layer of photoresist is coated on the fifth conductive material layer, and the photoresist is subjected to step exposure and development using a halftone or grayscale mask. An unexposed area with a certain thickness of photoresist is formed at the microneedle electrode position, and a fully exposed area without photoresist is formed at other positions, resulting in a third photoresist pattern layer 801; under the action of plasma, the fifth conductive layer (i.e., the microneedle electrode 501) is formed through anisotropic etching; the third photoresist pattern layer 801 is developed to remove the photoresist above the fifth conductive layer. Thus, since the microneedle electrode is disposed on the suspended portion of the first or second electrode, a movable or floating microneedle electrode that does not adhere to the passivation layer or other components can be obtained. Furthermore, in the electrode array structure, the array composed of microneedle electrodes in multiple repeating units can be similar to the Utah electrode array and the Michigan electrode array.

[0148] In one exemplary embodiment, the microneedle electrode is tapered.

[0149] In one exemplary embodiment, the fifth conductive material layer can be one or more of the following metals: aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, chromium, etc., or it can be a semiconductor material such as silicon or germanium, and can be a single-layer, double-layer, or multi-layer structure, and can be deposited using a radio frequency magnetron sputtering method.

[0150] Thus, the preparation was completed. Figure 9 The electrode array structure shown.

[0151] The structures and their fabrication processes shown in this disclosure are merely illustrative. In one exemplary embodiment, the corresponding structures and patterning processes can be modified and added or reduced according to actual circumstances.

[0152] This disclosure also provides an exemplary embodiment of an electrode array structure, wherein the electrode array structure is the electrode array structure as described in one or more exemplary embodiments above, and the fabrication method includes:

[0153] S1. A circuit structure layer is formed on a substrate. The circuit structure layer includes: multiple circuit units, multiple row control signal lines and multiple column control signal lines. Each circuit unit includes: at least one of a first control circuit and a second control circuit.

[0154] S2. An electrode structure layer is formed on the side of the circuit structure layer away from the substrate. The electrode structure layer includes: a plurality of electrode units. Each electrode unit includes: at least one of a first electrode and a second electrode. At least one of the first electrode and the second electrode is a single metal structure or a multi-layer metal structure. The multi-layer metal structure includes: a first metal layer and a second metal layer stacked sequentially. The orthogonal projection of the first metal layer on the substrate is located within the orthogonal projection of the second metal layer on the substrate.

[0155] In one exemplary embodiment, S2 may include:

[0156] S21. A first metal layer is formed on the side of the circuit structure layer away from the substrate.

[0157] S22. Photoresist is coated on the area of ​​the electrode structure layer that is not covered by the first metal layer, and the photoresist is exposed using a mask to form a first photoresist pattern layer.

[0158] S23. A second metal layer is formed on the first metal layer and the first photoresist pattern layer;

[0159] S24. Photoresist is coated on the area of ​​the first photoresist pattern layer that is not covered by the second metal layer, and the photoresist is exposed using a mask to form the second photoresist pattern layer.

[0160] S25. Develop the second photoresist pattern layer and the first photoresist pattern layer, remove the photoresist below the area of ​​the second metal layer that is not covered by the first metal layer, and form a cavity, such that at least one of the first electrode and the second electrode includes: a first region and a second region, the second region having a cavity, the first metal layer being located in the first region, and the second metal layer including: a support portion located in the first region and a suspended portion located in the second region connected in sequence, the support portion overlapping the first metal layer, and the suspended portion being suspended in the cavity.

[0161] In one exemplary embodiment, the fabrication method may further include: S3, forming a microneedle electrode on the side of the suspended portion away from the substrate.

[0162] Exemplary embodiments of this disclosure also provide a signal acquisition device, such as... Figure 2 As shown, the signal acquisition device may include: a row control circuit 21, a column control circuit 22, and an electrode array structure 23 as described in one or more exemplary embodiments above. The column control circuit 22 is connected to multiple column control signal lines (Source1 to Source2). n The horizontal control circuit 21 is connected to multiple horizontal control signal lines (SCAN1 to SCAN2). mThis allows for on-chip integration of the electrode array structure, row control circuitry, and column control circuitry. It facilitates the fabrication of the circuitry using semiconductor thin-film processing technology, simplifies the structure of the signal acquisition device, and reduces the use of dedicated chips and external processing circuits.

[0163] In one exemplary embodiment, on a plane parallel to the signal acquisition device, the signal acquisition device may include: an electrode region and a peripheral region surrounding the electrode region. An electrode array structure may be disposed in the electrode region, and row control circuits and column control circuits may be disposed in the peripheral region. For example, the row control circuit may be disposed on one side of a first direction of the electrode array structure, and the column control circuit may be disposed on one side of a second direction of the electrode array structure, the second direction intersecting the first direction.

[0164] In one exemplary embodiment, the row control circuitry can be configured as a shift register. For example, the row control circuitry may include multiple cascaded shift registers.

[0165] In one exemplary embodiment, the column control circuit can be configured as a data selector. For example, the column control circuit includes a plurality of data selectors MUX (first data selector MUX1 to nth data selector MUXn).

[0166] In one exemplary embodiment, Figure 18 This is a schematic diagram of an equivalent circuit of a signal acquisition device according to an exemplary embodiment of this disclosure. Figure 18 As shown, the signal acquisition device may include: a row control circuit 21, a column control circuit 22, and an electrode array structure 23. The column control circuit 22 is connected to multiple column control signal lines (Source1 to Source2). n The horizontal control circuit 21 is connected to multiple horizontal control signal lines (SCAN1 to SCAN2). mThe row control circuit 21 may include multiple cascaded shift registers. The column control circuit includes multiple data selectors MUX (first data selector MUX1 to nth data selector MUXn). The electrode array structure 23 may include multiple repeating units Pxij arranged in an array, where i and j can be natural numbers. At least one repeating unit Pxij may include a first electrode ED and a first control circuit 31 connected to the first electrode ED. The first control circuit 31 is configured to control the first electrode ED to output a stimulation signal to the target object under the control of the corresponding row control signal line SCAN and column control signal line Source. Thus, the repeating unit is composed of the first electrode and the first control circuit connected to the first electrode, and the multiple repeating units arranged in an array can realize an electrode array structure with a stimulation signal output network having a certain spatial resolution and resolution accuracy. Then, around the electrode array structure, special signal processing circuits such as row control circuits and column control circuits are constructed using transistor devices. This allows the addressing and write control signals of row 1 to m repeating units to be output sequentially in time, thereby compressing the number of signal lines in space and improving the utilization of row space. It also allows the write control signals of column 1 to n repeating units to be multiplexed, further compressing the number of signal lines in space and improving the utilization of column space. Furthermore, the row control circuits and column control circuits can be fabricated using semiconductor thin-film processing technology, enabling on-chip integration of the electrodes and control circuits in the electrode array structure described in one or more exemplary embodiments.

[0167] In one exemplary embodiment, Figure 19 This is a schematic diagram of an equivalent circuit for another signal acquisition device in an exemplary embodiment of the present disclosure. (As shown in the image...) Figure 19 As shown, the signal acquisition device may include: a row control circuit 21, a column control circuit 22, and an electrode array structure 23. The column control circuit 22 is connected to multiple column control signal lines (Source1 to Source2). n The horizontal control circuit 21 is connected to multiple horizontal control signal lines (SCAN1 to SCAN2). mThe row control circuit 21 may include multiple cascaded shift registers. The column control circuit includes multiple data selectors MUX (from the first data selector MUX1 to the nth data selector MUXn). The electrode array structure may include multiple repeating units Pxij arranged in an array, where i and j can be natural numbers. At least one repeating unit Pxij may include a second electrode ES and a second control circuit 32 connected to the second electrode ES. The second control circuit 32 is configured to acquire the EEG signal of the target object through the second electrode ES under the control of the corresponding row control signal line SCAN and column control signal line Source. Thus, the repeating unit is composed of the second electrode and the second control circuit connected to the second electrode, and the multiple repeating units arranged in an array can realize an electrode array structure of an EEG signal acquisition network with a certain spatial resolution and resolution accuracy. Then, around the electrode array structure, special signal processing circuits such as row control circuits and column control circuits are constructed using transistor devices. This allows the addressing and write control signals of row 1 to m repeating units to be output sequentially in time, thereby compressing the number of signal lines in space and improving the utilization of row space. It also allows the write control signals of column 1 to n repeating units to be multiplexed, further compressing the number of signal lines in space and improving the utilization of column space. Furthermore, the row control circuits and column control circuits can be fabricated using semiconductor thin-film processing technology, enabling on-chip integration of the electrodes and control circuits in the electrode array structure described in one or more exemplary embodiments.

[0168] Of course, in addition to the above exemplary equivalent circuit diagram, other circuit structures can be adopted according to the actual structure of the repeating units in the electrode array structure. For example, a repeating unit comprising a first electrode, a first control circuit, a second electrode, and a second control circuit can be used to form a multi-electrode repeating unit. The multiple repeating units arranged in an array can realize an electrode array structure with a certain spatial resolution and resolution accuracy for both the stimulation signal output network and the EEG signal acquisition network. However, this disclosure does not limit the scope of the embodiments.

[0169] In one exemplary embodiment, a first control circuit and a second control circuit in an electrode array structure, as well as row control circuits and column control circuits surrounding the electrode array structure, can be fabricated using an integrated circuit field-effect transistor (MOSFET) fabrication process or a thin-film transistor (TFT) fabrication process.

[0170] The description of the signal acquisition device embodiments above is similar to the description of the electrode array structure embodiments above, and has similar beneficial effects. For technical details not disclosed in the signal acquisition device embodiments of this disclosure, those skilled in the art should refer to the description in the electrode array structure embodiments of this disclosure for understanding, and will not repeat them here.

[0171] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. An electrode array structure, characterized in that, For use in brain-computer interface systems, the electrode array structure includes: multiple repeating units arranged in an array, and multiple row control signal lines and multiple column control signal lines connected to the multiple repeating units; At least one repetitive unit includes an electrode unit and a circuit unit. The electrode unit includes at least one of a first electrode and a second electrode. The circuit unit includes at least one of a first control circuit connected to the first electrode and a second control circuit connected to the second electrode. The first control circuit is configured to control the first electrode to output a stimulation signal to the target object under the control of corresponding row control signal lines and column control signal lines. The second control circuit is configured to acquire the electroencephalogram (EEG) signal of the target object through the second electrode under the control of corresponding row control signal lines and column control signal lines. In a direction perpendicular to the electrode array structure, the electrode array structure includes: a substrate, a circuit structure layer disposed on one side of the substrate, and an electrode structure layer disposed on the side of the circuit structure layer away from the substrate; wherein, The circuit structure layer includes: a plurality of circuit units, a plurality of row control signal lines, and a plurality of column control signal lines; The electrode structure layer includes: a plurality of electrode units, wherein at least one of the first electrode and the second electrode is a single metal structure or a multi-layer metal structure, wherein the multi-layer metal structure includes: a first metal layer and a second metal layer stacked sequentially, wherein the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate; At least one of the first electrode and the second electrode includes: a first region and a second region, the second region having a cavity, the first metal layer being located in the first region, and the second metal layer including: a support portion located in the first region and a suspended portion located in the second region connected in sequence, the support portion overlapping the first metal layer, and the suspended portion being suspended in the cavity; At least one of the first electrode and the second electrode further includes a microneedle electrode disposed on the side of the suspended portion away from the substrate.

2. The electrode array structure according to claim 1, characterized in that, The first control circuit includes: a first transistor, the control electrode of the first transistor being connected to the row control signal line, the first electrode of the first transistor being connected to the column control signal line, and the second electrode of the first transistor being connected to the first electrode.

3. The electrode array structure according to claim 1 or 2, characterized in that, The second control circuit includes: a first sub-circuit, a second sub-circuit, and a third sub-circuit; The first sub-circuit is connected to the row control signal line, the column control signal line and the first node respectively, and is configured to provide the column control signal line signal to the first node under the control of the signal of the row control signal line. The second sub-circuit is connected to the first power supply terminal, the first node, and the second node, respectively, and is configured to provide the signal from the first power supply terminal to the first node under the control of the second node. The third sub-circuit is connected to the reset signal terminal, the second power supply terminal, and the second node, respectively, and is configured to provide the second power supply terminal signal to the second node under the control of the reset signal terminal signal. The second electrode, connected to the second node, is configured to acquire electroencephalogram (EEG) signals.

4. The electrode array structure according to claim 3, characterized in that, The first sub-circuit includes: a second transistor, the first terminal of the second transistor being connected to the first node, the second terminal of the second transistor being connected to the column control signal line, and the control terminal of the second transistor being connected to the row control signal line; The second sub-circuit includes: a third transistor, wherein the control electrode of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first power supply terminal, and the second electrode of the third transistor is connected to the first node; The third sub-circuit includes: a fourth transistor, the control electrode of the fourth transistor being connected to the reset signal terminal, the first electrode of the fourth transistor being connected to the second power supply terminal, and the second electrode of the fourth transistor being connected to the second node.

5. The electrode array structure according to claim 1 or 2, characterized in that, The second control circuit includes: a second transistor, the first terminal of the second transistor being connected to the second electrode, the second terminal of the second transistor being connected to the column control signal line, and the control terminal of the second transistor being connected to the row control signal line.

6. The electrode array structure according to claim 1, characterized in that, The microneedle electrode is conical in shape.

7. The electrode array structure according to claim 1 or 6, characterized in that, The second metal layer can be either a comb-like structure or a hollow structure.

8. The electrode array structure according to claim 7, characterized in that, In a plane parallel to the electrode array structure, the comb-like structure includes: a first region extending along a first direction and a second region located on one side of the first region along the first direction. The second region includes: protrusions and first intervals alternately arranged along a second direction. The size of the protrusions gradually decreases along the first direction, and the size of the first intervals gradually increases along the first direction. The second direction intersects the first direction.

9. The electrode array structure according to claim 7, characterized in that, In a plane parallel to the electrode array structure, the hollow structure includes: a spiral-shaped hollow area and a spiral-shaped non-hollow area spaced apart.

10. The electrode array structure according to claim 7, characterized in that, In a plane parallel to the electrode array structure, the hollow structure includes: multiple main body portions extending along a first direction, multiple second interval portions extending along the first direction, multiple first connecting portions extending along a second direction, and multiple second connecting portions extending along the second direction. The main body portions and second interval portions are alternately arranged along the second direction, and the first connecting portions and second connecting portions are alternately arranged along the second direction. The second end of the i-th main body portion is connected to the first end of the i-th first connecting portion, the second end of the i-th first connecting portion is connected to the second end of the (i+1)-th main body portion, the first end of the (i+1)-th main body portion is connected to the first end of the i-th second connecting portion, and the second end of the i-th second connecting portion is connected to the first end of the (i+2)-th main body portion. i is a positive integer greater than or equal to 1, and the second direction intersects the first direction.

11. The electrode array structure according to claim 10, characterized in that, The dimensions of the plurality of main body portions along the first direction are all the same, and the dimensions of the plurality of second spacing portions along the first direction are all the same; or, the dimensions of the plurality of main body portions along the first direction increase sequentially in the second direction, and the dimensions of the plurality of second spacing portions along the first direction increase sequentially.

12. A method for fabricating an electrode array structure, characterized in that, The electrode array structure is the electrode array structure as described in any one of claims 1 to 11, and the preparation method includes: The circuit structure layer is formed on one side of the substrate, and the circuit structure layer includes: the plurality of circuit units, the plurality of row control signal lines and the plurality of column control signal lines, and each circuit unit includes: at least one of the first control circuit and the second control circuit; An electrode structure layer is formed on the side of the circuit structure layer away from the substrate. The electrode structure layer includes the plurality of electrode units, each electrode unit including at least one of a first electrode and a second electrode. At least one of the first electrode and the second electrode is a single metal structure or a multi-layer metal structure. The multi-layer metal structure includes a first metal layer and a second metal layer stacked sequentially. The orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the second metal layer on the substrate. The formation of the electrode structure layer on the side of the circuit structure layer away from the substrate includes: The first metal layer is formed on the side of the circuit structure layer away from the substrate. Photoresist is coated on the area of ​​the electrode structure layer not covered by the first metal layer, and the photoresist is exposed using a mask to form a first photoresist pattern layer. A second metal layer is formed on the first metal layer and the first photoresist pattern layer; Photoresist is coated on the area of ​​the first photoresist pattern layer that is not covered by the second metal layer, and the photoresist is exposed using a mask to form the second photoresist pattern layer. The second photoresist pattern layer and the first photoresist pattern layer are developed to remove the photoresist below the area of ​​the second metal layer that is not covered by the first metal layer, forming the cavity, such that at least one of the first electrode and the second electrode includes: a first region and a second region, the second region having the cavity, the first metal layer being located in the first region, and the second metal layer including: a support portion located in the first region and a suspended portion located in the second region connected in sequence, the support portion overlapping the first metal layer, and the suspended portion suspended in the cavity; and The microneedle electrode is formed on the side of the suspended portion away from the substrate.

13. A signal acquisition device, characterized in that, The signal acquisition device, applied to a brain-computer interface system, comprises: a row control circuit, a column control circuit, and an electrode array structure as described in any one of claims 1 to 11, wherein the column control circuit is connected to the plurality of column control signal lines respectively, and the row control circuit is connected to the plurality of row control signal lines respectively.

Images