Processing circuit and processing device for electrocardiosignal

Abstract

The application is suitable for the technical field of biomedical engineering, and provides a processing circuit and a processing device for electrocardiosignal, the processing circuit comprising: an electrocardiosignal input electrode, a first feedback module, two impedance boosting capacitors and a second feedback module, wherein the first feedback module comprises a switched capacitor, a first high-pass cutoff loop and a second high-pass cutoff loop, the input ends of the first high-pass cutoff loop and the second high-pass cutoff loop are coupled to the output end of the switched capacitor, the first output ends are respectively coupled to one end of one impedance boosting capacitor, the second output ends are respectively coupled to the output end of the switched capacitor, the input end of the second feedback module is coupled to the output end of the switched capacitor and comprises an output capacitor and a control unit, and the control unit is used for triggering the input end of the output capacitor to be coupled to a voltage end when the amplitude of the electrocardiosignal exceeds a threshold value of a dead zone preset in advance. Through the above scheme, the interference signal caused by human body movement in the electrocardiosignal can be effectively inhibited.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of biomedical engineering, and particularly relates to a processing circuit and processing device of an electrocardiosignal. BACKGROUND

[0002] An electrocardiosignal can comprehensively reflect various changes in the physiology of a human body, and is of great significance for the diagnosis and treatment of patients with cardiogenic diseases. Since the amplitude of an electrocardiosignal is as low as a microvolt level, and interference signals generated during movement can seriously affect the collection and recognition performance of an electrocardiosignal, the current traditional electrocardio monitoring technology usually requires a user to be in a quiet scene such as lying or sitting still, so as to realize high-quality signal collection. However, in order to obtain comprehensive and objective electrocardiosignal data to assist treatment, it is necessary to monitor heart activity in real time all day long, and therefore, during human movement, how to effectively suppress interference signals generated due to human movement in an electrocardiosignal is a key problem that must be solved. SUMMARY

[0003] The application aims to provide a processing circuit and processing device of an electrocardiosignal, which can effectively suppress interference signals generated due to human movement in an electrocardiosignal when a human body is in a movement state.

[0004] A first aspect of the embodiment of the application provides a processing circuit of an electrocardiosignal, which comprises:

[0005] an electrocardiosignal input electrode, a first feedback module, and two impedance boosting capacitors, the first feedback module comprising a switched capacitor, a first high-pass cutoff loop, and a second high-pass cutoff loop, the input ends of the first high-pass cutoff loop and the second high-pass cutoff loop being coupled to the output end of the switched capacitor, the first output ends of the first high-pass cutoff loop and the second high-pass cutoff loop each being coupled to one end of one impedance boosting capacitor, the second output ends of the first high-pass cutoff loop and the second high-pass cutoff loop each being coupled to the output end of the switched capacitor, the other end of each impedance boosting capacitor and the electrocardiosignal input electrode being coupled to the input end of the switched capacitor together, and a first feedback capacitor and a first chopping element being arranged in series on the second high-pass cutoff loop; and

[0006] a second feedback module, the input end of the second feedback module being coupled to the output end of the switched capacitor, and comprising an output capacitor and a control unit, the output end of the output capacitor being coupled between the first feedback capacitor and the first chopping element on the second high-pass cutoff loop, and the control unit being configured to trigger the input end of the output capacitor to be coupled to a voltage end when the amplitude of the electrocardiosignal exceeds a threshold value of a dead zone.

[0007] In an optional embodiment, between the electrocardiosignal input electrode and the input end of the first high-pass cutoff circuit, further comprising:

[0008] a second chopper element, an input end of the second chopper element being coupled to the electrocardiosignal input electrode, an output end of the second chopper element being coupled to an input end of the switched capacitor;

[0009] a first amplification element, an input end of the first amplification element being coupled to an output end of the switched capacitor;

[0010] a third chopper element, an input end of the third chopper element being coupled to an output end of the first amplification element;

[0011] a second amplification element, an input end of the second amplification element being coupled to an output end of the third chopper element, an output end of the second amplification element being coupled to input ends of the first high-pass cutoff circuit and the second high-pass cutoff circuit.

[0012] In an optional embodiment, the first high-pass cutoff circuit further comprises:

[0013] a fourth chopper element, an input end of the fourth chopper element being coupled to an input end of the first high-pass cutoff circuit;

[0014] a second feedback capacitor, an input end of the second feedback capacitor being coupled to an output end of the fourth chopper element, an output end of the second feedback capacitor being coupled to an output end of the switched capacitor.

[0015] In an optional embodiment, the second high-pass cutoff circuit further comprises:

[0016] an integration device, an input end of the integration device being coupled to an input end of the second high-pass cutoff circuit, an output end of the integration device being coupled to an input end of the first chopper element.

[0017] In an optional embodiment, the second feedback module further comprises:

[0018] an analog-to-digital conversion module, an input end of the analog-to-digital conversion module being coupled to input ends of the first high-pass cutoff circuit and the second high-pass cutoff circuit, an output end of the analog-to-digital conversion module being coupled to an external display processing device, so as to transmit a digital signal of the electrocardiosignal to the external display processing device;

[0019] a timing module, an input end of the timing module being coupled to an output end of the analog-to-digital conversion module, an output end of the timing module being coupled to the external display processing device, so as to transmit time characteristic data of the electrocardiosignal to the external display processing device.

[0020] In an optional embodiment, the analog-to-digital conversion module comprises:

[0021] a digital-to-analog conversion element, an input of which is coupled to inputs of the first high-pass cutoff circuit and the second high-pass cutoff circuit;

[0022] a microprocessor, an input of which is coupled to an output of the digital-to-analog conversion element;

[0023] a first input comparator, an input of which is coupled to an output of the microprocessor;

[0024] a first logic device, an input of which is coupled to an output of the first input comparator, a first output of which is coupled to the digital-to-analog conversion element, and a second output of which is coupled to the external display processing device.

[0025] In an optional embodiment, the analog-to-digital conversion module further comprises:

[0026] a second input comparator, an input of which is coupled between an output of the digital-to-analog conversion element and an input of the microprocessor, and an output of which is coupled to an input of the microprocessor;

[0027] a second logic device, an input of which is coupled to an output of the second input comparator;

[0028] a signal synthesis device, a first input of which is coupled to a second output of the first logic device, a second input of which is coupled to an output of the second logic device, and an output of which is coupled to the external display processing device.

[0029] In an optional embodiment, the timing module comprises:

[0030] a counting element, an input of which is coupled to an output of the signal synthesis device, and an output of which is coupled to the external display processing device;

[0031] In an optional embodiment, the timing module further comprises:

[0032] a triggering element, an input of which is coupled to an output of the signal synthesis device;

[0033] a sampling element, an input of which is coupled to an output of the triggering element;

[0034] an oscillation device, which is coupled to the sampling element;

[0035] a decoding device, an input of the decoding device being coupled to an output of the sampling element;

[0036] a third logic device, an input of the third logic device being coupled to an output of the decoding device, an output of the third logic device being coupled to the external display processing device.

[0037] The second aspect of the embodiment of the application provides a processing device of an electrocardiosignal, the processing device comprising:

[0038] the processing circuit as described in the first aspect above; and,

[0039] a display processing device, the display processing device being coupled to the processing circuit to acquire a digital signal and time characteristic data of the electrocardiosignal and display the electrocardiosignal after restoration processing.

[0040] The present application has the advantage

[0041] The electrocardiosignal processing circuit provided by the application comprises an electrocardiosignal input electrode, a first feedback module, a second feedback module and two impedance boosting capacitors. The first feedback module comprises a switched capacitor, a first high-pass cutoff loop and a second high-pass cutoff loop, the second high-pass cutoff loop is provided with a first feedback capacitor, the second feedback module comprises an output capacitor and a control unit. In the entire circuit architecture, the two impedance boosting capacitors and the branches in which they are located can improve the input impedance of the circuit and prevent the attenuation of the input signal. At the same time, the first high-pass cutoff loop and the second high-pass cutoff loop provided inside the first feedback module have a certain high-pass cutoff frequency and can suppress interference signals within a certain range. On the basis of the first feedback module, when the second feedback module detects that the amplitude of the electrocardiosignal exceeds the threshold value of the dead zone preset in advance, the input end of the output capacitor is coupled to a voltage end by the control unit, so that the output capacitor in the second feedback module and the first feedback capacitor in the first feedback module combine to form an equivalent feedback capacitor, thereby increasing the high-pass cutoff frequency of the processing circuit and achieving further suppression of interference signals in the electrocardiosignal. Through the above overall circuit architecture, a complete electrocardiosignal with lower interference signals can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0043] Figure 1An architecture schematic diagram of an analog front-end circuit provided by an embodiment of the present application is provided.

[0044] Figure 2 A schematic diagram of an electrocardiosignal provided by an embodiment of the present application is provided.

[0045] Figure 3 A structure schematic diagram of a processing circuit of an electrocardiosignal provided by an embodiment of the present application is provided.

[0046] Figure 4 An input impedance comparison schematic diagram provided by an embodiment of the present application is provided.

[0047] Figure 5 A structure schematic diagram of a timing module circuit provided by an embodiment of the present application is provided.

[0048] Figure 6 A comparison diagram of an electrocardiosignal processing provided by an embodiment of the present application is provided.

[0049] Figure 7 A structure schematic diagram of a processing device of an electrocardiosignal provided by an embodiment of the present application is provided.

[0050] Figure 8 A structure schematic diagram of a terminal device provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0051] In the following description, for the purposes of explanation and not limitation, specific details are set forth, such as particular sequences of acts, techniques, etc. in order to provide a thorough understanding of the embodiments of the application. However, it will be apparent to those skilled in the art that the embodiments of the application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the embodiments of the application with unnecessary detail.

[0052] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", when used in this specification and in the following claims, indicates the presence of the described features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0053] It is also to be understood that the terminology "and / or" when used in this specification and in the following claims, refers to at least one of the items, or any combination of one or more of the items, listed by this term.

[0054] As used in the specification and in the claims, the term “if’ can be interpreted as meaning “when,” or “upon,” or “in response to a determination,” or “in response to a detection” depending on the context. Similarly, the phrase “if it is determined” or “if [the described condition or event] is detected” can be interpreted as meaning “upon a determination” or “in response to a determination” or “upon a detection of [the described condition or event]” or “in response to a detection of [the described condition or event],” depending on the context.

[0055] In addition, in the description of the present application and the appended claims, the terms “first”, “second”, “third”, etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0056] In the present application, the reference “one embodiment” or “some embodiments” and the like means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the present application. Therefore, the statements “in one embodiment”, “in some embodiments”, “in other some embodiments”, “in further some embodiments” and the like appearing in different places in the specification are not necessarily all referring to the same embodiment, but mean “one or more but not all embodiments”, unless otherwise specifically emphasized. The terms “include”, “contain”, “have” and their variants mean “include but not limited to”, unless otherwise specifically emphasized.

[0057] It should be understood that the size of the serial number of each step in the embodiments does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0058] At present, cardiogenic diseases have high accidentality and suddenness, so it is difficult to predict and prevent in advance. The traditional prevention method for such diseases is usually to regularly perform professional examination, and the traditional medical monitoring equipment, similar to dynamic electrocardiograph, can accurately record the electrocardio signal of the human body and analyze the health status of the heart, but it is bulky, few in number, high in cost, and requires a large amount of manpower and material resources for each examination operation, which not only brings great inconvenience to patients, but more importantly, it is difficult to monitor the heart health status of patients in daily life for a long time.

[0059] In this regard, there are many portable electrocardio signal monitoring products on the market, the main principle of which is to form an electrocardio detection loop by touching the electrodes integrated on the watch test button with fingers, so as to realize short-term arrhythmia monitoring. Since the detection loop needs to be constructed by the conscious action of the patient touching the test button electrode with the fingers to form a dual-lead electrocardio monitoring, this type of equipment cannot meet the demand of all-weather real-time monitoring of heart activity.

[0060] To solve the above problems, researchers have proposed to use wearable fabric electronic medical devices to monitor the user's ECG signal in real time. This device has the advantages of low power consumption, low cost and high portability. By setting the fabric electrode on the designated monitoring part of the human body, the monitoring of various biological signals of the human body can be realized without affecting the user's normal life and work. However, due to the fact that the ECG signal itself is very weak, with an amplitude as low as microvolts, the use of general analog front-end circuit cannot realize high-quality signal acquisition. Therefore, in order to realize high-precision real-time capture of the tiny ECG signal, even in the case of low power consumption, the analog front-end circuit of the wearable fabric electronic medical device needs to have the characteristics of low input reference noise and high input impedance, so that the ECG signal can be processed and analyzed more accurately by the rear-end circuit.

[0061] In addition, in the case of normal life and work, the user will inevitably have a lot of activities, so the monitored ECG signal contains a lot of interference signals generated in the walking, running, fitness and other motion scenarios, such as motion artifacts and electrode DC offset. The existence of the above interference signals will seriously affect the acquisition and recognition performance of the ECG signal. Correspondingly, the analog front-end circuit for ECG signal acquisition and processing needs to not only meet the requirements of low power consumption, small area and high input impedance, but also needs to realize the elimination or suppression of various interference signals in order to realize high signal-to-noise ratio and high linearity of the acquisition and amplification of the ECG signal.

[0062] Therefore, the design of a multifunctional and high-performance analog front-end circuit has great challenges: 1) The wearable electronic medical device is powered by a battery and needs to work continuously for a long time, so the power consumption of the analog front-end circuit must be reduced accordingly; 2) Due to the weak amplitude (μV-mV order) and low frequency of physiological electrical signals, they are easily disturbed, so the analog front-end circuit needs to have an extremely low noise amplifier and an extremely large time constant filter, and it needs to be realized in a limited chip area; 3) There are electrode DC offset, power frequency interference, motion artifacts and other disturbances in the circuit, so the analog front-end circuit needs to be able to suppress and eliminate various environmental disturbances. In order to prevent signal attenuation during acquisition, the analog front-end circuit also needs to have a large input impedance.

[0063] Since the original ECG signal is an analog signal, the analog signal will be disturbed by various noises during signal transmission, resulting in distortion of the original signal. Digital signals have strong anti-interference ability and are easy to process by computers. Therefore, the earlier the analog-to-digital conversion is, the more conducive it is to the accuracy of ECG signal analysis and processing. Therefore, a direct digital analog-to-digital converter (Analog-Digital Converter, ADC) has become the development direction of wearable fabric electronic medical devices.

[0064] According to the above description, the present application provides an analog front-end circuit architecture for monitoring an ECG signal,Figure 1 An architecture schematic of an analog front-end circuit is shown, and the architecture schematic is provided by an embodiment of the present application, which is described with reference to Figure 1 The analog front-end circuit architecture includes an electrocardiosignal input electrode E1, a pre-amplification module M1, an analog-to-digital conversion module LC-ADC, a timing module TDC, and a digital auxiliary feedback loop DAL.

[0065] In the above analog front-end circuit architecture, since a comfortable fabric electrode is used as a sensor to capture a weak electrocardiosignal, the analog front-end circuit of the fabric electronic medical device needs to consider a high input impedance in design, and the pre-amplification module M1 ensures that the entire analog front-end circuit can obtain a complete ECG signal. When a large interference signal such as a motion artifact / electrode direct current offset (MA / EDO) is superimposed on the electrocardiosignal, in order to break the contradiction between the small signal capture and the large signal saturation of the LC-ADC and realize a high dynamic range, the present application further sets the digital auxiliary feedback loop DAL, obtains a direct current component in the output signal of the analog-to-digital conversion module LC-ADC, and feeds back the direct current component to an input node of the pre-amplification module M1 through an adaptive prediction algorithm and a DAC. The pre-amplification module M1 and the digital auxiliary feedback loop DAL jointly act to increase a high-pass cutoff frequency of the circuit, thereby effectively suppressing or eliminating the motion artifact and the electrode direct current offset and other interference signals in the signal.

[0066] It should be noted that the high-pass cutoff frequency means that a signal higher than a preset frequency is a passband, and a signal lower than the preset frequency is a stopband, that is, a signal greater than the preset frequency can pass through, and a signal less than the preset frequency is filtered out. The interference signals existing in the electrocardiosignal, such as the motion artifact and the electrode direct current offset, are all noise signals near 0 Hz, and therefore, increasing the high-pass cutoff frequency of the circuit can filter out more interference signals.

[0067] For example, the analog-to-digital conversion module LC-ADC can use a Level-crossing digitization module, which has a different working principle from that of a traditional Nyquist ADC. The working principle of the Level-crossing digitization module is to sample a signal based on amplitude variation, and sampling is only performed when the signal exceeds the upper and lower thresholds of the amplitude window predefined in advance. Figure 2 As shown in FIG. 6, the electrocardiosignal is a low-frequency signal, and the effective information of the electrocardiosignal is concentrated in the QRS segment, and the baseline part between every two electrocardiosignals is relatively smooth. Most of the samples collected by the Level-crossing digitization module come from the QRS segment of the electrocardiosignal, and only a small part is the baseline part.

[0068] In the analog front-end circuit architecture proposed in the present application, the electrocardiosignal of the user is input through the electrocardiosignal input electrode E1, the electrocardiosignal is preliminarily filtered and amplified by the pre-amplification module M1, the electrocardiosignal is converted into a digital signal by the analog-digital conversion module LC-ADC, and the digital auxiliary feedback loop DAL is turned on when the amplitude of the electrocardiosignal is detected to exceed the threshold value of the dead zone, so that the high-pass cutoff frequency of the analog front-end circuit architecture is increased by the joint action of the pre-amplification module M1 and the digital auxiliary feedback loop DAL, so as to suppress more interference signals such as electrode DC offset and motion artifact caused by human activity.

[0069] It should be noted that since the output format of the analog-digital conversion module LC-ADC is (t, p) = (increment of discrete time, discrete amplitude change polarity), when used as the input of the external display processing device, the timer Timer is required to record the discrete time increment between two LC events. It can be seen that, unlike the traditional Nyquist sampling ADC, the quantization noise of the LC-ADC does not depend on the size of the amplitude quantization window, but depends on the time accuracy between the adjacent two LC events, i.e. the ratio of the frequency of the timer Timer and the input signal bandwidth. Therefore, by setting the corresponding timing module TDC, the timing accuracy can be improved without increasing the clock frequency, and the signal-to-noise ratio of the analog-digital conversion module LC-ADC can be further improved.

[0070] It should be noted that the timing module TDC can be arranged inside or outside the analog-digital conversion module LC-ADC, without affecting the function implementation.

[0071] In order to illustrate the technical solutions of the present application, specific embodiments will be described below.

[0072] Figure 3 A structure schematic diagram of an electrocardiosignal processing circuit provided by an embodiment of the present application is shown.

[0073] Referring to Figure 3 , the processing circuit includes an electrocardiosignal input electrode E1, a first feedback module K1 and two impedance boosting capacitors C PF and C LPF , wherein the first feedback module K1 includes a switched capacitor C in , a first high-pass cutoff loop and a second high-pass cutoff loop, the input end P1 of the first high-pass cutoff loop and the second high-pass cutoff loop is coupled to the output end of the switched capacitor C in , the input end of the impedance boosting capacitor C PF is coupled to the first output end P2 of the first high-pass cutoff loop, and the second output end P3 of the first high-pass cutoff loop is coupled to the switched capacitor C inthe output terminal of the impedance boosting capacitor C LPF the input terminal of the second high-pass cutoff circuit P5 is coupled to the switch capacitor C in the output terminal of the impedance boosting capacitor C PF and C LPF the output terminal of the impedance boosting capacitor C in the input terminal of the switch capacitor C

[0074] It should be noted that the first feedback capacitor C DSL and the first chopping element Z1 are connected in series on the second high-pass cutoff circuit, the output terminal of the first feedback capacitor C DSL is coupled to the switch capacitor C in the output terminal of the first feedback capacitor C DSL is coupled to the output terminal of the first chopping element Z1, and the input terminal of the first chopping element Z1 is coupled to the input terminal P1 of the second high-pass cutoff circuit.

[0075] In other embodiments of the present application, the above-mentioned processing circuit further comprises a second feedback module K2, the input terminal of the second feedback module K2 is coupled to the output terminal of the switch capacitor C in , and comprises an output capacitor C DDSL and a control unit DAQ (Dgital-Assisted Quantification), the output terminal of the output capacitor C DDSL is coupled between the first feedback capacitor C DSL and the first chopping element Z1 on the second high-pass cutoff circuit, and the control unit DAQ is used to trigger the input terminal of the output capacitor C DDSL to be coupled to a voltage terminal VDD when the amplitude of the electrocardiosignal exceeds a preset threshold value of the dead zone.

[0076] It should be noted that the chopping technique can eliminate 1 / f noise and DC offset voltage, and improve the common-mode rejection ratio, but the high-frequency chopping frequency of the chopper will greatly reduce the input impedance of the circuit. In order to improve the input impedance, the prior art usually uses a positive feedback loop to improve the input impedance of the processing circuit, that is, the current at the output of the amplifier is provided to the switch capacitor circuit at the input of the amplifier through the positive feedback loop. Theoretically, if the DC current provided by the electrode is reduced to zero, the corresponding DC input impedance will be improved to infinity. However, the positive feedback circuit has the following two problems: the first problem is that the positive feedback loop is sensitive to the parasitic capacitance at the input node of the amplifier, which greatly limits the improvement of the input impedance; the second problem is that the positive feedback loop is driven by the output of the amplifier, and almost any analog front end will attenuate the DC signal at the output. Therefore, the positive feedback loop cannot provide the most needed DC current to the input terminal of the switch capacitor.

[0077] To this end, refer to Figure 3 , the present application adopts impedance boosting capacitor C PF and C LPF in the branch to form a composite impedance boosting circuit, compared with the positive feedback circuit, the composite impedance boosting circuit has lower noise, more compact structure, when the low frequency, integrator device G can drive the composite impedance boosting circuit to provide the required current to the branch where the switch capacitor C in , effectively improve the input impedance of the processing circuit, as Figure 4 shown, at near DC frequency, the composite impedance boosting circuit increases the input impedance by 157 times.

[0078] In the above embodiment of the present application, by adopting the first high-pass cutoff circuit, the second high-pass cutoff circuit and two impedance boosting capacitors to provide the required DC current to the switch capacitor, the input impedance of the processing circuit can be improved to obtain more complete electrocardio signal, in addition, when the second feedback module detects that the amplitude of the electrocardio signal exceeds the threshold value preset by the dead zone, the control unit triggers the input end of the output capacitor C DDSL and a voltage end, so that the output capacitor C DDSL and the first feedback capacitor C DSL combine to form an equivalent feedback capacitor, thereby increasing the high-pass cutoff frequency of the processing circuit and realizing the suppression of interference signals in the electrocardio signal.

[0079] In the implementation manner of the present application, between the electrocardio signal input electrode E1 and the input end P1 of the first high-pass cutoff circuit, a second chopping element Z2, a first amplifying element G m1 , a third chopping element Z3 and a second amplifying element G m2 are further included, wherein the input end of the second chopping element Z2 is coupled with the electrocardio signal input electrode E1, the output end of the second chopping element Z2 is coupled with the input end of the switch capacitor C in , the input end of the first amplifying element G m1 is coupled with the output end of the switch capacitor C in , the input end of the third chopping element Z3 is coupled with the output end of the first amplifying element G m1 , the input end of the second amplifying element G m2 is coupled with the output end of the third chopping element Z3, and the output end of the second amplifying element G m2 is coupled with the input end P1 of the first high-pass cutoff circuit and the second high-pass cutoff circuit.

[0080] In the embodiment of the present application, the second chopping element Z2, the first amplifying element G m1 , the third chopping element Z3 and the second amplifying element G m2The input signal is modulated, amplified, demodulated and amplified. Specifically, the ECG signal input electrode E1 is coupled to the second chopper element Z2 for modulating the input ECG signal without modulating the interference signal; the first amplifier element G m1 can amplify the interference signal and the modulated ECG signal; the third chopper element Z3 is added after the first amplifier element G m1 , which can demodulate the modulated ECG signal to restore the original ECG signal and eliminate the interference signal; the second amplifier element G m2 further amplifies the ECG signal after noise reduction processing.

[0081] In the implementation of the present application, the first high-pass cutoff circuit further comprises a fourth chopper element Z4 and a second feedback capacitor C fb , wherein the input end of the fourth chopper element Z4 is coupled to the input end P1 of the first high-pass cutoff circuit, the input end of the second feedback capacitor C fb is coupled to the output end of the fourth chopper element Z4, and the output end of the second feedback capacitor C fb is coupled to the output end of the switch capacitor C in .

[0082] It should be noted that between the ECG signal input electrode and the input end P1 of the first high-pass cutoff circuit, there are resistors R C1 , R C2 and capacitors C C1 , C C2 , wherein the resistor R C1 and the capacitor C C1 are connected in series and connected in parallel with the second amplifier element G m2 , the resistor R C2 and the capacitor C C2 are connected in series and connected in parallel with the second amplifier element G m2 .

[0083] wherein, referring to Figure 3 , the second amplifier element G m1 , the second amplifier element G m2 , the resistor R C1 , the resistor R C2 , the capacitor C C1 and the capacitor C C2 comprise a two-stage Miller compensation operational amplifier, and it can be understood that the feedback loop of the amplifier is composed of the switch capacitor C in and the second feedback capacitor C fb , which realizes the closed-loop gain of the amplifier and improves the stability of the overall circuit.

[0084] As a possible embodiment, the second high-pass cut-off circuit further comprises an integrating device G, an input end of the integrating device G being coupled to the input end P1 of the second high-pass cut-off circuit, and an output end of the integrating device G being coupled to an input end of the first chopper element Z1.

[0085] The integrating device G comprises a differential amplifier G m3 , a capacitor C i1 , a capacitor C i2 , a resistor R i1 , a resistor R i2 , a resistor R i1 , and a resistor R i2 , an input end of the capacitor C i1 and an input end of the capacitor C i2 being coupled to the input end P1 of the second high-pass cut-off circuit respectively, an output end of the resistor R m3 and an output end of the resistor R i1 being coupled to two input ends of the differential amplifier G i2 respectively, the capacitor C m3 and the capacitor C i1 being connected in parallel with the differential amplifier G i1 respectively, and the resistor R i2 being connected in series with the capacitor C i2 .

[0086] It should be noted that the capacitor C i1 and the capacitor C i2 have the same device parameters, and the resistor R i1 and the resistor R i2 have the same device parameters.

[0087] It should be noted that the integrating device G can drive the above-mentioned composite impedance boosting circuit to provide the required current to the branch where the switched capacitor is located at low frequency, so as to improve the input impedance.

[0088] It should be noted that the working principle of the second high-pass cut-off circuit is as follows: the interference signals such as electrode DC offset formed by the contact between the electrode and the human body and motion artifacts generated under the motion state of the human body are mixed with the useful electrocardio signals at the input end of the switched capacitor, and after the operations such as modulation, amplification and demodulation, the interference signals are extracted by the integrating device G in the second high-pass cut-off circuit, and then modulated to high frequency by the first chopper element Z1, and converted into current form by the first feedback capacitor C DSL at the output end of the main operational amplifier, so as to cancel the input interference signals, until the final output signal does not contain the interference signals, and then reach the steady state.

[0089] The high-pass cut-off frequency generated by the second high-pass cut-off circuit in the circuit is as follows:

[0090]

[0091] wherein R i denotes the resistance R i1 , R i2 denotes the capacitance C i1 , C i2 .

[0092] It should be noted that each chopper element described in the above embodiments of the present application can adopt a chopper, and each amplification element can adopt a differential amplifier.

[0093] In the implementation manner of the present application, the second feedback module further comprises an analog-digital conversion module LC-ADC and a timing module (Double Precision TDC, referred to as TDC), wherein an input end of the analog-digital conversion module LC-ADC is coupled to an input end P1 of the first high-pass cutoff circuit and the second high-pass cutoff circuit, an output end of the analog-digital conversion module is coupled to an external display processing device D1, so as to transmit the digital signal of the electrocardio signal to the external display processing device D1, an input end of the timing module TDC is coupled to an output end of the analog-digital conversion module LC-ADC, and an output end of the timing module TDC is coupled to the external display processing device D1, so as to transmit the time characteristic data of the electrocardio signal to the external display processing device D1.

[0094] In the embodiment of the present application, the signal output by the first feedback module K1 is converted into a digital signal by the analog-digital conversion module LC-ADC, which can improve the signal anti-interference capability, and by setting the timing module TDC, the timing precision can be improved without increasing the clock frequency, so as to improve the signal-to-noise ratio of the analog-digital conversion module LC-ADC.

[0095] In the preferred implementation manner of the present application, the analog-digital conversion module LC-ADC comprises a digital-analog conversion element DAC, a microprocessor MCU, a first input comparator B1 and a first logic device C C LOGIC, wherein an input end of the digital-analog conversion element DAC is coupled to the input end P1 of the first high-pass cutoff circuit and the second high-pass cutoff circuit; an input end of the microprocessor MCU is coupled to an output end of the digital-analog conversion element DAC; an input end of the first input comparator B1 is coupled to an output end of the microprocessor MCU; an input end of the first logic device C C LOGIC is coupled to an output end of the first input comparator B1; a first output end Y1 of the first logic device C C LOGIC is coupled to the digital-analog conversion element DAC; a second output end Y2 of the first logic device C C LOGIC is coupled to the external display processing device D1.

[0096] In the preferred embodiment of the present application, the analog-digital conversion module LC-ADC further comprises a second input comparator B2, a second logic device UD LOGIC and a signal combination device LC LOGIC, wherein the input end of the second input comparator B2 is coupled between the output end of the digital-analog conversion element DAC and the input end of the microprocessor MCU, the output end of the second input comparator B2 is coupled to the input end of the microprocessor MCU; the input end of the second logic device UD LOGIC is coupled to the output end of the second input comparator B2; the first input end of the signal combination device LC LOGIC is coupled to the output end of the first logic device C C LOGIC, the second input end of the signal combination device LC LOGIC is coupled to the output end of the second logic device UD LOGIC, and the output end of the signal combination device is coupled to the external display processing device D1.

[0097] In the analog-digital conversion module part, the digital-analog conversion element DAC is used to track the differential signal (V on+ -V on- ) pre-amplified by the first feedback module K1, that is, when (V on+ -V on- ) crosses V H (V L ) upwards (downwards), the first input comparator B1 will detect a level crossing event (represented by a C C asynchronous narrow pulse signal) and will change the feedback to the digital-analog conversion element DAC. The second input comparator B2 predicts the occurrence of a Vin extreme point event (represented by a C on+ asynchronous narrow pulse signal) by comparing V on- and V R . The signal combination device LC LOGIC combines the two pulse signals C C and C R into a CHANGE signal through an OR gate to record the feature points of the electrocardio signal.

[0098] Specifically, the second input comparator B2 receives the differential signal (i.e. the electrocardio signal) output by the first feedback module K1 and compares it, and sends the comparison result to the microprocessor MCU and the second logic device UD LOGIC in the form of a UD signal, the second logic device UD LOGIC outputs a C R asynchronous narrow pulse signal to the signal combination device LC LOGIC according to the UD signal, and the microprocessor MCU determines that the differential signal is V on+ or V on- according to the UD signal and inputs it to the first input comparator B1, wherein V H is the maximum value of the preset threshold range, and V LThe minimum value within a preset threshold range is compared by the first input comparator B1. If the differential signal exceeds the preset threshold range, i.e., when the differential signal is greater than V... H or less than V L When this happens, the first input comparator B1 will detect a level crossing event, and the first logic device C... C LOGIC outputs C respectively C An asynchronous narrow pulse signal is fed to a digital-to-analog converter (DAC) and a signal synthesizer (LC LOGIC). The DAC adjusts the differential signal, which exceeds a preset threshold range, to within that range. The LC LOGIC then uses an OR gate to connect the C signal to the DC signal. C and C R The two pulse signals are combined into a CHANGE signal and output to the external display processing device D1.

[0099] For example, the first input comparator B1 can be a four-input comparator, and the second input comparator B2 can be a two-input comparator.

[0100] To overcome the contradiction between the clock frequency of the LC-ADC timer and the signal-to-noise ratio (SNR) while maintaining low power consumption, this application adopts a low-cost, low-power timing module to achieve high-precision time measurement of the CHANGE signal pulse interval.

[0101] Figure 5 A schematic diagram of a timing module circuit provided in an embodiment of this application is shown.

[0102] Reference Figure 5 The timing module TDC includes a coarse-precision calculation unit K3, a fine-precision calculation unit K4, a trigger element TTrigger, and oscillators G1, G2, ..., G6, G7; among which, the coarse-precision calculation unit K3...

[0103] It includes a counter element; the fine-precision calculation unit K4 includes sampling elements Q1, Q2, ..., Q6, Q7, a decoder, and a third logic device TDC LOGIC.

[0104] Specifically, the input end of the counter component Counter is coupled to the output end of the signal combination device LC LOGIC, the output end of the counter component Counter is coupled to the external display processing device D1; the input end of the trigger component T Trigger is coupled to the output end of the signal combination device LC LOGIC; the input end of the sampling components Q1, Q2, …, Q6, Q7 is coupled to the output end of the trigger component T Trigger; the oscillator components G1, G2, …, G6, G7 are correspondingly coupled to the sampling components Q1, Q2, …, Q6, Q7; the input end of the decoding device Encoder is coupled to the output end of the sampling components Q1, Q2, …, Q6, Q7; the input end of the third logic device TDC LOGIC is coupled to the output end of the decoding device Encoder, and the output end of the third logic device TDC LOGIC is coupled to the external display processing device D1.

[0105] For example, the oscillator components G1, G2, …, G6, G7 provide the clock Fclk and different phase oscillation waveforms for the timing module TDC, the counter component Counter in the coarse precision calculation unit K3 counts the number of periods between two adjacent CHANGE pulses (Tclk=1 / Fclk), and transmits the result TDC[4:10] to the external display processing device D1; the fine precision calculation unit K4 divides one period of the oscillator into sixteen quadrants, after the coarse precision calculation unit K3 stops counting, the decoding device Encoder in the fine precision calculation unit K4 detects in which quadrant the stop signal falls, and the third logic device TDC LOGIC transmits the final result TDC[0:3] to the external display processing device D1.

[0106] It should be noted that the division of the sixteen quadrants correspondingly improves the time precision of the timing module TDC by sixteen times, that is, greatly improves the signal-to-noise ratio SNR under a lower clock frequency, and reduces the interference signals generated by the processing circuit.

[0107] According to the following formula, the signal-to-noise ratio of the analog-to-digital conversion module LC-ADC is improved by about 24.08dB.

[0108] SNR=20logOSR-11.2

[0109] Wherein, OSR is the clock oversampling rate, which refers to the ratio of the clock frequency to the input signal frequency.

[0110] It should be noted that the timing module TDC is coupled to the external power supply V TDC , and the on-off of the control circuit is controlled by setting the switch V ctrl , when the circuit is turned on, the voltage received by the timing module TDC is V DDTDC .

[0111] It should be noted that the external display processing device D1 can restore the electrocardio signal according to the received TDC signal, CHANGE signal and UD signal, and the comparison result between the processed electrocardio signal and the original input electrocardio signal is shown in Figure 6

[0112] For example, the external display processing device D1 can perform digital-to-analog conversion on the signal through the built-in restore program, so as to restore the electrocardio signal.

[0113] Figure 7 A structural schematic diagram of an electrocardio signal processing device provided by an embodiment of the present application is shown, and only parts related to the embodiment of the present application are shown for ease of description.

[0114] The electrocardio signal processing device can specifically include:

[0115] The processing circuit 701 is configured to suppress the interference signal in the electrocardio signal.

[0116] The display processing device 702 is coupled to the processing circuit 701, configured to acquire the digital signal and time characteristic data of the electrocardio signal output by the processing circuit, and display the electrocardio signal after restoration processing.

[0117] In a specific implementation, the display processing device described in the embodiment of the present application includes but is not limited to other portable devices such as mobile phones, laptop computers or tablet computers with touch-sensitive surfaces (for example, touch screen displays and / or touchpads).

[0118] Various application programs that can be executed on the display processing device can use at least one common physical user interface device such as a touch-sensitive surface. One or more functions of the touch-sensitive surface and the corresponding information displayed on the terminal can be adjusted and / or changed between application programs and / or within the corresponding application program. In this way, the common physical architecture (for example, the touch-sensitive surface) of the terminal can support various application programs with an intuitive and transparent user interface for the user.

[0119] Figure 8 A structural schematic diagram of a terminal device provided by an embodiment of the present application is shown. The terminal device 800 includes at least one processor 801 (only one processor is shown in the figure), a memory 802, and a computer program 803 stored in the memory 802 and executable on the at least one processor 801, wherein the processor 801 implements the steps in the above processing circuit embodiment when executing the computer program 803. Figure 8

[0120] ​​The terminal device 800 can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The terminal device can include, but is not limited to, a processor 801 and a memory 802. Those skilled in the art can understand that Figure 7 The terminal device 800 is only an example and is not limited to the terminal device 800, and can include more or fewer components than shown, or combine some components, or include different components, for example, can also include an input / output device, a network access device, and the like.

[0121] The processor 801 can be a central processing unit (CPU), and can also be other general-purpose processors, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, and the like. The general-purpose processor can be a microprocessor or can also be any conventional processor.

[0122] The memory 802 can be an internal storage unit of the terminal device 800 in some embodiments, for example, a hard disk or a memory of the terminal device 800. The memory 802 can also be an external storage device of the terminal device 800 in other embodiments, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, and the like. Further, the memory 802 can include both the internal storage unit and the external storage device of the terminal device 800. The memory 802 is used to store an operating system, an application program, a boot loader, data, and other programs, for example, program codes of the computer program, and the like. The memory 802 can also be used to temporarily store data that has been output or will be output.

[0123] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is taken as an example for description, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software functional unit. In addition, the specific names of each functional unit and module are only for convenient distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0124] In the above embodiments, the description of each embodiment has its own emphasis, and the rated part is not described or recorded in detail in a certain embodiment. Please refer to the related description of other embodiments.

[0125] The embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is executed by a processor to realize the steps in each method embodiment described above.

[0126] The embodiment of the present application provides a computer program product, when the computer program product runs on the mobile terminal, so that the mobile terminal executes to realize the steps in each method embodiment described above.

[0127] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0128] In the embodiments of the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other manners. For example, the described apparatus / network device embodiments are merely schematic. For example, the division of the modules or units is merely logical function division. There can be another division manner for actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units.

[0129] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0130] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can be a physically independent unit, or two or more units can be integrated in one unit. The above-mentioned units can be realized in the form of hardware or in the form of software.

[0131] The integrated module / unit, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware, and the computer program can be stored in a computer readable storage medium. When the processor executes the computer program, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable file or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the computer readable medium can include appropriate contents according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.

[0132] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A processing circuit of an electrocardiosignal, characterized in that, The processing circuit comprises: The ECG signal input electrode, the first feedback module and two impedance boosting capacitors, the first feedback module comprises a switched capacitor, a first high-pass cut-off loop and a second high-pass cut-off loop, the input end of the first high-pass cut-off loop and the second high-pass cut-off loop is coupled to the output end of the switched capacitor, the first output end of the first high-pass cut-off loop and the second high-pass cut-off loop is respectively coupled to one end of one impedance boosting capacitor, the second output end of the first high-pass cut-off loop and the second high-pass cut-off loop is respectively coupled to the output end of the switched capacitor, the other end of each impedance boosting capacitor is coupled to the input end of the switched capacitor together with the ECG signal input electrode, a first feedback capacitor and a first chopping element are arranged in series on the second high-pass cut-off loop; and The second feedback module, the input end of the second feedback module is coupled to the output end of the switched capacitor, and the second feedback module comprises an output capacitor and a control unit, the output end of the output capacitor is coupled between the first feedback capacitor and the first chopping element on the second high-pass cut-off loop, and the control unit is used to trigger the input end of the output capacitor to be coupled to a voltage end when the amplitude of the ECG signal exceeds a threshold value of a dead zone preset.

2. The processing circuitry of claim 1, wherein, Between the ECG signal input electrode and the input end of the first high-pass cut-off loop, further comprising: A second chopping element, the input end of the second chopping element is coupled to the ECG signal input electrode, and the output end of the second chopping element is coupled to the input end of the switched capacitor; A first amplifying element, the input end of the first amplifying element is coupled to the output end of the switched capacitor; A third chopping element, the input end of the third chopping element is coupled to the output end of the first amplifying element; A second amplifying element, the input end of the second amplifying element is coupled to the output end of the third chopping element, and the output end of the second amplifying element is coupled to the input end of the first high-pass cut-off loop and the second high-pass cut-off loop.

3. The processing circuitry of claim 1, wherein, The first high-pass cut-off loop further comprises: A fourth chopping element, the input end of the fourth chopping element is coupled to the input end of the first high-pass cut-off loop; A second feedback capacitor, the input end of the second feedback capacitor is coupled to the output end of the fourth chopping element, and the output end of the second feedback capacitor is coupled to the output end of the switched capacitor.

4. The processing circuitry of claim 1, wherein, The second high-pass cut-off loop further comprises: An integrating device, the input end of the integrating device is coupled to the input end of the second high-pass cut-off loop, and the output end of the integrating device is coupled to the input end of the first chopping element.

5. The processing circuitry of claim 1, wherein, The second feedback module further comprises: An analog-to-digital conversion module, the input end of the analog-to-digital conversion module is coupled to the input end of the first high-pass cut-off loop and the second high-pass cut-off loop, and the output end of the analog-to-digital conversion module is coupled to an external display processing device, so as to transmit a digital signal of the ECG signal to the external display processing device; A timing module, the input end of the timing module is coupled to the output end of the analog-to-digital conversion module, and the output end of the timing module is coupled to the external display processing device, so as to transmit time characteristic data of the ECG signal to the external display processing device.

6. The processing circuitry of claim 5, wherein, The analog-to-digital conversion module comprises: a digital-to-analog conversion element, an input end of which is coupled to input ends of the first high-pass cutoff circuit and the second high-pass cutoff circuit; a microprocessor, an input end of which is coupled to an output end of the digital-to-analog conversion element; a first input comparator, an input end of which is coupled to an output end of the microprocessor; a first logic device, an input end of which is coupled to an output end of the first input comparator, a first output end of which is coupled to the digital-to-analog conversion element, and a second output end of which is coupled to the external display processing device.

7. The processing circuitry of claim 6, wherein, The analog-to-digital conversion module further comprises: a second input comparator, an input end of which is coupled between an output end of the digital-to-analog conversion element and an input end of the microprocessor, and an output end of which is coupled to an input end of the microprocessor; a second logic device, an input end of which is coupled to an output end of the second input comparator; a signal synthesis device, a first input end of which is coupled to a second output end of the first logic device, a second input end of which is coupled to an output end of the second logic device, and an output end of which is coupled to the external display processing device.

8. The processing circuitry of claim 7, wherein, The timing module comprises: a counting element, an input end of which is coupled to an output end of the signal synthesis device, and an output end of which is coupled to the external display processing device.

9. The processing circuitry of claim 8, wherein, The timing module further comprises: a trigger element, an input end of which is coupled to an output end of the signal synthesis device; a sampling element, an input end of which is coupled to an output end of the trigger element; an oscillator device, which is coupled to the sampling element; a decoding device, an input end of which is coupled to an output end of the sampling element; a third logic device, an input end of which is coupled to an output end of the decoding device, and an output end of which is coupled to the external display processing device.

10. An apparatus for processing an electrocardiosignal, characterized in that The processing device comprises: the processing circuit according to any one of claims 1-9; and a display processing device, which is coupled to the processing circuit to acquire digital signals and time characteristic data of electrocardio signals, and to display the electrocardio signals after restoration processing.

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