A fast peak search circuit for a laser radar statistical distribution histogram

Abstract

The application relates to a peak value fast searching circuit of a laser radar statistical distribution histogram, which comprises a data interface circuit, a histogram storage circuit and a peak value judging circuit, wherein the histogram storage circuit comprises a plurality of histogram storage subunits, a data decoder and a full flag output circuit; the histogram storage subunits are used for counting time-of-flight data; the data decoder decodes time-of-flight code values, and selects the histogram storage subunit corresponding to the current event; the full flag output circuit judges whether the counting threshold is reached, and outputs a full flag signal; the peak value judging circuit updates the peak value register value according to the full flag signal and the current time-of-flight code value, and judges whether the current time-of-flight code value is the signal peak value position of the histogram statistics in this round. Compared with the prior art, the application uses a simple and efficient peak value judging mode, saves the area resource of the circuit, and can flexibly configure the peak value judging threshold according to the environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of laser radar detection, in particular to a peak value fast search circuit of laser radar statistical distribution histogram. BACKGROUND

[0002] Laser radar detection system can perceive the three-dimensional spatial information of the target. Laser radar detection principle is divided into two categories of direct photon time of flight detection and indirect time of flight. The laser radar system based on direct time of flight detection of Geiger avalanche device has lower power consumption and stronger anti-interference ability.

[0003] For direct time of flight detection laser radar, an important problem is to solve the problem of ambient light interference and device dark count: in a detection period, in addition to the signal photons that may be collected at a specific time, a large number of noise photons will be uniformly received in most of the time; in addition, the device itself will also generate random noise. Therefore, in the detection process, a statistical histogram needs to be constructed to count the distribution of photon time of flight data after multiple frame detection. Since the signal position is relatively fixed, the number of signal photons in the subdivided time period at the signal position is greater than the number of background noise photons under the same time period width. Finally, one or more peaks will be presented in the statistical histogram, that is, the position of the signal is determined.

[0004] A key bottleneck of laser radar chip is the storage and calculation of photon time statistical distribution: for array type laser radar detector, the use of a large number of statistical histograms will occupy a large chip area resource. On the other hand, the calculation and processing of data in the chip, especially in the pixel, will also consume a large amount of calculation resources and occupy a large amount of calculation time, thereby reducing the working frame frequency of detection. The storage and calculation of photon time statistical distribution have become an important factor to limit the pixel size, spatial resolution, working frame frequency and power consumption of the chip, and new technology is urgently needed to quickly and efficiently realize the accurate peak value extraction calculation of photon time statistical distribution. SUMMARY

[0005] The purpose of the present application is to provide a peak value fast search circuit of laser radar statistical distribution histogram, which can flexibly configure the peak value refresh speed to adapt to different application scenarios, improve the peak value search speed, and realize efficient and accurate peak value identification.

[0006] The purpose of the present application can be realized by the following technical solutions:

[0007] A peak value fast search circuit of laser radar statistical distribution histogram, comprising:

[0008] A data interface circuit, a histogram storage circuit and a peak value judgment circuit, wherein,

[0009] The data interface circuit comprises an address decoding circuit and a data receiving circuit; the data receiving circuit receives an event request of the probe pixel array; when a photon is detected by the probe pixel and converted into time-of-flight data, the bus interface determines whether to receive the pixel TDC data according to the busy condition of the bus; if the pixel TDC data is received, the address decoding circuit is called to continue decoding the pixel address code in the data; the address decoding circuit decodes the pixel address code in the data to determine whether the data is from the pixel corresponding to the current histogram; if yes, the data interface circuit receives the pixel TDC data and enables the histogram storage circuit;

[0010] The histogram storage circuit comprises a plurality of histogram storage subunits, a data decoder and a full flag output circuit; the histogram storage subunit comprises an asynchronous counter formed by cascading N D flip-flops, and is used for counting the time-of-flight data; the data decoder is used for decoding the time-of-flight code value, converting the time-of-flight code value into a one hot code value and selecting the histogram storage subunit corresponding to the current event; the full flag output circuit takes the output of the histogram storage subunit as input, determines whether there is a histogram storage subunit reaching the counting threshold and outputs a full flag signal;

[0011] The peak value judging circuit receives the full flag signal output by the histogram storage circuit; when the full flag signal is 1, the peak value register value is updated according to the current time-of-flight code value; and the time-of-flight code value transmitted each time is compared with the peak value register value; if the two values are equal, it is determined that the time-of-flight code value transmitted currently is the signal peak value position of the histogram statistics in this round.

[0012] The time-of-flight data is a 4-bit binary code.

[0013] After the data receiving circuit receives the time-of-flight data, it determines that the valid signal of the received data arrives; the valid signal and a bus idle signal in the rear stage are input into an AND gate; the output of the AND gate is connected to a first delay circuit; the module selection signal is obtained after the delay; the histogram storage circuit is driven; the output of the AND gate is a data preparation signal; when the data preparation signal is high, it indicates that the time-of-flight data transmitted by the front stage is allowed.

[0014] The address decoding circuit is composed of four XOR gates and a 4-input NOR gate; one input end of the four XOR gates is a 4-bit binary address code; the other input end is a pre-configured address; the outputs of the four XOR gates are input into the NOR gate; when the output of the NOR gate is high, the histogram storage circuit is enabled.

[0015] The time of flight data is outputted as BIN_SEL<15:0> signal after data decoder, only one signal in BIN_SEL<15:0> is equal to 1 in the same frame, and the rest are 0, which is used to represent the selection result of 16 histogram bins, and the histogram storage subunit corresponding to the current event is selected, that is, the histogram storage circuit includes 16 histogram storage subunits.

[0016] The module selection signal and BIN_SEL<15:0> signal are connected as the input of the first stage of the asynchronous counter, and when the module selection signal and BIN_SEL<15:0> signal are both 1, the counting of the corresponding histogram storage subunit is triggered once, and the counting is accumulated by the later stage of the asynchronous counter; the output of the later stage of the asynchronous counter is connected to the MUX, and the counting range is selected by the external control signal; once the corresponding position in the later stage of the asynchronous counter is high, it indicates that the counting of the BIN reaches the preset peak value, and the output of the MUX of the corresponding histogram storage subunit is high.

[0017] The full flag output circuit is an OR tree composed of five 4-input OR gates, and the outputs of the MUX of the 16 histogram storage subunits are inputted into the four 4-input OR gates at the same time, and the outputs of the four 4-input OR gates are inputted into one 4-input OR gate, so as to obtain the full flag signal.

[0018] Considering the counting characteristics of the asynchronous counter, when a peak value is searched, the full flag signal is high, the full flag signal is delayed to generate a clear signal, the histogram storage subunit is reset, and the full flag signal is reset, and the next round of statistics is performed.

[0019] When the full flag signal from the histogram storage circuit is received, the peak value judgment circuit updates the peak value register with the current time of flight data as the trigger edge, and considers that the time of flight code value is the peak value position; in the whole search process, whenever the histogram storage subunit searches a peak value, the full flag signal is set to 1, and the peak value register is updated; after the full flag signal is reset, the next round of statistics is performed, and when the full flag signal is 1 again, the peak value register is updated again.

[0020] The peak value judgment circuit takes the real-time transmitted time of flight data and the value stored in the peak value register as the input of four XOR gates, the output of the XOR gate is connected to a 4-input NOR gate, and the output of the NOR gate is inputted into a tri-state gate; if the current module selection signal is high and the real-time transmitted time of flight data is the same as the value stored in the peak value register, the output of the NOR gate is high, and the output of the tri-state gate is high, which indicates that the current transmitted time of flight data is in the interval of the signal peak value, and the peak value search is realized.

[0021] Compared with the prior art, the present application has the following beneficial effects:

[0022] (1) The histogram storage subunit is constructed using an asynchronous counting unit, so that the area resource overhead of hardware is reduced.

[0023] (2) The circuit for quickly judging whether the time-of-flight data detected in the current frame is in the signal peak value interval is designed in combination with the data characteristics of the histogram, and the speed of peak value refreshing can be flexibly configured to adapt to different application scenarios, so that the circuit is flexible, simple, configurable, and suitable for sensing and fusion design of a large-scale pixel array.

[0024] (3) The peak value search can be efficiently implemented under limited resource constraints, and the peak value can be accurately extracted. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 Fig. 1 is a structural schematic diagram of a peak value fast search circuit of the present application;

[0026] Figure 2 Fig. 2 is a structural schematic diagram of a data interface circuit in an embodiment;

[0027] Figure 3 Fig. 3 is a structural schematic diagram of a histogram storage unit in an embodiment;

[0028] Figure 4 Fig. 4 is a structural schematic diagram of a peak value judgment circuit in an embodiment;

[0029] In the drawings, the reference signs are as follows: 100-data interface circuit, 200-histogram storage unit, 300-peak value judgment circuit, 201-histogram storage subunit, 202-data decoder, and 203-full flag output circuit. DETAILED DESCRIPTION

[0030] The present application will be described in detail below in combination with the drawings and specific embodiments. The present embodiment is implemented on the premise of the technical solution of the present application, and detailed implementation modes and specific operation processes are given, but the protection scope of the present application is not limited to the following embodiments.

[0031] A peak value fast search circuit for a laser radar statistical distribution histogram, as shown in Fig. 1, comprises: Figure 1

[0032] (1) Data interface circuit 100

[0033] The data interface circuit 100 comprises an address decoding circuit and a data receiving circuit.

[0034] ​The data receiving circuit receives the event request of the probe pixel array, and when the probe pixel detects a photon and converts into time-of-flight data, the bus interface determines whether to receive the pixel TDC data according to the busy condition of the bus; if the pixel TDC data is received, the address decoding circuit is called to continue decoding the pixel address code in the data.

[0035] As shown in Figure 2 , the data receiving circuit includes an AND gate and a delay circuit. The inputs of the AND gate are the received data valid signal data_valid and the post-stage bus idle signal data_ready_post. When the received data valid signal data_valid arrives, it is determined whether the post-stage bus is idle. When the post-stage bus is idle, data_ready_post is high. After the data_valid signal passes through an AND gate, data_ready is high, indicating that the front-stage is allowed to transmit time-of-flight data.

[0036] In an embodiment, the data_ready passes through a delay circuit to generate the module selection signal histo_sel required by the histogram storage circuit 200. Each pulse of the histo_sel signal indicates that the time-of-flight data TDC<3:0> signal appears once. The delay circuit ensures that the address decoding is completed before the clock trigger, and the histogram storage circuit enable signal histo_en has reached a steady state.

[0037] The address decoding circuit decodes the pixel address code in the data to determine whether the data comes from the pixel corresponding to the current histogram. If so, the data interface circuit 100 receives the pixel TDC data and enables the histogram storage circuit and the peak judgment circuit.

[0038] As shown in Figure 2 , in this embodiment, the address decoding circuit is composed of four XOR gates and a 4-input NOR gate. The addresses are 4-bit binary codes data_addr<3:0> which are input into one input end of the four XOR gates. The other input end of the four XOR gates is set to a pre-configured address, and the outputs of the four XOR gates are input into the NOR gate.

[0039] In this embodiment, the configured address is 1001. That is, only when the input address code value data_addr<3:0> is equal to the address 1001 configured by the current data interface 100, the histogram storage circuit enable signal histo_en output by the NOR gate is high, indicating that the address matches, and the histogram storage circuit 200 starts to work.

[0040] (2) Histogram storage circuit 200

[0041] The histogram storage circuit 200 includes multiple histogram storage sub-units 201, a data decoder 202, and a full flag output circuit 203.

[0042] like Figure 3 As shown, when the histogram storage circuit enable signal `histo_en` is high, the lidar statistical distribution histogram is input into the data decoder 202 in the form of time-of-flight data `TDC<3:0>`. The time-of-flight data `TDC<3:0>` is represented by 4 bits of binary code. After being processed by the data decoder, it is converted into a one-hot code value, outputting the `BIN_SEL<15:0>` signal. One bit of `BIN_SEL<15:0>` is set to 1, and the rest to 0, representing the selection result of the 16 histogram BINs, thus selecting the histogram storage sub-unit corresponding to the current event. The data decoder ensures that only one BIN is selected at a time.

[0043] In this embodiment, the histogram storage circuit includes 16 histogram storage sub-units 201, each corresponding to the BIN_SEL<15:0> signal. To further save hardware resources, each histogram storage sub-unit 201 includes an asynchronous counter composed of 5 cascaded D flip-flops without enable terminals, used to count flight time data.

[0044] The module selection signal histo_sel and the BIN_SEL<15:0> signal are ANDed together and used as the input of the first stage (i.e., bit D0) of the 5-level asynchronous counter. When the histo_sel and BIN_SEL<15:0> signals are both 1, a count is triggered, and the count is accumulated by bits D1-D4.

[0045] The outputs of bits 2-5 (D1-D4) of the asynchronous counter are connected to a 4-input MUX, and the counting range is selected by the external THRE<1:0> control signal, which selects one of the following: 2, 4, 8, or 16. When the THRE<1:0> control signal is 00, D1 is set high, and the counting range is 2. 1 =2; When the THRE<1:0> control signal is 01, D2 is set high, and the counting range is 2. 2 =4; When the THRE<1:0> control signal is 10, D3 is set high, and the counting range is 2. 3 =8; When the THRE<1:0> control signal is 11, D4 is set high, and the counting range is 2. 4 =16.

[0046] Once the corresponding position in D1-D4 is set high, it indicates that the count of that BIN has reached the preset peak value, and the MUX output of that graph storage sub-unit is high. For example, as Figure 3As shown, if the THRE<1:0> control signal is set to 10, when the D3 bit of one of the 16 histogram storage subunits 201 is first set to high, it indicates that the BIN corresponding to the histogram storage subunit is the peak value. That is, the peak value of the histogram is searched according to the preset peak value threshold in this embodiment.

[0047] The full flag output circuit 203 takes the output of the histogram storage subunit 201 as input, judges whether there is a histogram storage subunit 201 reaching the count threshold, and outputs a full flag signal.

[0048] The full flag output circuit 203 is an OR tree composed of five 4-input OR gates. As shown, Figure 3 The output of the MUX of the 16 histogram storage subunits 201 is input into four 4-input OR gates of the full flag output circuit 203 in groups of four, and the output of the four OR gates is input into a 4-input OR gate to obtain the Full Flag signal. That is, when one of the output signals TH<15:0> of the MUX reaches the high level, it indicates that the Mth bit (corresponding to the D M ) of the histogram storage subunit 201 after accumulation of the current frame becomes 1, and the corresponding histogram BIN is determined as the peak value, and the full flag signal Full Flag is high.

[0049] At the same time, due to the counting characteristics of the asynchronous counter, after reaching the peak value once, the histogram storage unit 200 needs to be reset to all 0 state, and the full flag signal is also reset to 0 for the next round of statistics. In this embodiment, the reset process is realized in the following way: the full flag signal Full Flag is delayed to generate the clear signal CLEAR of the histogram storage subunit 201.

[0050] (3) Peak value judgment circuit 300

[0051] The peak value judgment circuit 300 receives the full flag signal output by the histogram storage circuit 200, and when the full flag signal is 1, the peak value register value is updated according to the current time of flight code value, and the time of flight code value transmitted each time is compared with the peak value register value. If they are equal, it is determined that the time of flight code value transmitted currently is the signal peak value position of this round of histogram statistics.

[0052] Specifically, as shown in Figure 4As shown, when the peak judging circuit 300 receives the full flag signal from the histogram storage circuit 200, the full flag signal is used as a trigger edge to update the peak register MASK REG<3:0> with the current time of flight data TDC<3:0>, and the time of flight code value is considered as the signal peak position. During the whole search process, whenever the histogram storage subunit 201 searches for a peak, the full flag signal Full Flag is set to 1, the peak register is updated, and then the full flag signal is reset to 0 for the next round of statistics. When the full flag signal is 1 again, the peak register is updated again.

[0053] Meanwhile, the real-time transmitted time of flight data and the value stored in the peak register are respectively used as the inputs of four XOR gates, the outputs of the XOR gates are connected to a 4-input NOR gate, and the output of the NOR gate is input to a tristate gate. If the current module selection signal histo_sel is high and the real-time transmitted time of flight data is the same as the value stored in the peak register, the output of the NOR gate is high, and then the output of the tristate gate is the determination result is_signal, which is high, indicating that the time of flight data TDC<3:0> of this transmission is in the interval where the signal peak is located.

[0054] The preferred embodiments of the present application are described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations without departing from the concept of the present application. Therefore, any technical solutions obtained by logical analysis, reasoning or limited experiments based on the concept of the present application and the prior art should be within the scope of protection of the present application as defined by the claims.

Claims

1. A fast peak search circuit for a laser radar statistical distribution histogram, characterized by, The application relates to a data interface circuit (100), a histogram storage circuit (200) and a peak value judging circuit (300), wherein, The data interface circuit (100) comprises an address decoding circuit and a data receiving circuit; the data receiving circuit receives an event request of a pixel array; when a photon is detected by a pixel and converted into time-of-flight data, a bus interface judges whether to receive pixel TDC data according to the busy condition of a bus; if the pixel TDC data is received, the address decoding circuit is called to continue decoding the pixel address code in the data; the address decoding circuit decodes the pixel address code in the data to determine whether the data is from a pixel corresponding to a current histogram, and if yes, the data interface circuit (100) receives the pixel TDC data and enables the histogram storage circuit (200); The histogram storage circuit (200) comprises a plurality of histogram storage subunits (201), a data decoder (202) and a full flag output circuit (203); the histogram storage subunit (201) comprises an asynchronous counter formed by cascading N D flip-flops and is used for counting time-of-flight data; the data decoder (202) is used for decoding a time-of-flight code value, converting the time-of-flight code value into a one hot code value and selecting a histogram storage subunit corresponding to a current event; the full flag output circuit (203) takes the output of the histogram storage subunit (201) as input, judges whether there is a histogram storage subunit (201) reaching a counting threshold and outputs a full flag signal; The peak value judging circuit (300) receives the full flag signal output by the histogram storage circuit (200); when the full flag signal is 1, a peak value register value is updated according to a current time-of-flight code value, and the time-of-flight code value transmitted each time is compared with the peak value register value; if the two values are equal, it is determined that the time-of-flight code value transmitted currently is a signal peak value position of the current histogram statistics. The time-of-flight data is a 4-bit binary code.

2. A fast peak search circuit for a laser radar statistical distribution histogram according to claim 1, characterized in that, After the data receiving circuit receives the time-of-flight data, a valid signal of the received data is determined, and the valid signal and a bus idle signal in the rear stage are input into an AND gate; the output of the AND gate is connected with a first delay circuit, and a module selection signal is obtained after delay, thereby driving the histogram storage circuit (200); the output of the AND gate is a data preparation signal, and when the data preparation signal is high, it indicates that the time-of-flight data transmitted by the front stage is allowed.

3. A fast peak search circuit for a laser radar statistical distribution histogram according to claim 2, characterized in that, The address decoding circuit is composed of four XOR gates and a 4-input NOR gate; one input end of the four XOR gates is a 4-bit binary address code, and the other input end is a pre-configured address; the outputs of the four XOR gates are input into the NOR gate; when the output of the NOR gate is high, the histogram storage circuit (200) is enabled.

4. The fast peak search circuit for a laser radar statistical distribution histogram according to claim 1, wherein, The time-of-flight data is output as a BIN_SEL<15:0> signal after passing through the data decoder; in the same frame, only one signal in the BIN_SEL<15:0> signal is equal to 1, and the rest are all 0, which are used to represent the selection result of 16 histogram bins; the histogram storage subunit (201) corresponding to a current event is selected, that is, the histogram storage circuit (200) comprises 16 histogram storage subunits (201).

5. A fast peak search circuit for a laser radar statistical distribution histogram according to claim 3, wherein, ​ 6. A fast peak search circuit for a histogram of a statistical distribution of a lidar according to claim 5, wherein, The module selection signal and the BIN_SEL<15:0> signal are inputs of the first stage of the asynchronous counter after being ANDed, and the counting of the corresponding histogram storage subunit (201) is triggered once when the module selection signal and the BIN_SEL<15:0> signal are both 1, and the counting is accumulated by the later stage of the asynchronous counter; the output of the later stage of the asynchronous counter is connected to the MUX, and the counting range is selected by the external control signal; once the corresponding position in the later stage of the asynchronous counter is high, it indicates that the counting of the BIN reaches the preset peak value, and the output of the MUX of the corresponding histogram storage subunit (201) is high.

7. A fast peak search circuit for a histogram of a statistical distribution of a lidar according to claim 5, wherein, The full flag output circuit (203) is an OR tree composed of five 4-input OR gates, and the outputs of the MUXs of the 16 histogram storage subunits (201) are input into the four 4-input OR gates of the full flag output circuit (203) in groups of four, and the outputs of the four OR gates are input into one 4-input OR gate, to obtain the full flag signal.

8. The fast peak search circuit for a laser radar statistical distribution histogram according to claim 1, wherein, Considering the counting characteristics of the asynchronous counter, when a peak value is searched, the full flag signal is high, and after the full flag signal is delayed, a clear signal is generated, the histogram storage subunit (201) is reset, and the full flag signal is reset, and the next round of statistics is performed.

9. A fast peak search circuit for a laser radar statistical distribution histogram according to claim 8, wherein, The peak value judgment circuit (300) receives the full flag signal from the histogram storage circuit (200), uses the full flag signal as a trigger edge, updates the peak value register with the current time-of-flight data, and considers that the time-of-flight code value is the peak value position; during the entire search process, whenever the histogram storage subunit (201) searches for a peak value, the full flag signal is set to 1, and the peak value register is updated; after the full flag signal is reset, the next round of statistics is performed, and when the full flag signal is 1 again, the peak value register is updated again.

10. A fast peak search circuit for a laser radar statistical distribution histogram according to claim 5, wherein, The peak value judgment circuit (300) inputs the real-time transmitted time-of-flight data and the value stored in the peak value register into four XOR gates, and the output of the XOR gate is connected to a 4-input NOR gate, and the output of the NOR gate is input into a tri-state gate; if the current module selection signal is high and the real-time transmitted time-of-flight data is the same as the value stored in the peak value register, the output of the NOR gate is high, the output of the tri-state gate is high, and it is determined that the current transmitted time-of-flight data is in the interval of the signal peak value, and the peak value search is realized.

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