Power supply timing control circuit

Abstract

The application provides a power supply timing control circuit, comprising: at least one timing control module and a power supply module; each timing control module comprises a timing control chip and an adjusting element, the adjusting element being connected with a delay setting end of the timing control chip; a first output end of the at least one timing control module is connected with a first input end of the power supply module in one-to-one correspondence; when an enable signal received by the timing control chip is in an effective state, a plurality of power supply enable signals are generated and output through the corresponding first output end, and there is a delay interval corresponding to the adjusting element of the timing control module between adjacent signals in the plurality of power supply enable signals; the power supply module generates and outputs a power supply signal corresponding to the power supply enable signal in response to the power supply enable signal in the effective state, and the scheme saves the cost of power supply timing control.

Description

Technical Field

[0001] This application relates to the field of timing control technology, and in particular to a power supply timing control circuit. Background Technology

[0002] As electronic products are constantly being updated and iterated, their functions and structures are becoming increasingly complex, and their circuit integration is becoming increasingly high. In most cases, the various components in electronic products require power signals with different timing sequences. With the continuous updates and iterations of electronic products, the timing requirements between power signals are increasing, making power signal timing design and debugging more complex.

[0003] In related technologies, the power-on and power-off timing of multiple power signals is controlled by complex programmable logic devices (CPLDs) or programmable timing chips. All of these technologies require software programming, and firmware (FW) needs to be burned during mass production.

[0004] In practical applications, when there are a large number of power signals, the timing requirements for each power signal vary considerably. Software programming can meet the power signal requirements of more complex boards. However, when there are a small number of power signals, the above method requires firmware flashing, resulting in higher costs for power timing control. Summary of the Invention

[0005] This application provides a power supply timing control circuit, which aims to solve the problem of high timing control cost when the number of power signals is small.

[0006] In a first aspect, this application provides a power timing control circuit, comprising: each timing control module including a timing control chip and an adjustment element, the timing control chip having a delay setting terminal, and the adjustment element being connected to the delay setting terminal of the timing control chip; each timing control module including a plurality of first output terminals, the power module including a plurality of first input terminals, and the first output terminal of the at least one timing control module being connected to the first input terminal of the power module in a one-to-one correspondence; the timing control chip of each timing control module receiving an enable signal corresponding to the timing control module, and being used to generate a plurality of power enable signals and output them through the corresponding first output terminals when the enable signal is in an active state, wherein there is a delay interval between adjacent signals among the plurality of power enable signals corresponding to the adjustment element of the timing control module; the power module receiving the power enable signal and power supply signal output by the at least one timing control module, and being used to generate and output a power signal corresponding to the power enable signal in response to the power enable signal in an active state.

[0007] Optionally, the adjustment element includes a first capacitor; one end of the first capacitor is connected to the delay setting terminal of the timing control chip, and the other end of the first capacitor is grounded.

[0008] Optionally, the power module includes multiple power chips, each power chip corresponding to a first input terminal of the power module; each power chip receives the power supply signal at its power input terminal, and the power chip's enable input terminal is connected to the corresponding first input terminal. The power chip is used to generate a power signal corresponding to the power supply enable signal based on the power supply signal when the received power enable signal is valid.

[0009] Optionally, the power supply timing control circuit can be divided into a power-on phase and a power-off phase.

[0010] Optionally, the number of timing control modules is one, and the number of the first output terminals of the timing control module is three.

[0011] Optionally, the number of timing control modules is multiple, and the multiple timing control modules are arranged sequentially; the power timing control circuit further includes: an indicator module corresponding to each timing control module; the indicator module receives a trigger signal, and the output terminal of the indicator module is connected to the corresponding timing control module; the indicator module is used to generate an enable signal corresponding to the timing control module according to the trigger signal; wherein, during the power-on phase, the order in which the indicator modules corresponding to each timing control module output the enable signals in a valid state is consistent with the arrangement order of the multiple timing control modules; during the power-off phase, the order in which the indicator modules corresponding to each timing control module output the enable signals in a valid state is reversed compared to the arrangement order of the multiple timing control modules.

[0012] Optionally, the number of timing control modules is two; the first input terminal of the indicator module corresponding to the first timing control module receives the trigger signal, and the second input terminal of the indicator module is connected to the first output terminal of the other timing control module; the first input terminal of the indicator module corresponding to the other timing control module receives the trigger signal, and the second input terminal of the other indicator module is connected to the last output terminal of the first timing control module.

[0013] Optionally, the indicator module corresponding to the first timing control module includes a first OR gate, and the indicator module corresponding to the other timing control module includes a first AND gate; the first input terminal of the first OR gate receives the trigger signal, the second input terminal of the first OR gate is connected to the first output terminal of the other timing control module, and the output terminal of the first OR gate is connected to the first timing control module; the first input terminal of the first AND gate receives the trigger signal, the second input terminal of the first AND gate is connected to the last first output terminal of the first timing control module, and the output terminal of the first AND gate is connected to the other timing control module.

[0014] Optionally, the power timing control circuit further includes a second AND gate corresponding to each power chip other than the first power chip; the first input terminal of the second AND gate is connected to the PG terminal of the previous power chip, the second input terminal of the second AND gate is connected to the first output terminal corresponding to the power chip, and the output terminal of the second AND gate is connected to the enable input terminal of the corresponding power chip.

[0015] Optionally, during the power-on phase, the valid state is a high-level state, and during the power-off phase, the valid state is a low-level state.

[0016] The power timing control circuit provided in this application includes at least one timing control module and a power module. Each timing control module includes a timing control chip and an adjustment element. The adjustment element is connected to the delay setting terminal of the timing control chip. The first output terminal of at least one timing control module is connected to the first input terminal of the power module in a one-to-one correspondence. When the enable signal received by the timing control chip is in an active state, multiple power enable signals are generated and output through the corresponding first output terminals. There is a delay interval between adjacent signals in the multiple power enable signals that corresponds to the adjustment element of the timing control module. The power module responds to the active power enable signal by generating and outputting the power signal corresponding to the power enable signal. In the solution of this application, for each timing control module, the adjustment element corresponds to the delay interval between adjacent signals among the multiple power enable signals output by the timing control module. The timing control module outputs multiple power enable signals in response to the enable signal in the valid state. The power module receives multiple power enable signals and generates power signals corresponding to the multiple power enable signals. This realizes the output of multiple power signals with different timings in a non-programming manner, without the need to burn firmware. It is especially suitable for scenarios with a small number of power signals, saving the cost of power timing control. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 This is a schematic diagram of the structure of a power supply timing control circuit provided in Embodiment 1 of this application;

[0019] Figure 2 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 1 of this application;

[0020] Figure 3 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 1 of this application;

[0021] Figure 4 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 2 of this application;

[0022] Figure 5 This is a signal state diagram of the power-on phase provided in Embodiment 2 of this application;

[0023] Figure 6 This is a signal state diagram of the power-down phase provided in Embodiment 2 of this application;

[0024] Figure 7 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 3 of this application;

[0025] Figure 8 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 3 of this application;

[0026] Figure 9 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 3 of this application;

[0027] Figure 10 This is a signal state diagram of the power-on phase provided in Embodiment 3 of this application;

[0028] Figure 11 This is a signal state diagram of the power-down phase provided in Embodiment 3 of this application;

[0029] Figure 12 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 4 of this application;

[0030] Figure 13 This is a signal state diagram of the power-on phase provided in Embodiment 4 of this application;

[0031] Figure 14 This is a signal state diagram for the power-down phase provided in Embodiment 4 of this application.

[0032] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0034] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0035] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise indicated. It should be understood that such terms can be used interchangeably where appropriate, for example, to implement the application in a sequence other than those given in the embodiments illustrated or described herein.

[0036] Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover but not exclude inclusion. For example, a product or device that includes a series of components is not necessarily limited to those explicitly listed, but may include other components not explicitly listed or inherent to such product or device. As used in this application, the term "module" means any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0037] With the continuous upgrading and iteration of electronic products, their functions and structures are becoming increasingly complex, and the integration level of circuits is getting higher and higher. Electronic products integrate different functional modules, and the timing and magnitude of power signals required for the operation of components in different functional modules vary. In most cases, each module requires power signals with different timing sequences. As electronic products are upgraded and iterated, the timing requirements between power signals increase, making power signal timing design and debugging more complex.

[0038] In related technologies, electronic products include programmable logic devices or programmable timing chips. The power supply signal VCC supplies power to the electronic products. The programmable logic device or programmable timing chip receives the power supply signal VCC and obtains the power supply signals corresponding to each component by software programming the programmable logic device or programmable timing chip. The power supply signals corresponding to each component are then transmitted to each component to realize the timing control of power-on and power-off of each component.

[0039] In the aforementioned technologies, power timing control using programmable logic devices or programmable timing chips requires software programming, necessitating firmware flashing during mass production. In practical applications, when there are a large number of power signals, the timing requirements for each signal vary considerably, and software programming can meet the power signal needs of more complex boards. However, for cases with a small number of power signals, the above methods require firmware flashing, resulting in higher costs for power timing control.

[0040] In view of this, embodiments of this application provide a power timing control circuit, which includes at least one timing control module and a power module. Each timing control module includes a timing control chip and an adjustment element. The adjustment element is connected to the delay setting terminal of the timing control chip, and the adjustment element corresponds to the delay interval between adjacent signals in a plurality of power enable signals output by the timing control module. A first output terminal of at least one timing control module is connected to a first input terminal of the power module. The timing control module receives an enable signal, and when the enable signal is in an active state, the timing control module outputs a plurality of power enable signals to the power module through the plurality of first output terminals. The power module generates a power signal corresponding to the power enable signal based on the active power enable signal, thereby realizing the output of multiple power signals with different timings in a non-programming manner, without the need for firmware burning, saving the cost of power timing control.

[0041] The technical solutions of this application will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. In the description of this application, unless otherwise expressly specified and limited, the terms should be broadly understood within the art. The embodiments of this application will now be described with reference to the accompanying drawings.

[0042] Example 1

[0043] Figure 1 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 1 of this application, as shown below. Figure 1 As shown, this embodiment provides a power supply timing control circuit, including: at least one timing control module 10 and a power supply module 11.

[0044] In this embodiment, each timing control module 10 includes a timing control chip 12 and an adjustment element 13. The timing control chip 12 has a delay setting terminal TEST, and the adjustment element 13 is connected to the delay setting terminal TEST of the timing control chip 12. Each timing control module 10 includes multiple first output terminals FLAG, and the power module 11 includes multiple first input terminals. At least one first output terminal FLAG of the timing control module 10 is connected to a first input terminal of the power module 11 in a one-to-one correspondence.

[0045] In this embodiment, the timing control chip 12 of each timing control module 10 receives the enable signal EN corresponding to the timing control module 10. When the enable signal EN is in an active state, it generates multiple power enable signals FLAGEN and outputs them through the corresponding first output terminal FLAG. There is a delay interval between adjacent signals in the multiple power enable signals FLAGEN that corresponds to the adjustment element 13 of the timing control module 10.

[0046] In this embodiment, the power module 11 receives a power enable signal FLAGEN and a power supply signal VCC output by at least one timing control module 10, and generates and outputs a power signal corresponding to the power enable signal FLAGEN in response to the power enable signal FLAGEN being in an active state.

[0047] In practical applications, the timing control chip 12 is a non-programmable control chip used to output multiple power enable signals (FLAGEN) to control the power module 11 to output multiple power signals. For example, the timing control chip 12 can be a power sequencer. Specifically, the timing control chip 12 can be a TPK1031L1-VS1R-S, TPK1031, or LM3881, etc.

[0048] The timing control chip 12 includes a power input terminal and an enable input terminal. The power input terminal of the timing control chip 12 receives a power supply signal VCC, and the enable input terminal of the timing control chip 12 receives an enable signal EN. The timing control chip 12 includes multiple output terminals, which are correspondingly connected to the first output terminal FLAG of the timing control module 10.

[0049] It should be noted that the power supply signal VCC is used to power the timing control chip 12. The timing control module 10 will only output the power enable signal FLAGEN when both the power supply signal VCC and the enable signal EN are active. The enable signal EN is used to control the timing of the power enable signal FLAGEN output by the multiple first output terminals FLAG of the timing control module 10.

[0050] In practical applications, the operation of the power supply timing control circuit is divided into a power-on phase and a power-off phase. The effective state of the enable signal EN differs between the power-on and power-off phases, and the timing of the power enable signals output by the multiple first output terminals FLAG of at least one timing control module 10 is different.

[0051] For example, during the power-on phase, the effective state of the enable signal EN is a high level. When the enable signal EN corresponding to the timing control module 10 changes from a low level to a high level, the multiple first output terminals FLAG of the timing control module 10 output the enable signal FLAGEN, which changes from a low level to a high level, in a top-to-bottom order.

[0052] Correspondingly, during the power-down phase, the effective state of the enable signal EN is low. When the enable signal EN corresponding to the timing control module 10 changes from high to low, the multiple first output terminals FLAG of the timing control module 10 output the enable signal FLAGEN, which changes from high to low, in a bottom-to-top order.

[0053] For example, the timing control module 10 includes three first output FLAGs, which are FLAG1, FLAG2, and FLAG3 in top-to-bottom order. During power-up, the timing control module 10 receives the corresponding enable signal EN, and the level of the enable signal EN changes from low to high. The power enable signals FLAGEN output by the first output FLAG1, FLAG2, and FLAG3 then sequentially change from low to high. During power-down, the timing control module 10 receives the corresponding enable signal EN, and the level of the enable signal EN changes from high to low. The power enable signals FLAGEN output by the first output FLAG3, FLAG2, and FLAG1 then sequentially change from high to low.

[0054] In practical applications, during the power-on phase, the transition times of adjacent signals in the multiple power enable signals FLAGEN from low to high levels are separated by a fixed delay interval; during the power-off phase, the transition times of adjacent signals in the multiple power enable signals FLAGEN from high to low levels are separated by a fixed delay interval.

[0055] In this embodiment, the delay setting terminal TEST of the timing control chip 12 is externally connected to an adjustment element 13 to control the delay interval between adjacent signals in the power enable signal output by the timing control chip 12. The timing control chip 12 responds to different states of the enable signal EN and outputs the power enable signal FLAGEN according to different timing sequences through the first output terminal FLAG.

[0056] Referring to the above example, the timing of multiple power enable signals FLAGEN is controlled by the enable signal EN, and the delay interval between adjacent signals in the multiple power enable signals FLAGEN is determined based on the adjustment element. It can be understood that the timing control chip 12 can output multiple power enable signals FLAGEN without programming.

[0057] In practical applications, the power module 11 receives a power supply signal VCC, which supplies power to the power module 11. The first input terminal of the power module 11 is connected to the first output terminal FLAG of at least one timing control module 10. The first input terminal of the power module 11 receives a power enable signal FLAGEN, and the power module 11 outputs a power signal corresponding to the power enable signal in response to the power enable signal FLAGEN being in an active state.

[0058] Based on the above example, during the power-on phase, the power enable signal FLAGEN changes from a low level to a high level, and the power module 11 outputs the power signal corresponding to the power enable signal FLAGEN, which changes from a low level to a high level. During the power-off phase, the power enable signal FLAGEN changes from a low level to a high level, and the power module 11 outputs the power signal corresponding to the power enable signal FLAGEN, which changes from a high level to a low level.

[0059] It should be noted that there is a fixed time interval between the power signal and the corresponding power enable signal FLAGEN, and the timing of the multiple power signals output by the power module 11 corresponds to the timing of the multiple power enable signals FLAGEN. In practical applications, each power signal corresponds to a component in an electronic product. For different components, the required power signal size may be different, and the power module 11 can output multiple power signals of different sizes.

[0060] It is understandable that the timing control module 10 and the power supply module 11 can output power signals with certain timing and different magnitudes, thereby realizing the power timing control of different components.

[0061] In this embodiment, for each timing control module 10, the adjustment element 13 corresponds to the delay interval between adjacent signals in the multiple power enable signals FLAGEN output by the timing control module 10. The timing control module 10 outputs multiple power enable signals FLAGEN in response to the enable signal EN in the valid state. The power module 11 receives the multiple power enable signals FLAGEN and generates power signals corresponding to the multiple power enable signals FLAGEN. This realizes the output of multiple power signals with different timings in a non-programming manner, without the need to burn firmware, thus saving the cost of power timing control.

[0062] Optionally, for the adjusting element 13, in one possible implementation, Figure 2 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 1 of this application, as shown below. Figure 2 As shown, the adjustment element 13 includes a first capacitor C1;

[0063] One end of the first capacitor C1 is connected to the delay setting terminal TEST of the timing control chip 12, and the other end of the first capacitor C1 is grounded.

[0064] In practical applications, the timing control chip 12 includes a delay setting terminal TEST. By connecting a first capacitor C1 to the delay setting terminal TEST, the delay interval between adjacent signals in the multiple power enable signals FLAGEN output by the timing control module 10 can be controlled.

[0065] For example, the delay setting terminal TEST of the timing control chip 12 is in the voltage range of V H and V L Between, the delay setting terminal TEST is approximately I SOURCE The source current charges the first capacitor C1, and the delay setting terminal TEST charges it with approximately I... SINK The current draws through the capacitor discharges the first capacitor C1. Calculate the charging period T of the first capacitor C1. CHG The discharge period T of the first capacitor C1 DISCHG The sum of these values ​​is used as the aforementioned delay interval. The delay interval can be expressed as T. CLK Delay interval T CLK The calculation expression is:

[0066]

[0067] It is understood that the delay interval is positively correlated with the capacitance value of the first capacitor C1. Therefore, the size of the delay interval can be adjusted based on the first capacitor C1. For the timing control module 10, the delay interval between adjacent signals in the power enable signals FLAGEN output by the multiple first output terminals FLAG of the timing control module 10 is the same and is related to the capacitance value of the first capacitor C1 in the timing control module 10.

[0068] In one example, the capacitance value of the first capacitor C1 in each timing control module 10 of the power timing control circuit is the same, and the delay interval between the multiple power enable signals FLAGEN output by different timing control modules 10 in the power timing control circuit is the same.

[0069] Optionally, the power timing control circuit includes multiple timing control modules 10. The capacitance value of the first capacitor C1 in different timing control modules 10 is different, and the delay interval between the multiple power enable signals FLAGEN output by different timing control modules 10 in the power timing control circuit is different.

[0070] In this embodiment, the adjustment element includes a first capacitor, which is connected to the delay setting terminal of the timing control chip. The first capacitor can control the delay interval between adjacent signals in the multiple power enable signals output by the timing control module. When the enable signal received by the timing control module is in an active state, it outputs multiple power enable signals according to the delay interval corresponding to the first capacitor. The power module receives the multiple power enable signals and generates power signals corresponding to the multiple power enable signals. This realizes the output of multiple power signals with different timings in a non-programming manner, without the need to burn firmware, thus saving the cost of power timing control.

[0071] Optionally, for power module 11, in one possible implementation, Figure 3 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 1 of this application, as shown below. Figure 3 As shown, the power module 11 includes multiple power chips (DC-CDC), and each of the multiple power chips (DC-CDC) corresponds to a first input terminal of the power module.

[0072] Each power supply chip DC-DC receives a power supply signal VCC at its power input terminal. The enable input terminal of the power supply chip DC-DC is connected to the corresponding first input terminal. When the received power enable signal FLAGEN is valid, the power supply chip DC-DC generates a power signal corresponding to the power enable signal FLAGEN based on the power supply signal VCC.

[0073] The DC-DC power supply chip is a DC-to-DC converter chip. It receives the power supply signal VCC and its corresponding power enable signal FLAGEN, generating a power signal of the corresponding magnitude. In practical applications, during the power-on phase, the DC-DC power supply chip receives the power enable signal FLAGEN, which changes from a low level to a high level, and outputs a power signal of the corresponding magnitude. During the power-off phase, the DC-DC power supply chip receives the power enable signal FLAGEN, which changes from a high level to a low level, and stops outputting a power signal.

[0074] In practical applications, each power supply chip (DC-CDC) corresponds to a power enable signal (FLAGEN), and the timing of different power enable signals (FLAGEN) is different. It can be understood that the timing of the multiple power signals output by multiple power supply chips (DC-CDC) corresponds to the timing of the multiple power enable signals (FLAGEN) output by the timing control module 10.

[0075] For example, during the power-on phase, the timing control module 10 sends power enable signals FLAGEN1, FLAGEN2, FLAGEN3, and FLAGEN4 in sequence. Power enable signal FLAGEN1 corresponds to power chip DC-DC1, power enable signal FLAGEN2 corresponds to power chip DC-DC2, power enable signal FLAGEN3 corresponds to power chip DC-DC3, and power enable signal FLAGEN4 corresponds to power chip DC-DC4. Power chips DC-DC1, DC-DC2, DC-DC3, and DC-DC4 output their corresponding power signals in sequence.

[0076] Correspondingly, during the power-down phase, the timing control module 10 sends power enable signals in the following order: FLAGEN4, FLAGEN3, FLAGEN2, and FLAGEN1; power chips DC-CDC4, DC-CDC3, DC-CDC2, and DC-CDC1 output their corresponding power signals in sequence.

[0077] In this embodiment, the power module includes multiple power chips, and each power enable signal corresponds to a power chip. The power chip generates power signals of different magnitudes in response to the corresponding power enable signal. Furthermore, the timing of the power signals output by the power chips corresponds to the corresponding power enable signals. The power timing control circuit realizes the output of multiple power signals with different timings in a non-programming manner, eliminating the need for firmware burning and saving the cost of power timing control.

[0078] The power timing control circuit provided in this embodiment includes at least one timing control module and a power module. Each timing control module includes a timing control chip and an adjustment element, with the adjustment element connected to the delay setting terminal of the timing control chip. The first output terminal of at least one timing control module is connected to the first input terminal of the power module in a one-to-one correspondence. When the enable signal received by the timing control chip is in an active state, multiple power enable signals are generated and output through their corresponding first output terminals. Adjacent signals among the multiple power enable signals have a delay interval corresponding to the adjustment element of the timing control module. The power module, in response to an active power enable signal, generates and outputs a power signal corresponding to that power enable signal. In this embodiment, for each timing control module, the adjustment element corresponds to the delay interval between adjacent signals among the multiple power enable signals output by the timing control module. The timing control module outputs multiple power enable signals in response to an active enable signal. The power module receives multiple power enable signals and generates power signals corresponding to those signals, achieving the output of multiple power signals with different timings without programming, eliminating the need for firmware burning and saving on power timing control costs.

[0079] Example 2

[0080] Embodiment 2 of this application provides a power timing control circuit, the operation of which is divided into a power-on stage and a power-off stage. Figure 4 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 2 of this application. Based on the above embodiments, as follows... Figure 4 As shown, the power supply timing control circuit has one timing control module 10, and the timing control module 10 has three first output terminals.

[0081] In this embodiment, the three first output terminals of the timing control module 10 have the same function. To facilitate differentiation, they are represented by different identifiers. For example, the timing control module 10 includes three first output terminals, which, in order from top to bottom, are: first output terminal FLAG1, first output terminal FLAG2, and first output terminal FLAG3. Correspondingly, the first output terminal FLAG1 of the timing control module 10 outputs a first power enable signal FLAGEN1, the first output terminal FLAG2 outputs a second power enable signal FLAGEN2, and the first output terminal FLAG3 outputs a third power enable signal FLAGEN3.

[0082] The delay interval between two adjacent signals in the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3 is the delay interval corresponding to the adjustment element 13 in the timing control module 10.

[0083] In practical applications, the power module 11 includes three first input terminals, which are connected one-to-one with the three first output terminals of the timing control module 10. For ease of differentiation, different identifiers are used. For example, the three first input terminals of the power module 11, in top-to-bottom order, are: first input terminal I1, first input terminal I2, and first input terminal I3. Specifically, first input terminal I1 is connected to the first output terminal FLAG1 and receives the first power enable signal FLAGEN1; first input terminal I2 is connected to the first output terminal FLAG2 and receives the second power enable signal FLAGEN2; and first input terminal I3 is connected to the first output terminal FLAG3 and receives the third power enable signal FLAGEN3.

[0084] Correspondingly, the power module 11 includes three output terminals. In response to the first power enable signal FLAGEN1, the power module 11 outputs a first power signal V1; in response to the second power enable signal FLAGEN2, the power module 11 outputs a second power signal V2; and in response to the third power enable signal FLAGEN3, the power module 11 outputs a first power signal V3.

[0085] It should be noted that the number of first output terminals of the timing control module 10 is not limited to three. The number of first output terminals is determined by the internal structure of the timing control module 10 and actual needs, and will not be limited here.

[0086] In one example, during the power-on phase, the valid state is high, and during the power-off phase, the valid state is low. To facilitate understanding of the scheme, the following section combines... Figure 5 and Figure 6 The operation of the power-on and power-off phases of the power supply timing control circuit is explained. Figure 5 This is a signal state diagram for the power-on phase provided in Embodiment 2 of this application. Figure 6 This is a signal state diagram for the power-down phase provided in Embodiment 2 of this application.

[0087] Combination Figure 4 and Figure 5Understandably, during the power-on phase, the timing control module 10 receives the enable signal EN. The level of the enable signal EN changes from a low level to a high level. The first output terminal FLAG1, the first output terminal FLAG2, and the first output terminal FLAG3 output the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3, which are in an effective state. That is, the level of the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3 changes from a low level to a high level in sequence.

[0088] Correspondingly, during the power-on phase, the power enable signals FLAGEN1, FLAGEN2, and FLAGEN3 change from low to high levels in sequence, and the power module 11 outputs the first power signal V1, the second power signal V2, and the third power signal V3 in sequence at high levels.

[0089] Combination Figure 4 and Figure 6 Understandably, during the power-down phase, the timing control module 10 receives the enable signal EN. The level of the enable signal EN changes from a high level to a low level. The first output terminal FLAG3, the first output terminal FLAG2, and the first output terminal FLAG1 output the third power enable signal FLAGEN3, the second power enable signal FLAGEN2, and the first power enable signal FLAGEN1, which are in an active state. That is, the level of the third power enable signal FLAGEN3, the second power enable signal FLAGEN2, and the first power enable signal FLAGEN1 changes from a high level to a low level.

[0090] Correspondingly, during the power-down phase, the power enable signals FLAGEN3, FLAGEN2, and FLAGEN1 change from high to low levels in sequence, and the power module 11 stops outputting the third power signal V3, the second power signal V2, and the first power signal V1 in sequence.

[0091] In this embodiment, the power timing control circuit includes a timing control module 10, which has three first output terminals. The timing control module 10 outputs three power enable signals in response to an enable signal in an active state. The delay interval between adjacent power enable signals output by the timing control module 10 corresponds to the adjustment element in the timing control module. The power module 11 receives the three power enable signals and generates a power signal corresponding to each power enable signal, thus achieving the output of three power signals with different timings without programming, eliminating the need for firmware burning and saving on the cost of power timing control.

[0092] In one example, the power module 11 includes three power chips: a first power chip DC-DC1, a second power chip DC-DC2, and a third power chip DC-DC3. The input terminal of the first power chip DC-DC1 is connected to the first output terminal FLAG1 of the timing control module 10 and receives the first power enable signal FLAGEN1. The input terminal of the second power chip DC-DC2 is connected to the first output terminal FLAG2 of the timing control module 10 and receives the second power enable signal FLAGEN2. The input terminal of the third power chip DC-DC3 is connected to the first output terminal FLAG3 of the timing control module 10 and receives the third power enable signal FLAGEN3.

[0093] Optionally, in one example, the power timing control circuit further includes a second AND gate corresponding to the second power chip DC-DC2 and a second AND gate corresponding to the third power chip DC-DC3.

[0094] The first input terminal of the second AND gate is connected to the PG terminal of the first power chip DC-DC1, the second input segment of the second AND gate is connected to the first output terminal FLAG2 of the timing control module 10, and the output terminal of the second AND gate is connected to the enable input terminal of the second power chip DC-DC2.

[0095] The first input of the second AND gate is connected to the PG terminal of the second power supply chip DC-DC2, the second input segment of the second AND gate is connected to the first output terminal FLAG3 of the timing control module 10, and the output terminal of the second AND gate is connected to the enable input terminal of the third power supply chip DC-DC3.

[0096] In this example, each power chip is connected to the first output terminal of the timing control module 10. There is a sequence between the output terminals of the timing control module 10. The sequence of the output terminals of the timing control module 10 depends on the timing of the multiple power enable signals output by the timing control module 10. Therefore, the order of the power chips also depends on the timing of the power enable signals.

[0097] During the power-on phase, the timing control module 10 outputs a first power enable signal FLAGEN1, a second power enable signal FLAGEN2, and a third power enable signal FLAGEN3 sequentially through the first output terminal FLAG1, the first output terminal FLAG2, and the first output terminal FLAG3. Based on the timing of the multiple output power enable signals, the first output terminal FLAG1 is taken as the first output terminal of the timing control module 10. Correspondingly, the first power chip DCCDC1 corresponding to the first output terminal FLAG1 is taken as the first power chip, and the second power chip DCCDC2 and the third power chip DCCDC3 are taken as each power chip except the first power chip.

[0098] The signal output from the PG terminal is used to indicate whether the power chip is outputting a power signal normally. During the power-on phase, the power chip receives a power enable signal. When the power enable signal changes from a low level to a high level, the power chip responds to the high-level power enable signal and outputs a power signal. The PG terminal of the power chip outputs a high-level PG signal.

[0099] During the power-down phase, the power chip receives a power enable signal. The power enable signal changes from a high level to a low level. In response to the low-level power enable signal, the power chip stops outputting power signals, and the PG terminal of the power chip stops the PG signal.

[0100] Specifically, during the power-on phase, the enable input of the first power chip DC-DC1 receives the first power enable signal FLAGEN1. FLAGEN1 changes from a low level to a high level, and in response, DC-DC1 outputs the first power signal V1. The PG terminal of DC-DC1 also outputs a high-level signal PG1. The first input of the second AND gate receives the PG1 signal, and the second input receives the second power enable signal FLAGEN2. When both PG1 and FLAGEN2 are high, the output of the second AND gate outputs a high-level signal, and the second power chip DC-DC2 outputs the second power signal V2. The PG terminal of the second power chip DC-DC2 also outputs a high-level signal PG2. The first input of the second AND gate receives the PG2 signal, and the second input of the second AND gate receives the third power enable signal FLAGEN3. When both the PG2 signal and the third power enable signal FLAGEN3 are in a high-level state, the output of the second AND gate outputs a high-level signal, and the third power chip DCDC3 outputs the third power signal V3.

[0101] In this example, the non-first power chip is controlled by the combined PG signal output by the previous power chip and the corresponding power enable signal of the power chip. During the power-on phase, the power chip can output the power signal after the previous power chip has been powered on, which improves the accuracy of power timing control.

[0102] In this embodiment, the power timing control circuit includes a timing control module with three first output terminals. The timing control module outputs three power enable signals in response to an active enable signal. The delay interval between adjacent power enable signals corresponds to the adjustment element in the timing control module. The power module receives the three power enable signals and generates a power signal corresponding to each power enable signal, thus achieving the output of three power signals with different timings without programming. This eliminates the need for firmware flashing and saves on the cost of power timing control.

[0103] Example 3

[0104] Embodiment 3 of this application provides a power supply timing control circuit, the operation of which is divided into a power-on phase and a power-off phase. Based on the above embodiments, Figure 7 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 3 of this application. Based on the above embodiments, as follows... Figure 7 As shown, there are multiple timing control modules 10, which are arranged sequentially; the power supply timing control circuit also includes an indicator module 71 corresponding to each timing control module 10.

[0105] In this embodiment, the indicator module 71 receives the trigger signal PWOK, and the output terminal of the indicator module 71 is connected to the corresponding timing control module 10. The indicator module 71 is used to generate an enable signal EN corresponding to the timing control module 10 according to the trigger signal PWOK. In the power-on stage, the order in which the indicator modules 71 corresponding to each timing control module 10 output the enable signals in the valid state is consistent with the arrangement order of the multiple timing control modules 10. In the power-off stage, the order in which the indicator modules 71 corresponding to each timing control module 10 output the enable signals EN in the valid state is reversed compared to the arrangement order of the multiple timing control modules 10.

[0106] It is understandable that the power timing control circuit needs to generate multiple power signals with different timings, and control the output of multiple power enable signals with different timings through multiple timing control modules 10. The multiple power enable signals with different timings are transmitted to the power module 11, and the power module 11 outputs multiple power signals with different timings based on the multiple power enable signals with different timings.

[0107] In practical applications, the arrangement order of the multiple timing control modules 10 corresponds to the timing order of the multiple power enable signals output by the timing control modules 10. For example, the power timing control circuit includes a first timing control module 10A and a second timing control module 10B, dividing the multiple power enable signals with different timings into two groups. During the power-on phase, the signals with earlier timings are grouped together and output by the first timing control module 10A; the signals with later timings are grouped together and output by the second timing control module 10B. The first timing control module 10A is positioned above the second timing control module 10B.

[0108] In this embodiment, during the power-on phase, the effective state of the trigger signal PWOK is high, and the effective state of the enable signal EN is high; during the power-off phase, the effective state of the trigger signal PWOK is low, and the effective state of the enable signal EN is low.

[0109] In practical applications, during the power-on phase, according to the arrangement order of the multiple timing control modules 10, the enable signals output by the indicator modules 71 corresponding to each timing control module 10 sequentially change from a low level to a high level. During the power-off phase, according to the reverse order of the arrangement order of the multiple timing control modules 10, the enable signals output by the indicator modules 71 corresponding to each timing control module 10 sequentially change from a high level to a low level.

[0110] For example, the power timing control circuit needs to generate nine power signals with different timings. The power timing control circuit includes a first timing control module 10A, a second timing control module 10B, and a third timing control module 10C. The first timing control module 10A corresponds to the first indicator module 71A, the second timing control module 10B corresponds to the second indicator module 71B, and the third timing control module 10C corresponds to the third indicator module 71C.

[0111] During the power-on phase, the first indicator module 71A, the second indicator module 71B, and the third indicator module 71C receive the trigger signal PWOK, which changes from a low level to a high level. The enable signal EN1 output by the first indicator module 71A changes from a low level to a high level. In response to the active enable signal EN1, the first timing control module 10A outputs the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3, which sequentially change from a low level to a high level.

[0112] Correspondingly, after the third power enable signal FLAGEN3 output by the first timing control module 10A changes from a low level to a high level, the enable signal EN2 output by the second indicator module 71B changes from a low level to a high level. In response to the enabled signal EN2 being in an active state, the fourth power enable signal FLAGEN4, the fifth power enable signal FLAGEN5, and the sixth power enable signal FLAGEN6 output by the second timing control module 10B change from a low level to a high level in sequence.

[0113] Correspondingly, after the sixth power enable signal FLAGEN6 output by the second timing control module 10B changes from a low level to a high level, the enable signal EN3 output by the third indicator module 71C changes from a low level to a high level. In response to the enabled signal EN3 being in an active state, the seventh power enable signal FLAGEN7, the eighth power enable signal FLAGEN8, and the ninth power enable signal FLAGEN9 output by the third timing control module 10C change from a low level to a high level in sequence.

[0114] During the power-down phase, the first indicator module 71A, the second indicator module 71B, and the third indicator module 71C receive the trigger signal PWOK, which changes from a high level to a low level. The enable signal EN3 output by the third indicator module 71C changes from a high level to a low level. In response to the active enable signal EN3, the third timing control module 10C outputs the ninth power enable signal FLAGEN9, the eighth power enable signal FLAGEN8, and the seventh power enable signal FLAGEN7, which sequentially change from a high level to a low level.

[0115] Correspondingly, after the seventh power enable signal FLAGEN7 output by the third timing control module 10C changes from a high level to a low level, the enable signal EN2 output by the second indicator module 71B changes from a high level to a low level. In response to the enable signal EN2 being in an active state, the sixth power enable signal FLAGEN6, the fifth power enable signal FLAGEN5, and the fourth power enable signal FLAGEN4 output by the second timing control module 10B change from a high level to a low level in sequence.

[0116] Correspondingly, after the fourth power enable signal FLAGEN4 output by the second timing control module 10B changes from a high level to a low level, the enable signal EN1 output by the first timing control module 10A changes from a high level to a low level. In response to the enable signal EN1 being in an active state, the third power enable signal FLAGEN3, the second power enable signal FLAGEN2, and the first power enable signal FLAGEN1 output by the first timing control module 10A change from a high level to a low level in sequence.

[0117] Based on the above example, for each timing control module 10, the multiple power enable signals FLAGEN output by the timing control module 10 have a certain timing order, and the timing control module 10 outputs the corresponding timing power enable signal FLAGEN in response to the enable signal EN in the active state.

[0118] In this embodiment, during the power-on phase, the indicator module 71 corresponding to each timing control module 10 outputs an enable signal EN in an active state according to the arrangement order of the multiple timing control modules 10; during the power-off phase, the indicator module 71 corresponding to each timing control module 10 outputs an enable signal EN in an active state in the reverse order of the arrangement order of the multiple timing control modules 10, thereby realizing the timing control of the power enable signals FLAGEN output by different timing control modules 10. Each timing control module 10 responds to the corresponding enable signal EN and outputs a power enable signal FLAGEN with the corresponding timing. The power module 11 receives the power enable signal FLAGEN in an active state and outputs a power signal with the corresponding timing based on the power enable signal FLAGEN, thereby realizing the timing control of multiple power signals.

[0119] Optionally, in one example, the number of timing control modules 10 described above is two;

[0120] Among them, the first input terminal of the indicator module 71 corresponding to the first timing control module 10 receives the trigger signal PWOK, and the second input terminal of the indicator module 71 is connected to the first output terminal of the other timing control module 10.

[0121] The first input terminal of the indicator module 71 corresponding to the other timing control module 10 receives the trigger signal PWOK, and the second input terminal of the other indicator module 71 is connected to the first output terminal at the end of the first timing control module 10.

[0122] For example, each timing control module 10 has three first output terminals. Figure 8 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 3 of this application, as shown below. Figure 8As shown, the power supply timing control circuit includes: a first timing control module 10A, a second timing control module 10B, a first indicator module 71A corresponding to the first timing control module 10A, a second indicator module 71B corresponding to the second timing control module 10B, and a power supply module 11.

[0123] The first timing control module 10A is the first power timing control module, and the second timing control module 10B is the other timing control module. The first timing control module 10A includes three first output terminals, designated as FLAG1, FLAG2, and FLAG3 according to the timing of the power enable signals output during the power-on phase. The second timing control module 10B includes three first output terminals, designated as FLAG4, FLAG5, and FLAG6 according to the timing of the power enable signals output during the power-on phase. The first output terminal of the other timing control module 10 is FLAG4, and the last first output terminal of the first timing control module 10 is FLAG3.

[0124] like Figure 8 As shown, the first input terminal of the first indicator module 71A receives the trigger signal PWOK, and the second input terminal of the first indicator module 71A is connected to the first output terminal FLAG4 of the second timing control module 10B; the first input terminal of the second indicator module 71B receives the trigger signal PWOK, and the second input terminal of the second indicator module 71B is connected to the first output terminal FLAG3 of the first timing control module 10A.

[0125] In practical applications, for the first indicator module 71A, during the power-on phase, as long as there is a valid signal among the signals received by the first input segment and the second input terminal of the first indicator module 71A, the first indicator module 71A will output an enable signal EN1 that is in a valid state; during the power-off phase, the first indicator module 71A will only output an enable signal EN1 that is in a valid state when all signals received by the first input segment and the second input terminal of the first indicator module 71A are in a valid state.

[0126] For the second indicator module 71B, during the power-on phase, the second indicator module 71B will only output an enable signal when all signals received by the first input segment and the second input terminal of the second indicator module 71B are in a valid state; during the power-off phase, the second indicator module 71B will output an enable signal as long as there is a valid signal among the signals received by the first input terminal and the second input terminal of the second indicator module 71B.

[0127] In one example, during the power-on phase, the valid state is a high level; during the power-off phase, the valid state is a low level. In practical applications, when one of the signals received by the first input terminal and the second input terminal of the first indicator module 71A is in a high-level state, the first indicator module 71A outputs a high-level enable signal EN1; when both the first input terminal and the second input terminal of the first indicator module 71A receive signals in a low-level state, the first indicator module 71A outputs a low-level enable signal EN1. When both the first input terminal and the second input terminal of the second indicator module 71B receive signals in a high-level state, the second indicator module 71B outputs a high-level enable signal EN2; when both the first input terminal and the second input terminal of the second indicator module 71B receive signals in a low-level state, the second indicator module 71B outputs a low-level enable signal EN2.

[0128] Specifically, during the power-on phase, the trigger signal PWOK changes from a low level to a high level. The first input terminal of the first indicator module 71A receives the trigger signal PWOK, and the enable signal EN1 output by the first indicator module 71A changes from a low level to a high level. In response to the high-level enable signal EN1, the first timing control module 10A outputs the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3, which sequentially change from a low level to a high level. The first input terminal of the second indicator module 71B receives the trigger signal PWOK, and the second input terminal receives the third power enable signal FLAGEN3, both of which are at a high level. The enable signal EN2 output by the second indicator module 71B changes from a low level to a high level. In response to the high-level enable signal EN2, the second timing control module 10B outputs the fourth power enable signal FLAGEN4, the fifth power enable signal FLAGEN5, and the sixth power enable signal FLAGEN6, which sequentially change from a low level to a high level.

[0129] Correspondingly, during the power-down phase, the trigger signal PWOK changes from a high level to a low level. The first input terminal of the second indicator module 71B receives the trigger signal PWOK, and the enable signal EN2 output by the second indicator module 71B changes from a high level to a low level. In response to the low-level enable signal EN2, the second timing control module 10B outputs the sixth power enable signal FLAGEN6, the fifth power enable signal FLAGEN5, and the fourth power enable signal FLAGEN4, which sequentially change from a high level to a low level. The first input terminal of the first indicator module 71A receives the trigger signal PWOK, and the second input terminal receives the fourth power enable signal FLAGEN4, both of which are at a low level. The enable signal EN1 output by the first indicator module 71A changes from a high level to a low level. In response to the low-level enable signal EN1, the first timing control module 10A outputs the third power enable signal FLAGEN3, the second power enable signal FLAGEN2, and the first power enable signal FLAGEN1, which sequentially change from a high level to a low level.

[0130] In this example, the indicator module corresponding to the first timing control module receives a trigger signal and a power enable signal output from the first output terminal of another timing control module. During the power-down phase, after the other timing control module completes the output of a valid power enable signal, the first timing control module can be controlled to output a valid power enable signal. The indicator module corresponding to the other timing control module receives a trigger signal and a power enable signal output from the last output terminal of the first timing control module. During the power-on phase, after the first timing control module completes the output of a valid power enable signal, the other timing control module can be controlled to output a valid power enable signal. This achieves control over the timing of the power enable signals output by different timing control modules. The power module receives power enable signals of different timings and generates power signals of corresponding timings, thus achieving timing control of the power signals.

[0131] In one example, Figure 9 This is a schematic diagram of another power supply timing control circuit provided in Embodiment 3 of this application, as shown below. Figure 9 As shown, the indicator module 71A corresponding to the first timing control module 10A includes a first OR gate 91, and the indicator module 71B corresponding to the other timing control module 10B includes a first AND gate 92.

[0132] The first input terminal of the first OR gate 91 receives the trigger signal PWOK, the second input terminal of the first OR gate 91 is connected to the first output terminal of another timing control module 10, and the output terminal of the first OR gate 91 is connected to the enable input terminal of the first timing control module 10.

[0133] The first input of the first AND gate 92 receives the trigger signal PWOK. The second input of the first AND gate 92 is connected to the first output of the first timing control module 10. The output of the first AND gate 92 is connected to the enable input of another timing control module 10.

[0134] In practical applications, for the first OR gate 91, during the power-on phase, as long as there is a valid signal among the signals received by the first input segment and the second input terminal of the first OR gate 91, the first OR gate 91 will output the valid enable signal EN1; during the power-off phase, the first OR gate 91 will only output the valid enable signal EN1 when all signals received by the first input segment and the second input terminal of the first OR gate 91 are valid.

[0135] For the first AND gate 92, during the power-on phase, the first AND gate 92 will only output an enable signal when all signals received by the first input segment and the second input terminal of the first AND gate 92 are in a valid state; during the power-off phase, the first AND gate 92 will output an enable signal as long as there is a valid signal among the signals received by the first input terminal and the second input terminal of the first AND gate 92.

[0136] In one example, during the power-on phase, the valid state is high; during the power-off phase, the valid state is low. In practical applications, when one of the signals received by the first input and the second input of the first OR gate 91 is high, the first OR gate 91 outputs a high-level enable signal EN1; when both the first and second inputs of the first OR gate 91 are low, the first OR gate 91 outputs a low-level enable signal EN1. Similarly, when both the first and second inputs of the first AND gate 92 are high, the first AND gate 92 outputs a high-level enable signal EN2; when both the first and second inputs of the first AND gate 92 are low, the first AND gate 92 outputs a low-level enable signal EN2.

[0137] To facilitate understanding the solution, the following will be combined with... Figure 10 and Figure 11 The operation of the power-on and power-off phases of the power supply timing control circuit is explained. Figure 10 This is a signal state diagram for the power-on phase provided in Embodiment 3 of this application. Figure 11 This is a signal state diagram for the power-down phase provided in Embodiment 3 of this application.

[0138] Combination Figure 9 and Figure 10During the power-on phase, the trigger signal PWOK changes from a low level to a high level. The first input of the first OR gate 91 receives the trigger signal PWOK, and the enable signal EN1 output by the first OR gate 91 changes from a low level to a high level. In response to the high-level enable signal EN1, the first timing control module 10A outputs the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3, which sequentially change from a low level to a high level. The first input of the first AND gate 92 receives both the trigger signal PWOK and the third power enable signal FLAGEN3, both of which are high. The enable signal EN2 output by the first AND gate 92 changes from a low level to a high level. In response to the high-level enable signal EN2, the second timing control module 10B outputs the fourth power enable signal FLAGEN4, the fifth power enable signal FLAGEN5, and the sixth power enable signal FLAGEN6, which sequentially change from a low level to a high level.

[0139] Combination Figure 9 and Figure 11 During the power-down phase, the trigger signal PWOK changes from a high level to a low level. The first input of the first AND gate 92 receives the trigger signal PWOK, and the enable signal EN2 output by the first AND gate 92 changes from a high level to a low level. In response to the low-level enable signal EN2, the second timing control module 10B outputs the sixth power enable signal FLAGEN6, the fifth power enable signal FLAGEN5, and the fourth power enable signal FLAGEN4, which sequentially change from a high level to a low level. The first input of the first OR gate 91 receives both the trigger signal PWOK and the fourth power enable signal FLAGEN4, which are both low. The enable signal EN1 output by the first OR gate 91 changes from a high level to a low level. In response to the low-level enable signal EN1, the first timing control module 10A outputs the third power enable signal FLAGEN3, the second power enable signal FLAGEN2, and the first power enable signal FLAGEN1, which sequentially change from a high level to a low level.

[0140] In this example, the first OR gate corresponding to the first timing control module receives a trigger signal and a power enable signal output from the first output terminal of the other timing control module. During the power-down phase, after the other timing control module completes the output of a valid power enable signal, the first timing control module can be controlled to output a valid power enable signal. The first AND gate corresponding to the other timing control module receives a trigger signal and a power enable signal output from the last output terminal of the first timing control module. During the power-on phase, after the first timing control module completes the output of a valid power enable signal, the other timing control module can be controlled to output a valid power enable signal. This achieves control over the timing of the power enable signals output by different timing control modules. The power module receives power enable signals of different timings and generates power signals of corresponding timings, thus achieving timing control of the power signals.

[0141] In this embodiment, the power timing control circuit includes multiple timing control modules, each corresponding to an indicator module. The indicator module receives a trigger signal. During the power-on phase, the indicator modules corresponding to each timing control module output enable signals in an active state according to the arrangement order of the multiple timing control modules. During the power-off phase, the indicator modules corresponding to each timing control module output enable signals in an active state in the reverse order of the arrangement order of the multiple timing control modules, thus realizing timing control of the power enable signals output by different timing control modules. Each timing control module responds to its corresponding enable signal and outputs a power enable signal with the corresponding timing. The power module receives the active power enable signal and outputs a power signal with the corresponding timing based on the power enable signal, thereby realizing timing control of multiple power signals.

[0142] Example 4

[0143] Figure 12 This is a schematic diagram of a power supply timing control circuit provided in Embodiment 4 of this application. Based on the above embodiments, as follows... Figure 12 As shown, the power timing control circuit further includes: a second AND gate 122 corresponding to the second power chip DC-DC2, a second AND gate 123 corresponding to the third power chip DC-DC3, a second AND gate 124 corresponding to the fourth power chip DC-DC4, a second AND gate 125 corresponding to the fifth power chip DC-DC5, and a second AND gate 126 corresponding to the sixth power chip DC-DC6.

[0144] In this embodiment, the power module 11 includes six power chips: a first power chip DC-DC1, a second power chip DC-DC2, a third power chip DC-DC3, a fourth power chip DC-DC4, a fifth power chip DC-DC5, and a sixth power chip DC-DC6. The input terminal of the first power chip DC-DC1 is connected to the first output terminal FLAG1 of the first timing control module 10A and receives the first power enable signal FLAGEN1.

[0145] Wherein, the first input terminal of the second AND gate 122 is connected to the PG terminal of the first power chip DC-DC1, the second input segment of the second AND gate 122 is connected to the first output terminal FLAG2 of the first timing control module 10A, and the output terminal of the second AND gate 122 is connected to the enable input terminal of the second power chip DC-DC2.

[0146] The first input terminal of the second AND gate 123 is connected to the PG terminal of the second power chip DC-DC2, the second input segment of the second AND gate 123 is connected to the first output terminal FLAG3 of the first timing control module 10A, and the output terminal of the second AND gate 123 is connected to the enable input terminal of the third power chip DC-DC3.

[0147] The first input terminal of the second AND gate 124 is connected to the PG terminal of the third power chip DC-DC3, the second input segment of the second AND gate 124 is connected to the first output terminal FLAG4 of the second timing control module 10B, and the output terminal of the second AND gate 124 is connected to the enable input terminal of the third power chip DC-DC4.

[0148] The first input terminal of the second AND gate 125 is connected to the PG terminal of the third power chip DC-DC4, the second input segment of the second AND gate 125 is connected to the first output terminal FLAG5 of the second timing control module 10B, and the output terminal of the second AND gate 125 is connected to the enable input terminal of the third power chip DC-DC5.

[0149] The first input terminal of the second AND gate 126 is connected to the PG terminal of the third power supply chip DC-DC5, the second input segment of the second AND gate 126 is connected to the first output terminal FLAG6 of the second timing control module 10B, and the output terminal of the second AND gate 126 is connected to the enable input terminal of the third power supply chip DC-DC6.

[0150] In this example, each power chip corresponds to the first output terminal of the timing control module. There is a sequence among the output terminals of the timing control module. The sequence of the output terminals of the timing control module depends on the timing of the multiple power enable signals output by the timing control module. Therefore, the order of the power chips also depends on the timing of the power enable signals.

[0151] During the power-on phase, the trigger signal PWOK changes from a low level to a high level, and the output of the first OR gate 91 outputs a high-level enable signal EN1. The first timing control chip 12A in the first timing control module 10A sequentially outputs the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3. The first AND gate 92 receives the third power enable signal FLAGEN3 and the trigger signal PWOK. Since both the third power enable signal FLAGEN3 and the trigger signal PWOK are at a high level, the first AND gate 92 outputs the enable signal EN2. The second timing control chip 12B in the second timing control module 10B sequentially outputs the fourth power enable signal FLAGEN4, the fifth power enable signal FLAGEN5, and the sixth power enable signal FLAGEN6.

[0152] Based on the timing of the multiple power enable signals output, the first output terminal FLAG1 is taken as the first output terminal of the first timing control module 10A. Correspondingly, the first power chip DC-DC1 corresponding to the first output terminal FLAG1 is taken as the first power chip, and the second power chip DC-DC2, the third power chip DC-DC3, the fourth power chip DC-DC4, the fifth power chip DC-DC5, and the sixth power chip DC-DC6 are taken as each power chip except the first power chip.

[0153] The signal output from the PG terminal is used to indicate whether the power chip is outputting a power signal normally. During the power-on phase, the power chip receives a power enable signal. When the power enable signal changes from a low level to a high level, the power chip responds to the high-level power enable signal and outputs a power signal. The PG terminal of the power chip outputs a high-level PG signal.

[0154] During the power-down phase, the power chip receives a power enable signal. When the power enable signal changes from a high level to a low level, the power chip responds to the low-level power enable signal and stops outputting the power signal. The PG terminal of the power chip stops the PG signal.

[0155] To facilitate understanding the solution, the following will be combined with... Figure 13 and Figure 14 The operation of the power-on and power-off phases of the power supply timing control circuit is explained. Figure 13 This is a signal state diagram for the power-on phase provided in Embodiment 4 of this application. Figure 14 This is a signal state diagram for the power-down phase provided in Embodiment 4 of this application.

[0156] Combination Figure 12 and Figure 13During the power-on phase, the trigger signal PWOK changes from a low level to a high level. The first OR gate 91 receives the trigger signal PWOK, and the first timing control chip U1 in the first timing control module 10A sequentially outputs the first power enable signal FLAGEN1, the second power enable signal FLAGEN2, and the third power enable signal FLAGEN3 in a high level state. The first AND gate 92 receives the trigger signal PWOK and the third power enable signal FLAGEN3, and the output of the first AND gate 92 outputs the enable signal EN2 in a high level state. The second timing control chip U2 in the second timing control module 10B sequentially outputs the fourth power enable signal FLAGEN4, the fifth power enable signal FLAGEN5, and the sixth power enable signal FLAGEN6 in a high level state.

[0157] During the power-on phase, the enable input terminal of the first power chip DC-DC1 receives the first power enable signal FLAGEN1. The first power enable signal FLAGEN1 changes from a low level to a high level. In response to the high-level first power enable signal FLAGEN1, the first power chip DC-DC1 outputs the first power signal V1. The PG terminal of the first power chip DC-DC1 outputs the high-level PG1 signal.

[0158] The first input terminal of the second AND gate 122 receives the PG1 signal, and the second input terminal of the second AND gate 122 receives the second power enable signal FLAGEN2. When both the PG1 signal and the second power enable signal FLAGEN2 are in a high-level state, the output terminal of the second AND gate 122 outputs a high-level signal, the second power chip DC-DC2 outputs the second power signal V2, and the PG terminal of the second power chip DC-DC2 outputs a high-level PG2 signal.

[0159] The first input of the second AND gate 123 receives the PG2 signal, and the second input of the second AND gate 123 receives the third power enable signal FLAGEN3. When both the PG2 signal and the third power enable signal FLAGEN3 are in a high-level state, the output of the second AND gate 123 outputs a high-level signal, and the third power chip DC-DC3 outputs the third power signal V3. The PG terminal of the third power chip DC-DC3 outputs the high-level PG3 signal.

[0160] The first input of the second AND gate 124 receives the PG3 signal, and the second input of the second AND gate 124 receives the fourth power enable signal FLAGEN4. When both the PG3 signal and the fourth power enable signal FLAGEN4 are in a high-level state, the output of the second AND gate 124 outputs a high-level signal, the fourth power chip DC-DC4 outputs the fourth power signal V4, and the PG terminal of the fourth power chip DC-DC4 outputs a high-level PG4 signal.

[0161] The first input of the second AND gate 125 receives the PG4 signal, and the second input of the second AND gate 125 receives the fifth power enable signal FLAGEN5. When both the PG4 signal and the fifth power enable signal FLAGEN5 are in a high-level state, the output of the second AND gate 125 outputs a high-level signal, and the fifth power chip DC-DC5 outputs the fifth power signal V5. The PG terminal of the fifth power chip DC-DC5 outputs a high-level PG5 signal.

[0162] The first input of the second AND gate 126 receives the PG5 signal, and the second input of the second AND gate 126 receives the sixth power enable signal FLAGEN6. When both the PG5 signal and the sixth power enable signal FLAGEN6 are in a high-level state, the output of the second AND gate 126 outputs a high-level signal, and the sixth power chip DC-DC6 outputs the sixth power signal V6.

[0163] Combination Figure 12 and Figure 14 During the power-down phase, the trigger signal PWOK changes from a high level to a low level. The output of the first AND gate 92 outputs a low-level enable signal EN2. The second timing control chip U2 in the second timing control module 10B sequentially outputs a low-level sixth power enable signal FLAGEN6, a fifth power enable signal FLAGEN5, and a fourth power enable signal FLAGEN4. The first OR gate 91 receives the fourth power enable signal FLAGEN4 and the trigger signal PWOK. The output of the first OR gate 91 outputs a low-level enable signal EN1. The first timing control chip U1 in the first timing control module 10A sequentially outputs a low-level third power enable signal FLAGEN3, a second power enable signal FLAGEN2, and a first power enable signal FLAGEN1.

[0164] During the power-down phase, each second AND gate outputs a low-level signal in response to the received power enable signal, and the corresponding power chip outputs a low-level power signal; the first power chip outputs a low-level power signal in response to the corresponding power enable signal.

[0165] In this embodiment, for each timing control module, the adjustment element corresponds to the delay interval between adjacent signals among the multiple power enable signals output by the timing control module. The timing control module outputs multiple power enable signals in response to an enable signal in an active state. For the first power chip, the power enable signal is received, and a power signal corresponding to the power enable signal is generated. For other power chips, the PG signal output by the previous power chip and the power enable signal corresponding to the power chip are combined to generate a power signal corresponding to the power enable signal. This achieves the output of multiple power signals with different timings in a non-programming manner, eliminating the need for firmware burning and saving the cost of power timing control.

[0166] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0167] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A power supply timing control circuit, characterized in that, include: At least one timing control module and a power supply module; Each timing control module includes a timing control chip and an adjustment element. The timing control chip has a delay setting terminal, and the adjustment element is connected to the delay setting terminal of the timing control chip. Each timing control module includes multiple first output terminals, and the power module includes multiple first input terminals. The first output terminal of the at least one timing control module is connected to the first input terminal of the power module in a one-to-one correspondence. Each timing control module's timing control chip receives an enable signal corresponding to that timing control module. When the enable signal is active, it generates multiple power enable signals and outputs them through corresponding first output terminals. Adjacent power enable signals generated and output by the timing control chip have a delay interval corresponding to an adjustment element of the timing control module. The adjustment element is a capacitor. The delay interval is determined as follows: obtaining the voltage range of the delay setting terminal of the timing control chip; determining the quotient of the voltage range and the source current of the delay setting terminal to obtain a first quotient value; and determining the quotient of the voltage range and the sink current of the delay setting terminal to obtain a second quotient value. The product of the sum of the first quotient and the second quotient and the capacitance value of the capacitor is determined to obtain the delay interval; The power module receives the power enable signal and the power supply signal output by the at least one timing control module, and generates and outputs the power signal corresponding to the power enable signal in response to the power enable signal that is in an active state.

2. The power supply timing control circuit according to claim 1, characterized in that, The regulating element includes a first capacitor; One end of the first capacitor is connected to the delay setting terminal of the timing control chip, and the other end of the first capacitor is grounded.

3. The power supply timing control circuit according to claim 1, characterized in that, The power module includes multiple power chips, and each of the multiple power chips corresponds to a first input terminal of the power module. Each power chip receives the power supply signal at its power input terminal, and the power chip's enable input terminal is connected to the corresponding first input terminal. The power chip is used to generate a power signal corresponding to the power supply enable signal based on the power supply signal when the received power enable signal is valid.

4. The power supply timing control circuit according to claim 1, characterized in that, The operation of the power supply timing control circuit is divided into a power-on phase and a power-off phase.

5. The power supply timing control circuit according to claim 4, characterized in that, The timing control module has one unit, and the first output terminal of the timing control module has three units.

6. The power supply timing control circuit according to claim 4, characterized in that, The number of timing control modules is multiple, and the multiple timing control modules are arranged in sequence; the power supply timing control circuit also includes: an indicator module corresponding to each timing control module; The indicator module receives a trigger signal, and its output is connected to a corresponding timing control module. The indicator module generates an enable signal corresponding to the timing control module based on the trigger signal. During the power-on phase, the order in which the indicator modules corresponding to each timing control module output the enable signals in a valid state is consistent with the arrangement order of the multiple timing control modules. During the power-off phase, the order in which the indicator modules corresponding to each timing control module output the enable signals in a valid state is reversed compared to the arrangement order of the multiple timing control modules.

7. The power supply timing control circuit according to claim 6, characterized in that, The number of timing control modules is two; The first input terminal of the indicator module corresponding to the first timing control module receives the trigger signal, and the second input terminal of the indicator module is connected to the first output terminal of the first timing control module. The first input terminal of the indicator module corresponding to the other timing control module receives the trigger signal, and the second input terminal of the indicator module corresponding to the other timing control module is connected to the first output terminal at the end of the first timing control module.

8. The power supply timing control circuit according to claim 7, characterized in that, The indication module corresponding to the first timing control module includes a first OR gate, and the indication module corresponding to the other timing control module includes a first AND gate. The first input terminal of the first OR gate receives the trigger signal, the second input terminal of the first OR gate is connected to the first output terminal of another timing control module, and the output terminal of the first OR gate is connected to the first timing control module. The first input terminal of the first AND gate receives the trigger signal, the second input terminal of the first AND gate is connected to the first output terminal at the end of the first timing control module, and the output terminal of the first AND gate is connected to the other timing control module.

9. The power supply timing control circuit according to any one of claims 3-8, characterized in that, The power timing control circuit also includes a second AND gate for each power chip except the first power chip; The first input terminal of the second AND gate is connected to the PG terminal of the previous power chip, the second input terminal of the second AND gate is connected to the first output terminal of the corresponding power chip, and the output terminal of the second AND gate is connected to the enable input terminal of the corresponding power chip.

10. The power supply timing control circuit according to any one of claims 4-8, characterized in that, During the power-on phase, the effective state is a high-level state; during the power-off phase, the effective state is a low-level state.

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