Pixel driving circuit

Abstract

A pixel driving circuit includes a light emitting unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a capacitor, and a control circuit. The light emitting unit is coupled to a first operating voltage source. The first switch unit has a first terminal, a second terminal, and a control terminal, the first terminal of the first switch unit is coupled to the light emitting unit, and the second terminal of the first switch unit is coupled to a second operating voltage source. The second switch unit has a first terminal and a second terminal, the first terminal of the second switch unit is coupled to the second operating voltage source. The third switch unit has a first terminal, and the first terminal of the third switch unit is coupled to the second terminal of the second switch unit. The fourth switch unit is coupled to the control terminal of the first switch unit. The capacitor is coupled between the control terminal of the first switch unit and the second terminal of the second switch unit. The control circuit is used to set the potential of the control terminal of the first switch unit.

Description

[0001] This application is a divisional application of the application with the title of “Pixel driving circuit”, the application number of 202011084746.7, and the application date of October 12, 2020, which is filed by the applicant of Hon Hai Precision Industry Co., Ltd. TECHNICAL FIELD

[0002] The present disclosure relates to a pixel driving circuit, in particular, to a pixel driving circuit of a light emitting diode. BACKGROUND

[0003] Light emitting diodes have been widely used in current displays. The brightness of a light emitting diode is related to the driving current. When a high brightness is output, the operating region of a transistor needs to be controlled by increasing the voltage difference to effectively control the current, which results in a large power consumption. In addition, due to the variation of each transistor in the process and use, the threshold voltage may be different. Because of the resistance generated in the circuit transmission process, the operating voltage source received by each transistor is different. If the threshold voltage and the operating voltage source are not compensated, the brightness of the light emitting diodes in the display may be uneven. SUMMARY

[0004] To solve the above problems, an embodiment of the present disclosure relates to a pixel driving circuit, which includes a light emitting unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a capacitor, and a control circuit. The light emitting unit is coupled to a first operating voltage source. The first switch unit has a first end, a second end, and a control end. The first end of the first switch unit is coupled to the light emitting unit, and the second end of the first switch unit is coupled to a second operating voltage source. The second switch unit has a first end and a second end. The first end of the second switch unit is coupled to the second operating voltage source. The third switch unit has a first end. The first end of the third switch unit is coupled to the second end of the second switch unit. The fourth switch unit is coupled to the control end of the first switch unit. The capacitor is coupled between the control end of the first switch unit and the second end of the second switch unit. The control circuit is used to set the potential of the control end of the first switch unit.

[0005] Another embodiment of the present disclosure is to provide a pixel driving circuit, which includes a light emitting unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, and a sixth switch unit. The first switch unit has a first terminal, a second terminal, and a control terminal, the first terminal of the first switch unit is coupled to the light emitting unit, and the second terminal of the first switch unit is coupled to a second operating voltage source. The second switch unit has a first terminal and a second terminal, the first terminal of the second switch unit is coupled to the control terminal of the first switch unit, and the second terminal of the second switch unit is coupled to a data voltage. The third switch unit has a first terminal and a second terminal, the first terminal of the third switch unit is coupled to the second operating voltage source. The fourth switch unit is coupled to the second terminal of the third switch unit. The fifth switch unit has a first terminal, a second terminal, and a control terminal, the first terminal of the fifth switch unit is coupled to the second terminal of the third switch unit. The sixth switch unit has a first terminal and a second terminal, the first terminal of the sixth switch unit is coupled to the second terminal and the control terminal of the fifth switch unit, and the second terminal of the sixth switch unit is coupled to a reference voltage.

[0006] Another embodiment of the present disclosure is to provide a pixel driving circuit, which includes a light emitting unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a capacitor, a fifth switch unit, and a sixth switch unit. The light emitting unit is coupled to a first operating voltage source. The first switch unit has a first terminal, a second terminal, and a control terminal, the first terminal of the first switch unit is coupled to the light emitting unit, and the second terminal of the first switch unit is coupled to a second operating voltage source. The second switch unit has a first terminal and a second terminal, the first terminal of the second switch unit is coupled to the second terminal of the first switch unit, and the second terminal of the second switch unit is coupled to the control terminal of the first switch unit. The third switch unit has a first terminal and a second terminal, the first terminal of the third switch unit is coupled to the control terminal of the first switch unit and the second terminal of the second switch unit. The fourth switch unit has a first terminal and a second terminal, the first terminal of the fourth switch unit is coupled to the second terminal of the third switch unit, and the second terminal of the fourth switch unit is coupled to a data voltage. The capacitor has a first terminal and a second terminal, the first terminal of the capacitor is coupled to the second terminal of the third switch unit and the first terminal of the fourth switch unit. The fifth switch unit has a first terminal and a second terminal, the first terminal of the fifth switch unit is coupled to the second terminal of the capacitor, and the second terminal of the fifth switch unit is coupled to the second operating voltage source. The sixth switch unit has a first terminal, a second terminal, and a control terminal, the first terminal of the sixth switch unit is coupled to the second terminal of the capacitor, and the control terminal and the second terminal of the sixth switch unit are coupled to a reference voltage.

[0007] Another embodiment of the present disclosure provides a pixel driving circuit, which includes a light emitting unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a capacitor, and a control circuit. The light emitting unit is coupled to a first operating voltage source. The first switch unit has a first end, a second end, and a control end, the first end of the first switch unit is coupled to the light emitting unit, and the second end of the first switch unit is coupled to a second operating voltage source. The second switch unit has a first end and a second end, and the first end of the second switch unit is coupled to the second operating voltage source. The third switch unit is coupled between a data voltage and the control end of the first switch unit. The fourth switch unit is coupled to the second end of the second switch unit. The capacitor is coupled between the control end of the first switch unit and the second end of the second switch unit. The control circuit is coupled to the second end of the second switch unit to control a potential of the second end of the second switch unit. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the drawings of the specification are described as follows:

[0009] Figure 1 The circuit architecture diagram of the pixel driving circuit of an embodiment of the present disclosure.

[0010] Figure 2 The control signal timing diagram of the pixel driving circuit in Figure 1

[0011] Figure 3A The circuit state diagram of the pixel driving circuit in Figure 1 Figure 2

[0012] Figure 3B The circuit state diagram of the pixel driving circuit in Figure 1 Figure 2

[0013] Figure 3C The circuit state diagram of the pixel driving circuit in Figure 1 Figure 2

[0014] Figure 3D The circuit state diagram of the pixel driving circuit in Figure 1 Figure 2

[0015] Figure 4 The circuit architecture diagram of the pixel driving circuit of another embodiment of the present disclosure.

[0016] Figure 5 The control signal timing diagram of the pixel driving circuit in Figure 4 ​​​​​​​​​Control signal timing diagram of the pixel driving circuit in FIG. 1.

[0017] Figure 6A For Figure 4 Circuit state diagram of the pixel driving circuit in FIG. 1 during the first period. Figure 5

[0018] Figure 6B For Figure 4 Circuit state diagram of the pixel driving circuit in FIG. 1 during the second period. Figure 5

[0019] Figure 6C For Figure 4 Circuit state diagram of the pixel driving circuit in FIG. 1 during the third period. Figure 5

[0020] Figure 6D For Figure 4 Circuit state diagram of the pixel driving circuit in FIG. 1 during the fourth period. Figure 5

[0021] Figure 7 Circuit architecture diagram of the pixel driving circuit according to another embodiment of the present disclosure.

[0022] Figure 8 For Figure 7 Control signal timing diagram of the pixel driving circuit in FIG. 1.

[0023] Figure 9A For Figure 7 Circuit state diagram of the pixel driving circuit in FIG. 1 during the first period. Figure 8

[0024] Figure 9B For Figure 7 Circuit state diagram of the pixel driving circuit in FIG. 1 during the second period. Figure 8

[0025] Figure 9C For Figure 7 Circuit state diagram of the pixel driving circuit in FIG. 1 during the third period. Figure 8

[0026] Figure 9D For Figure 7 Circuit state diagram of the pixel driving circuit in FIG. 1 during the fourth period. Figure 8

[0027] Figure 10 Circuit architecture diagram of the pixel driving circuit according to another embodiment of the present disclosure.

[0028] Figure 11 For Figure 10 Control signal timing diagram of the pixel driving circuit in FIG. 1.​​​​​​​​

[0029] Figure 12A For Figure 10 the pixel driving circuit in Figure 11 the first period shown in the circuit state diagram.

[0030] Figure 12B For Figure 10 the pixel driving circuit in Figure 11 the second period shown in the circuit state diagram.

[0031] Figure 12C For Figure 10 the pixel driving circuit in Figure 11 the third period shown in the circuit state diagram.

[0032] Figure 13 For the pixel driving circuit in

[0033] the fourth period shown in the circuit state diagram. Figure 14 Figure 13 For

[0034] the pixel driving circuit in Figure 15A the first period shown in the circuit state diagram. Figure 13 Figure 14 For

[0035] the pixel driving circuit in Figure 15B the second period shown in the circuit state diagram. Figure 13 Figure 14 For

[0036] the pixel driving circuit in Figure 15C the third period shown in the circuit state diagram. Figure 13 Figure 14 For

[0037] the pixel driving circuit in Figure 15D the fourth period shown in the circuit state diagram. Figure 13 Figure 14 For

[0038] the pixel driving circuit in Figure 16 the circuit architecture diagram of the pixel driving circuit of another embodiment of the disclosure.

[0039] Figure 17 For Figure 16 the control signal timing diagram of the pixel driving circuit in

[0040] Figure 18A For Figure 16 the pixel driving circuit in Figure 17 the first period shown in the circuit state diagram.

[0041] Figure 18B For Figure 16 the pixel driving circuit in Figure 17 the second period shown in the circuit state diagram.

[0042] Figure 18C For Figure 16 the pixel driving circuit in Figure 17 the third period shown in the circuit state diagram.

[0043] Figure 18D For Figure 16 the pixel driving circuit in Figure 17 the fourth period shown in the circuit state diagram.

[0044] Figure 19 For Figure 1 the voltage simulation diagram of node A.

[0045] Figure 20A For Figure 1 the current error rate simulation diagram.

[0046] Figure 20B For Figure 1 another current error rate simulation diagram.

[0047] Figure 20C For Figure 1 another current error rate simulation diagram.

[0048] Explanation of reference signs:

[0049] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the following is a description of the symbols:

[0050] 100, 400, 700, 1000, 1300, 1600: pixel driving circuit

[0051] A ~ D: node

[0052] T1 ~ T7: switch unit

[0053] S1 ~ S3: control signal

[0054] EM: light emission signal

[0055] VDD: first operating voltage source

[0056] VSS: second operating voltage source

[0057] Vref1, Vref2: reference voltage

[0058] Vdata: data voltage

[0059] VH: voltage level

[0060] L1: light emitting unit

[0061] C1: capacitor

[0062] ΔVth: threshold voltage variation

[0063] ΔVSS: second operating voltage source variation

[0064] VA1-VA3: voltage DETAILED DESCRIPTION

[0065] All words used herein are intended to be given their ordinary meaning. Definitions of the above words are found in commonly available dictionaries, and the use of any of these words in the present specification is intended to be illustrative only and should not be limiting to the scope and meaning of the present disclosure. Similarly, the present disclosure is not limited to the various embodiments shown in this specification.

[0066] In this document, the words "first", "second", "third", etc. are used merely to describe various elements, components, regions, layers and / or regions. These elements, components, regions, layers and / or regions should not be limited by these terms. These words are merely used to distinguish one element, component, region, layer and / or region from another element, component, region, layer and / or region. Thus, a first element, component, region, layer and / or region below can also be referred to as a second element, component, region, layer and / or region without departing from the spirit of the present disclosure. As used herein, "and / or" includes any one of the associated listed items, as well as all combinations of the items.

[0067] As used herein, "coupled" or "connected" can mean that two or more elements are in direct physical or electrical contact with each other, or that two or more elements are not in direct contact with each other, but can still cooperate or interact with each other.

[0068] Figure 1 A circuit architecture diagram of a pixel driving circuit 100 according to an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the pixel driving circuit 100 includes switching units T1-T4, a control circuit 110, a capacitor C1, and a light emitting unit L1. Figure 1

[0069] In the pixel driving circuit 100, the switching units T1-T4 are controlled by the control circuit 110 to perform the following operations. Figure 1 ​In the illustrated embodiment, each of the switch units T1-T4 includes an N-type MOSFET (N-type Metal Oxide Semiconductor Field Effect Transistor, hereinafter referred to as NMOS) switch element. In the following embodiments, the NMOS switch element will be taken as an example for illustration. However, the switch units T1-T4 are not limited to including an NMOS switch element in the present disclosure. In other embodiments, each of the switch units T1-T4 can include multiple NMOS switches connected to each other, a bipolar junction transistor (BJT), one or more equivalent switching circuits, and the present disclosure is not limited thereto.

[0070] In some embodiments, the switch unit T1 and the light-emitting unit L1 are coupled between a first operating voltage source VDD and a second operating voltage source VSS. The first end of the light-emitting unit L1 is coupled to the first operating voltage source VDD, the second end of the light-emitting unit L1 is coupled to the first end of the switch unit T1, and the second end of the switch unit T1 is coupled to the second operating voltage source VSS. The switch unit T2 and the switch unit T3 are coupled between a reference voltage Vref2 and the second operating voltage source VSS, and the reference voltage Vref2 is used for resetting the circuit. The first end of the switch unit T2 is coupled to the second operating voltage source VSS, the second end of the switch unit T2 is coupled to the first end of the switch unit T3, the second end of the switch unit T3 is connected to the reference voltage Vref2, and the control end of the switch unit T3 is coupled to a control signal S2. The first end of the switch unit T4 is coupled to the reference voltage Vref1, the second end of the switch unit T4 is coupled to the control end (node A) of the switch unit T1, and the control end of the switch unit T4 is connected to a control signal S1. One end of the capacitor C1 is coupled to the control end (node A) of the switch unit T1, and the other end is coupled between the switch unit T2 and the switch unit T3 (node B). The control circuit 110 is coupled to the control end of the switch unit T1 to set the potential of the node A.

[0071] In some embodiments, the control circuit 110 includes switch units T5-T7. In some embodiments, each of the switch units T5-T7 includes an NMOS switch element. In the following embodiments, the NMOS switch element will be taken as an example for illustration. However, the switch units T5-T7 are not limited to including an NMOS switch element in the present disclosure. In other embodiments, each of the switch units T5-T7 can include multiple NMOS switches connected to each other, a BJT, one or more equivalent switching circuits, and the present disclosure is not limited thereto.

[0072] In some embodiments, the first terminal of switch unit T5 is coupled to the control terminal (node ​​A) of switch unit T1 and the first terminal of switch unit T6. The control terminal of switch unit T5 is connected to control signal S2. The second terminal of switch unit T5 is connected to the control terminal (node ​​C) of switch unit T6. The first terminal of switch unit T7 is coupled to data voltage Vdata. The second terminal of switch unit T7 is coupled to the second terminal (node ​​D) of switch unit T6. The control terminal of switch unit T7 is connected to control signal S3.

[0073] It should be noted that in other embodiments, those skilled in the art can replace the switching units T1 to T7 with P-type MOSFET (PMOS) switches, C-type MOSFET (CMOS) switches, or other similar switching elements, and adjust the logic levels of the system voltage (e.g., the first operating voltage source VDD and the second operating voltage source VSS), the light emission signal (e.g., the light emission signal EM), and the control signal (e.g., the control signals S1 to S3) accordingly to achieve the same function as in this embodiment.

[0074] Figure 2 for Figure 1 Timing diagram of control signals for the pixel driving circuit. Figure 2 In this process, the pixel driving circuit operates sequentially during the first period P1, the second period P2, the third period P3, and the fourth period P4.

[0075] Figure 3A for Figure 1 The middle pixel driving circuit 100 is in Figure 2 The circuit state diagram shown is for the first period P1, and the first period P1 belongs to the reset phase. Figure 2 As shown, during the first period P1, control signals S1 and S2 are high-level signals, while control signal S3 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 3AAs shown, switch unit T1, switch unit T2 and switch unit T7 are in the off state, and switch units T3-T6 are in the on state. In this case, there are three current paths in the pixel driving circuit 100, one of which is from the reference voltage Vrefl through node A and switch unit T6 to node D, one of which is from the reference voltage Vrefl through node A to switch unit T5 and node C and then through switch unit T6 to node D, and the other of which is from the reference voltage Vref2 through switch unit T3 to node B. Therefore, the potentials of nodes A and C are pulled to be equal to the reference voltage Vrefl, the potential of node B is pulled to be equal to the reference voltage Vref2, and the potential of node D is lower than that of node C by a threshold voltage Vth, which is the threshold voltage of switch unit T6 (hereinafter denoted as Vth_T6, which is not shown in the figure).

[0076] Figure 3B For Figure 1 the pixel driving circuit 100 in the second period P2 shown in the circuit state diagram, and the second period P2 belongs to the compensation stage. As shown, Figure 2 in the second period P2, the control signal S2 and the control signal S3 are high-level signals, and the control signal S1 and the emission signal EM are low-level signals. Correspondingly, as shown, Figure 2 switch unit T1, switch unit T2 and switch unit T4 are in the off state, and switch units T3, T5, T6 and T7 are in the on state. In this case, the current path of switch unit T3 and the potential of the corresponding node B remain the same as in the first period P1. Switch unit T4 is off and switch unit T5 is on, so that the current path is from node A, directly through switch unit T6 and through switch unit T6 via switch unit T5 and node C, and then converges at node D and flows to the data voltage Vdata via switch unit T7. At this time, the potential of node D is the same as the data voltage Vdata, and the potentials of nodes C and A are higher than that of node D by a threshold voltage, which is the threshold voltage of switch unit T6 (Vth_T6). Figure 3B Figure 3A For

[0077] the pixel driving circuit 100 in the third period P3 shown in the circuit state diagram, and the third period P3 belongs to the emission stage. As shown, Figure 3C in the third period P3, the control signals S1-S3 are low-level signals, and the emission signal EM is a high-level signal. Correspondingly, as shown, Figure 1 switch unit T1, switch unit T2 and switch unit T4 are in the off state, and switch units T3, T5, T6 and T7 are in the on state. In this case, the current path of switch unit T3 and the potential of the corresponding node B remain the same as in the first period P1. Switch unit T4 is off and switch unit T5 is on, so that the current path is from node A, directly through switch unit T6 and through switch unit T6 via switch unit T5 and node C, and then converges at node D and flows to the data voltage Vdata via switch unit T7. At this time, the potential of node D is the same as the data voltage Vdata, and the potentials of nodes C and A are higher than that of node D by a threshold voltage, which is the threshold voltage of switch unit T6 (Vth_T6). Figure 2 Figure 2 Figure 3C ​​As shown, switch unit T1 and switch unit T2 are in the on state, and switch units T3-T7 are in the off state. In this case, the current path is collectively formed by the first operating voltage source VDD via the light emitting unit L1 and the switch unit T1, respectively flows to the second operating voltage source VSS and the node B (via the switch unit T2), and causes the light emitting unit L1 to emit light. In this stage, the potential of the node B is changed from the reference voltage Vref2 in the previous stage to the same as the second operating voltage source VSS, and because the node A is floating, when the voltage level of the second end of the capacitor C1 changes, the level change amount will be coupled to the node A. As known from the foregoing, the level change amount of the node B is VSS-Vref2, and the coupling of the node B to the node A via the capacitor C1 causes the potential of the node A to change from Vdata+Vth_T6 in the previous stage to (Vdata+Vth_T6)+(VSS-Vref2), so that the voltage across the control end and the second end of the switch unit T1 is raised, the voltage across the first end and the second end of the switch unit T1 is reduced, and the power consumption is reduced.

[0078] In addition, because the current flowing through the light emitting unit L1 is equal to the current flowing through the switch unit T1, if

[0079] Let the threshold voltage of the switch unit T1 be represented by Vth_T1, and the current flowing through the switch unit T1 be represented by I, then according to the current flowing through the switch unit T1 formula is:

[0080] #

[0081]

[0082] Assuming that the threshold voltage Vth_T6 of the switch unit T6 and the threshold voltage Vth_T1 of the switch unit T1 are equal, and offsetting the two can be obtained:

[0083]

[0084] Because the threshold voltage of the transistor itself is in an unstable state, and the impedance on the entire current path causes the voltage value of the second operating voltage source VSS received by different pixels on the panel to be different, the current control of the light emitting diode will be affected. Based on the above embodiment, and under the assumption that the threshold voltage of the switch unit T1 and the threshold voltage of the switch unit T6 are the same, the second operating voltage source VSS and the threshold voltage Vth can be successfully compensated, so that the current calculation of the light emitting unit L1 is independent of the second operating voltage source VSS and the threshold voltage Vth, i.e. is not affected by the change of the second operating voltage source VSS and the threshold voltage Vth.

[0085] In some embodiments, Figure 2 The control signal timing diagram in the above embodiment further includes a fourth period P4. Figure 3D For Figure 1 The middle pixel driving circuit 100 is in Figure 2 The circuit state diagram shown is for the fourth period P4, which is the anti-dizziness stage. Figure 2 As shown, during the fourth period P4, control signal S1 is a high-level signal, while control signals S2-S4 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 3D As shown, switch unit T4 is in the on state, while the other switch units T1-T3 and switch units T5-T7 are in the off state. Compared to the third period P3, in this case, only one current path flows from the reference voltage Vref1 through switch unit T4 to node A, making the potential of node A the same as the reference voltage Vref1, thereby turning off switch unit T1 and preventing the light-emitting unit L1 from continuing to emit light and causing glare.

[0086] Please refer to Figure 4 . Figure 4 This is a circuit architecture diagram of a pixel driving circuit 400 according to some embodiments of the present disclosure. Figure 4 and Figure 1 The difference is that, Figure 4 The control circuit 410 and Figure 1 The components and their coupling relationships in the control circuit 110 are different. Except for the control circuit 410 and its coupled voltage and signal, the rest of the pixel driving circuit 400 is the same as the pixel driving circuit 100, and will not be described again here.

[0087] In some embodiments, the control circuit 410 includes switching units T5 to T6. In some embodiments, each of the switching units T5 to T6 includes an NMOS switching element. The following embodiments will be described using this as an example. However, the switching units T5 to T6 are not limited to including only one NMOS switching element in this disclosure. In other embodiments, each switching unit T5 to T6 may include multiple interconnected NMOS switches, include a BJT, or include one or more equivalent switching circuits. This disclosure is not limited thereto.

[0088] In some embodiments, the first terminal of the switching unit T5 is coupled to the control terminal (node ​​A) of the switching unit T1, the control terminal of the switching unit T5 is coupled to the control signal S2, the second terminal of the switching unit T5 is coupled to the control terminal and the first terminal of the switching unit T6, and the second terminal of the switching unit T6 is coupled to the reference voltage Vref2, wherein the reference voltage Vref2 is a low-level voltage.

[0089] In some embodiments, the pixel driving circuit 400 further includes a switching unit T7 coupled between the second terminal of the switching unit T1 and the control terminal (node ​​A) of the switching unit T1, and the control terminal of the switching unit T7 is coupled to the control signal S3. It should be noted that the switching unit T7 in this disclosure can be composed of other components, and the present invention is not limited thereto.

[0090] It should be noted that in other embodiments, those skilled in the art can replace the switching units T1 to T7 with PMOS switches, CMOS switches or other similar switching elements, and adjust the logic levels of the system voltage (e.g., the first operating voltage source VDD and the second operating voltage source VSS), the light emission signal (e.g., the light emission signal EM), and the control signal (e.g., the control signals S1 to S3) accordingly to achieve the same function as in this embodiment.

[0091] Figure 5 for Figure 4 Timing diagram of control signals for pixel driving circuit 400. Figure 5 In this process, the pixel driving circuit 400 operates sequentially in the first period P1, the second period P2, the third period P3, and the fourth period P4.

[0092] Figure 6A for Figure 4 The mid-pixel drive circuit 400 is in Figure 5 The circuit state diagram shown is for the first period P1, and the first period P1 belongs to the reset phase. Figure 5 As shown, during the first period P1, control signals S1 and S2 are high-level signals, while control signal S3 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 6A As shown, switching units T1, T2, T6, and T7 are in the off state, while switching units T3 to T5 are in the on state. In this case, the pixel driving circuit 400 has two current paths. One path flows from the reference voltage Vref1 sequentially through switching unit T4, node A, and switching unit T5 to node C. The other path flows from the data voltage Vdata through switching unit T3 to node B. Therefore, the potentials of nodes A and C are pulled to be equal to the reference voltage Vref1, and the potential of node B is pulled to be equal to the data voltage Vdata.

[0093] Figure 6B for Figure 4 The mid-pixel drive circuit 400 is in Figure 5 The circuit state diagram for the second period P2 is shown, and the second period P2 belongs to the compensation stage. Figure 5 As shown, during the second period P2, control signal S2 is a high-level signal, while control signals S1, S3, and the light emission signal EM are low-level signals. Correspondingly, as... Figure 6B As shown, switch unit T1, switch unit T2, and switch unit T4 and switch unit T7 are in the off state, and switch unit T3, switch unit T5, and switch unit T6 are in the on state. In this case, one current path flows from node A to reference voltage Vref2 through switch unit T5 and switch unit T6, and another current path flows from data voltage Vdata to node B through switch unit T3. At this time, the potentials of node A and node C are equal, and both are higher than reference voltage Vref2 by a threshold voltage Vth, which is the threshold voltage of switch unit T6 (hereinafter denoted as Vth_T6, which is not shown in the figure). The potential of node B is equal to data voltage Vdata.

[0094] In some embodiments, reference voltage Vref2 is equal to reference voltage Vref1 or equal to data voltage Vdata.

[0095] Figure 6C For Figure 4 The middle pixel driving circuit is in Figure 5 The circuit state diagram in the third period P3 is shown, and the third period P3 belongs to the light-emitting stage. As shown, Figure 5 As shown, in the third period P3, control signals S1-S3 are low-level signals, and light-emitting signal EM is a high-level signal. Correspondingly, as shown, Figure 6C As shown, switch unit T1 and switch unit T2 are in the on state, and switch unit T3-T7 are in the off state. In this case, one current path flows from second operating voltage source VSS to node B through switch unit T2, so that the potential of node B is equal to the second operating voltage source. Another current path flows from first operating voltage source VDD to second operating voltage source VSS through light-emitting unit L1 and switch unit T1, so that light-emitting unit L1 emits light. In this stage, the potential of node B changes from data voltage Vdata in the previous stage to the same as second operating voltage source VSS, and because node A is floating, when the voltage level of the second end of capacitor C1 changes, the level change amount will be coupled to node A. As described above, the level change amount of node B is VSS-Vdata, which is coupled to node A through capacitor C1, so that the potential of node A changes from Vref2+Vth_T6 in the previous stage to (Vref2+Vth_T6)+(VSS-Vdata). Therefore, the voltage across the control end and the second end of switch unit T1 is raised, the voltage across the first end and the second end of switch unit T1 is reduced, and the power consumption is reduced.

[0096] Furthermore, since the current flowing through the light-emitting unit L1 is equal to the current flowing through the switching unit T1, if we represent the critical voltage of the switching unit T1 as Vth_T1 and the current flowing through the switching unit T1 as I, then according to the formula for the current flowing through the switching unit T1, we have:

[0097]

[0098] #

[0099]

[0100] Assuming that the critical voltage Vth_T6 of switching unit T6 is equal to the critical voltage Vth_T1 of switching unit T1, canceling them out yields the following:

[0101]

[0102] Because the threshold voltage of the transistor itself is unstable, and the impedance along the entire current path causes different pixels on the panel to receive different voltage values ​​from the second operating voltage source VSS, the current control of the light-emitting diode will be affected. Based on the above embodiment, and assuming that the threshold voltages of switching units T1 and T6 are the same, the second operating voltage source VSS and the threshold voltage Vth can be successfully compensated, so that the current calculation of the light-emitting unit L1 is independent of the second operating voltage source VSS and the threshold voltage Vth, that is, it is not affected by changes in the second operating voltage source VSS and the threshold voltage Vth.

[0103] In some embodiments, Figure 5 The control signal timing diagram also includes a fourth period, P4. Figure 6D for Figure 4 The mid-pixel drive circuit 400 is in Figure 5 The circuit state diagram shown is for the fourth period P4, which is the anti-glare stage. Figure 5 As shown, during the fourth period P4, control signal S3 is a high-level signal, while control signals S1, S2, and the light emission signal EM are low-level signals. Correspondingly, as... Figure 6D As shown, switch unit T7 is in the on state, while the other switch units T1 to T6 are all in the off state. Compared to the third period P3, in this case, only one current path flows from the second operating voltage source VSS through switch unit T7 to node A, making the potential of node A the same as that of the second operating voltage source VSS, thereby turning off switch unit T1 and preventing the light-emitting unit L1 from continuing to emit light and causing glare.

[0104] As described above, the switch unit T7 in the pixel driving circuit 400 is only in the on state in the fourth period P4, for setting the potential of the node A equal to the second operating voltage source VSS, to turn off the light emitting unit L1. Except for the rest of the fourth period P4, the switch unit T7 is in the off state, which can be omitted.

[0105] Please refer to Figure 7 . Figure 7 The circuit architecture diagram of the pixel driving circuit 700 of some embodiments of the present disclosure is shown. As shown in Figure 7 , the pixel driving circuit 700 includes switch units T1-T6, a capacitor C1, and a light emitting unit L1. In some embodiments, the switch units T1-T6 each include an NMOS switch element, and the following embodiments will be described by taking this as an example. However, the switch units T1-T6 in the present disclosure are not limited to including an NMOS switch element, and in other embodiments, each of the switch units T1-T6 can include multiple NMOS switches connected to each other, include a BJT, include one or more switching circuits having equivalent functions, and the present disclosure is not limited thereto.

[0106] In some embodiments, the switch unit T1 and the light emitting unit L1 are coupled between the first operating voltage source VDD and the second operating voltage source VSS. The first end of the light emitting unit L1 is coupled to the first operating voltage source VDD, the second end of the light emitting unit L1 is coupled to the first end of the switch unit T1, and the second end of the switch unit T1 is coupled to the second operating voltage source VSS. The switch unit T2 is coupled between the data voltage Vdata and the control end (node A) of the switch unit T1, and the control end of the switch unit T2 is coupled to the control signal S1. The first end of the switch unit T3 is coupled to the second operating voltage source VSS, and the control end of the switch unit T3 is coupled to the light emitting signal EM. The first end of the switch unit T4 is coupled to the second end (node B) of the switch unit T3, the second end of the switch unit T4 is coupled to the reference voltage Vref1, and the control end of the switch unit T4 is coupled to the control signal S2. The first end of the switch unit T5 is coupled to the first end (node B) of the switch unit T4, the control end and the second end of the switch unit T5 are coupled to the first end (node C) of the switch unit T6, the second end of the switch unit T6 is coupled to the reference voltage Vref2, and the control end of the switch unit T6 is coupled to the control signal S3. The capacitor C1 is coupled between the control end (node A) of the switch unit T1 and the second end (node B) of the switch unit T4.

[0107] In Figure 7In the illustrated embodiment, switching units T1 to T6 are exemplified using NMOS switches, but this disclosure is not intended to limit the scope. In another embodiment, those skilled in the art can replace switching units T1 to T6 with PMOS switches, CMOS switches, or other similar switching elements, and adjust the logic levels of the system voltage (e.g., the first operating voltage source VDD and the second operating voltage source VSS), the light emission signal (e.g., the light emission signal EM), and the control signals (e.g., control signals S1 to S3) accordingly to achieve the same functionality as in this embodiment.

[0108] Figure 8 for Figure 7 The timing diagram of the control signals for the pixel driving circuit 700 is shown. In some embodiments, the waveforms of control signal S2 and control signal S3 are identical after a delay of one period. For example, in... Figure 8 The control signal S2 during the first period P1 is the same as the control signal during the second period P2, and the control signal S2 during the second period P2 is the same as the control signal during the third period P3. Therefore, in some embodiments, by adding a buffer or other design, the control terminals of switching unit T4 and switching unit T6 can be coupled to the same control signal. Figure 8 In this process, the pixel driving circuit operates sequentially during the first period P1, the second period P2, the third period P3, and the fourth period P4.

[0109] Figure 9A for Figure 7 The 700-pixel drive circuit in the middle pixel is Figure 8 The circuit state diagram shown is for the first period P1, and the first period P1 belongs to the reset phase. Figure 8 As shown, during the first period P1, control signal S1 is a high-level signal, while control signals S2-S3 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 9A As shown, switching units T1, T3, and T6 are in the off state, while switching units T2, T4, and T5 are in the on state. In this configuration, the pixel driving circuit 700 has two current paths: one from the data voltage Vdata through switching unit T2 to the control terminal (node ​​A) of switching unit T1, and the other from the second terminal (node ​​C) of switching unit T5 through switching unit T5, node B, and switching unit T4 to the reference voltage Vref1. Therefore, the potential of node A is pulled to the same level as the data voltage Vdata, thereby turning off switching unit T1 to prevent current from flowing through the light-emitting unit L1 and causing flickering. The potential of node B is set to the reference voltage Vref1, while the potential of node C is higher than that of node B by a threshold voltage, which is the threshold voltage of switching unit T5 (hereinafter referred to as Vth_T5, this symbol is not shown in the attached figure).

[0110] Figure 9B for Figure 7 The 700-pixel drive circuit in the middle pixel is Figure 8 The circuit state diagram for the second period P2 is shown, and the second period P2 belongs to the compensation stage. Figure 8 As shown, during the second period P2, control signals S1 and S2 are high-level signals, while control signal S3 and the light-emitting signal are low-level signals. Correspondingly, as... Figure 9B As shown, switch units T1, T3, and T4 are in the off state, while switch units T2, T5, and T6 are in the on state. In this case, there are two current paths in the pixel driving circuit 700. One path flows from the data voltage Vdata through switch unit T2 to node A, and the other path flows from the reference voltage Vref2 sequentially through switch unit T6, node C, and switch unit T5 to node B. At this time, the potential of node A is the same as the data voltage Vdata in the previous period, the potential of node C is pulled to be the same as the reference voltage Vref2, and the potential of node B is lower than that of node C by the threshold voltage of switch unit T5 (the potential of node B can be expressed as Vref2 - Vth_T5).

[0111] Figure 9C for Figure 7 The 700-pixel drive circuit in the middle pixel is Figure 8 The circuit state diagram shown is for the third period P3, which is the light-emitting stage. Figure 8 As shown, during the third period P3, control signals S1 to S3 are low-level signals, and the light emission signal EM is a high-level signal. Correspondingly, as... Figure 9C As shown, switching units T1 and T3 are in the ON state, while switching units T2 and T4-T6 are in the OFF state. At this time, the potential of node C remains constant at the reference voltage Vref2, and the potential of node B is the same as the second operating voltage source VSS. Node A is floating. If there is a voltage change at the second terminal of capacitor C1, the change will be coupled to node A. As mentioned earlier, the voltage change at node B is VSS - (Vref2 - Vth_T5). Coupled to node A via capacitor C1, this will cause the potential of node A to change from Vdata in the previous stage to Vdata + VSS - (Vref2 - Vth_T5). Therefore, the voltage across the control terminal and the second terminal of switching unit T1 increases, reducing the voltage across the first and second terminals of switching unit T1, thereby reducing power consumption.

[0112] In addition, since the current flowing through the light emitting unit L1 is equal to the current flowing through the switching unit T1, if the threshold voltage of the switching unit T1 is denoted as Vth_T1 and the current flowing through the switching unit T1 is denoted as I, then according to the current flowing through the switching unit T1 formula is:

[0113]

[0114] Assuming that the threshold voltage Vth_T5 of the switching unit T5 is equal to the threshold voltage Vth_T1 of the switching unit T1, and the two are offset, it can be obtained that:

[0115]

[0116] Since the threshold voltage of the transistor itself is in an unstable state, and the impedance on the entire current path causes the voltage value of the second operating voltage source VSS received by different pixels on the panel to be different, the current control of the light emitting diode will be affected. Based on the above embodiment, and under the assumption that the threshold voltages of the switching unit T1 and the switching unit T5 are the same, the second operating voltage source VSS and the threshold voltage Vth can be successfully compensated, so that the current calculation of the light emitting unit L1 is independent of the second operating voltage source VSS and the threshold voltage Vth, that is, is not affected by the change of the second operating voltage source VSS and the threshold voltage Vth.

[0117] In some embodiments, Figure 8 The control signal timing diagram in the pixel driving circuit 1000 further includes a fourth period P4. Figure 9D For Figure 7 The pixel driving circuit 700 in Figure 8 The circuit state diagram in the fourth period P4 shown in FIG. 7C, and the fourth period P4 belongs to the anti-glare stage. As shown in Figure 8 In the fourth period P4, the control signal S1 is a high-level signal, and the control signals S2-S4 and the light emitting signal EM are low-level signals. Correspondingly, as shown in Figure 9D The switching unit T2 is in the on state, and the remaining switching units T1 and T3-T6 are in the off state. Compared with the third period P3, in this case, only one current path flows through the switching unit T2 to the node A from the data voltage Vdata, so that the potential of the node A is the same as the data voltage Vdata, and thereby the switching unit T1 is closed, avoiding the case that the light emitting unit L1 continues to emit light to cause glare.

[0118] Please refer to Figure 10 . Figure 10 The circuit architecture diagram of the pixel driving circuit 1000 of some embodiments of the present disclosure. As shown in Figure 10As shown, the pixel driving circuit 1000 includes switching units T1 to T6, capacitor C1, and light-emitting unit L1. In some embodiments, switching units T1 to T6 each include an NMOS switching element. The following embodiments will be described using this as an example. However, the switching units T1 to T6 are not limited to including only one NMOS switching element in this disclosure. In other embodiments, each switching unit T1 to T6 may include multiple interconnected NMOS switches, include a BJT, or include one or more equivalent switching circuits. This disclosure is not limited thereto. In some embodiments, switching unit T1 and light-emitting unit L1 are coupled between a first operating voltage source VDD and a second operating voltage source VSS. The first end of light-emitting unit L1 is coupled to the first operating voltage source VDD, the second end of light-emitting unit L1 is coupled to the first end of switching unit T1, and the second end of switching unit T1 is coupled to the second operating voltage source VSS. One end of switch unit T2 is coupled to the second end of switch unit T1 (also coupled to the second operating voltage source VSS), and the other end of switch unit T2 is coupled to the control terminal (node ​​A) of switch unit T1. The control terminal of switch unit T2 is coupled to the control signal S1. The first end of switch unit T3 is coupled to the control terminal (node ​​A) of switch unit T1, and the control terminal of switch unit T3 is coupled to the light emission signal EM. The second end of switch unit T3 is coupled to the first end (node ​​B) of switch unit T4. The second end of switch unit T4 is coupled to the data voltage Vdata, and the control terminal of switch unit T4 is coupled to the control signal S1. The first end of capacitor C1 is coupled to the second end (node ​​B) of switch unit T3, and the second end of capacitor C1 is coupled to the first ends of switch units T5 and T6 (node ​​C). The second end of switch unit T5 is coupled to the second operating voltage source VSS, and the control terminal of switch unit T5 is coupled to the control signal S2. The second end and control terminal of switch unit T6 are coupled to the control signal S3.

[0119] At Figure 10 In the illustrated embodiment, switching units T1 to T6 are exemplified using N-type metal-oxide-semiconductor field-effect transistor (NMOS) switches, but this disclosure is not limited thereto. In another embodiment, those skilled in the art can replace switching units T1 to T6 with P-type metal-oxide-semiconductor field-effect transistor (PMOS) switches, C-type metal-oxide-semiconductor field-effect transistor (CMOS) switches, or other similar switching elements, and adjust the logic levels of the system voltage (e.g., the first operating voltage source VDD and the second operating voltage source VSS), the light emission signal (e.g., the light emission signal EM), and the control signals (e.g., control signals S1 to S3) accordingly to achieve the same function as in this embodiment.

[0120] Figure 11 for Figure 10 Timing diagram of control signals for pixel drive circuit 1000. Figure 11 In the first period P1, the pixel driving circuit 1000 is operated in the reset phase. As shown in the circuit state diagram of the first period P1, the control signals S1-S2 are high level signals, and the control signal S3 and the emission signal EM are low level signals. Correspondingly, as shown in the circuit state diagram of the first period P1, the switch unit T1, the switch unit T3 and the switch unit T6 are in the off state, and the switch unit T2, the switch unit T4 and the switch unit T5 are in the on state. In this case, the potentials of the node A and the node C are pulled to the same as the second operating voltage source VSS, thereby closing the switch unit T1 to avoid current flowing through the light emitting unit L1 to generate flicker. The potential of the node B is the same as the data voltage Vdata.

[0121] Figure 12A In the second period P2, the pixel driving circuit 1000 is operated in the compensation phase. As shown in the circuit state diagram of the second period P2, the control signal S1 and the control signal S3 are high level signals, and the control signal S2 and the emission signal EM are low level signals. In this case, the high level of the control signal S3 is represented by the voltage level VH. Correspondingly, as shown in the circuit state diagram of the second period P2, the switch unit T1, the switch unit T3 and the switch unit T5 are in the off state, and the switch unit T2, the switch unit T4 and the switch unit T6 are in the on state. At this time, the potentials of the node A and the node B remain the same as in the previous period, and the potential of the node C is lower than the control signal S3 by a threshold voltage, which is the threshold voltage of the switch unit T6 (represented by Vth_T6, which is not marked in the figure). Therefore, the potential of the node C can be represented as VH-Vth_T6. Figure 10 Figure 11 Figure 11 Figure 12A

[0122] Figure 12B In the third period P3, the pixel driving circuit 1000 is operated in the emission phase. As shown in the circuit state diagram of the third period P3, the control signal S1 and the control signal S3 are low level signals, and the control signal S2 and the emission signal are high level signals. Correspondingly, as shown in the circuit state diagram of the third period P3, the switch unit T1, the switch unit T3 and the switch unit T5 are in the off state, and the switch unit T2, the switch unit T4 and the switch unit T6 are in the on state. At this time, the potentials of the node A and the node B remain the same as in the previous period, and the potential of the node C is lower than the control signal S3 by a threshold voltage, which is the threshold voltage of the switch unit T6 (represented by Vth_T6, which is not marked in the figure). Therefore, the potential of the node C can be represented as VH-Vth_T6. Figure 10 Figure 11 Figure 11 Figure 12B

[0123] Figure 12C Figure 10 Figure 11 Figure 11 Figure 12C ​​​​​​​​​​​​As shown, switching units T1, T3, and T5 are in the ON state, while switching units T2, T4, and T6 are in the OFF state. At this time, the potential of node C is pulled to the same level as the second operating voltage source VSS, and its change from the previous period is VSS - (VH - Vth_T6). Node B is floating; when there is a voltage level change at the second terminal of capacitor C1, the change will be coupled to node B. Since the potential of node B in the previous period was the data voltage Vdata, the potential after coupling through capacitor C1 is Vdata + VSS - (VH - Vth_T6), and the potential of node A is the same. Therefore, the voltage across the control terminal and the second terminal of switching unit T1 can be increased, reducing the voltage across the first terminal and the second terminal of switching unit T1, thereby reducing power consumption.

[0124] Furthermore, if we represent the critical voltage of switching unit T1 as Vth_T1 and the current flowing through switching unit T1 as I, then the formula for the current flowing through switching unit T1 is as follows:

[0125]

[0126] Assume the critical voltage Vth_T6 of switching unit T6 and the critical voltage Vth_T1 of switching unit T1.

[0127]

[0128] Since they are equal, canceling them out yields: #

[0129] Because the threshold voltage of the transistor itself is unstable, and the impedance along the entire current path causes different pixels on the panel to receive different voltage values ​​from the second operating voltage source VSS, the current control of the light-emitting diode will be affected. Based on the above embodiment, and assuming that the threshold voltages of switching units T1 and T6 are the same, the second operating voltage source VSS and the threshold voltage Vth can be successfully compensated, so that the current calculation of the light-emitting unit L1 is independent of the second operating voltage source VSS and the threshold voltage Vth, that is, it is not affected by changes in the second operating voltage source VSS and the threshold voltage Vth.

[0130] Please refer to Figure 13 . Figure 13 This is a circuit architecture diagram of a pixel driving circuit 1300 according to an embodiment of this disclosure. Figure 13As shown, the pixel driving circuit 1300 comprises switch units T1-T4, a control circuit 1310, a capacitor C1, and a light emitting unit L1. In some embodiments, each of the switch units T1-T4 comprises an NMOS switch element, and the following embodiments will be described by taking the NMOS switch element as an example. However, the switch units T1-T4 in the present disclosure are not limited to comprising an NMOS switch element, and in other embodiments, each of the switch units T1-T4 can comprise a plurality of NMOS switches connected to each other, a BJT, one or more switch circuits having equivalent functions, and the present disclosure is not limited thereto.

[0131] In some embodiments, the switch unit T1 and the light emitting unit L1 are coupled between a first operating voltage source VDD and a second operating voltage source VSS. A first end of the light emitting unit L1 is coupled to the first operating voltage source VDD, a second end of the light emitting unit L1 is coupled to a first end of the switch unit T1, and a second end of the switch unit T1 is coupled to the second operating voltage source VSS. A first end of the switch unit T2 is coupled to the second operating voltage source VSS, and a control end of the switch unit T2 is coupled to an emission signal EM. A first end of the switch unit T3 is coupled to a data voltage Vdata, a control end of the switch unit T3 is coupled to a control signal S1, and a second end of the switch unit T3 is coupled to a control end (node A) of the switch unit T1. One end of the capacitor C1 is coupled to the control end (node A) of the switch unit T1, and the other end of the capacitor C1 is coupled to a second end (node B) of the switch unit T2. A first end of the switch unit T4 is coupled to a second end (node B) of the capacitor C1, a control end of the switch unit T4 is coupled to a control signal S2, and a second end of the switch unit T4 is coupled to a reference voltage Vref1, wherein the reference voltage Vref1 is a low-level voltage. The control circuit 1310 is coupled to the second end (node B) of the capacitor C1 to set a potential of the node B.

[0132] In some embodiments, the control circuit 130 comprises a switch unit T5, and the switch unit T5 comprises an NMOS switch element, and the following embodiments will be described by taking the NMOS switch element as an example. However, the switch unit T5 in the present disclosure can be composed of other elements, and the present disclosure is not limited thereto.

[0133] In some embodiments, a first end of the switch unit T5 is coupled to the second end (node B) of the capacitor C1, and a second end and a control end of the switch unit T5 are coupled to a reference voltage Vref2.

[0134] It should be noted that in other embodiments, those skilled in the art can replace the switch units T1-T5 with PMOS switches, CMOS switches, or other similar switch elements, and correspondingly adjust the logic levels of the system voltages (such as the first operating voltage source VDD and the second operating voltage source VSS), the emission signal (such as the emission signal EM), and the control signals (such as the control signals S1-S3), which can also achieve the same functions as the present embodiments.

[0135] Figure 14 for Figure 13 Timing diagram of control signals for the pixel driving circuit. Figure 14 In the process, the pixel driving circuit 1300 operates sequentially in the first period P1, the second period P2, the third period P3, and the fourth period P4. Figure 15A for Figure 13 The 1300 mid-pixel drive circuit is in Figure 14 The circuit state diagram shown is for the first period P1, and the first period P1 belongs to the reset phase. Figure 14 As shown, during the first period P1, control signals S1 and S2 are high-level signals, and the light emission signal EM is low-level signal. Correspondingly, as... Figure 15A As shown, switch units T1, T2, and T5 are in the off state, while switch units T3 and T4 are in the on state. In this situation, one current path flows from the data voltage Vdata through switch unit T2 to node A, pulling the node's potential to the same level as the data voltage Vdata, thereby turning off switch unit T1 to prevent current from flowing through the light-emitting unit L1 and causing flickering. The other current path flows from node B through switch unit T4 to the reference voltage Vref1, resetting the potential of node B to the same level as the reference voltage Vref1.

[0136] Figure 15B for Figure 13 The 1300 mid-pixel drive circuit is in Figure 14 The circuit state diagram for the second period P2 is shown, and the second period P2 belongs to the compensation stage. Figure 14 As shown, during the second period P2, control signal S1 is a high-level signal, while control signal S2 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 15B As shown, switch units T1, T2, and T4 are in the off state, while switch units T3 and T5 are in the on state. In this case, the potential of node A remains at the data voltage Vdata, while the potential of node B is pulled down to a threshold voltage lower than the reference voltage Vref2 because the current path changes from the reference voltage Vref2 to flow to node B through switch unit T5. This threshold voltage is the threshold voltage of switch unit T5 (hereinafter referred to as Vth_T5, this symbol is not shown in the attached figure).

[0137] Figure 15C for Figure 13 The 1300 mid-pixel drive circuit is in Figure 14 The circuit state diagram shown is for the third period P3, which is the light-emitting stage. Figure 14As shown, during the third period P3, control signals S1 and S2 are low-level signals, while the light emission signal EM is high-level signal. Correspondingly, as... Figure 15C As shown, switching units T1 and T2 are in the ON state, while switching units T3 to T5 are in the OFF state. In this case, the potential of node B is pulled to the same level as the second operating voltage source VSS. Node A is floating. When there is a voltage level change at the second terminal of capacitor C1 (node ​​B), the change in voltage level will be coupled to node A. Since the potential change of node B compared to the previous stage is VSS - (Vref2 - Vth_T5), the potential of node A at this time can be expressed as Vdata + VSS - (Vref2 - Vth_T5). Therefore, the voltage across the control terminal and the second terminal of switching unit T1 can be increased, reducing the voltage across the first terminal and the second terminal of switching unit T1, thereby reducing power consumption.

[0138] Furthermore, since the current flowing through the light-emitting unit L1 is equal to the current flowing through the switching unit T1, if we represent the critical voltage of the switching unit T1 as Vth_T1 and the current flowing through the switching unit T1 as I, then according to the formula for the current flowing through the switching unit T1, we have:

[0139]

[0140] Assuming the critical voltage Vth_T5 of switching unit T5 is equal to the critical voltage Vth_T5 of switching unit T1, canceling them out yields the following:

[0141]

[0142] Because the threshold voltage of the transistor itself is unstable, and the impedance along the entire current path causes different pixels on the panel to receive different voltage values ​​from the second operating voltage source VSS, the current control of the light-emitting diode will be affected. Based on the above embodiment, and assuming that the threshold voltages of switching units T1 and T6 are the same, the second operating voltage source VSS and the threshold voltage Vth can be successfully compensated, so that the current calculation of the light-emitting unit L1 is independent of the second operating voltage source VSS and the threshold voltage Vth, that is, it is not affected by changes in the second operating voltage source VSS and the threshold voltage Vth.

[0143] In some embodiments, Figure 14 The control signal timing diagram also includes a fourth period, P4. Figure 15D for Figure 13 The 1300 mid-pixel drive circuit is in Figure 14 The circuit state diagram shown is for the fourth period P4, which is the anti-glare stage. Figure 14As shown, in the fourth period P4, the control signal S1 is a high level signal, the control signal S2 and the emitting signal EM are low level signals. Correspondingly, as shown in FIG. 13B, the switch unit T3 is in the on state, and the remaining switch units T1-T2 and T4-T5 are in the off state. Compared with the third period P3, in this case, only one current path flows through the switch unit T3 to the node A from the data voltage Vdata, so that the potential of the node A is the same as the data voltage Vdata, and thereby the switch unit T1 is closed, avoiding the case that the light emitting unit L1 continues to emit light to cause glare. Figure 15D As shown, in the fourth period P4, the control signal S1 is a high level signal, the control signal S2 and the emitting signal EM are low level signals. Correspondingly, as shown in FIG. 13B, the switch unit T3 is in the on state, and the remaining switch units T1-T2 and T4-T5 are in the off state. Compared with the third period P3, in this case, only one current path flows through the switch unit T3 to the node A from the data voltage Vdata, so that the potential of the node A is the same as the data voltage Vdata, and thereby the switch unit T1 is closed, avoiding the case that the light emitting unit L1 continues to emit light to cause glare.

[0144] Please refer to Figure 16 . Figure 16 The circuit architecture diagram of the pixel driving circuit 1600 of some embodiments of the present disclosure. Figure 16 and Figure 13 The difference between the pixel driving circuit 1600 and the pixel driving circuit 1300 lies in that the elements contained in the control circuit 1610 in the pixel driving circuit 1600 and the control circuit 1310 in the pixel driving circuit 1300 are different, and the remaining parts of the pixel driving circuit 1600 are the same as the pixel driving circuit 1300 except the control circuit 1610 and the voltage and signals coupled thereto, which will not be described here. Figure 16 Figure 13 In some embodiments, the control circuit 1610 contains the switch units T5-T7. In some embodiments, the switch units T5-T7 each contain an NMOS switch element, and the following embodiments will be described by taking this as an example, but the switch units T5-T7 in the present disclosure are not limited to containing an NMOS switch element, and in other embodiments, each of the switch units T5-T7 can contain multiple NMOS switches connected to each other, contain a BJT, contain one or more switching circuits with equivalent functions, and the present disclosure is not limited thereto.

[0145] In some embodiments, the first end of the switch unit T5 is coupled to the first operating voltage source VDD, the second end of the switch unit T5 is coupled to the second end (node B) of the capacitor C1, and the control end of the switch unit T5 is coupled to the first end of the switch unit T6 and the first end of the switch unit T7 (node C). The second end of the switch unit T6 is coupled to the reference voltage Vref1, and the second end of the switch unit T6 is coupled to the control signal S2, wherein the reference voltage Vref is a low level voltage for turning off the circuit. The second end of the switch unit T7 is coupled to the reference voltage Vref2, and the control end of the switch unit T7 is coupled to the control signal S3.

[0146] In some embodiments, the first end of the switch unit T5 is coupled to the first operating voltage source VDD, the second end of the switch unit T5 is coupled to the second end (node B) of the capacitor C1, and the control end of the switch unit T5 is coupled to the first end of the switch unit T6 and the first end of the switch unit T7 (node C). The second end of the switch unit T6 is coupled to the reference voltage Vref1, and the second end of the switch unit T6 is coupled to the control signal S2, wherein the reference voltage Vref is a low level voltage for turning off the circuit. The second end of the switch unit T7 is coupled to the reference voltage Vref2, and the control end of the switch unit T7 is coupled to the control signal S3.

[0147] In some embodiments, the first end of the switch unit T5 is coupled to the first operating voltage source VDD, the second end of the switch unit T5 is coupled to the second end (node B) of the capacitor C1, and the control end of the switch unit T5 is coupled to the first end of the switch unit T6 and the first end of the switch unit T7 (node C). The second end of the switch unit T6 is coupled to the reference voltage Vref1, and the second end of the switch unit T6 is coupled to the control signal S2, wherein the reference voltage Vref is a low level voltage for turning off the circuit. The second end of the switch unit T7 is coupled to the reference voltage Vref2, and the control end of the switch unit T7 is coupled to the control signal S3. Figure 16 ​In the illustrated embodiment, switching units T1 to T7 are exemplified using NMOS switches, but this disclosure is not intended to limit the scope. In another embodiment, those skilled in the art can replace switching units T1 to T7 with PMOS switches, CMOS switches, or other similar switching elements, and adjust the logic levels of the system voltage (e.g., the first operating voltage source VDD and the second operating voltage source VSS), the light emission signal (e.g., the light emission signal EM), and the control signals (e.g., control signals S1 to S3) accordingly to achieve the same functionality as in this embodiment.

[0148] Figure 17 for Figure 16 Timing diagram of control signals for pixel drive circuit 1600. Figure 17 In this process, the pixel driving circuit 1600 operates sequentially in the first period P1, the second period P2, the third period P3, and the fourth period P4.

[0149] Figure 18A for Figure 16 The 1600 mid-pixel drive circuit is in Figure 17 The circuit state diagram shown is for the first period P1, and the first period P1 belongs to the reset phase. Figure 17 As shown, during the first period P1, control signals S1 and S2 are high-level signals, while control signal S3 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 18A As shown, switch units T1, T2, T5, and T7 are in the off state, while switch units T3, T4, and T6 are in the on state. At this time, one current flows from the data voltage Vdata through switch unit T3 to node A, setting the potential of node A to the same level as the data voltage Vdata, thereby turning off switch unit T1 to prevent current from flowing through the light-emitting unit L1 and causing flickering. A second current path flows from node B through switch unit T4 to the reference voltage Vref1, setting node B to the same level as the reference voltage Vref1. A third current path flows from node C through switch unit T6 to the reference voltage Vref1, setting node C, like node B, to the same level as the reference voltage Vref1.

[0150] Figure 18B for Figure 16 The 1600 mid-pixel drive circuit is in Figure 17 The circuit state diagram for the second period P2 is shown, and the second period P2 belongs to the compensation stage. Figure 17 As shown, during the second period P2, control signals S1 and S3 are high-level signals, while control signal S2 and the light emission signal EM are low-level signals. Correspondingly, as... Figure 18BAs shown, switch unit T1, switch unit T2, switch unit T4 and switch unit T6 are in the off state, and switch unit T3, switch unit T5 and switch unit T7 are in the on state. At this time, the potential of node A remains the same as in the previous stage. Since the current path is from the reference voltage Vref2 to node C via the on switch unit T7, the potential of node C is pulled to the same as the reference voltage Vref2. Finally, since switch unit T5 is on, the potential of node B at the source of switch unit T5 needs to be lower than the potential of node C at the gate of switch unit T5 by a threshold voltage, which is the threshold voltage of switch unit T5 at this time. If it is denoted as Vth_T5 (not shown in the figure), the potential of node B in this stage is Vref2-Vth_T5.

[0151] Figure 18C For Figure 16 The middle pixel driving circuit 1600 is in Figure 17 The circuit state diagram in the third period P3 is shown, and the third period P3 belongs to the light-emitting stage. As shown Figure 17 As shown, in the third period P3, the light-emitting signal EM is a high-level signal, and the control signals S1-S3 are low-level signals. Correspondingly, as shown Figure 18C As shown, switch unit T1 and switch unit T2 are in the on state, and switch units T3-T7 are in the off state. At this time, the potential of node B changes from Vref2-Vth_T5 in the previous stage to the same as the second operating voltage source VSS. Again, since node A is floating, when the voltage level of the second end (node B) of capacitor C1 changes, the level change amount will be coupled to node A. As described above, the level change amount of node B is VSS-(Vref2-Vth_T5), which is coupled to node A via capacitor C1, causing the potential of node A to change from Vdata in the previous stage to Vdata+VSS-(Vref2-Vth_T5). Therefore, the voltage across the control end and the second end of switch unit T1 can be raised, reducing the voltage across the first end and the second end of switch unit T1, thereby reducing power consumption.

[0152] In addition, since the current flowing through the light-emitting unit L1 is equal to the current flowing through the switch unit T1, if the threshold voltage of switch unit T1 is denoted as Vth_T1 and the current flowing through switch unit T1 is denoted as I, then according to the current formula through switch unit T1:

[0153]

[0154] Assuming that the threshold voltage Vth_T5 of switch unit T5 and the threshold voltage Vth_T1 of switch unit T1 are equal, and offsetting both, we can get:

[0155]

[0156] Since the threshold voltage of the transistor itself is unstable, and the impedance on the entire current path causes the voltage value of the second operating voltage source VSS received by different pixels on the panel to be different, the current control of the light-emitting diode will be affected. Based on the above embodiment, and under the assumption that the threshold voltage of switch unit T1 and switch unit T5 is the same, the second operating voltage source VSS and the threshold voltage Vth can be successfully compensated, so that the current calculation of the light-emitting unit L1 is independent of the second operating voltage source VSS and the threshold voltage Vth, that is, is not affected by the change of the second operating voltage source VSS and the threshold voltage Vth.

[0157] In some embodiments, Figure 17 The control signal timing diagram in Figure 18D For Figure 16 The pixel driving circuit 1600 in Figure 17 The circuit state diagram in the fourth period P4 shown in FIG. 16B, and the fourth period P4 belongs to the anti-glare stage. As shown in Figure 17 In the fourth period P4, the control signal S1 is a high-level signal, and the control signal S1, the control signal S2 and the light-emitting signal EM are low-level signals. Correspondingly, as shown in Figure 18D The switch unit T3 is in the on state, and the remaining switch units T1, T2 and T4-T7 are in the off state. Compared with the third period P3, in this case, only one current path flows through the switch unit T3 to the node A from the data voltage Vdata, so that the potential of the node A is the same as the data voltage Vdata, and thereby the switch unit T1 is closed, avoiding the case that the light-emitting unit L1 continues to emit light causing glare.

[0158] As can be seen from the above, through the circuit architecture design of the pixel driving circuit 100, the pixel driving circuit 400, the pixel driving circuit 700, the pixel driving circuit 1000, the pixel driving circuit 1300 and the pixel driving circuit 1600, the voltage compensation method can be used to make the current of the light-emitting unit L1 not affected by the variation of the second operating voltage source VSS and the threshold voltage Vth, and at the same time, the potential of the second operating voltage source VSS is increased, so that the potential difference between the first operating voltage source VDD and the second operating voltage source VSS is reduced, thereby reducing power consumption.

[0159] Please refer to Figure 19 . Figure 19 For Figure 1 The voltage simulation diagram of the node A in Figure 19As shown, the voltages VA1 to VA3 corresponding to three different critical voltage changes (ΔVth, not shown in the figure) of +0.3V, -0.3V, and 0V respectively demonstrate that the critical voltage was successfully compensated during the compensation stage. Furthermore, by combining three different critical voltage changes (ΔVth) with the second operating voltage source change ΔVSS (not shown in the figure), namely ΔVth = +0.3V / ΔVSS = +0.5V, ΔVth = -0.3V / ΔVSS = +0.5V, and ΔVth = 0V / ΔVSS = 0V, it can be seen that the change in VSS was successfully compensated during the light-emitting stage. In other words, the problem of output current errors caused by differences in the voltage of the second operating voltage source VSS received by different transistors or pixels due to line resistance in the circuit transmission path is avoided.

[0160] Figure 20A for Figure 1 Simulation graph of medium current error rate. (See figure) Figure 20A As shown, when the second operating voltage source changes by ΔVSS to a fixed value of +0.5 volts (V), the error rate of the current effect of different input data voltages Vdata is within 10%.

[0161] Figure 20B for Figure 1 Another simulation graph of the current error rate. (See figure below.) Figure 20B As shown, when the critical voltage change ΔVth is fixed at +0.3 volts (V) or -0.3 volts (V), the error rate of the current effect of different input data voltages Vdata is within 5%.

[0162] Figure 20C for Figure 1 Another simulation graph of the current error rate. (See figure below.) Figure 20C As shown, when the second operating voltage source change ΔVSS is fixed at +0.5 volts (V) and the critical voltage change ΔVth is fixed at +0.3 volts (V), or when the second operating voltage source change ΔVSS is fixed at +0.5 volts (V) and the critical voltage change ΔVth is fixed at -0.3 volts (V), the error rate of the current effect of different input data voltages Vdata is within 10%.

[0163] Through the above Figure 19 The voltage simulation shown and Figures 20A to 20C The current error rate simulation shown demonstrates the successful compensation and its effect achieved through the design of the pixel drive circuit 100.

[0164] Similarly, the aforementioned pixel driving circuits 400, 700, 1000, 1300, and 1600 can all utilize similar technologies. Figure 19 The voltage simulation shown and Figures 20A to 20C The current error rate simulation shown verifies the successful compensation effect for the threshold voltage and the second operating voltage source, which is not described here for the sake of simplicity.

[0165] In summary, the pixel driving circuit provided by the present disclosure can compensate for the threshold voltage and the operating voltage, so as to minimize the correlation between the current of the light-emitting diode and the threshold voltage and the operating voltage. In addition, the present disclosure reduces the required driving voltage difference of the pixel circuit, thereby reducing power consumption.

[0166] Although the present disclosure has been disclosed in the embodiments as above, it is not limited to the present disclosure, and any person skilled in the art can make various changes and modifications without departing from the concept and scope of the present disclosure, and therefore the protection scope of the present disclosure shall be subject to the claims.

Claims

1. A pixel driving circuit, comprising: a light emitting unit coupled to a first operating voltage source; a first switch unit having a first terminal, a second terminal and a control terminal, the first terminal of the first switch unit being coupled to the light emitting unit, the second terminal of the first switch unit being coupled to a second operating voltage source; a second switch unit having a first terminal and a second terminal, the first terminal of the second switch unit being coupled to the second operating voltage source; a third switch unit coupled between a data voltage and the control terminal of the first switch unit; a fourth switch unit coupled to the second terminal of the second switch unit; a capacitor coupled between the control terminal of the first switch unit and the second terminal of the second switch unit; and a control circuit coupled to the second terminal of the second switch unit for controlling a potential of the second terminal of the second switch unit; a fifth switch unit having a first terminal, a second terminal and a control terminal, the first terminal of the fifth switch unit being coupled to the first operating voltage source, the second terminal of the fifth switch unit being coupled to the second terminal of the second switch unit; a sixth switch unit coupled to the control terminal of the fifth switch unit; and a seventh switch unit coupled between a reference voltage and the control terminal of the fifth switch unit.

2. The pixel driving circuit of claim 1, wherein the control circuit is further coupled to the control terminal of the fifth switch unit.

3. The pixel driving circuit of claim 1, wherein the control circuit is further coupled to the control terminal of the sixth switch unit.

4. The pixel driving circuit of claim 1, wherein the control circuit is further coupled to the control terminal of the seventh switch unit.

5. The pixel driving circuit of claim 1, wherein the control circuit is further coupled to the control terminal of the third switch unit.

6. The pixel driving circuit of claim 1, wherein the control circuit is further coupled to the control terminal of the fourth switch unit.

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