Method and apparatus for recombining upstream frames in a pon

By employing a reassembly information table and dynamic mapping strategy based on service data frames in the PON chip, the problems of excessively large reassembly information table dimensions and insufficient cache resources in multi-channel PON chips are solved, achieving more efficient reassembly processing and lower logic circuit complexity, while reducing chip area and power consumption.

CN116723432BActive Publication Date: 2026-06-23FIBERHOME TELECOMMUNICATION TECHNOLOGIES CO LTD +1

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
FIBERHOME TELECOMMUNICATION TECHNOLOGIES CO LTD
Filing Date
2023-07-05
Publication Date
2026-06-23

AI Technical Summary

Technical Problem

In existing PON chips, the data interfaces of different channels vary greatly, which requires maintaining a large number of reassembly information tables at the same time. This results in excessive demand for internal cache resources and high difficulty in implementing logic circuits.

Method used

By authorizing the use and release of reassembly sequence numbers based on service data frames and dynamically mapping them with PON uplink T-CONT, the reassembly information table is reduced from M*N to R, and the data cache is reduced from (M*N+P)*MAU to (R+P)*MAU. By adopting a frame-based reassembly information table and dynamic mapping strategy, the dimensionality of the reassembly information table and cache resources are reduced.

Benefits of technology

It reduces chip area, power consumption and cost, simplifies logic circuit implementation, improves the maintenance efficiency of the reorganized information table and the robustness of the system, and can flexibly handle channel slices of different sizes.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN116723432B_ABST
    Figure CN116723432B_ABST
Patent Text Reader

Abstract

The application discloses a PON uplink frame reorganization method: based on service data frame authorization use and release reorganization serial number, dynamic mapping with PON uplink T-CONT, converting reorganization information table based on T-CONT binding into reorganization information table based on service data frame, and reducing reorganization information table and data cache. The application reduces reorganization information table dimension through dynamic mapping, reduces chip data cache resources; converts Combo PON parallel reorganization of wavelength division multiplexing into serial reorganization of time slot access, time division multiplexes circuits, and reduces chip area; through authorized use of reorganization information table, dynamic mapping, converting information table based on T-CONT into authorization and release based on data frame, and reducing logical circuit implementation difficulty; combining frame serial number management with DBA of the PON system, and strengthening robustness; through a more flexible reorganization strategy, different size slices of each channel input can form blocks of any size or complete service frames. The application also provides a corresponding PON uplink frame reorganization device.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] This invention belongs to the field of PON (Passive Optical Network) technology, and more specifically, relates to a PON uplink frame reassembly method and apparatus. It is applicable to broadband access network chips, including existing 10G and next-generation 50GOLT (Optical Line Terminal) chips. Background Technology

[0002] The PON chip has M channels, and each channel has N T-CONTs (Transmission Containers). Depending on operator requirements, N>=2048 for 50G-PON (50Gbit Passive Optical Network) and XGS-PON (10Gbit Symmetric Passive Optical Network). Service data frames within a T-CONT are fragmented and transmitted after bandwidth allocation according to DBA (Dynamic Bandwidth Assignment). These fragments are interleaved within each T-CONT of the channel. The receiving side reassembles these interleaved fragments into complete service data frames for continuous, uninterrupted transmission.

[0003] Taking a 10G Combo PON chip as an example, it has a total of 16 PON interfaces. Combo PON integrates multiple modes, and each PON port has 2 wavelength division multiplexing channels (XG-PON / GPON). The number of PON channels is M = 16 * 2 = 32. The number of T-CONTs is related to the number of ONUs (Optical Network Units) that can be connected to it. A single channel needs to support at least 256 ONUs, and each ONU needs to support at least 8 T-CONTs. The minimum is N = 256 * 8 = 2048. Summary of the Invention

[0004] The technical problem to be solved:

[0005] Due to the significant differences in data interfaces between different channels, existing technologies fragment and reassemble N T-CONT service data frames within M PON channels. If a maximum of M*N service data frame fragments need to be reassembled simultaneously within the chip, then M*N reassembly information tables must be maintained concurrently.

[0006] Considering the processing latency of logic circuit release and the burstiness of interleaved service data frame tails, the reserved internal cache (including but not limited to RAM) or external cache (including but not limited to DDR) resources need to be slightly larger than the number of entries in the reorganized information table, with the margin denoted as P. The number of MAUs (Memory Access Units) is recorded as (M*N+P)*MAU.

[0007] To achieve the above objectives, according to one aspect of the present invention, a PON uplink frame reassembly method is provided, comprising: authorizing the use and release of a reassembly sequence number based on a service data frame, dynamically mapping it to a PON uplink T-CONT, converting a reassembly information table based on the T-CONT into a reassembly information table based on the service data frame, and reducing the reassembly information table and data cache.

[0008] In one embodiment of the present invention, the reorganization information table and data cache are reduced, specifically as follows:

[0009] The reassembly information table is reduced from M*N to R, where R is less than M*N. The data cache is reduced from (M*N+P)*MAU to (R+P)*MAU, where M is the number of channels, N is the number of T-CONTs per channel, P is the reserved cache margin, MAU is the number of MAUs, and R is the number of entries in the reduced reassembly information table based on the service data frame.

[0010] In one embodiment of the present invention, the reassembly information table based on the service data frame specifically comprises:

[0011] Maintain R reassembly information entries, corresponding to the frame sequence number; the reassembly information table is initialized at the beginning of the fragmentation and a block of available MAUs is requested from the buffer; intra-frame fragments are written to the buffer according to the current MAU address and fragment length, and the internal information of the MAU is updated after each buffer write is completed; at the end of the fragmentation, the information table is sent to the transmission queue and the corresponding reassembly information table is formatted.

[0012] In one embodiment of the present invention, the reassembly information includes: offset, length, and frame description within the MAU.

[0013] In one embodiment of the present invention, the dynamic mapping of the authorized use and release of the reassembly sequence number based on the service data frame with the PON uplink T-CONT specifically includes:

[0014] When the frame header fragment of T-CONT[i] arrives, a frame sequence number [i] is requested from the frame sequence number address pool and written into the T-CONT mapping table;

[0015] When the middle fragment of frame T-CONT[i] arrives, the frame sequence number [i] is obtained by looking up the T-CONT mapping table. The reassembly information table is then looked up, and the fragment data is written to the corresponding buffer space according to the reassembly information table. The reassembly information table is then updated. This process is repeated multiple times according to the number of fragments until the last fragment is reached.

[0016] When the end fragment of T-CONT[i] arrives, the end fragment is written to the buffer and reassembled. The reassembled message is then read into the subsequent queue to await scheduling. The frame sequence number [i] is released back to the frame sequence number address pool, and the corresponding T-CONT mapping table is cleared.

[0017] In one embodiment of the present invention, when there are other TCONT[j,k...] fragment interleavings, if a frame header fragment occurs, the requested frame sequence numbers are [j,k...], which cannot conflict with [i].

[0018] In one embodiment of the present invention, the management of frame sequence numbers specifically includes:

[0019] Upon system power-on initialization, R frame sequence numbers are stored in the frame sequence number address pool, and the address pool counter C = R.

[0020] After initialization, the system enters the working scenario. When the frame header arrives, a frame sequence number is requested, and the address pool counter C = C-1. When the frame tail arrives, the sequence number is released, and the address pool counter C = C+1.

[0021] When the value of the address pool counter C is less than the pre-configured threshold U, a reorganization report is issued to notify the DBA of the existing reorganization information, and a PAUSE instruction is given; the DBA responds by suspending the bandwidth of the newly launched T-CONT fragmentation.

[0022] When the end of the frame arrives, the sequence number is released, the address pool counter C = C + 1, and when the value of the address pool counter C is restored to the pre-configured threshold V, PAUSE is canceled.

[0023] In one embodiment of the present invention, the method of managing the address pool by frame sequence number specifically includes:

[0024] Address pool is managed in a matrix manner: During initialization, all frame sequence numbers are sequentially filled into a K*P matrix, where K*P = R, K is the row of the matrix, and P is the column of the matrix. When requesting a frame sequence number, the matrix is ​​scanned row by row and column by column to find the first unused frame sequence number for use in the mapping table and marked as used. When releasing a frame sequence number, the mark is changed to unused.

[0025] The address pool is managed in a first-in-first-out (FIFO) manner: the PUSH end writes data, the POP end reads data, and POP is performed according to the first-in-first-out rule. The depth of the FIFO is R. During initialization, all frame sequence numbers are pushed into the FIFO in sequence. When requesting a frame sequence number, the sequence number is POPed out of the FIFO. When releasing a frame sequence number, the frame sequence number is pushed back into the FIFO.

[0026] According to another aspect of the present invention, a PON uplink frame reassembly apparatus is also provided, comprising an access module, an authorization module, a reassembly information table, a management module, a frame / block reassembler, and a buffer, wherein:

[0027] The access module converts M parallel multi-channel PON processing circuits into time-division multiplexed serial access circuits.

[0028] The authorization module, based on frame reassembly authorization and release, requests an available frame sequence number from the management module at the beginning of the service data frame fragmentation. The T-CONT is bound to the frame sequence number during the reassembly time of the frame. When subsequent fragments arrive, the T-CONT is mapped to a frame sequence number. The reassembly information table is then queried using the frame sequence number.

[0029] The reassembly information table maintains R reassembly information entries, each corresponding to a frame sequence number.

[0030] The management module manages R frame sequence numbers and records the frame sequence numbers requested by the authorized module and released by the frame / block reassembler.

[0031] The frame / block reassembler implements a programmable reassembly architecture, which can assemble any input fragment into blocks of any size or into complete service frames; after completion, it reads the buffer and releases the frame sequence number.

[0032] In one embodiment of the present invention, the reassembly information table is initialized at the beginning of the fragmentation and a block of available MAUs is requested from the cache; intra-frame fragments are written to the cache according to the current MAU address and fragment length, and the reassembly information is updated after each cache write is completed; at the end of the fragmentation, the information table is sent to the sending queue and the corresponding reassembly information table is formatted.

[0033] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0034] (1) The present invention reduces the dimension of the reorganized information table through dynamic mapping, thereby reducing the data cache resources of the chip;

[0035] (2) The present invention converts the wavelength division multiplexing Combo PON parallel reassembly into time slot access serial reassembly, and the circuit time division multiplexes to reduce chip area;

[0036] (3) This invention reduces the difficulty of logic circuit implementation by dynamically mapping the authorized use of the information table and converting the TCONT-based information table into a data frame-based authorization and release.

[0037] (4) This invention combines frame sequence number management with the DBA of the PON system, which enhances the robustness of the solution implementation;

[0038] (5) The present invention uses a more flexible recombination strategy to combine slices of different sizes input to each channel into blocks of any size or into complete service frames. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of a PON uplink frame reassembly device according to an embodiment of the present invention;

[0040] Figure 2 This is a frame reassembly authorization and release step in an embodiment of the present invention;

[0041] Figure 3 This is a flowchart illustrating frame sequence number management in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the structure of a frame sequence number management address pool according to an embodiment of the present invention; wherein Figure 4 (a) represents method one. Figure 4 (b) is method two;

[0043] Figure 5 This is a schematic diagram of a flexible programmable reconfiguration architecture according to an embodiment of the present invention; wherein... Figure 5 (a) represents method one. Figure 5 (b) is method two. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0045] This invention authorizes the use and release of reassembly sequence numbers based on service data frames and dynamically maps them to the PON uplink T-CONT. It converts the reassembly information table based on T-CONT binding into a reassembly information table based on service data frames, reducing the reassembly information table from M*N to R (R is much smaller than M*N) and the data buffer from (M*N+P)*MAU to (R+P)*MAU. This reduces the chip area, power consumption, and cost, while maintaining a simpler and more efficient reassembly information table. It also reduces the difficulty of logic circuit implementation and improves reliability.

[0046] To address the technical problems existing in this invention, this invention discloses a PON uplink frame reassembly device. Its structure is as follows: Figure 1 As shown, it mainly includes: access module, authorization module, reassembly information table, management module, frame / block reassembler, and cache.

[0047] Access module: Converts M parallel multi-channel PON processing circuits into time-division multiplexed serial access circuits.

[0048] Authorization Module: Based on frame reassembly authorization and release, it requests an available frame sequence number from the management module during the fragmentation header of the service data frame. The T-CONT is bound to the frame sequence number during the frame's reassembly time. When subsequent fragments arrive, they are mapped to frame sequence numbers based on the T-CONT. The reassembly information table is then queried using the frame sequence number.

[0049] Reassembly Information Table: Maintains R reassembly information entries, corresponding to frame sequence numbers. This information includes the current MAU address in the cache, as well as the offset, length, and frame description within the MAU. The reassembly information table is initialized at the beginning of fragmentation and a block of available MAUs is requested from the cache. Intra-frame fragmentation writes to the cache based on the current MAU address and fragment length. After each cache write, the offset, length, and frame description within the MAU are updated. At the end of fragmentation, the information table is sent to the transmission queue, and the corresponding reassembly information table is formatted.

[0050] Management Module: Manages R frame sequence numbers, recording frame sequence numbers requested by authorized modules and released by the frame / block reassembler. Because it is based on frame-based request and frame / block-based release, any T-CONT can correspond to the same or different frame sequence numbers when reassembly begins, achieving time-division multiplexing and dynamic management. When the managed sequence number is less than a threshold, a PAUSE instruction is given to the DBA, notifying the DBA to suspend bandwidth allocation for newly connected T-CONTs.

[0051] Frame / block reassembler: A flexible and programmable reassembly architecture that can assemble any input fragment into blocks of arbitrary size, or into complete service frames. After completion, it reads the buffer and releases the frame sequence number.

[0052] Example 1:

[0053] An example of frame reassembly authorization for use and release, such as Figure 2 As shown.

[0054] The authorization for the reassembly, use, and release of any service data frame within T-CONT[i] is dynamically mapped to the PON uplink T-CONT, and is generally divided into three steps:

[0055] S201: The frame header fragment of T-CONT[i] arrives. Request a frame sequence number[i] from the frame sequence number address pool and write it into the T-CONT mapping table.

[0056] S202: The intermediate fragment of frame T-CONT[i] arrives. Look up the T-CONT mapping table to get the frame sequence number[i]. Look up the reassembly information table. The fragment data is written to the corresponding buffer space according to the reassembly information table. Update the reassembly information table.

[0057] The T-CONT mapping table enables dynamic mapping between T-CONTs and frame sequence numbers, and maintains the binding relationship between T-CONTs and frame sequence numbers during the reassembly of a service data frame. There are three ways to implement the T-CONT mapping table, any of which can achieve the method and apparatus of this patent:

[0058] The first method uses directly addressed entries, utilizing internal memory or registers, with the address being TCONT and the data content being the frame sequence number. Of the three methods, the first method is the simplest to implement, has the best logic timing, and the smallest area; however, it is only suitable for situations with a small number of T-CONTs.

[0059] The second method, TCAM (Ternary Content Addressable Memory), writes the TCONT into the memory content, with the address being the frame sequence number. Of the three methods, this one is relatively simple to implement, has good logic timing, and has the largest area, making it suitable for situations with a large number of T-CONTs.

[0060] The third method is hashing, which uses internal memory or registers. The address is the hash value of TCONT, and the data content includes the frame sequence number and TCONT. The TCONT in the data content is used to resolve hash collisions. Among the three methods, this one is the most complex to implement, has the worst logic circuit timing, and has a medium area, making it suitable for situations with a large number of T-CONTs.

[0061] The reorganization information table maintains information such as the address, offset, length, and frame description of the data fragment write cache.

[0062] Depending on the number of fragments, S202 will repeat many times until the last fragment.

[0063] S203: The end fragment of frame T-CONT[i] arrives. After the end fragment is written to the buffer, reassembly is completed, and the reassembled message is read into the subsequent queue to await scheduling. Frame sequence number [i] is released back to the frame sequence number address pool, and the corresponding T-CONT mapping table is cleared.

[0064] For the reassembly of any service data frame, the frame header fragmentation is performed in step S201, the frame middle fragmentation is performed in step S202, and the frame tail fragmentation is performed in step S203.

[0065] During the reassembly of a service data frame, fragments of other service data frames will be interspersed, and each service frame will undergo the above steps independently.

[0066] During the interleaving of other TCONT[j,k...] fragments between S201 and S203, if a frame header fragment occurs, the requested frame sequence numbers are [j,k...], which cannot conflict with [i].

[0067] It is worth noting that, because the frame sequence number [i] is released back to the frame sequence number address pool in step S203 and the corresponding T-CONT mapping table is cleared, the frame sequence number requested by any subsequent T-CONT[i,j,k…] service data frame can be the same frame sequence number [i], thereby realizing dynamic mapping and time division multiplexing.

[0068] Example 2:

[0069] One implementation of frame sequence number management, such as Figure 3 As shown:

[0070] S301: System power-on initialization, storing R frame sequence numbers in the frame sequence number address pool, address pool counter C = R.

[0071] S302: After initialization, the system enters the working scenario. When the frame header arrives, a frame sequence number is requested, and the address pool counter C = C - 1. When the frame tail arrives, the sequence number is released, and the address pool counter C = C + 1.

[0072] S303: When the value of the address pool counter C is less than the pre-configured threshold U, a reorganization report is issued, notifying the DBA of the existing reorganization information, which is equivalent to issuing a PAUSE instruction. The DBA responds to the instruction and suspends the bandwidth of the newly connected T-CONT fragment.

[0073] S304: When the end of the frame arrives, release the sequence number and increment the address pool counter C by C+1. When the value of the address pool counter C returns to the pre-configured threshold V, cancel PAUSE.

[0074] It should be noted that step S302 is the normal operating mode, where the frame header is requested and the frame tail is released. However, in this step, the address pool counter is already lower than the preset threshold U, so no more frame headers are being received, and only the frame tail is being released. The frame tail must also be released to allow the address pool to return to the threshold V.

[0075] Where R is the number of entries in the recombined information table, R is determined according to the application scenario and can be much smaller than M*N. The smaller R is, the greater the probability of pausing the DBA. For a device example of DBA security, R = N / 2. As long as R is made less than M*N through this method, the technical solution of this invention can be considered to have beneficial effects.

[0076] U is the minimum threshold. If the value falls below the minimum threshold, there may be insufficient resources for subsequent reorganization, resulting in packet loss. V is the recovery threshold. If the value rises above the recovery threshold, normal requests can continue. V is greater than or equal to U.

[0077] For a specific T-CONT, as a compensation mechanism for the instantaneous bandwidth loss caused by the pause in bandwidth allocation, after the PAUSE ends, the DBA will prioritize allocating fragmented bandwidth to the affected T-CONT.

[0078] Example 3:

[0079] Based on Example 2, such as Figure 4 As shown, two methods for managing the frame sequence number address pool are disclosed.

[0080] like Figure 4 (a) shows Method 1, which manages the address pool using a matrix approach. During initialization, all frame sequence numbers are sequentially filled into a K*P matrix, where K*P = R (the number of entries in the reassembly information table). K represents the number of rows in the matrix, and P represents the number of columns. When requesting a frame sequence number, the matrix is ​​scanned row by row and column by column to find the first unused frame sequence number for use in the mapping table and mark it as used. This row-by-row scanning can be performed in ascending / descending order from a fixed starting point, or it can be performed using a non-repeating random number sequence each time. When releasing a frame sequence number, since the row and column to which the frame sequence number belongs are known, the mark is simply changed to unused.

[0081] like Figure 4 (b) shows method 2, which manages the address pool using a FIFO (First Input First Output) method. FIFO is a common memory structure in chip design. Data is written to the PUSH terminal and read from the POP terminal, following a first-in-first-out (POP) rule. The FIFO has a depth of R. During initialization, all frame sequence numbers are sequentially PUSHed into the FIFO. When requesting a frame sequence number, it is POPed from the FIFO. When releasing a frame sequence number, it is PUSHed back into the FIFO.

[0082] In terms of technical implementation, the initial frame sequence number can be a continuous value or a random discrete value. The duration of time a frame sequence number is occupied after allocation is related to the length of the corresponding reassembled business data frame; therefore, the release of the frame sequence number is random and not continuous. In the working state, the frame sequence number address pool contains random discrete values. Furthermore, if an external cache (including but not limited to DDR) is used, considering the possibility of MAU (Memory Access Unit) failure due to physical characteristics, it is recommended to use a random discrete value for the initial frame sequence number to reduce the probability of using a failed MAU. Even so, using a continuous value for the initial frame sequence number can still achieve the technical solution of this invention.

[0083] Example 4:

[0084] This invention provides a business data frame reassembly architecture. Examples demonstrate two methods, such as... Figure 5 :

[0085] like Figure 5 (a) shows Method 1, which allows for the assembly of blocks of any size according to programming configuration. One block's space is reserved in the cache (internal cache includes but is not limited to RAM, external cache includes but is not limited to DDR). Once assembled, it can be passed on. Service data frames are sorted according to the order in which they enter the device; those not shown have already been reassembled and released. The block space size can be flexibly configured. For whole-frame reassembly, taking Ethernet data frames as an example, the block space size is set to be able to cache the largest frame (e.g., 9600 bytes). Reassembly is considered complete after the service data frame endplate is written, and the reassembler schedules the entire packet to the subsequent module or service interface. For block reassembly of a specific size, the block space size is set to be able to cache one block (e.g., 256 bytes). Reassembly is considered complete when this area is full of data or when the service data frame endplate is written, and the reassembler schedules the service data block to the subsequent module or service interface.

[0086] like Figure 5 (b) shows Method 2, the reassembly of business data frames, which can also use the standard linked list processing method. The linked list records and chains together the addresses of the business data frames in the cache, recording the address of the next data segment cached at each step. The example includes three linked lists:

[0087] 1. Linked list of business data frame 0: starting address add0->addr11->addr12…

[0088] 2. Linked list of business data frame 7: starting address addr3->addr5…

[0089] 3. Linked list of business data frame 101: starting address addr1->addr2->addr4->addr6->addr7->addr8->addr9->addr10…

[0090] The reassembler only needs to maintain the starting address and length information of each business data frame, and the cache automatically links to the cache address corresponding to the next data fragment. By breaking links according to the configured length, it can also assemble blocks or entire frames of arbitrary size.

[0091] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PON uplink frame reassembly method, characterized in that, include: Based on the authorization and release of reassembly sequence numbers in service data frames, dynamic mapping with the PON uplink transport container T-CONT is used to convert the reassembly information table based on T-CONT into a reassembly information table based on service data frames, thereby reducing the size of the reassembly information table and data buffer. Specifically, the reassembly information table based on service data frames involves: maintaining R reassembly information entries, each corresponding to a frame sequence number; initializing the reassembly information table at the fragmentation header and requesting an available MAU from the buffer; writing intra-frame fragments to the buffer according to the current MAU address and fragment length, updating the internal information of the MAU after each buffer write; and sending the information table to the transmission queue at the fragmentation tail and formatting the corresponding reassembly information table.

2. The PON uplink frame reassembly method as described in claim 1, characterized in that, The information table and data cache will be reorganized and reduced, specifically as follows: The reorganization information table is reduced from M*N to R, where R is less than M*N, and the data cache is reduced from (M*N+P)*MAU to (R+P)*MAU, where M is the number of channels and N is the T of each channel. CONT number, P is the reserved buffer margin, MAU is the number of MAUs, and R is the number of entries in the reduced reassembled information table based on the service data frame.

3. The PON uplink frame reassembly method as described in claim 1 or 2, characterized in that, The reassembly information includes: offsets, lengths, and frame descriptions within the MAU.

4. The PON uplink frame reassembly method as described in claim 1 or 2, characterized in that, Based on the authorization of use and release of reassembly sequence numbers in service data frames, and dynamic mapping with PON uplink T-CONT, the specific details include: When the frame header fragment of T-CONT[i] arrives, a frame sequence number [i] is requested from the frame sequence number address pool and written into the T-CONT mapping table; When the middle fragment of frame T-CONT[i] arrives, the frame sequence number [i] is obtained by looking up the T-CONT mapping table. The reassembly information table is then looked up, and the fragment data is written to the corresponding buffer space according to the reassembly information table. The reassembly information table is then updated. This process is repeated multiple times according to the number of fragments until the last fragment is reached. When the end fragment of T-CONT[i] arrives, the end fragment is written to the buffer and reassembled. The reassembled message is then read into the subsequent queue to await scheduling. The frame sequence number [i] is released back to the frame sequence number address pool, and the corresponding T-CONT mapping table is cleared.

5. The PON uplink frame reassembly method as described in claim 4, characterized in that, When there are other T-CONT[j,k...] fragments interspersed, if a frame header fragment occurs, the requested frame sequence numbers are [j,k...], which cannot conflict with [i].

6. The PON uplink frame reassembly method as described in claim 1 or 2, characterized in that, Frame sequence number management specifically includes: Upon system power-on initialization, R frame sequence numbers are stored in the frame sequence number address pool, and the address pool counter C=R; After initialization, the system enters the working scenario. When the frame header arrives, a frame sequence number is requested, and the address pool counter C = C - 1. When the frame tail arrives, the sequence number is released, and the address pool counter C = C + 1. When the value of the address pool counter C is less than the pre-configured threshold U, a reorganization report is issued to notify the DBA of the existing reorganization information, and a PAUSE instruction is given; the DBA responds by suspending the bandwidth of the newly launched T-CONT fragmentation. When the end of the frame arrives, the sequence number is released, the address pool counter C = C + 1, and when the value of the address pool counter C is restored to the pre-configured threshold V, PAUSE is canceled.

7. The PON uplink frame reassembly method as described in claim 6, characterized in that, The methods for managing the address pool using frame sequence numbers specifically include: Address pool is managed in a matrix manner: During initialization, all frame sequence numbers are sequentially filled into a K*P matrix, where K*P=R, K is the row of the matrix, and P is the column of the matrix. When requesting a frame sequence number, the matrix is ​​scanned row by row and column by column to find the first unused frame sequence number for use in the mapping table and marked as used. When releasing a frame sequence number, the mark is changed to unused. The address pool is managed in a first-in-first-out (FIFO) manner: the PUSH end writes data, the POP end reads data, and POP is performed according to the first-in-first-out rule. The depth of the FIFO is R. During initialization, all frame sequence numbers are pushed into the FIFO in sequence. When requesting a frame sequence number, the sequence number is POPed out of the FIFO. When releasing a frame sequence number, the frame sequence number is pushed back into the FIFO.

8. A PON uplink frame reassembly device, characterized in that, It includes an access module, an authorization module, a reassembly information table, a management module, a frame / block reassembler, and a cache, among which: The access module converts M parallel multi-channel PON processing circuits into time-division multiplexed serial access circuits. The authorization module, based on frame reassembly authorization and release, requests an available frame sequence number from the management module during the fragmentation header of the service data frame. The T-CONT is bound to the frame sequence number during the frame reassembly time. When subsequent fragments arrive, based on the T-CONT... CONT is mapped to a frame sequence number; the reassembly information table is then queried using the frame sequence number. The reassembly information table maintains R reassembly information entries, corresponding to the frame sequence number. The reassembly information table is initialized at the beginning of fragmentation and a block of available MAU is requested from the buffer. Intra-frame fragmentation is written to the buffer according to the current MAU address and fragment length. After each buffer write is completed, the internal information of the MAU is updated. At the end of fragmentation, the information table is sent to the transmission queue and the corresponding reassembly information table is formatted. The management module manages R frame sequence numbers and records the frame sequence numbers requested by the authorized module and released by the frame / block reassembler. The frame / block reassembler implements a programmable reassembly architecture, which can assemble any input fragment into blocks of any size or into complete service frames; after completion, it reads the buffer and releases the frame sequence number.

9. The PON uplink frame reassembly apparatus as described in claim 8, characterized in that, The reassembly information table is initialized at the beginning of the fragmentation and a block of available MAUs is requested from the cache. Intra-fragmentation is written to the cache according to the current MAU address and fragment length. The reassembly information is updated after each cache write. At the end of the fragmentation, the information table is sent to the transmission queue and the corresponding reassembly information table is formatted.