Memory structure

Abstract

The application discloses a memory structure, comprising a substrate, a first element layer arranged on the substrate, and a second element layer arranged between the substrate and the first element layer. The first element layer comprises a plurality of memory blocks, and a plurality of word lines and bit lines for controlling memory cells of the memory blocks. The second element layer comprises a first peripheral block and a second peripheral block, wherein in a vertical direction, the first peripheral block and the second peripheral block respectively partially overlap with two adjacent memory blocks. The embodiment of the application can improve the area ratio of the memory blocks, and obtain higher storage capacity in a limited wafer area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory structure. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, which includes memory array blocks containing memory cells and peripheral blocks containing peripheral circuitry.

[0003] Currently, common DRAMs place the memory blocks and peripheral blocks on the same component layer. The advantage is that the circuit structure of both can be integrated and manufactured, and it is easy to directly run word lines (WL) and bit lines (BL) that control the write and read operations of memory cells to the peripheral blocks.

[0004] However, the peripheral blocks of this design occupy a relatively large area of ​​the memory blocks, reducing the cell ratio. In addition, with the miniaturization of component sizes and increasingly complex circuit designs, the tolerance for process variations has become increasingly tight, leading to greater difficulty and cost in integrated manufacturing. Summary of the Invention

[0005] The purpose of this invention is to provide a memory structure that solves the technical problem in the prior art where peripheral blocks occupy the usable area of ​​the storage block, reducing the storage block area ratio and leading to increasingly higher difficulties and costs in integration and manufacturing.

[0006] An embodiment of the present invention provides a memory structure, which includes a substrate, a first element layer disposed on the substrate, a plurality of memory blocks located in the first element layer, a plurality of word lines and bit lines disposed in the first element layer for controlling memory cells of the memory blocks, a second element layer disposed between the substrate and the first element layer, and a first peripheral block and a second peripheral block located in the second element layer, wherein, in the vertical direction, the first peripheral block and the second peripheral block partially overlap with two adjacent memory blocks respectively.

[0007] Beneficial effects

[0008] The beneficial effects of this invention over the prior art include at least the following: by setting the memory blocks and peripheral blocks of the memory structure in different structural layers, the peripheral blocks do not occupy the area between the memory blocks, effectively improving the area ratio of the memory blocks and obtaining higher storage capacity within a limited wafer area. Attached Figure Description

[0009] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0010] Figure 1 This is a cross-sectional schematic diagram of a memory structure according to an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram of the layout of a memory structure according to an embodiment of the present invention, which includes a plurality of memory blocks disposed in a first element layer and a plurality of peripheral blocks disposed in a second element layer.

[0012] Figure 3 for Figure 2 A schematic diagram of the layout of one of the storage blocks and its surrounding blocks.

[0013] Figure 4 This is a cross-sectional schematic diagram of a memory structure according to an embodiment of the present invention, which includes a memory cell consisting of a transistor and a capacitor.

[0014] Figure 5 This is a schematic diagram of the layout of a memory structure according to an embodiment of the present invention, which includes a plurality of memory blocks disposed in a first element layer and a plurality of peripheral blocks disposed in a second element layer.

[0015] Figure 6 for Figure 5 A schematic diagram of the layout of one of the storage blocks and its surrounding blocks.

[0016] Figure 7 This is a cross-sectional schematic diagram of a memory structure according to an embodiment of the present invention, which includes a memory cell composed of two transistors.

[0017] Figure 8 and Figure 9 These are cross-sectional schematic diagrams of a memory structure according to an embodiment of the present invention, which includes... Figure 7 The storage unit shown is an interconnect structure that electrically connects the storage unit to a surrounding block.

[0018] The reference numerals in the attached figures are explained as follows:

[0019]

[0020]

[0021]

[0022] Detailed Implementation

[0023] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, along with accompanying drawings, to explain in detail the technical solutions and desired effects of this invention. Those skilled in the art can, without departing from the spirit of this invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0024] Please refer to Figures 1 to 3 . Figure 1 This is a schematic cross-sectional view of a memory structure according to an embodiment of the present invention in the XZ plane (a plane defined by the X and Z directions). Figure 2 This is a schematic diagram of the layout of a memory structure according to an embodiment of the present invention in the XY plane (a plane defined by the X and Y directions). Figure 3 for Figure 2 This is a schematic diagram of the layout of one of the storage blocks and its surrounding blocks. The X and Y directions shown in the diagram are perpendicular to each other, and the Z direction is perpendicular to the XY plane.

[0025] like Figure 1 As shown, the memory structure of the present invention includes a substrate L0, a first element layer L1 disposed on the substrate L0, and a second element layer L2 disposed between the substrate L0 and the first element layer L1. The first element layer L1 includes a plurality of memory blocks 10, and a plurality of bit lines BL and a plurality of word lines WL controlling the write and read operations of memory cells MC of the memory blocks 10. The second element layer L2 includes a plurality of peripheral blocks 20. The substrate L0 includes any material layer or structure that can provide support for the memory structure, such as a semiconductor substrate, wafer, chip, or circuit board, but is not limited thereto. Semiconductor manufacturing processes can be performed on the substrate 10 to sequentially form the second element layer L2 and the first element layer L1. In some embodiments, semiconductor manufacturing processes can be performed to form the first element layer L1 on the second element layer L2, and then the second element layer L2 can be bonded to the substrate L0.

[0026] like Figure 2 and Figure 3As shown, storage blocks 10 are arranged in rows along the X direction and in columns along the Y direction. Peripheral blocks 20 include a first peripheral block 22, a second peripheral block 24, a third peripheral block 26, and a fourth peripheral block 28. In some embodiments, the first peripheral block 22 and the second peripheral block 24 respectively include peripheral circuitry controlling the bit line BL, such as a row decoder and a sense amplifier. The third peripheral block 26 and the fourth peripheral block 28 respectively include peripheral circuitry controlling the word line WL, such as a column decoder. The first peripheral blocks 22 and the second peripheral blocks 24 are alternately arranged below each row of storage blocks 10 along the X direction, located between two adjacent storage blocks 10, and partially overlap with the two adjacent storage blocks 10 in the vertical direction (i.e., the Z direction). In other words, the first peripheral blocks 22 and the second peripheral blocks 24 respectively partially overlap with two adjacent storage blocks 10. The third peripheral block 26 and the fourth peripheral block 28 are each arranged in rows along the X direction, and the rows of the third peripheral block 26 and the rows of the fourth peripheral block 28 are alternately located between the rows of storage block 10 along the Y direction, adjacent to the upper or lower edge of storage block 10, without overlapping storage block 10.

[0027] Bit lines BL extend along the X direction and are arranged parallel to the Y direction. Word lines WL extend along the Y direction and are arranged parallel to the X direction. The intersection of bit lines BL and word lines WL is approximately the location of the memory cell MC. Specifically, odd-numbered row bit lines BLa are controlled by the first peripheral block 22, even-numbered row bit lines BLb are controlled by the second peripheral block 24, odd-numbered column word lines WLa are controlled by the third peripheral block 26, and even-numbered column word lines WLb are controlled by the fourth peripheral block 28. Furthermore, the first peripheral block 22 simultaneously controls the odd-numbered row bit lines BLa of the two adjacent memory blocks 10 that overlap with it; the second peripheral block 24 simultaneously controls the even-numbered row bit lines BLb of the two adjacent memory blocks 10 that overlap with it; the third peripheral block 26 simultaneously controls the odd-numbered column word lines WLa of the memory blocks 10 above and below it; and the fourth peripheral block 28 simultaneously controls the even-numbered column word lines WLb of the memory blocks 10 above and below it.

[0028] Interconnect structure 104 is used to electrically connect bit lines BL to the first peripheral block 22 or the second peripheral block 24, respectively. Interconnect structure 104 may include a single conductive portion or be composed of multiple conductive portions. The design of the storage block 10 and the first peripheral block 22 or the second peripheral block 24 overlapping in the vertical direction allows for convenient selection of the interconnect structure 104 within the layout area where the first peripheral block 22 or the second peripheral block 24 overlaps with the storage block 10, or as... Figure 3The layout area shown is located within the non-overlapping storage block 10 of the first peripheral block 22 or the second peripheral block 24, as long as the bit line BL can be smoothly electrically connected to the corresponding peripheral block. This improves the flexibility of the layout design, shortens the winding distance, and reduces power loss. The interconnect structure 104 can be entirely disposed in the second element layer L2, or include conductive portions disposed in the second element layer L2 and the first element layer L1, respectively.

[0029] Interconnect structure 106 is used to electrically connect word lines WL to the third peripheral block 26 or the fourth peripheral block 28, respectively. Interconnect structure 106 includes a single conductive portion or is composed of multiple conductive portions. Depending on layout design requirements, interconnect structure 106 can be selectively placed within the layout area of ​​storage block 10, or as... Figure 3 The layout area shown is located in the third peripheral block 26 or the fourth peripheral block 28, as long as the word line WL can be electrically connected to the corresponding peripheral block smoothly. The interconnect structure 106 can be completely disposed in the first element layer L1, or it can be disposed in the conductive portions of the first element layer L1 and the second element layer L2 respectively.

[0030] For ease of understanding, Figure 3 Interconnect structures 104 and 106 are schematically marked to represent the electrical connections of odd-numbered row lines BLa, even-numbered row lines BLb, odd-numbered column lines WLa, and even-numbered column lines WLb to the first peripheral block 22, the second peripheral block 24, the third peripheral block 26, and the fourth peripheral block 28, respectively. The actual positions of interconnect structures 104 and 106 can be adjusted according to design requirements and are not limited to... Figure 3 As shown. The conductive portions constituting interconnect structures 104 and 106 can be vias or metal lines, but are not limited thereto. The materials of each conductive portion can include metallic conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metals, but are not limited thereto.

[0031] Please refer to Figure 4 The diagram shows a cross-sectional view of a memory structure according to an embodiment of the present invention. The memory cell is composed of a transistor and a capacitor (1T1C). The transistor controls the charging and discharging of the capacitor to achieve the purpose of storing data. It is worth noting that... Figure 4 The transistors in the memory cells have a vertical channel structure, with two control terminals controlled by the bit line and word line respectively, allowing for easy integration. Figure 2 and Figure 3 The layout design shown achieves a memory structure with a high cell ratio.

[0032] like Figure 4 As shown, the memory structure includes a substrate L0, a first element layer L1 disposed on the substrate L0, and a second element layer L2 disposed between the substrate L0 and the first element layer L1. The first element layer L1 includes a plurality of memory cells MC, and bit lines BL and word lines WL controlling the memory cells MC. Specifically, each memory cell MC includes a source structure 204, a channel structure 210 located on the source structure 204, a gate structure 208 located on the sidewall of the channel structure 210, a gate dielectric layer 212 located between the gate structure 208 and the channel structure 210, a drain structure 214 located on the channel structure 210, and a capacitor structure SN located on the drain structure 214 as a storage node. In some embodiments, to ensure smooth connection of the bit line BL circuit, the first element layer L1 may also include a conductive structure, such as a conductive structure 201. In some embodiments, the memory cell MC may further include a contact structure 202 for electrically connecting the source structure 204 and the bit line BL (or conductive structure 201), and a contact structure 206 for electrically connecting the source structure 204 and the channel structure 210.

[0033] Source structure 204, drain structure 214, gate structure 208, contact structure 202, and contact structure 206 all include conductive materials, such as metallic conductive materials, non-metallic conductive materials, or combinations thereof. Suitable metallic conductive materials may be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers including the aforementioned metals, but are not limited thereto. Suitable non-metallic conductive materials may be amorphous silicon, polysilicon, or doped silicon, but are not limited thereto.

[0034] The channel structure 210 is vertically disposed between the source structure 204 and the drain structure 214, with its bottom end electrically connected to the source structure 204 via a contact structure 206, and its top end directly electrically connected to the drain structure 214. In some embodiments, the channel structure 210 may include a dielectric core 210b and a semiconductor layer 210a located between the sidewalls of the dielectric core 210b and the gate dielectric layer 212. The dielectric core 210b includes a dielectric material, such as silicon oxide (SiO2) or silicon nitride (SiN), but is not limited thereto. The semiconductor layer 210a includes a semiconductor material, such as silicon, polysilicon, or metal oxide semiconductor, but is not limited thereto.

[0035] The gate dielectric layer 212 may be composed of a single layer or multiple layers of dielectric material. Suitable dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium oxynitride (HfSiON), aluminum oxide (AlO), zinc oxide (ZrO2), titanium oxide (TiO2), and other metal oxide dielectrics, or combinations of the above materials, but are not limited thereto.

[0036] The capacitor structure SN includes a bottom electrode vertically erected on the drain structure 214, a capacitor dielectric layer covering the surface of the bottom electrode, and a top electrode located on the capacitor dielectric layer and capacitively coupled to the bottom electrode through the capacitor dielectric layer. The bottom electrode and top electrode each comprise a conductive material, such as a metallic conductive material. Suitable metals include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metallic materials, but are not limited thereto. In some embodiments, the top electrode may comprise a semiconductor material, such as polysilicon. The capacitor dielectric layer comprises a dielectric material, such as, but not limited to, the material selected from the aforementioned materials suitable for the gate dielectric layer 208.

[0037] Bit line BL is located below source structure 204 and is electrically connected to source structure 204 via contact structure 202. In some embodiments, bit line BL may be integrally formed with conductive structure 201 in the same layer and include the same material (e.g., the aforementioned applicable metallic conductive material). Bit line BL is electrically connected to conductive structure 102 in the second element layer via interconnect structure 104, wherein conductive structure 102 may be part of first peripheral block 22 or second peripheral block 24.

[0038] The word line WL is located between the source structure 204 and the drain structure 214. In some embodiments, the word line WL and the gate structure 208 may be in the same layer and integrally formed, including the same material (e.g., the aforementioned applicable metallic conductive material), and the word line WL overlaps a portion of the channel structure 210, which is the gate structure 208. The word line WL is electrically connected to the conductive structure of the third peripheral block 26 or the fourth peripheral block 28 in the second element layer through the interconnect structure 106.

[0039] In some embodiments, the bit line BL (conductive structure 201) is made of a first metal layer M1, the contact structure 202 is made of a second metal layer M2, the source structure 204 is made of a third metal layer M3, the gate structure 208 and the word line WL are made of a fourth metal layer M4, and the drain structure 214 is made of a fifth metal layer M5. The first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, and the fifth metal layer M5 are sequentially disposed in the first element layer L1 from bottom (closer to substrate L0) to top (away from substrate L0). The first element layer L1 also includes an interlayer dielectric layer, such as a silicon oxide (SiO2) or silicon nitride (SiN) layer, between the aforementioned metal layers and the elements of the memory structure.

[0040] Please refer to Figure 5 and Figure 6 . Figure 5 This is a schematic diagram of the layout of a memory structure according to an embodiment of the present invention, which includes a plurality of memory blocks disposed in a first element layer L1 and a plurality of peripheral blocks disposed in a second element layer L2. Figure 5 and Figure 6 and Figure 2 and Figure 3 The difference in the illustrated embodiment is that, Figure 5 and Figure 6 The layout design can be applied to memory cells (MCs) in memory structures, such as... Figure 7 As shown, this involves four control terminals, requiring two bit lines (BL) and two word lines (WL) to control their operation.

[0041] like Figure 5 and Figure 6 As shown, storage blocks 10 are arranged in rows along the X direction and in columns along the Y direction. Peripheral blocks 20 include a first peripheral block 22, a second peripheral block 24, a third low-voltage peripheral block 26LV, a third high-voltage peripheral block 26HV, a fourth low-voltage peripheral block 28LV, and a fourth high-voltage peripheral block 28HV. In some embodiments, the first peripheral block 22 and the second peripheral block 24 respectively include peripheral circuitry controlling the bit line BL, such as a row decoder and a sense amplifier. The third low-voltage peripheral block 26LV, the third high-voltage peripheral block 26HV, the fourth low-voltage peripheral block 28LV, and the fourth high-voltage peripheral block 28HV respectively include peripheral circuitry controlling the word line WL, such as a column decoder. The arrangement of the first peripheral block 22 and the second peripheral block 24 in this embodiment is... Figure 2The configuration is the same in the illustrated embodiment, with storage blocks 10 arranged alternately below each row along the X direction and partially overlapping with two adjacent storage blocks 10 in the vertical direction (i.e., the Z direction). The third low-voltage peripheral block 26LV, the third high-voltage peripheral block 26HV, the fourth low-voltage peripheral block 28LV, and the fourth high-voltage peripheral block 28HV are each arranged in a row along the X direction and arranged in pairs along the Y direction between the rows of storage blocks 10, adjacent to the upper or lower edge of the storage blocks 10, without overlapping the storage blocks 10.

[0042] In this embodiment, the bit line BL and word line WL are respectively divided into read bit line rBL, write bit line wBL, read word line rWL, and write word line wWL. The read bit line rBL and write bit line wBL extend along the X direction and are arranged parallel to each other along the Y direction. The read word line rWL and write word line wWL extend along the Y direction and are arranged parallel to each other along the X direction. It should be noted that, for the sake of simplicity, in... Figure 6 In a memory cell (MC), the read bit line (rBL) and write bit line (wBL) controlling the same memory cell (MC) are represented by the same straight line, as are the read word line (rWL) and write word line (wWL) controlling the same memory cell (MC). The intersection of these two lines roughly indicates the location of the memory cell (MC).

[0043] like Figure 6 As shown, the odd-numbered row bit lines BLa (including the odd-numbered row read bit line rBL and write bit line wBL) are controlled by the first peripheral block 22, and the even-numbered row bit lines BLb (including the even-numbered row read bit line rBL and write bit line wBL) are controlled by the second peripheral block 24. The first peripheral block 22 simultaneously controls the odd-numbered row bit lines BLa of the two adjacent memory blocks 10 that overlap with it, and the second peripheral block 24 simultaneously controls the even-numbered row bit lines BLb of the two adjacent memory blocks 10 that overlap with it. The third low-voltage peripheral block 26LV, the third high-voltage peripheral block 26HV, the fourth low-voltage peripheral block 28LV, and the fourth high-voltage peripheral block 28HV are each arranged in rows along the X direction and arranged in pairs along the Y direction between the rows of memory blocks 10, adjacent to the upper or lower edge of memory blocks 10, and do not overlap memory blocks 10. It is worth noting that the third low-voltage peripheral block 26LV and the fourth low-voltage peripheral block 28LV control the lower voltage word lines WL (e.g., Figure 7 The word line rWL is read from the third high-voltage peripheral block 26HV and the fourth high-voltage peripheral block 28HV, which control the higher voltage word line WL (e.g., ...). Figure 7 The write line (wWL) is used for writing. For ease of understanding, Figure 6The third interconnect structure 506 and the fourth interconnect structure 508, schematically marked on the same straight line, represent the feature of electrically connecting the set of odd-row read bit lines rBL and write bit lines wBL or even-row read bit lines rBL and write bit lines wBL to the first peripheral block 22 or the second peripheral block 24. Similarly, the eighth interconnect structure 516 and the tenth interconnect structure 520, marked on the same straight line, represent the feature of electrically connecting the set of odd-row read word lines rWL and write word lines wWL or even-row read word lines rWL and write word lines wWL to the third low-voltage peripheral block 26LV, the third high-voltage peripheral block 26HV, the fourth low-voltage peripheral block 28LV, or the fourth high-voltage peripheral block 28HV. The actual positions of interconnect structures 506, 508, 516, and 520 can be adjusted according to design requirements and are not limited to... Figure 6 As shown, as long as the read bit line rBL, write bit line wBL, read word line rWL, and write word line wWL can be successfully electrically connected to the corresponding peripheral blocks, it is acceptable.

[0044] Please refer to Figure 7 The diagram shows a cross-sectional view of a memory structure according to an embodiment of the present invention. The memory cell is composed of two vertically stacked vertical channel transistors, and the parasitic capacitance between the two transistors is the memory node of the memory cell. Figure 7 The storage unit includes four control terminals, requiring two bit lines and two word lines for control. Figure 7 The structure can be combined Figure 5 and Figure 6 The layout design is used to achieve a high cell ratio in memory structures.

[0045] like Figure 7As shown, the first element layer L1 of the memory structure includes multiple memory cells MC, each consisting of a read transistor Tr and a write transistor Tw stacked on top of the read transistor Tr. Specifically, the read transistor Tr includes a first gate structure 308, a first channel layer 304 disposed along the sidewalls and bottom surface of the first gate structure 308, a first gate dielectric layer 306 located between the first gate structure 308 and the first channel layer 304, a first drain structure 310 directly contacting the first channel layer 304 located on the upper sidewall of the first gate structure 308, and a first source structure 302 directly contacting the first channel layer 304 located on the lower sidewall of the first gate structure. The write transistor Tw includes a second gate structure 408, a second channel layer 404 disposed along the sidewall and bottom surface of the second gate structure 408, a second gate dielectric layer 406 disposed between the second gate structure 408 and the second channel layer 404, a second drain structure 410 directly contacting the second channel layer 404 located on the upper sidewall of the second gate structure 408, and a second source structure 402 directly contacting the second channel layer 404 located on the lower sidewall of the second gate structure.

[0046] like Figure 7 As shown, the first gate structure 308 of the read transistor Tr and the second source structure 402 of the write transistor Tw are electrically connected, and can also be integrally formed. The first drain structure 310 is electrically connected to the read word line rWL, and can also be integrally formed. The first source structure 302 is electrically connected to the read bit line rBL, and can also be integrally formed. The second drain structure 410 is electrically connected to the write bit line wBL, and can also be integrally formed. The second gate structure 408 is electrically connected to the write word line wWL, and can also be integrally formed. The capacitor structure SN formed by the second source structure 402 is the storage node of the storage cell MC.

[0047] The first gate structure 308, the first drain structure 310, the first source structure 302, the second gate structure 408, the second drain structure 410, and the second source structure 402 each comprise a conductive material, such as a metallic conductive material, a non-metallic conductive material, or a combination thereof. Suitable metallic conductive materials may be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metals, but are not limited thereto. Suitable non-metallic conductive materials may be amorphous silicon, polycrystalline silicon, or doped silicon, but are not limited thereto. The first channel layer 304 and the second channel layer 404 comprise semiconductor materials, such as silicon, polycrystalline silicon, or metal oxide semiconductors, but are not limited thereto. The first gate dielectric layer 306 and the second gate dielectric layer 406 may be composed of a single layer or multiple layers of dielectric material. Applicable dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium oxynitride (HfSiON), aluminum oxide (AlO), zinc oxide (ZrO2), titanium oxide (TiO2), and other metal oxide dielectrics, or combinations of the above materials, but are not limited thereto.

[0048] In some embodiments, the first source structure 302 and the read bit line rBL are made of a first metal layer M1, the first drain structure 310 and the read word line rWL are made of a second metal layer M2, the second source structure 402 is made of a third metal layer M3, the second drain structure 410 and the write bit line BL are made of a fourth metal layer M4, and the write word line WL is made of a fifth metal layer M5. The first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, and the fifth metal layer M5 are sequentially disposed in the first element layer L1 from bottom (closer to substrate L0) to top (away from substrate L0). The first element layer L1 also includes an interlayer dielectric layer, such as a silicon oxide (SiO2) or silicon nitride (SiN) layer, between the aforementioned metal layers and the elements of the memory structure.

[0049] Please refer to Figure 8 and Figure 9 These are cross-sectional schematic diagrams of a memory structure according to an embodiment of the present invention. Figure 8 and Figure 9 As shown, the memory structure includes a substrate (not shown), a second element layer L2, and a first element layer L1 sequentially disposed on the substrate. The second element layer L2 includes multiple conductive structures 102, which can be respectively as follows: Figure 6The diagram shows a portion of the first peripheral block 22, the second peripheral block 24, the third low-voltage peripheral block 26LV, the third high-voltage peripheral block 26HV, the fourth low-voltage peripheral block 28LV, and the fourth high-voltage peripheral block 28HV. The first component layer L1 includes, as shown... Figure 7 The storage cell MC shown, along with the read bit line rBL, write bit line wBL, read word line rWL, and write word line wWL controlling the storage cell, are electrically connected to corresponding peripheral blocks in the second element layer L2 via multiple interconnect structures disposed in and on the first element layer L1. For example, as... Figure 8 and Figure 9 As shown, the write bit line wBL is electrically connected to the conductive structure 102 (belonging to the first peripheral block 22 or the second peripheral block 24) through the first interconnect structure 502 on the first element layer L1 and the second interconnect structure 504 and the third interconnect structure 506 in the first element layer L1. The read bit line rBL is electrically connected to the conductive structure 102 (belonging to the first peripheral block 22 or the second peripheral block 24) through the fourth interconnect structure 508 in the first element layer L1. The read word line rWL is electrically connected to the conductive structure 102 of the third low-voltage peripheral block 26LV or the fourth low-voltage peripheral block 28LV through the tenth interconnect structure 520 on the first element layer L1 and the seventh interconnect structure 514 and the eighth interconnect structure 516 in the first element layer L1. The write word line wWL is electrically connected to the conductive structure 102 of the third high voltage peripheral block 26HV or the fourth high voltage peripheral block 28HV through the sixth interconnect structure 512 on the first element layer L1 and the ninth interconnect structure 518 and the tenth interconnect structure 520 in the first element layer L1.

[0050] The first interconnect structure 502, the second interconnect structure 504, the third interconnect structure 506, the fourth interconnect structure 508, the fifth interconnect structure 510, the sixth interconnect structure 512, the seventh interconnect structure 514, the eighth interconnect structure 516, the ninth interconnect structure 518, and the tenth interconnect structure 520 may each include a single conductive portion or be composed of multiple conductive portions. For example, as Figure 8 and Figure 9 As shown, the third interconnect structure 506 can be composed of three conductive portions 506a, 506b, and 506c; the eighth interconnect structure 516 can be composed of three conductive portions 516a, 516b, and 516c; and the tenth interconnect structure 52 can be composed of three conductive portions 520a, 520b, and 520c. Each conductive portion can be a via or a metal line structure, but is not limited thereto. The material of each conductive portion can include metallic conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metals, but is not limited thereto.

[0051] In summary, the memory structures and layouts provided by the various embodiments of the present invention place the memory blocks and peripheral blocks on different structural layers. Therefore, the peripheral blocks do not occupy the area between the memory blocks, effectively improving the cell ratio and achieving higher storage capacity within a limited wafer area. The vertical overlap design of the memory blocks and peripheral blocks in the present invention improves the flexibility of layout design, shortens wiring distance, and reduces power loss.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memory structure, characterized in that, include: Substrate; A first element layer is disposed on the substrate; Multiple storage blocks are located in the first element layer; Multiple word lines and bit lines are set in the first element layer to control the storage cells of the storage block; A second element layer is disposed between the substrate and the first element layer; as well as The first peripheral block and the second peripheral block are located in the second element layer, wherein in the vertical direction, the first peripheral block and the second peripheral block partially overlap with two adjacent memory blocks respectively; The bit lines in the odd-numbered rows are electrically connected to the first peripheral block, and the bit lines in the even-numbered rows are electrically connected to the second peripheral block. Both the first peripheral block and the second peripheral block include a line decoder and a sensing amplifier.

2. The memory structure as described in claim 1, characterized in that, Also includes: The third peripheral block and the fourth peripheral block are located in the second element layer. The third peripheral block is adjacent to either the upper edge or the lower edge of the storage block, and the fourth peripheral block is adjacent to either the upper edge or the lower edge of the storage block. The word lines in the odd-numbered columns are electrically connected to the third peripheral block, and the word lines in the even-numbered columns are electrically connected to the fourth peripheral block.

3. The memory structure as described in claim 2, characterized in that, In the vertical direction, the third peripheral block and the fourth peripheral block do not overlap with the storage block.

4. The memory structure as described in claim 2, characterized in that, Both the third and fourth peripheral blocks include column decoders.

5. The memory structure as described in claim 1, characterized in that, The storage unit includes: Source structure; A channel structure is located on the source structure; A gate structure is located on the sidewall of the channel structure and is electrically connected to the word line; A gate dielectric layer is located between the gate structure and the channel structure; A drain structure is located on the channel structure; A capacitor structure is located on the drain structure; and A contact structure, located below the source structure, electrically connects the source structure to the bit line.

6. The memory structure as described in claim 5, characterized in that, The channel structure includes a dielectric core and a semiconductor layer, wherein the semiconductor layer is located between the gate dielectric layer and the sidewall of the dielectric core.

7. The memory structure as described in claim 5, characterized in that, The bit line is made of a first metal layer, the contact structure is made of a second metal layer, the source structure is made of a third metal layer, the gate structure and word line are made of a fourth metal layer, and the drain structure is made of a fifth metal layer. The first metal layer, the second metal layer, the third metal layer, the fourth metal layer and the fifth metal layer are arranged sequentially from bottom to top in the first element layer.

8. The memory structure as described in claim 1, characterized in that, The storage unit includes: Reading transistors, including: First gate structure; The first channel layer covers the sidewalls and bottom surface of the first gate structure; A first gate dielectric layer is located between the first gate structure and the first channel layer; The first drain structure directly contacts the first channel layer covering the upper part of the first gate structure; and The first source structure directly contacts the first channel layer covering the lower part of the first gate structure; and The write transistor, disposed on the read transistor, includes: Second gate structure; The second channel layer covers the sidewalls and bottom surface of the second gate structure; The second gate dielectric layer is located between the second gate structure and the second channel layer; The second drain structure directly contacts the second channel layer covering the upper part of the second gate structure; and The second source structure is located between the first gate structure and the second gate structure, directly contacting the top surface of the first gate structure and covering the lower part of the second channel layer of the second gate structure.

9. The memory structure as described in claim 8, characterized in that, The word lines include read word lines and write word lines, and the bit lines include read bit lines and write bit lines. The read word lines are electrically connected to the first drain structure, the read bit lines are electrically connected to the first source structure, the write word lines are electrically connected to the second gate structure, and the write bit lines are electrically connected to the second drain structure.

10. The memory structure as described in claim 9, characterized in that, The first source structure and the read bit line are made of a first metal layer, the first drain structure and the read word line are made of a second metal layer, the second source structure is made of a third metal layer, the second drain structure and the write bit line are made of a fourth metal layer, and the write word line is made of a fifth metal layer. The first metal layer, the second metal layer, the third metal layer, the fourth metal layer and the fifth metal layer are disposed in the first element layer from bottom to top.

11. The memory structure as described in claim 9, characterized in that, Also includes: A first interconnect structure is located on the first element layer; as well as The second interconnect structure, the third interconnect structure, and the fourth interconnect structure are located in the first element layer, wherein the second interconnect structure is electrically connected to the write bit line and the first interconnect structure, the third interconnect structure is electrically connected to the first interconnect structure and one of the first peripheral block and the second peripheral block, and the fourth interconnect structure is electrically connected to the read bit line and one of the first peripheral block and the second peripheral block.

12. The memory structure as described in claim 9, characterized in that, Also includes: The third low-voltage peripheral block and the fourth high-voltage peripheral block are located in the second element layer. The third low-voltage peripheral block is adjacent to one of the upper edge or the lower edge of the storage block, and the fourth high-voltage peripheral block is adjacent to the other of the upper edge or the lower edge of the storage block. as well as The third high-voltage peripheral block and the fourth low-voltage peripheral block are located in the second element layer. The third high-voltage peripheral block is adjacent to the third low-voltage peripheral block, and the fourth low-voltage peripheral block is adjacent to the fourth high-voltage peripheral block. The write word lines and read word lines of the even-numbered columns of each memory block are electrically connected to the third high-voltage peripheral block and the fourth low-voltage peripheral block, respectively, and the write word lines and read word lines of the odd-numbered columns are electrically connected to the third low-voltage peripheral block and the fourth high-voltage peripheral block, respectively.

13. The memory structure as described in claim 12, characterized in that, Also includes: The fifth and sixth interconnect structures are located on the first element layer; as well as The seventh interconnect structure, the eighth interconnect structure, the ninth interconnect structure, and the tenth interconnect structure are located in the first element layer, wherein the seventh interconnect structure electrically connects the read word line to the fifth interconnect structure, the eighth interconnect structure electrically connects the fifth interconnect structure to the third low-voltage peripheral block or the fourth low-voltage peripheral block, the ninth interconnect structure electrically connects the write word line to the sixth interconnect structure, and the tenth interconnect structure electrically connects the sixth interconnect structure to the third high-voltage peripheral block or the fourth high-voltage peripheral block.

14. The memory structure as described in claim 12, characterized in that, The third low-voltage peripheral block, the fourth high-voltage peripheral block, the third high-voltage peripheral block, and the fourth low-voltage peripheral block all include column decoders.

15. The memory structure as described in claim 1, characterized in that, The overlapping area between the storage block and the first surrounding block is equal to the overlapping area between the storage block and the second surrounding block.

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