Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a first fan-out wire and a second fan-out wire; a first test circuit is located in a binding area and comprises a first transistor; a second test circuit is located outside the binding area and comprises a second transistor; an input end of the first transistor is electrically connected to a test terminal through a first test wire, and an input end of the second transistor is electrically connected to the test terminal through a second test wire; a first fan-out section extends between a connection position of the first transistor and a display area, and a second fan-out section extends between a connection position of the second transistor and the display area; the impedance of the first fan-out section is greater than the impedance of the second fan-out section; and the display panel satisfies at least one of the following conditions: the channel width-length ratio of the first transistor is greater than the channel width-length ratio of the second transistor, and the impedance of the first test wire is less than the impedance of the second test wire. According to the embodiments of the application, the test split-screen problem can be improved, and the accuracy of the test result can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous updating of display panel technology, the screen ratio of the display panel is continuously improved, and the lower border of the display panel is also getting smaller and smaller.

[0003] However, there are many wirings in the display panel, and the wiring lengths of the wirings at different positions in the lower border are different, which leads to uneven load and thus uneven display. SUMMARY

[0004] The display panel and the display device provided by the embodiments of the present application are beneficial to reduce the display brightness difference of different areas during testing, thereby improving the test split screen problem and improving the accuracy of the test result.

[0005] In a first aspect, the embodiments of the present application provide a display panel having a display area and a non-display area at least partially surrounding the display area, the non-display area including a binding area, the display panel comprising: a fan-out line including a first fan-out wiring and a second fan-out wiring; a first test circuit located in the binding area and including a first transistor, an output end of the first transistor being electrically connected to the first fan-out wiring; a second test circuit located outside the binding area and including a second transistor, an output end of the second transistor being electrically connected to the second fan-out wiring; a test terminal, an input end of the first transistor being electrically connected to the test terminal through a first test wiring, and an input end of the second transistor being electrically connected to the test terminal through a second test wiring; the first fan-out wiring includes a first fan-out segment, the first fan-out segment extending between the connection with the first transistor and the display area, the second fan-out wiring includes a second fan-out segment, the second fan-out segment extending between the connection with the second transistor and the display area, and the impedance of the first fan-out segment is greater than the impedance of the second fan-out segment; the display panel satisfies at least one of the following: the channel width-length ratio of the first transistor is greater than the channel width-length ratio of the second transistor, and the impedance of the first test wiring is less than the impedance of the second test wiring.

[0006] Based on the same inventive concept, in a second aspect, the embodiments of the present application provide a display device comprising the display panel as described in the first aspect.

[0007] According to the display panel and the display device provided in the embodiments of the present application, since the impedance of the first fan-out section is greater than the impedance of the second fan-out section, further, the channel width-length ratio of the first transistor is greater than the channel width-length ratio of the second transistor, and / or the impedance of the first test trace is less than the impedance of the second test trace, the difference between the test signals transmitted to the display area corresponding to the second fan-out trace and the test signals transmitted to the display area corresponding to the first fan-out trace can be reduced, which is beneficial to reducing the display brightness difference of different areas during testing, thereby improving the test split-screen problem and improving the accuracy of the test result. BRIEF DESCRIPTION OF DRAWINGS

[0008] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings, in which like references denote like features, and in which:

[0009] Figure 1 FIG. 1 shows a structure schematic diagram of a local area of a display panel in the related art;

[0010] Figure 2 FIG. 2 shows a structure schematic diagram of a local area of a display panel provided in an embodiment of the present application;

[0011] Figure 3 FIG. 3 shows a structure schematic diagram of a test circuit in a display panel provided in an embodiment of the present application;

[0012] Figure 4 FIG. 4 shows a simulation schematic diagram of a display panel provided in an embodiment of the present application;

[0013] Figure 5 FIG. 5 shows another structure schematic diagram of a local area of a display panel provided in an embodiment of the present application;

[0014] Figure 6 FIG. 6 shows still another structure schematic diagram of a local area of a display panel provided in an embodiment of the present application;

[0015] Figure 7 FIG. 7 shows still another structure schematic diagram of a local area of a display panel provided in an embodiment of the present application;

[0016] Figure 8 FIG. 8 shows a cross-sectional structure schematic diagram of a display panel provided in an embodiment of the present application;

[0017] Figure 9 FIG. 9 shows a structure schematic diagram of an electrostatic protection circuit in a display panel provided in an embodiment of the present application;

[0018] Figure 10 FIG. 10 shows a structure schematic diagram of a display device provided in an embodiment of the present application.

[0019] BRIEF DESCRIPTION OF DRAWINGS

[0020] 100 - display panel;

[0021] 10 - fan-out line;

[0022] 11 - first fan-out line; 111 - first fan-out segment; 1111 - first fan-out subsection; 1112 - second fan-out subsection; h1 - first via;

[0023] 12 - second fan-out line; 121 - second fan-out segment; 1213 - third fan-out subsection; 1214 - fourth fan-out subsection; h2 - second via;

[0024] 122 - connection segment; 1221 - first connection segment; 1222 - second connection segment; 1223 - third connection segment;

[0025] 21 - first test circuit; 22 - second test circuit;

[0026] 30 - test terminal; 31 - first test terminal; 32 - second test terminal;

[0027] 41 - first test line;

[0028] 42 - second test line; 421 - first test segment; 422 - second test segment;

[0029] 50 - binding terminal; 51 - first binding terminal; 52 - second binding terminal;

[0030] 61 - first data line; 62 - second data line;

[0031] 71 - first electrostatic protection circuit; 72 - second electrostatic protection circuit;

[0032] 80 - gating circuit;

[0033] 91 - pixel electrode; 92 - common electrode; 93 - pixel circuit;

[0034] 1000 - display device. DETAILED DESCRIPTION

[0035] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0037] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0038] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0039] It should be noted that when a component is described as "connected" or "electrically connected" to another component, it can be directly connected to the other component, or there may be one or more intermediate components in between.

[0040] Various modifications and changes can be made to the application as disclosed in the specification without departing from the spirit and scope of the application. It is intended that the application cover all such modifications and changes as fall within the scope of the corresponding claims (technical solutions claimed in the patent) and their equivalents. It should be explained that the implementation manners provided in the embodiments of the application can be combined with each other without contradiction.

[0041] Before the technical solutions provided by the embodiments of the application are described, the problems existing in the related art are first described in detail in order to facilitate the understanding of the embodiments of the application.

[0042] As shown in Figure 1 The non-display area NA of the display panel can include a binding area BA, and the binding area BA can be used to bind a driving chip. In order to realize a narrow frame, the first part of the fan-out wire 1 can be connected to the output pin of the driving chip on the side close to the display area AA, and the second part of the fan-out wire 2 can be connected to the output pin of the driving chip on the side away from the display area AA. The test circuit 3 connected to the first part of the fan-out wire 1 can be located in the binding area BA, and the test circuit 4 connected to the second part of the fan-out wire 2 can be moved out of the binding area BA. The second part of the fan-out wire 2 includes a first segment 201 and a second segment 202, the first segment 201 extends between the test circuit 4 and the display area AA, and the second segment 202 extends between the test circuit 4 and the driving chip.

[0043] The first part of the fan-out wire 1 can be used to provide a driving signal to the middle display area AA1, and the second part of the fan-out wire 2 can be used to provide a driving signal to the edge display area AA2.

[0044] The inventors have found that in order to ensure the display effect when the driving chip is driven, the impedance of the second part of the fan-out wire 2 and the first part of the fan-out wire 1 can be uniformly transitioned. Since the length of the first segment 201 of the second part of the fan-out wire 2 is less than the length of the first part of the fan-out wire 1, when testing (for example, VT testing before the display panel binds the driving chip), the impedance of the first segment 201 is too small, which causes the display brightness of the edge display area AA2 to be different from the display brightness of the middle display area AA1, for example, the brightness of the edge display area AA2 is brighter than the brightness of the middle display area AA1 under a 127 gray scale picture, forming a split screen, thereby affecting the test result.

[0045] To solve the above problems, the embodiments of the application provide a display panel and a display device, which will be described below in conjunction with the accompanying drawings.

[0046] The display panel provided by the embodiment of the present application can be an organic light emitting diode (OLED) display panel, and of course can also be other types of display panels, which are not limited by the present application.

[0047] As shown in Figure 2 , the display panel 100 can have a display area AA and a non-display area NA at least partially surrounding the display area AA, and the non-display area NA can include a binding area BA.

[0048] The display panel can include a fan-out line 10, a first test circuit 21, a second test circuit 22, and a test terminal 30.

[0049] For example, the fan-out line 10 can include a first fan-out wire 11 and a second fan-out wire 12. The first fan-out wire 11 can be used to provide a driving signal to the middle display area AA1, and the second fan-out wire 12 can be used to provide a driving signal to the edge display area AA2.

[0050] The first test circuit 21 is located in the binding area BA. As shown in Figure 3 , the first test circuit 21 can include a first transistor T1, the output end of the first transistor T1 can be electrically connected to the first fan-out wire 11, and the input end of the first transistor T1 can be electrically connected to the test terminal 30 through a first test wire 41.

[0051] The second test circuit 22 can be located outside the binding area BA. The second test circuit 22 can include a second transistor T2, the output end of the second transistor T2 can be electrically connected to the second fan-out wire 12, and the input end of the second transistor T2 can be electrically connected to the test terminal 30 through a second test wire 42.

[0052] The test terminal 30 can be located outside the binding area BA.

[0053] The gate of the first transistor T1 and the gate of the second transistor T2 can be electrically connected to the same gate control line SW. The first transistor T1 and the second transistor T2 can both be P-type transistors, or the first transistor T1 and the second transistor T2 can both be N-type transistors.

[0054] The test terminal 30 can be used to provide a test signal to perform a VT test on the display panel.

[0055] The first fan-out wire 11 can include a first fan-out segment 111 extending between the connection with the first transistor T1 to the display area AA. The second fan-out wire 12 can include a second fan-out segment 121 extending between the connection with the second transistor T2 to the display area AA. The impedance of the first fan-out segment 111 is greater than the impedance of the second fan-out segment 121.

[0056] For example, the length of the binding area BA in the first direction X is less than the length of the display area AA in the first direction X. The first transistor T1 of the first test circuit 21 is located in the binding area BA, and the second transistor T2 of the second test circuit 22 is located outside the binding area BA, for example, the second test circuit 22 is located on one side or both sides of the binding area BA in the first direction X. For example, the distance between the second transistor T2 and the second display area AA2 can be set to be closer, and the distance between the first transistor T1 and the first display area AA1 is relatively far, so that the length of the wire of the first fan-out segment 111 is greater than the length of the wire of the second fan-out segment 121, so that the impedance of the first fan-out segment 111 is greater than the impedance of the second fan-out segment 121.

[0057] For example, the plurality of second fan-out segments 121 and the plurality of first fan-out segments 111 can be arranged in the first direction X, the plurality of first fan-out segments 111 can be arranged in the middle region, and the plurality of second fan-out segments 121 can be arranged in the edge region. The length of the wire of the first fan-out segment 111 can be greater than the length of the wire of the second fan-out segment 121.

[0058] The display panel can satisfy at least one of the following: the channel width-length ratio of the first transistor T1 is greater than the channel width-length ratio of the second transistor T2, and the impedance of the first test wire 41 is less than the impedance of the second test wire 42.

[0059] During testing, a test signal can be provided to the display area of the display panel through the test terminal 30, and the test signal is transmitted to the first data line 61 of the middle display area AA1 through the first test wire 41, the first transistor T1 and the first fan-out segment 111, and another test signal is transmitted to the second data line 62 of the edge display area AA2 through the second test wire 42, the second transistor T2 and the second fan-out segment 121.

[0060] The greater the channel width-length ratio of the transistor, the more sufficient the charging of the data line, and vice versa. The greater the impedance of the test wire, the less sufficient the charging of the data line, and vice versa.

[0061] In the embodiments of the present application, since the impedance of the first fan-out segment 111 is greater than the impedance of the second fan-out segment 121, further, the channel width-length ratio of the first transistor T1 is greater than the channel width-length ratio of the second transistor T2, and / or the impedance of the first test wire 41 is less than the impedance of the second test wire 42, thereby reducing the difference between the test signal transmitted to the display area corresponding to the second fan-out wire 12 and the test signal transmitted to the display area corresponding to the first fan-out wire 11, that is, reducing the difference between the test signal received by the first data line 61 and the test signal received by the second data line 62, which is beneficial to reduce the difference in display brightness in different areas during testing, thereby improving the test split screen problem and improving the accuracy of the test result.

[0062] For example, the test signal can be a voltage signal. As Figure 4 shown, Figure 4 the simulation data, Figure 4 the horizontal axis represents the channel width-length ratio of the transistor, and the vertical axis represents the voltage ratio of the data line of the edge display area to the middle display area during testing. VTSW40 / 4 represents that the channel width-length ratio of the first transistor T1 is 40 / 4, VTSW38 / 4, VTSW37 / 4, VTSW36 / 4, VTSW35 / 4 represent that the channel width-length ratio of the second transistor T2 is 38 / 4, 37 / 4, 36 / 4, 35 / 4 respectively, and the corresponding channel width-length ratio of the first transistor T1 is 40 / 4 at this time. It can be seen that the channel width-length ratio of the first transistor T1 is greater than the channel width-length ratio of the second transistor T2, and the voltage received by the data line of the edge display area during testing will be reduced, thereby the difference between the test voltage transmitted to the display area corresponding to the second fan-out wire 12 and the test voltage transmitted to the display area corresponding to the first fan-out wire 11, that is, the difference between the test signal transmitted to the first data line 61 and the test signal transmitted to the second data line 62, can be reduced. The optimal channel width-length ratio of the second transistor T2 can be determined through simulation to minimize the difference in the voltage ratio of the data line of the edge display area to the middle display area.

[0063] It should be noted that, Figure 4 the simulation data shown is only an example and is not intended to limit the present application.

[0064] For example, the display area of the display panel can include a plurality of data lines arranged along the first direction X (not shown in the figure). As Figure 3 shown, the test terminal 30 can include a first test terminal 31 and a second test terminal 32, the first test terminal 31 can be used to provide a test signal to the odd-numbered data lines, and the second test terminal 32 can be used to provide a test signal to the even-numbered data lines.

[0065] In some embodiments, as Figure 5 shown, the first fan-out segment 111 can include a first fan-out sub-segment 1111 and a second fan-out sub-segment 1112 connected to each other by a first via h1, the impedance per unit length in the first fan-out sub-segment 1111 is greater than the impedance per unit length in the second fan-out sub-segment 1112, and the wire length of the first fan-out sub-segment 1111 is equal to the wire length of the second fan-out sub-segment 1112. The first via h1 is located at about 1 / 2 of the wire length of the first fan-out segment 111.

[0066] It should be noted that the lengths of the two fan-out segments introduced in various embodiments of the present application are equal, and it is not required that the lengths of the two fan-out segments are absolutely equal, for example, there are design errors or manufacturing process errors, as long as the lengths of the two fan-out segments are equal within the error range. For example, the lengths of the two fan-out segments of the same fan-out segment are d1 and d2, and in the case of -10%≤(d1-d2) / d1≤10%, or in the case of -10%≤(d1-d2) / d2≤10%, the lengths of the two fan-out segments can be considered equal. For example, in the first direction X, and in the direction from the edge to the center, the absolute value of (d1-d2) / d1 can become larger and larger.

[0067] For example, the plurality of first fan-out segments 111 are arranged in a fan shape, and the plurality of first vias h1 can be arranged on an arc line.

[0068] It should be noted that the plurality of vias introduced herein are arranged on an arc line, which can be understood as a line passing through the plurality of vias being approximately an arc line, and it is not intended to limit the line passing through the plurality of vias to be an absolute arc line.

[0069] For example, the plurality of first vias h1 can be arranged on an arc line L1. For example, the plurality of first fan-out segments 111 are arranged along the first direction X, and the data lines of the display area extend along the second direction Y, and the extension direction of at least part of the arc segment of the arc line L1 can be the third direction Z. The first direction X, the second direction Y and the third direction Z intersect. The first direction X can be the row direction, the second direction Y can be the column direction, and the third direction Z can be the diagonal direction.

[0070] It can be understood that the first fan-out segment 1111 and the second fan-out segment 1112 are located in different metal film layers. In this way, the first fan-out segment 111 can occupy at least two metal film layers, which is beneficial to setting the spacing between two adjacent first fan-out segments 111 smaller while avoiding signal crosstalk, thereby also being beneficial to achieving narrow frame. On the other hand, the first fan-out segment 111 occupies at least two metal film layers, so that the two first fan-out segments 111 can be arranged in an overlapping manner, and the two first fan-out segments 111 are equivalent to occupying the space of only one fan-out segment, so that the lower frame space at the corresponding position can be saved, for example, the saved space can be used to arrange other devices, so that in the case of arranging relatively more wires and devices, the area of the lower frame occupied as a whole will be smaller, thereby achieving narrow frame.

[0071] In addition, the first fan-out segment 111 adopts a wire changing design, and the plurality of first vias h1 are approximately at 1 / 2 of the length of the first fan-out segment 111, which can make the impedance of the first fan-out segment 111 transition uniformly.

[0072] Exemplarily, in the first direction X, the first via h1 corresponding to the first fan-out segment 111 from the edge to the center is sequentially arranged as a first first via h1 to an nth first via h1, and the distance between the first first via h1 to the nth first via h1 and the display area AA in the second direction Y can gradually decrease.

[0073] Exemplarily, in the two adjacent first fan-out segments 111 in the top view, the first fan-out sub-segment 1111 of the first first fan-out segment 111 is adjacent to the second fan-out sub-segment 1112 of the second first fan-out segment 111, and the second fan-out sub-segment 1112 of the first first fan-out segment 111 is adjacent to the first fan-out sub-segment 1111 of the second first fan-out segment 111.

[0074] It should be noted that, in order to clearly distinguish the arrangement of the first fan-out sub-segment 1111 and the second fan-out sub-segment 1112 of different first fan-out segments 111, the first fan-out sub-segment 1111 is shown by a solid line and the second fan-out sub-segment 1112 is shown by a dashed line in the drawings of the present application.

[0075] In some embodiments, as shown in Figure 5 The second fan-out segment 121 can include a third fan-out sub-segment 1213 and a fourth fan-out sub-segment 1214 connected to each other by a second via h2, and the impedance per unit length in the third fan-out sub-segment 1213 is greater than the impedance per unit length in the fourth fan-out sub-segment 1214. The second test circuit 22 is located on one side of the display area AA in the second direction Y, and the distance between the second via h2 and the display area AA in the second direction Y is greater than the distance between the second via h2 and the second test circuit 22 in the second direction Y. That is, the second via h2 is close to the second test circuit 22.

[0076] The plurality of second fan-out segments 121 can be arranged in a fan shape, and the plurality of second vias h2 can be arranged on an arc line.

[0077] It should be noted that, in the drawings herein, only a part of the arc segment of the arc line L1 on which the plurality of first vias h1 are arranged and a part of the arc segment of the arc line L2 on which the plurality of second vias h2 are arranged are shown, and the length of the arc segment is relatively short, which is approximately a straight line in vision, but this does not limit the present application.

[0078] In the case that the second via h2 is close to the second test circuit 22, the plurality of second vias h2 and the plurality of first vias h1 can be arranged on the same arc line or different arc lines. Figure 5 In some embodiments, as shown in

[0079] It can be understood that the third fan-out segment 1213 and the fourth fan-out segment 1214 are located in different metal film layers. In this way, the second fan-out segment 121 can occupy at least two metal film layers, which is more conducive to realizing a narrow frame. In addition, the second fan-out segment 121 adopts a line-changing design, and the plurality of second vias h2 are arranged on the same arc line, so that the impedance of the second fan-out segment 121 can be uniformly transitioned.

[0080] For example, in the first direction X, the order of the second vias h2 corresponding to the second fan-out segment 121 from the edge to the center is the first second via h2 to the mth second via h2, and the distance of the first second via h2 to the mth second via h2 from the display area AA in the second direction Y can gradually decrease.

[0081] For example, in the two adjacent second fan-out segments 121, the third fan-out segment 1213 of the first second fan-out segment 121 is adjacent to the fourth fan-out segment 1214 of the second second fan-out segment 121, and the fourth fan-out segment 1214 of the first second fan-out segment 121 is adjacent to the third fan-out segment 1213 of the second second fan-out segment 121.

[0082] It should be noted that, in order to clearly distinguish the arrangement of the third fan-out segment 1213 and the fourth fan-out segment 1214 of different second fan-out segments 121, the third fan-out segment 1213 is shown by a solid line and the fourth fan-out segment 1214 is shown by a dashed line in the drawings of the present application.

[0083] In some embodiments, the channel width-length ratio of the first transistor T1 is greater than the channel width-length ratio of the second transistor T2, as shown in FIG. 1. Figure 5 As shown, the plurality of second vias h2 and the plurality of first vias h1 are arranged continuously. For example, the plurality of second vias h2 and the plurality of first vias h1 can be arranged on the same arc line.

[0084] In the two adjacent second fan-out segments 121, the channel width-length ratio of the second transistor T2 electrically connected to the second fan-out segment 121 with a longer wire length of the third fan-out segment 1213 is greater than the channel width-length ratio of the second transistor T2 electrically connected to the second fan-out segment 121 with a shorter wire length of the third fan-out segment 1213.

[0085] In the embodiments of the present application, the positions of the wire changing holes of the second fan-out section 121 are arranged in a consistent gradient with the positions of the wire changing holes of the first fan-out section 111, which is beneficial to simplify the complexity of drawing in the design stage of the display panel. In addition, since the impedance per unit length in the third fan-out subsection 1213 is greater than the impedance per unit length in the fourth fan-out subsection 1214, the longer the wire length of the third fan-out subsection 1213, the greater the impedance of the second fan-out section 121 as a whole. The channel width-length ratio of the second transistor T2 electrically connected to the second fan-out section 121 with a longer wire length of the third fan-out subsection 1213 is greater, and the channel width-length ratio of the second transistor T2 electrically connected to the second fan-out section 121 with a shorter wire length of the third fan-out subsection 1213 is smaller. In this way, the difference between the test signals received by the data lines corresponding to different second fan-out sections 121 and the second transistors T2 connected thereto can be reduced.

[0086] In some embodiments, as shown in FIG. 1B, the wire length of the third fan-out subsection 1213 in the same second fan-out section 121 can be equal to the wire length of the fourth fan-out subsection 1214, and the channel width-length ratios of the second transistors T2 electrically connected to at least two adjacent second fan-out sections 121 can be equal. Figure 6

[0087] That is, the second via h2 corresponding to the second fan-out section 121 for wire changing can be located at about 1 / 2 of the wire length of the second fan-out section 121. In this way, the sizes of the second transistors T2 connected to the second fan-out sections 121 can adopt the same design, which is beneficial to reduce the simulation workload in the early stage.

[0088] As introduced above, in addition to differentiating the channel width-length ratios of the first transistors and the channel width-length ratios of the second transistors, the impedances of the first test wires and the impedances of the second test wires can also be differentiated.

[0089] In some embodiments, the impedance of the first test wire 41 is smaller than the impedance of the second test wire 42, as shown in FIG. 1B. The second test wire 42 can include a first test section 421 and a second test section 422 connected to each other, and the impedance per unit length in the first test section 421 is greater than the impedance per unit length in the second test section 422. Figure 3

[0090] In the embodiments of the present application, a resistance with a greater impedance is added to the input end of the second transistor T2. In this way, during testing, the voltage received by the data line electrically connected to the second fan-out section 121 can be reduced, thereby reducing the difference between the test signals transmitted to the display area corresponding to the second fan-out wire 12 and the test signals transmitted to the display area corresponding to the first fan-out wire 11, which is beneficial to reduce the difference in display brightness in different areas during testing, thereby improving the test split screen problem and improving the accuracy of the test results.

[0091] ​​For example, the material of the first test segment 421 can include a semiconductor. Since the impedance of the semiconductor material is large, this can avoid the first test segment 421 having a long wire length, and can help to reduce the frame while increasing the overall impedance of the first test wire 41.

[0092] It should be noted that, Figure 3 In order to clearly distinguish the first test segment 421 and the second test segment 422, the second test segment 422 is schematically shown, and the first test segment 421 is schematically shown by a dashed line.

[0093] For example, the material of the first test segment 421 can include polycrystalline silicon (poly).

[0094] For example, the first test segment 421 and the active layer of the second transistor T2 can be located in the same film layer. That is, the semiconductor material of the first test segment 421 and the semiconductor material of the active layer AL of the second transistor T2 can be the same, so that an additional film layer does not need to be added to arrange the first test segment 421.

[0095] For example, the second test wire 42 can include a plurality of second test segments 422, and the two ends of the first test segment 421 can be connected with the second test segments 422, respectively.

[0096] In some embodiments, referring to Figure 5 The first fan-out segment 111 can include a first fan-out sub-segment 1111 and a second fan-out sub-segment 1112 connected with each other by a first via h1, and the impedance per unit length in the first fan-out sub-segment 1111 is greater than the impedance per unit length in the second fan-out sub-segment 1112. The second fan-out segment 121 can include a third fan-out sub-segment 1213 and a fourth fan-out sub-segment 1214 connected with each other by a second via h2, and the impedance per unit length in the third fan-out sub-segment 1213 is greater than the impedance per unit length in the fourth fan-out sub-segment 1214. The plurality of second vias h2 and the plurality of first vias h1 can be arranged in series. For example, the plurality of second vias h2 and the plurality of first vias h1 can be arranged on the same arc line.

[0097] Among the two adjacent second fan-out segments 121, the impedance of the first test segment 421 electrically connected to the second fan-out segment 121 having a longer wire length of the third fan-out sub-segment 1213 is smaller than the impedance of the first test segment 421 electrically connected to the second fan-out segment 121 having a shorter wire length of the third fan-out sub-segment 1213.

[0098] In the embodiments of the present application, the positions of the wire changing holes of the second fan-out section 121 and the positions of the wire changing holes of the first fan-out section 111 are arranged in a consistent gradient, which is beneficial to simplify the complexity of drawing in the design stage of the display panel. In addition, since the impedance per unit length in the third fan-out subsection 1213 is greater than the impedance per unit length in the fourth fan-out subsection 1214, the longer the wire length of the third fan-out subsection 1213, the greater the impedance of the second fan-out section 121 as a whole. The impedance of the first test section 421 electrically connected to the second fan-out section 121 with a longer wire length of the third fan-out subsection 1213 is smaller, and the impedance of the first test section 421 electrically connected to the second fan-out section 121 with a shorter wire length of the third fan-out subsection 1213 is greater. In this way, the difference in the overall impedance of different second fan-out sections 121 and the first test sections 421 connected thereto can be reduced.

[0099] In some embodiments, referring to Figure 6 , the second fan-out section 121 can include a third fan-out subsection 1213 and a fourth fan-out subsection 1214 connected to each other by a second via h2. The impedance per unit length in the third fan-out subsection 1213 is greater than the impedance per unit length in the fourth fan-out subsection 1214. The wire length of the third fan-out subsection 1213 in the same second fan-out section 121 can be equal to the wire length of the fourth fan-out subsection 1214. The impedance of the first test section 421 electrically connected to at least two adjacent second fan-out sections 121 is equal.

[0100] That is, the second via h2 corresponding to the second fan-out section 121 for wire changing can be located at about 1 / 2 of the wire length of the second fan-out section 121. In this way, the size of the first test section 421 connected to the second fan-out section 121 can be designed in the same way, which can be beneficial to reduce the simulation workload in the early stage.

[0101] For example, as Figure 6 shown, a plurality of second vias h2 can be arranged on an arc line L2, and a plurality of first vias h1 can be arranged on an arc line L1. The arc line L2 and the arc line L1 are different arc lines. In this way, the simulation workload in the early stage can be reduced.

[0102] For example, the first fan-out subsection 1111 and the third fan-out subsection 1213 can be located in the same film layer and have the same material. In this way, the first fan-out subsection 1111 and the third fan-out subsection 1213 can be prepared at the same time, which is beneficial to reduce the process steps and reduce the cost.

[0103] The second fan-out subsection 1112 and the fourth fan-out subsection 1214 can be located in the same film layer and have the same material. Similarly, the second fan-out subsection 1112 and the fourth fan-out subsection 1214 can be prepared at the same time, which is beneficial to reduce the process steps and reduce the cost.

[0104] In some embodiments, as Figure 5or Figure 6 As shown, the display panel may also include a bonding terminal 50. The bonding terminal 50 is located in the bonding area BA. The bonding terminal 50 may include a plurality of first bonding terminals 51 and a plurality of second bonding terminals 52. The plurality of first bonding terminals 51 and the plurality of second bonding terminals 52 may be arranged in a first direction X, with the plurality of second bonding terminals 52 located near the edge and the plurality of first bonding terminals 51 located near the center.

[0105] The first bonding terminal 51 is electrically connected to the first fan-out trace 11, and the second bonding terminal 52 is electrically connected to the second fan-out trace 12. The second fan-out trace 12 also includes a connecting segment 122, which extends from the connection point with the second transistor T2 to the second bonding terminal 52.

[0106] In two adjacent second fan-out segments 121, the impedance of the connecting segment 122 to which the second fan-out segment 121 with higher impedance is lower than the impedance of the connecting segment 122 to which the second fan-out segment 121 with lower impedance is connected. It is understood that the second fan-out segments 121 and the connecting segment 122 constitute the second fan-out trace 12. This helps to reduce the impedance difference between adjacent second fan-out traces 12, thereby improving the display effect when driven by the driver chip.

[0107] like Figure 5 or Figure 6 As shown, the connecting segment 122 may include a first connecting segment 1221 and a second connecting segment 1222. The first connecting segment 1221 is electrically connected between the second fan-out segment 121 and the second connecting segment 1222. The second connecting segment 1222 is connected to the second bonding terminal 52. For example, the impedance per unit length within the first connecting segment 1221 is greater than the impedance per unit length within the second connecting segment 1222.

[0108] In some embodiments, such as Figure 7 As shown, in two adjacent second fan-out sections 121, the connecting section 122 electrically connected to the second fan-out section 121 with the smaller impedance may further include a third connecting section 1223, which is electrically connected between the first connecting section 1221 and the second connecting section 1222. The second connecting section 1222 is located on the side of the first connecting section 1221 closer to the bonding area BA, and the third connecting section 1223 is at least partially located on the side of the first connecting section 1221 away from the bonding area BA.

[0109] In the embodiments of the present application, for the second fan-out segment 121 with small impedance, a third connection segment 1223 is additionally added in the transmission path of the test signal to reduce the impedance difference of the adjacent second fan-out wires 12. The third connection segment 1223 is at least partially located on the side of the first connection segment 1221 away from the bonding area BA, so that the third connection segment 1223 can be added without increasing the width of the non-display area NA in the second direction Y, thereby facilitating the narrow frame design.

[0110] For example, the third connection segment 1223 can have a "U" shape.

[0111] For example, the first connection segment 1221 and the third connection segment 1223 can be located in the same film layer.

[0112] For example, the first connection segment 1221 and the third connection segment 1223 can be located in the same film layer. The first connection segment 1221 and the second connection segment 1222 can be connected by a third via hole h3, and the third connection segment 1223 and the second connection segment 1222 can be connected by a third via hole h3.

[0113] It should be noted that, in order to clearly distinguish the connection segments 122 of different second fan-out wires 12, the first connection segment 1221 and the third connection segment 1223 are shown by solid lines, and the second connection segment 1222 is shown by dashed lines in the drawings of the present application.

[0114] For example, as shown in Figure 8 , the display panel can include a substrate 01, and a semiconductor layer 02, a first metal layer M1 and a second metal layer M2 located on one side of the substrate 01. The display panel can further include a plurality of insulating layers, such as a gate insulating layer GI, an interlayer dielectric layer ILD, and a planarization layer PLN. The positional relationship of each film layer can be referred to Figure 8 , which will not be described in detail here.

[0115] For example, the display panel can be a liquid crystal display panel, as shown in Figure 8 , the display panel can further include a pixel electrode 91 and a common electrode 92, and the pixel electrode 91 can be connected with a pixel circuit 93. The side of the pixel electrode 91 away from the substrate 01 can further include a liquid crystal layer (not shown in the figure), and the side of the liquid crystal layer away from the substrate can further include a color filter substrate.

[0116] It should be noted that, Figure 8 The common electrode 92 and the pixel electrode 91 are shown as being located in different film layers of the array substrate, which is not used to limit the present application. In other examples, the common electrode 92 and the pixel electrode 91 can be located in the same film layer of the array substrate. In addition, Figure 8For example, the display panel can also be an Organic Light-Emitting Diode (OLED) display panel, or other types of display panels.

[0117] As an example, the first fan-out segment 1111 and the third fan-out segment 1213 can be located at the first metal layer M1. The second fan-out segment 1112 and the fourth fan-out segment 1214 can be located at the second metal layer M2.

[0118] The first connection segment 1221 and the third connection segment 1223 can be located at the first metal layer M1. The second connection segment 1222 can be located at the second metal layer M2.

[0119] The first test segment 421 can be located at the semiconductor layer 02. The active layer of the second transistor T2 and the active layer of the first transistor T1 can be located at the semiconductor layer 02.

[0120] Part of the second test segment 422 can be located at the first metal layer M1, and part of the second test segment 422 can be located at the second metal layer M2.

[0121] As an example, as shown in Figure 5 or Figure 6 The display panel can further include a first electrostatic protection circuit 71 and a second electrostatic protection circuit 72. The first electrostatic protection circuit 71 can be located within the bonding area BA, and the second electrostatic protection circuit 72 can be located outside the bonding area BA. The first electrostatic protection circuit 71 can be arranged adjacent to the first test circuit 21, and the second electrostatic protection circuit 72 can be arranged adjacent to the second test circuit 22.

[0122] As an example, as shown in Figure 9 The display panel can further include a touch signal line 73. The first electrostatic protection circuit 71 and the second electrostatic protection circuit 72 can be connected to different touch signal lines 73, and can protect the touch circuit to avoid static shock.

[0123] The circuit structure of the first electrostatic protection circuit 71 and the second electrostatic protection circuit 72 can be the same. As an example, as shown in Figure 9As shown, the first electrostatic protection circuit 71 and the second electrostatic protection circuit 72 can include a third transistor T3 and a fourth transistor T4. The first electrode of the third transistor T3 is connected to the high-voltage signal line VGH, and the second electrode of the third transistor T3 is connected to the touch signal line 73. The first electrode of the fourth transistor T4 is connected to the low-voltage signal line VGL, and the second electrode of the fourth transistor T4 is connected to the touch signal line 73. In the case that the voltage on the touch signal line 73 is too high, the third transistor T3 is turned on, and the charge on the touch signal line 73 is discharged to the high-voltage signal line VGH. In the case that the voltage on the touch signal line 73 is too low, the fourth transistor T4 is turned on, and the charge on the touch signal line 73 is discharged to the low-voltage signal line VGL.

[0124] As shown in the example, Figure 5 or Figure 6 As shown, the display panel can further include a gating circuit 80. The gating circuit 80 can include one input end and multiple output ends. The input end of the gating circuit 80 can be connected to the fan-out line 10, and the output ends of the gating circuit 80 can be connected to the data lines. In this way, the driving signals can be transmitted to the multiple data lines by using the integrated fan-out line, which is conducive to reducing the number of fan-out lines 10, thereby facilitating the realization of a narrow frame.

[0125] It should be noted that the transistors in the embodiments of the present application can be N-type transistors or P-type transistors. For an N-type transistor, the on level is high and the off level is low. That is, when the gate potential of the N-type transistor is high, the first electrode and the second electrode thereof are turned on, and when the gate potential of the N-type transistor is low, the first electrode and the second electrode thereof are turned off. For a P-type transistor, the on level is low and the off level is high. That is, when the gate potential of the P-type transistor is low, the first electrode and the second electrode thereof are turned on, and when the gate potential of the P-type transistor is high, the first electrode and the second electrode thereof are turned off. In the specific implementation, the gate of each transistor is used as the control electrode thereof, and according to the signal of the gate of each transistor and the type thereof, the first electrode thereof can be used as the source electrode and the second electrode thereof can be used as the drain electrode, or the first electrode thereof can be used as the drain electrode and the second electrode thereof can be used as the source electrode, which are not distinguished herein. In addition, the on level and the off level in the embodiments of the present application are generic. The on level refers to any level that can turn on the transistor, and the off level refers to any level that can turn off / turn off the transistor.

[0126] The present application also provides a display device including the display panel provided by the present application. Please refer to Figure 10 , Figure 10 FIG. 1 is a structural schematic diagram of a display device provided by an embodiment of the present application. Figure 10 The display device 1000 provided by the present application includes the display panel 100 provided by any of the above embodiments of the present application. Figure 10The embodiments are described by taking the mobile phone as an example to describe the display device 1000, and it can be understood that the display device provided by the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, and the present application does not make specific limitations thereon. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application, and specific descriptions can be made with reference to the specific descriptions of the display panel in the above embodiments, and the embodiments will not be described herein again.

[0127] In accordance with the embodiments of the present application as described above, the embodiments do not describe all the details, nor limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made in light of the above descriptions. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, A display panel has a display area and a non-display area at least partially surrounding the display area, the non-display area includes a binding area, the display panel includes: a fan-out line including a first fan-out wire and a second fan-out wire; a first test circuit located in the binding area, including a first transistor, an output terminal of the first transistor being electrically connected to the first fan-out wire; a second test circuit located outside the binding area, including a second transistor, an output terminal of the second transistor being electrically connected to the second fan-out wire; a test terminal, an input terminal of the first transistor being electrically connected to the test terminal through a first test wire, an input terminal of the second transistor being electrically connected to the test terminal through a second test wire; the first fan-out wire includes a first fan-out segment, the first fan-out segment extending between a connection with the first transistor to the display area, the second fan-out wire includes a second fan-out segment, the second fan-out segment extending between a connection with the second transistor to the display area, an impedance of the first fan-out segment being greater than an impedance of the second fan-out segment; the display panel satisfies at least one of the following: a channel width-length ratio of the first transistor is greater than a channel width-length ratio of the second transistor, an impedance of the first test wire is less than an impedance of the second test wire; the first fan-out segment includes a first fan-out sub-segment and a second fan-out sub-segment connected to each other through a first via, an impedance per unit length in the first fan-out sub-segment being greater than an impedance per unit length in the second fan-out sub-segment; a wire length of the first fan-out sub-segment is equal to a wire length of the second fan-out sub-segment; the first fan-out sub-segment and the second fan-out sub-segment are located in different metal layers, in a top view, in two adjacent first fan-out segments, a first fan-out sub-segment of a first one of the first fan-out segments is adjacent to a second fan-out sub-segment of a second one of the first fan-out segments, and a second fan-out sub-segment of the first one of the first fan-out segments is adjacent to a first fan-out sub-segment of the second one of the first fan-out segments.

2. The display panel of claim 1, wherein, the second fan-out segment includes a third fan-out sub-segment and a fourth fan-out sub-segment connected to each other through a second via, an impedance per unit length in the third fan-out sub-segment being greater than an impedance per unit length in the fourth fan-out sub-segment; the second test circuit is located on one side of the display area in a second direction, a distance between the second via and the display area in the second direction is greater than a distance between the second via and the second test circuit in the second direction.

3. The display panel of claim 2, wherein, a channel width-length ratio of the first transistor is greater than a channel width-length ratio of the second transistor, a plurality of the first vias and a plurality of the second vias are arranged continuously; in two adjacent second fan-out segments, a channel width-length ratio of the second transistor electrically connected to the second fan-out segment with a longer wire length of the third fan-out sub-segment is greater than a channel width-length ratio of the second transistor electrically connected to the second fan-out segment with a shorter wire length of the third fan-out sub-segment.

4. The display panel of claim 2, wherein, in the same second fan-out segment, a wire length of the third fan-out sub-segment is equal to a wire length of the fourth fan-out sub-segment, channel width-length ratios of the second transistors electrically connected to at least two adjacent second fan-out segments are equal.

5. The display panel of claim 1, wherein, An impedance of the first test trace is less than an impedance of the second test trace. The second test trace comprises a first test segment and a second test segment connected to each other, and an impedance per unit length in the first test segment is greater than an impedance per unit length in the second test segment.

6. The display panel of claim 5, wherein, The first fan-out segment comprises a first fan-out sub-segment and a second fan-out sub-segment connected to each other by a first via, and an impedance per unit length in the first fan-out sub-segment is greater than an impedance per unit length in the second fan-out sub-segment. The second fan-out segment comprises a third fan-out sub-segment and a fourth fan-out sub-segment connected to each other by a second via, and an impedance per unit length in the third fan-out sub-segment is greater than an impedance per unit length in the fourth fan-out sub-segment. The first via and the second via are arranged in succession. In adjacent second fan-out segments, an impedance of the first test segment electrically connected to the second fan-out segment with a longer third fan-out sub-segment is less than an impedance of the first test segment electrically connected to the second fan-out segment with a shorter third fan-out sub-segment.

7. The display panel of claim 5, wherein, The second fan-out segment comprises a third fan-out sub-segment and a fourth fan-out sub-segment connected to each other by a second via, and an impedance per unit length in the third fan-out sub-segment is greater than an impedance per unit length in the fourth fan-out sub-segment, a wire length of the third fan-out sub-segment is equal to a wire length of the fourth fan-out sub-segment, and an impedance of the first test segment electrically connected to at least two adjacent second fan-out segments is equal.

8. The display panel of claim 5, wherein, The first test segment comprises a semiconductor.

9. The display panel of claim 8, wherein, The first test segment and an active layer of the second transistor are located in a same film layer.

10. The display panel of any one of claims 2-4, 6, wherein, The first fan-out sub-segment and the third fan-out sub-segment are located in a same film layer and have a same material. The second fan-out sub-segment and the fourth fan-out sub-segment are located in a same film layer and have a same material.

11. The display panel of claim 1, wherein, The display panel further comprises: The binding terminal is located in the binding area and comprises a first binding terminal and a second binding terminal, the first binding terminal is electrically connected to the first fan-out trace, and the second binding terminal is electrically connected to the second fan-out trace. The second fan-out trace further comprises a connecting segment, and the connecting segment extends between the second transistor and the second binding terminal. In adjacent second fan-out segments, an impedance of the connecting segment electrically connected to the second fan-out segment with a greater impedance is less than an impedance of the connecting segment electrically connected to the second fan-out segment with a smaller impedance.

12. The display panel of claim 11, wherein, The connecting segment comprises a first connecting segment and a second connecting segment, and the first connecting segment is electrically connected between the second fan-out segment and the second connecting segment. In adjacent second fan-out segments, the connecting segment electrically connected to the second fan-out segment with a smaller impedance further comprises a third connecting segment, and the third connecting segment is electrically connected between the first connecting segment and the second connecting segment. The second connecting segment is located on a side of the first connecting segment close to the binding area, and the third connecting segment is at least partially located on a side of the first connecting segment away from the binding area.

13. The display panel of claim 12, wherein, Any one of the first connecting segment and the second connecting segment is located in a same film layer as the third connecting segment.

14. A display device comprising: The display panel comprises any one of the display panels according to claims 1 to 13.

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