Splicing display device, display panel and array substrate

Abstract

The present disclosure provides a tiled display device, a display panel and an array substrate. The array substrate comprises n pixel regions and a peripheral region surrounding the pixel regions, n>=2, the pixel regions being provided with pixel circuits; the array substrate comprises a substrate, n chip groups provided on one side of the substrate and located in the peripheral region, the n chip groups corresponding to the n pixel regions, at least one driving chip being included in one chip group, the driving chip in one chip group being electrically connected to the pixel circuit in the corresponding pixel region; the driving chips in the n chip groups being electrically connected to the same circuit board. The present disclosure reduces the number of circuit boards.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a spliced display device, a display panel and an array substrate. BACKGROUND

[0002] With the progress of the times, electronic consumer goods have attracted more and more attention from people. Some existing display devices still need to be improved. SUMMARY

[0003] The purpose of the present disclosure is to provide a spliced display device, a display panel and an array substrate.

[0004] According to one aspect of the present disclosure, an array substrate is provided, which comprises n pixel regions distributed at intervals and a peripheral region surrounding the pixel regions, n≥2, and the pixel regions are provided with pixel circuits; the array substrate comprises:

[0005] a substrate;

[0006] n chip groups arranged on one side of the substrate and located in the peripheral region, the n chip groups correspond to the n pixel regions, at least one driving chip is included in one chip group, and the driving chip in one chip group is electrically connected to the pixel circuit in the corresponding pixel region; the driving chips in the n chip groups are electrically connected to the same circuit board.

[0007] In some embodiments, in a first direction, m pixel regions and m chip groups are staggered and arranged, 2≤m≤n, and the m pixel regions and the m chip groups arranged in a staggered manner correspond.

[0008] In some embodiments, the m pixel regions include first to mth pixel regions arranged in sequence, the m chip groups include first to mth chip groups arranged in sequence, and the first to mth chip groups correspond to the first to mth pixel regions; the array substrate further comprises:

[0009] a connection pad arranged in the peripheral region, in the first direction, the connection pad is located on a side of the first pixel region away from the mth pixel region, the first chip group is located between the connection pad and the first pixel region, and the connection pad is electrically connected to the circuit board;

[0010] wherein the driving chip in the kth chip group is electrically connected to the connection pad through a plurality of signal connection lines, 1

[0011] In some embodiments, the pixel circuit includes a switch transistor including a gate and a source-drain electrode, the gate being disposed between the substrate and the source-drain electrode, at least a portion of the signal connection line being disposed in the same layer as the gate or the source-drain electrode.

[0012] In some embodiments, the pixel region includes a plurality of pixel columns, each pixel column including a plurality of pixels arranged along the first direction.

[0013] In some embodiments, the array substrate further includes:

[0014] 2n gate drive circuits in the peripheral region, one pixel region corresponding to two gate drive circuits, and the pixel region being located between the corresponding two gate drive circuits; one chip set corresponding to two gate drive circuits, the two gate drive circuits being electrically connected to the drive chip in the corresponding chip set; the two gate drive circuits and one chip set corresponding to the same pixel region.

[0015] In some embodiments, 2(k-1) gate drive circuits corresponding to the first to (k-1)th pixel regions are located between the two line groups.

[0016] In some embodiments, the pixel region further includes a pixel electrode and a common electrode for generating an electric field, the common electrode in each pixel region being electrically connected to the circuit board.

[0017] According to an aspect of the present disclosure, a display panel is provided, including the array substrate.

[0018] According to an aspect of the present disclosure, a tiled display device is provided, including a plurality of the display panel.

[0019] The tiled display device, the display panel and the array substrate of the present disclosure can include n pixel regions distributed at intervals and a peripheral region surrounding the pixel regions, n chip sets corresponding to the n pixel regions, and drive chips in the n chip sets being electrically connected to the same circuit board, so that a plurality of pixel regions can share one circuit board, reducing the number of circuit boards; at the same time, when the array substrate of the present disclosure is tiled into a display device, due to the small number of circuit boards, the large tile seam can be avoided, and for the tiled display device capable of transparent display, the circuit board can avoid affecting the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 FIG. 1 is a schematic diagram of a tiled display device in the related art.

[0021] Figure 2 and Figure 3 FIG. 1 is a schematic diagram of a tiled display device in the related art.

[0022] Figure 4 is a pixel distribution schematic diagram of an embodiment of the present disclosure.

[0023] Figure 5 is a cross-sectional distribution schematic diagram of an array substrate of an embodiment of the present disclosure.

[0024] Figure 6 is a schematic diagram of a spliced display device of an embodiment of the present disclosure.

[0025] Legend: 1, substrate; 2, chip set; 201, driving chip; 3, line set; 301, signal connection line; 4, gate; 5, source-drain electrode; 6, connection pad; 7, first insulating layer; 8, pixel electrode; 9, second insulating layer; 10, common electrode; 11, data signal line; 12, pixel circuit; 13, gate driving circuit; 14, pixel; 1401, sub-pixel; 15, pixel column; 16, pixel row; 17, active layer; 18, gate insulating layer; 19, circuit board; 20, flexible circuit board; A0, pixel area; A1, peripheral area; T1, switching transistor; 100, display panel. DETAILED DESCRIPTION

[0026] The exemplary embodiments will be described in detail herein with reference to the attached drawings. The following description is only exemplary and is not intended to limit the present disclosure to the described embodiments. In fact, those skilled in the art will recognize that the present disclosure is applicable to any device that is configured to perform the functions described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will recognize that the present disclosure can be practiced without the specific details given herein. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present disclosure.

[0027] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the present disclosure have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and similar terms do not imply any order, quantity, or importance, but are used to distinguish one element from another, and are used arbitrarily. Also, "one" or "the" and similar terms do not denote a quantity of particularly one, but rather denote the existence of at least one. "Multiple" or "a plurality" denotes two or more. Unless otherwise indicated, the terms "front", "rear", "upper", and / or "lower" and similar terms are used for ease of description and are not intended to be limiting to one position or spatial orientation. The terms "include" or "comprise" and similar terms do not exclude the presence of other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections or links, but also include electrical connections or links, whether direct or indirect. The terms "a", "an", and "the" used in the present disclosure and the appended claims are intended to include both singular and plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or", as used herein, refers to and encompasses any or all possible combinations of one or more of the associated listed items.

[0028] Figure 1 is a schematic diagram of a tiled display device in the related art. In Figure 1 , the tiled display device is tiled by eight display panels 100. Each display panel 100 is electrically connected to a circuit board 19, which is capable of sending signals to the display panel 100. In the A2 region in Figure 1 , the seam of the display panel 100 is located. In this region, the seam is larger due to the presence of the circuit board 19, and for the tiled display device capable of transparent display, the presence of the circuit board 19 will affect the display effect.

[0029] Figure 2 is a schematic diagram of an array substrate including a plurality of pixel regions A0 in an embodiment of the present disclosure. Figure 3 is a schematic diagram of an array substrate including two pixel regions A0 in an embodiment of the present disclosure. As shown in Figure 2 , the array substrate of the present disclosure can include n pixel regions A0 distributed at intervals, and a peripheral region A1 surrounding the pixel regions A0, n≥2. The pixel region A0 can be rectangular, square, circular, elliptical, etc. As shown in Figure 3 , each pixel region A0 can be provided with a pixel circuit 12.

[0030] Figure 4 is a schematic diagram of the distribution of pixels 14 in each pixel region A0 in an embodiment of the present disclosure. As shown in the diagram, each pixel region A0 can include a plurality of pixels 14. One pixel 14 can include a plurality of sub-pixels 1401. Specifically, one pixel 14 can include three sub-pixels 1401, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The three sub-pixels 1401 in one pixel 14 can be distributed in a first direction (the Y direction in the diagram) in sequence, or can be distributed in a second direction (the X direction in the diagram) in sequence, but the present disclosure does not make special limitations on this. The second direction can be perpendicular or substantially perpendicular to the first direction. The plurality of pixels 14 can be distributed in an array. In the plurality of pixels 14 distributed in the array, the plurality of pixels 14 distributed along the first direction can constitute a pixel column 15, and the plurality of pixels 14 distributed along the second direction can constitute a pixel row 16. Figure 4

[0031] As shown in the diagram, the array substrate can include a substrate 1 (see Figure 3 ) and n chip groups 2. The n chip groups 2 are arranged on one side of the substrate 1 and located in the peripheral region A1. The n chip groups 2 correspond to the n pixel regions A0, at least one driving chip 201 is included in one chip group 2, and the driving chip 201 in one chip group 2 is electrically connected to the pixel circuit 12 in the corresponding pixel region A0. The driving chips 201 in the n chip groups 2 are electrically connected to the same circuit board 19. Figure 5 The array substrate in an embodiment of the present disclosure can include n pixel regions A0 distributed at intervals and a peripheral region A1 surrounding the pixel regions A0, n chip groups 2 correspond to the n pixel regions A0, and the driving chips 201 in the n chip groups 2 are electrically connected to the same circuit board 19, so that the plurality of pixel regions A0 can share one circuit board 19, reducing the number of circuit boards 19; at the same time, when the array substrate in the present disclosure is spliced into a display device, the number of circuit boards 19 is small, which can avoid a large splicing seam, and for a spliced display device capable of transparent display, the circuit board 19 can avoid affecting the display effect.

[0032] The following describes in detail each part of the array substrate in an embodiment of the present disclosure:

[0033] As shown in the diagram, the substrate 1 can be a rigid substrate. The rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc. Of course, the substrate 1 can also be a flexible substrate.

[0034] Figure 5

[0035] As shown in the diagram, the substrate 1 can be a rigid substrate. The rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc. Of course, the substrate 1 can also be a flexible substrate. Figure 3 ​​​As shown, the pixel circuit 12 is arranged on one side of the substrate 1. Each pixel region A0 can be provided with the pixel circuit 12. The number of the pixel circuits 12 in each pixel region A0 can be multiple and correspond to the multiple sub-pixels 1401 in each pixel region A0 one by one. The multiple pixel circuits 12 in each pixel region A0 can be arranged in an array. Among the multiple pixel circuits 12 arranged in an array, the multiple pixel circuits 12 arranged along the first direction can constitute a circuit column, and the multiple pixel circuits 12 arranged along the second direction can constitute a circuit row.

[0036] As shown, Figure 3 Each pixel region A0 can also be provided with a data signal line 11. The data signal line 11 can be arranged on one side of the substrate 1 and electrically connected to the pixel circuit 12. Among the multiple pixel circuits 12 in one circuit column, the multiple pixel circuits 12 can be connected to the same data signal line 11. Further, multiple data signal lines 11 can be arranged in each pixel region A0, and the multiple data signal lines 11 can correspond to the multiple circuit columns one by one. The data signal lines 11 and the circuit columns can be staggered in the second direction, and the multiple pixel circuits 12 in each circuit column are electrically connected to the corresponding data signal line 11.

[0037] As shown, Figure 3 Each pixel region A0 can also be provided with a scan signal line. The scan signal line can be arranged on one side of the substrate 1 and electrically connected to the pixel circuit 12. Among the multiple pixel circuits 12 in one circuit row, the multiple pixel circuits 12 can be connected to the same scan signal line. Further, multiple scan signal lines can be arranged in each pixel region A0, and the multiple scan signal lines can correspond to the multiple circuit rows one by one. The scan signal lines and the circuit rows can be staggered in the first direction, and the multiple pixel circuits 12 in each circuit row are electrically connected to the corresponding scan signal line.

[0038] As shown, Figure 5As shown, each pixel circuit 12 may include a switching transistor T1. The switching transistor T1 may be a thin-film transistor. The switching transistor T1 may include a gate 4 and source / drain electrodes 5. The gate 4 of the switching transistor T1 may be disposed on one side of the substrate 1. The aforementioned scan signal line may be disposed on the same layer as the gate 4 of the switching transistor T1 and electrically connected to the gate 4. The source / drain electrodes 5 of the switching transistor T1 are located on the side of the gate 4 of the switching transistor T1 facing away from the substrate 1. The aforementioned data signal line 11 may be disposed on the same layer as the source / drain electrodes 5 of the switching transistor T1 and electrically connected to the source / drain electrodes 5. The switching transistor T1 may also include an active layer 17 and a gate insulating layer 18. Taking a bottom-gate thin-film transistor as an example, the active layer 17 of the switching transistor T1 may be disposed on the side of the gate 4 of the switching transistor T1 facing away from the substrate 1, the gate insulating layer 18 may be disposed on the side of the active layer 17 of the switching transistor T1 facing away from the substrate 1, and the source / drain electrodes 5 of the switching transistor T1 may be disposed on the side of the active layer 17 facing away from the substrate 1. In other embodiments, the switching transistor T1 may also be a top-gate thin-film transistor.

[0039] like Figure 5 As shown, the array substrate of this disclosure may further include a first insulating layer 7, a pixel electrode 8, a second insulating layer 9, and a common electrode 10. Each pixel region A0 is provided with a pixel electrode 8 and a common electrode 10. Within a pixel region A0, there may be multiple pixel electrodes 8, and each pixel electrode 8 may correspond one-to-one with multiple pixel circuits 12. The first insulating layer 7 may be disposed on the side of the second source / drain of the switching transistor T1 facing away from the substrate 1. The pixel electrode 8 and the common electrode 10 may be located on the side of the first insulating layer 7 facing away from the substrate 1. Specifically, the common electrode 10 may be disposed on the side of the pixel electrode 8 facing away from the substrate 1, and the second insulating layer 9 is disposed between the common electrode 10 and the pixel electrode 8. The pixel electrode 8 is electrically connected to the second source / drain of the switching transistor T1. In other embodiments, the common electrode 10 may also be disposed on the side of the pixel electrode 8 facing the substrate 1. A horizontal electric field, i.e., an electric field in ADS (Advanced SuperDimension Switch) mode or an electric field in IPS (In-Plane Switching) mode, can be generated between the common electrode 10 and the pixel electrode 8. In addition, the common electrode 10 in each pixel area A0 is electrically connected to the circuit board 19.

[0040] like Figure 3As shown, the array substrate of the present disclosure can also include 2n gate drive circuits 13. The gate drive circuit 13 can include a plurality of cascaded shift registers. The gate drive circuit 13 can be disposed in the peripheral area A1, and the signal output end of the shift register can be electrically connected with the scan signal line, for transmitting signals to the scan signal line. Among them, one pixel area A0 can correspond to two gate drive circuits 13, and the pixel area A0 is located between the corresponding two gate drive circuits 13.

[0041] As shown, one of the above chip sets 2 can include one, two, three, four or more drive chips 201. A plurality of drive chips 201 can be distributed along the second direction, but the present disclosure is not limited thereto. n chip sets 2 correspond to n pixel areas A0, and the drive chip 201 in one chip set 2 is electrically connected with the pixel circuit 12 in the corresponding pixel area A0. Among them, the drive chip 201 can be electrically connected with the pixel circuit 12 through the data signal line 11, to send signals to the above-mentioned switch transistor T1. In addition, one chip set 2 corresponds to two gate drive circuits 13, and the two gate drive circuits 13 are electrically connected with the drive chip 201 in the corresponding chip set 2. It should be noted that the two gate drive circuits 13 and one chip set 2 correspond to the same pixel area A0. Figure 3 As shown, in the first direction, there are m pixel areas A0 and m chip sets 2 arranged alternately, 2≤m≤n, and the m pixel areas A0 and m chip sets 2 arranged alternately correspond one by one. Specifically, among the m pixel areas A0 and m chip sets 2 arranged alternately, the m pixel areas A0 include the 1st to mth pixel areas A0 distributed in turn along the first direction, and the m chip sets 2 include the 1st to mth chip sets 2 distributed in turn, the 1st to mth chip sets 2 correspond to the 1st to mth pixel areas A0 one by one.

[0042] Figure 3 As shown, in the first direction, there are m pixel areas A0 and m chip sets 2 arranged alternately, 2≤m≤n, and the m pixel areas A0 and m chip sets 2 arranged alternately correspond one by one. Specifically, among the m pixel areas A0 and m chip sets 2 arranged alternately, the m pixel areas A0 include the 1st to mth pixel areas A0 distributed in turn along the first direction, and the m chip sets 2 include the 1st to mth chip sets 2 distributed in turn, the 1st to mth chip sets 2 correspond to the 1st to mth pixel areas A0 one by one.

[0043] As shown, in the first direction, there are m pixel areas A0 and m chip sets 2 arranged alternately, 2≤m≤n, and the m pixel areas A0 and m chip sets 2 arranged alternately correspond one by one. Specifically, among the m pixel areas A0 and m chip sets 2 arranged alternately, the m pixel areas A0 include the 1st to mth pixel areas A0 distributed in turn along the first direction, and the m chip sets 2 include the 1st to mth chip sets 2 distributed in turn, the 1st to mth chip sets 2 correspond to the 1st to mth pixel areas A0 one by one. Figure 3 ​As shown, the array substrate of the present disclosure can further include a connection pad 6. The connection pad 6 can be disposed in the peripheral area A1. In the first direction, the connection pad 6 can be located on the side of the first pixel area A0 away from the mth pixel area A0. The first chip set 2 can be located between the connection pad 6 and the first pixel area A0. The driving chip 201 can be electrically connected to the circuit board 19 through the connection pad 6. The connection pad 6 can be electrically connected to the circuit board 19 through a flexible circuit board 2019. By arranging the flexible circuit board 2019, the circuit board 19 can be arranged on the backlight side of the array substrate. In the first to mth chip sets 2, the driving chip 201 in the kth chip set 2 is electrically connected to the connection pad 6 through a plurality of signal connection lines 301, 1 < k ≤ m, the plurality of signal connection lines 301 include two line groups 3, the line group 3 includes one or more signal connection lines 301; the first to (k-1)th pixel areas A0 are located between the two line groups 3; and the 2(k-1) gate drive circuits 13 corresponding to the first to (k-1)th pixel areas A0 can be located between the two line groups 3. In addition, the number of signal connection lines 301 in the two line groups 3 can be the same, of course, they can also be different. At least part of the signal connection lines 301 can be arranged in the same layer as the gate electrode 4 or the source / drain electrode 5 of the switching transistor T1.

[0044] The display panel can include the array substrate of any of the above embodiments. The display panel can further include a counter substrate and a liquid crystal layer. The counter substrate is arranged opposite to the array substrate, and the liquid crystal layer can be arranged between the array substrate and the counter substrate.

[0045] The display panel can include the array substrate of any of the above embodiments. The display panel can further include a counter substrate and a liquid crystal layer. The counter substrate is arranged opposite to the array substrate, and the liquid crystal layer can be arranged between the array substrate and the counter substrate. Figure 6 As shown, the display panel can include four array substrates. Since the number of circuit boards 19 included in the array substrate is reduced, the width of the seam L1 can be reduced.

[0046] The display device, the display panel and the array substrate provided by the embodiments of the present disclosure belong to the same inventive concept, and the descriptions of the related details and beneficial effects can be referred to each other, and will not be repeated here.

[0047] The above merely describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure in any form. Although the present disclosure has been described as above with the preferred embodiments, it is not intended to limit the present disclosure, and any person skilled in the art can make some changes or modifications to the equivalent embodiments with the above disclosed technical contents without departing from the scope of the technical solutions of the present disclosure. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present disclosure shall still fall within the scope of the technical solutions of the present disclosure.

Claims

1. A splicing display device, characterized in that, The splicing display device is composed of multiple display panels spliced ​​together. Each display panel includes an array substrate, which includes n pixel regions spaced apart and an outer region surrounding the pixel regions, where n ≥ 2. Each pixel region is provided with pixel circuitry. The array substrate includes: Substrate; n chip groups are disposed on one side of the substrate and located in the peripheral area. The n chip groups correspond to the n pixel areas. Each chip group includes at least one driver chip. The driver chip in the chip group is electrically connected to the pixel circuit in the corresponding pixel area. The driver chips in the n chip groups are electrically connected to the same circuit board. In the first direction, there are m pixel regions and m chip groups arranged alternately, 2≤m≤n, and the m pixel regions and m chip groups arranged alternately correspond to each other.

2. The splicing display device according to claim 1, characterized in that, The m pixel regions include sequentially distributed pixel regions 1 to m, and the m chip groups include sequentially distributed chip groups 1 to m, with each chip group corresponding to a pixel region 1 to m; the array substrate further includes: A connecting pad is provided in the peripheral area. In the first direction, the connecting pad is located on the side of the first pixel area away from the m-th pixel area. The first chipset is located between the connecting pad and the first pixel area. The connecting pad is electrically connected to the circuit board. The driver chip in the k-th chip group is electrically connected to the connection pad through multiple signal connection lines, where 1 < k ≤ m. The multiple signal connection lines include two line groups, and each line group includes one or more signal connection lines. The first to (k-1)-th pixel regions are located between the two line groups.

3. The splicing display device according to claim 2, characterized in that, The pixel circuit includes a switching transistor, which includes a gate and a source / drain electrode. The gate is disposed between the substrate and the source / drain electrode, and at least a portion of the signal connection line is disposed on the same layer as the gate or the source / drain electrode.

4. The splicing display device according to claim 1, characterized in that, The pixel region is provided with multiple pixel columns, and the pixel columns include multiple pixels distributed along the first direction.

5. The splicing display device according to any one of claims 1-4, characterized in that, The array substrate further includes: 2n gate driving circuits are located in the peripheral region. One pixel region corresponds to two gate driving circuits, and the pixel region is located between the corresponding two gate driving circuits. One chipset corresponds to two gate driving circuits, and the two gate driving circuits are electrically connected to the driving chip in the corresponding chipset. Two gate driving circuits and one chipset correspond to the same pixel region.

6. The splicing display device according to claim 5, characterized in that, The two (k-1) gate drive circuits corresponding to the first to (k-1)th pixel regions are located between the two line groups.

7. The splicing display device according to claim 1, characterized in that, The pixel region is further provided with pixel electrodes and common electrodes for generating an electric field, and the common electrode in each pixel region is electrically connected to the circuit board.

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