Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. A plurality of scanning lines and a plurality of data lines are insulated and crossed on the array substrate to define a plurality of sub-pixel units. Two adjacent data lines are a first data line and a second data line, and two adjacent sub-pixel units are connected to different data lines. A plurality of sub-pixel units form a repeating unit area. A plurality of first data lines in each repeating unit area are electrically connected to each other, and a plurality of second data lines in each repeating unit area are electrically connected to each other. Two adjacent scanning lines are a first scanning line and a second scanning line, and the first scanning line and the second scanning line are arranged between two adjacent rows of sub-pixel units. The sub-pixel units in each row are selectively electrically connected to the first scanning line and the second scanning line. When the data signal switching frequency is changed, there is no obvious difference between brightness and darkness, SDRRS under point inversion is realized, driving power consumption is reduced, and the aperture ratio of the pixel is not affected.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, display panel, and display device. Background Technology

[0002] With the development of science and technology, LCD (Liquid Crystal Display) monitors have replaced bulky CRT monitors and are increasingly integrated into people's daily lives. In particular, LCD monitors have developed rapidly in recent years due to their small size, light weight, thinness, low power consumption, and no radiation. They occupy a dominant position in the current flat panel display market and are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, computers, mobile phones, PDAs, GPS, automotive displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] During image display, each liquid crystal pixel in an LCD flat panel display is driven by a thin film transistor (TFT) integrated in a TFT thin film transistor array substrate, and together with the peripheral driving circuit, the image is displayed. Figure 1 This is one of the structural schematic diagrams of array substrates in the prior art. Figure 2 It corresponds to existing technology Figure 1 A schematic diagram of the arrangement of R / G / B color resists on the color filter substrate. Figure 3 It corresponds to existing technology Figure 1 A waveform diagram of the scanning signal and data signal, as shown below. Figures 1 to 3 As shown, for conventional dual-gate LCD products, when SDRRS (seamless dynamic refresh rate switch) is enabled, the data signal switches multiple times per frame due to changes in charging time. When the frequency changes, the charging time changes accordingly, resulting in different charging voltages for different sub-pixels. This leads to noticeable differences in brightness in some areas of the image. Furthermore, the rapid switching frequency of the data signal typically results in high power consumption. To avoid this problem of noticeable differences in brightness when SDRRS is enabled... Figure 4 This is the second schematic diagram of the structure of an array substrate in the prior art. Figure 5 It corresponds to existing technology Figure 4 A schematic diagram of the arrangement of R / G / B color resists on the color filter substrate. Figure 6 It corresponds to existing technology Figure 4 A waveform diagram of the scanning signal and data signal, as shown below. Figures 3 to 6As shown, another type of dual-gate LCD product distributes pixel electrodes of the same polarity in a staggered manner, allowing the same data line to connect to the same polarity pixel electrodes. Therefore, the data signal does not need to switch within each frame; it only needs to switch once per frame. This reduces the switching and amplitude changes of the data signal, resulting in more uniform pixel charging and less noticeable brightness differences when switching drive frequencies. However, in this structure, the source electrode line is relatively long, which not only increases the source resistance but also affects the pixel aperture ratio. Furthermore, when switching frequencies in a solid color grayscale image, brightness differences still exist, leading to noticeable brightness differences in solid color images. Summary of the Invention

[0004] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an array substrate, a display panel, and a display device to solve the problems of high driving power consumption and reduced aperture ratio in the dot-reversal display in the prior art.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] The present invention provides an array substrate, wherein the array substrate is provided with multiple scan lines and multiple data lines, the multiple scan lines and multiple data lines are mutually insulated and intersecting to form multiple sub-pixel units distributed in an array, two adjacent data lines are respectively a first data line and a second data line, the first data line and the second data line are arranged alternately, and two adjacent sub-pixel units are respectively connected to different data lines;

[0007] The array substrate is provided with multiple repeating unit areas, each repeating unit area has multiple columns of sub-pixel units, all the first data lines in each repeating unit area are electrically connected to each other, and all the second data lines in each repeating unit area are electrically connected to each other.

[0008] The two adjacent scan lines are the first scan line and the second scan line, which are arranged alternately. Each row of sub-pixel units is provided with the first scan line and the second scan line. The first scan line and the second scan line are provided between two adjacent rows of sub-pixel units. The first scan line is located above the corresponding row of sub-pixel units, and the second scan line is located below the corresponding row of sub-pixel units. Each sub-pixel unit in each row is selectively electrically connected to the first scan line and the second scan line.

[0009] Furthermore, within each repeating unit area, all sub-pixel units connected to the same first data line are connected to either the first scan line or the second scan line; all sub-pixel units connected to the same second data line are connected to either the first scan line or the second scan line.

[0010] Furthermore, within each repeating unit area, two adjacent sub-pixel units connected to the same first data line are respectively connected to the first scan line and the second scan line; two adjacent sub-pixel units connected to the same second data line are respectively connected to the first scan line and the second scan line.

[0011] Furthermore, in the same row of sub-pixel units within each repeating unit area, the sub-pixel units connected by two adjacent first data lines are respectively connected to different scan lines, and the sub-pixel units connected by two adjacent second data lines are respectively connected to different scan lines.

[0012] Furthermore, in the same row of sub-pixel units within each repeating unit area, the sub-pixel units connected by an odd number of the first data lines are all electrically connected to the first scan line, and the sub-pixel units connected by an even number of the first data lines are all electrically connected to the second scan line.

[0013] Furthermore, in the same row of sub-pixel units within each repeating unit area, the sub-pixel units connected by an odd number of the first data lines are all electrically connected to the second scan line, and the sub-pixel units connected by an even number of the first data lines are all electrically connected to the first scan line.

[0014] Furthermore, in the same row of sub-pixel units within each repeating unit area, the sub-pixel units connected by an odd number of the second data lines are all electrically connected to the first scan line, and the sub-pixel units connected by an even number of the second data lines are all electrically connected to the second scan line.

[0015] Furthermore, in the same row of sub-pixel units within each repeating unit area, the sub-pixel units connected by an odd number of the second data lines are electrically connected to the second scan line, and the sub-pixel units connected by an even number of the second data lines are electrically connected to the first scan line.

[0016] This application also provides a display panel, including a color filter substrate and an array substrate as described above. The color filter substrate and the array substrate are disposed opposite to each other, and a liquid crystal layer is disposed between the color filter substrate and the array substrate. An upper polarizer is disposed on the color filter substrate, and a lower polarizer is disposed on the array substrate. The light transmission axes of the upper polarizer and the lower polarizer are perpendicular to each other.

[0017] This application also provides a display device, including the display panel described above.

[0018] Beneficial effects of this invention:

[0019] By connecting adjacent sub-pixel units to different data lines, and electrically connecting multiple first data lines within each repeating unit area to each other, and electrically connecting multiple second data lines within each repeating unit area to each other, the first and second data lines are arranged alternately. Each row of sub-pixel units is provided with a first scan line and a second scan line, and each sub-pixel unit in each row is selectively electrically connected to the first scan line and the second scan line. Therefore, when implementing dot inversion, the polarity of each data line only needs to be inverted once per frame, without multiple inversions within each frame. Moreover, in grayscale images, there is no voltage difference switching of the data signal, and the pixel charging is uniform. When the data signal switching frequency is high, the difference between brightness and darkness is not obvious, thereby achieving high-quality SDRRS and reducing driving power consumption. At the same time, it is not necessary to set a long source line, reducing the source resistance and power consumption, and it does not affect the pixel aperture ratio. Attached Figure Description

[0020] Figure 1 This is one of the structural schematic diagrams of array substrates in the prior art;

[0021] Figure 2 It corresponds to existing technology Figure 1 A schematic diagram of the arrangement structure of R / G / B color resists on the color filter substrate;

[0022] Figure 3 It corresponds to existing technology Figure 1 A schematic diagram of the waveforms of the scanning signal and the data signal;

[0023] Figure 4 This is the second schematic diagram of the structure of an array substrate in the prior art;

[0024] Figure 5 It corresponds to existing technology Figure 4 A schematic diagram of the arrangement structure of R / G / B color resists on the color filter substrate;

[0025] Figure 6 It corresponds to existing technology Figure 4 A schematic diagram of the waveforms of the scanning signal and the data signal;

[0026] Figure 7 This is a schematic diagram of the array substrate structure in Embodiment 1 of the present invention;

[0027] Figure 8 This is a schematic diagram of the array substrate structure in Embodiment 2 of the present invention;

[0028] Figure 9 This is a schematic diagram of the array substrate structure in Embodiment 3 of the present invention;

[0029] Figure 10 This is a schematic diagram of the array substrate structure in Embodiment 4 of the present invention;

[0030] Figure 11 This is a schematic diagram of the array substrate structure in Embodiment 5 of the present invention;

[0031] Figure 12 This is a schematic diagram of the array substrate structure in Embodiment Six of the present invention;

[0032] Figure 13 This is a schematic diagram of the display device in the black state in this invention;

[0033] Figure 14 This is a schematic diagram of the arrangement structure of R / G / B color filters on the color filter substrate in this invention;

[0034] Figure 15 This is a schematic diagram of the display device in the white state in this invention. Detailed Implementation

[0035] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate, display panel, and display device proposed according to the present invention:

[0036] [Example 1]

[0037] Figure 7 This is a schematic diagram of the array substrate in Embodiment 1 of the present invention, as shown below. Figure 7 As shown in Embodiment 1 of the present invention, an array substrate is provided. The array substrate has multiple scan lines and multiple data lines. The scan lines and data lines are mutually insulated and intersect each other, defining multiple sub-pixel units P arranged in an array. Two adjacent data lines are designated as a first data line 21 and a second data line 22, which are arranged alternately. That is, in any two adjacent data lines, one data line is defined as the first data line 21, and the other as the second data line 22. Adjacent sub-pixel units P are connected to different data lines. In each row, adjacent sub-pixel units P are connected to different data lines, and in each column, adjacent sub-pixel units P are also connected to different data lines.

[0038] The array substrate has multiple repeating unit areas, each containing multiple columns of sub-pixel units P. All first data lines 21 within each repeating unit area are electrically connected to each other, and all second data lines 22 within each repeating unit area are electrically connected to each other. The corresponding first data lines 21 and second data lines 22 within each repeating unit area can be electrically connected to each other in the non-display area, or they can be bonded to the same pad, thereby applying the same data signal to all first data lines 21 and all second data lines 22. However, data signals of different polarities are applied to the first data lines 21 and second data lines 22, thus requiring only one inversion per frame to achieve pixel inversion.

[0039] Each repeating unit area contains N columns of sub-pixel units P, N / 2 first data lines 21, and N / 2 second data lines 22, where N is a positive even number greater than or equal to 4. For example, each repeating unit area may contain 4 columns of sub-pixel units P, 2 first data lines 21, and 2 second data lines 22; alternatively, each repeating unit area may contain 6 columns of sub-pixel units P, 3 first data lines 21, and 3 second data lines 22. The specific number of sub-pixel units P, first data lines 21, and second data lines 22 can be set according to actual needs.

[0040] Two adjacent scan lines are designated as first scan line 11 and second scan line 12. First scan line 11 and second scan line 12 are arranged alternately; that is, in any two adjacent scan lines, one scan line is defined as first scan line 11, and the other as second scan line 12. Each row of sub-pixel units P is provided with a corresponding first scan line 11 and second scan line 12. A first scan line 11 and a second scan line 12 are provided between adjacent rows of sub-pixel units P. The first scan line 11 is located above the corresponding row of sub-pixel units P, and the second scan line 12 is located below the corresponding row of sub-pixel units P. Each sub-pixel unit P in each row is selectively electrically connected to either the first scan line 11 or the second scan line 12.

[0041] In this embodiment, in the same row of sub-pixel units P within each repeating unit area, the sub-pixel units P connected by two adjacent first data lines 21 are respectively connected to different scan lines, and the sub-pixel units P connected by two adjacent second data lines 22 are respectively connected to different scan lines.

[0042] like Figure 7As shown, in the same row of sub-pixel units P within each repeating unit area, the sub-pixel units P connected by the odd number of first data lines 21 are all electrically connected to the first scan line 11, and the sub-pixel units P connected by the even number of first data lines 21 are all electrically connected to the second scan line 12; the sub-pixel units P connected by the odd number of second data lines 22 are all electrically connected to the first scan line 11, and the sub-pixel units P connected by the even number of second data lines 22 are all electrically connected to the second scan line 12.

[0043] In this embodiment, within each repeating unit area, all sub-pixel units P connected to the same first data line 21 are connected to either the first scan line 11 or the second scan line 12; similarly, all sub-pixel units P connected to the same second data line 22 are connected to either the first scan line 11 or the second scan line 12. That is, all sub-pixel units P connected to the same data line are connected to the same type of scan line (wherein, scan lines of the same type are not necessarily the same scan line), either all connected to the first scan line 11 or all connected to the second scan line 12.

[0044] like Figure 7 As shown, in each repeating unit area, the sub-pixel units P connected by the odd number of first data lines 21 are all electrically connected to the first scan line 11, and the sub-pixel units P connected by the even number of first data lines 21 are all electrically connected to the second scan line 12; the sub-pixel units P connected by the odd number of second data lines 22 are all electrically connected to the first scan line 11, and the sub-pixel units P connected by the even number of second data lines 22 are all electrically connected to the second scan line 12.

[0045] [Example 2]

[0046] Figure 8 This is a schematic diagram of the array substrate structure in Embodiment 2 of the present invention, as shown below. Figure 8 As shown, the array substrate provided in Embodiment 2 of the present invention is similar to that in Embodiment 1. Figure 7 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0047] In the same row of sub-pixel units P within each repeating unit area, the sub-pixel units P connected by the odd number of first data lines 21 are all electrically connected to the second scan line 12, and the sub-pixel units P connected by the even number of first data lines 21 are all electrically connected to the first scan line 11; the sub-pixel units P connected by the odd number of second data lines 22 are all electrically connected to the second scan line 12, and the sub-pixel units P connected by the even number of second data lines 22 are all electrically connected to the first scan line 11.

[0048] like Figure 8As shown, within each repeating unit area, the sub-pixel units P connected by the odd number of first data lines 21 are all electrically connected to the second scan line 12, and the sub-pixel units P connected by the even number of first data lines 21 are all electrically connected to the first scan line 11; the sub-pixel units P connected by the odd number of second data lines 22 are all electrically connected to the second scan line 12, and the sub-pixel units P connected by the even number of second data lines 22 are all electrically connected to the first scan line 11.

[0049] Compared to Embodiment 1, the timing of the activation of the sub-pixel unit P in this application is different. Different timing signals can be used for driving, and a similar display effect can be achieved.

[0050] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0051] [Example 3]

[0052] Figure 9 This is a schematic diagram of the array substrate structure in Embodiment 3 of the present invention, as shown below. Figure 9 As shown, the array substrate provided in Embodiment 3 of the present invention is similar to that in Embodiment 1 ( Figure 7 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0053] In the same row of sub-pixel units P within each repeating unit area, the sub-pixel units P connected by the odd number of first data lines 21 are all electrically connected to the second scan line 12, and the sub-pixel units P connected by the even number of first data lines 21 are all electrically connected to the first scan line 11; the sub-pixel units P connected by the odd number of second data lines 22 are all electrically connected to the first scan line 11, and the sub-pixel units P connected by the even number of second data lines 22 are all electrically connected to the second scan line 12.

[0054] In other embodiments, within the same row of sub-pixel units P in each repeating unit area, the odd number of sub-pixel units P connected by the first data lines 21 may all be electrically connected to the first scan line 11, and the even number of sub-pixel units P connected by the first data lines 21 may all be electrically connected to the second scan line 12; the odd number of sub-pixel units P connected by the second data lines 22 may all be electrically connected to the second scan line 12, and the even number of sub-pixel units P connected by the second data lines 22 may all be electrically connected to the first scan line 11.

[0055] like Figure 9As shown, within each repeating unit area, the sub-pixel units P connected by the odd number of first data lines 21 are all electrically connected to the second scan line 12, and the sub-pixel units P connected by the even number of first data lines 21 are all electrically connected to the first scan line 11; the sub-pixel units P connected by the odd number of second data lines 22 are all electrically connected to the first scan line 11, and the sub-pixel units P connected by the even number of second data lines 22 are all electrically connected to the second scan line 12.

[0056] Compared to Embodiment 1, the timing of the activation of the sub-pixel unit P in this application is different. Different timing signals can be used for driving, and a similar display effect can be achieved.

[0057] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0058] [Example 4]

[0059] Figure 10 This is a schematic diagram of the array substrate structure in Embodiment 4 of the present invention, as shown below. Figure 10 As shown, the array substrate provided in Embodiment 4 of the present invention is similar to that in Embodiment 1 ( Figure 7 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0060] Within each repeating unit area, two adjacent sub-pixel units P connected to the same first data line 21 are respectively connected to the first scan line 11 and the second scan line 12; two adjacent sub-pixel units P connected to the same second data line 22 are respectively connected to the first scan line 11 and the second scan line 12.

[0061] like Figure 7 As shown, in each repeating unit area, in the odd-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11, and the even-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12; the odd-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11, and the even-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12. In each repeating unit area, in the even-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12, and the even-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11; the odd-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12, and the even-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11.

[0062] Compared to Embodiment 1, the timing of the activation of the sub-pixel unit P in this application is different. Different timing signals can be used for driving, and a similar display effect can be achieved.

[0063] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0064] [Example 5]

[0065] Figure 11 This is a schematic diagram of the array substrate in Embodiment 5 of the present invention, as shown below. Figure 11 As shown, the array substrate provided in Embodiment 5 of the present invention is similar to that in Embodiment 1 ( Figure 7 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0066] Within each repeating unit area, two adjacent sub-pixel units P connected to the same first data line 21 are respectively connected to the first scan line 11 and the second scan line 12; two adjacent sub-pixel units P connected to the same second data line 22 are respectively connected to the first scan line 11 and the second scan line 12.

[0067] like Figure 7 As shown, in each repeating unit area, in the odd-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12, and the even-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11; the odd-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12, and the even-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11. In each repeating unit area, in the even-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11, and the even-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12; the odd-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11, and the even-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12.

[0068] Compared to Embodiment 1, the timing of the activation of the sub-pixel unit P in this application is different. Different timing signals can be used for driving, and a similar display effect can be achieved.

[0069] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0070] [Example 6]

[0071] Figure 12This is a schematic diagram of the array substrate in Embodiment Six of the present invention, as shown below. Figure 12 As shown, the array substrate provided in Embodiment Six of the present invention is similar to that in Embodiment One ( Figure 7 The array substrates in this embodiment are basically the same, except that in this embodiment:

[0072] Within each repeating unit area, two adjacent sub-pixel units P connected to the same first data line 21 are respectively connected to the first scan line 11 and the second scan line 12; two adjacent sub-pixel units P connected to the same second data line 22 are respectively connected to the first scan line 11 and the second scan line 12.

[0073] like Figure 7 As shown, in each repeating unit area, in the odd-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12, and the even-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11; the odd-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11, and the even-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12. In each repeating unit area, in the even-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11, and the even-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12; the odd-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12, and the even-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11.

[0074] In other embodiments, in each repeating unit area, in the odd-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11, and the even-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12; the odd-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12, and the even-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11. In each repeating unit area, in the even-numbered rows of sub-pixel units P, the odd-numbered first data lines 21 connect the sub-pixel units P to the second scan line 12, and the even-numbered first data lines 21 connect the sub-pixel units P to the first scan line 11; the odd-numbered second data lines 22 connect the sub-pixel units P to the first scan line 11, and the even-numbered second data lines 22 connect the sub-pixel units P to the second scan line 12.

[0075] Compared to Embodiment 1, the timing of the activation of the sub-pixel unit P in this application is different. Different timing signals can be used for driving, and a similar display effect can be achieved.

[0076] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0077] Figure 13 This is a schematic diagram of the display device in the black state according to the present invention. Figure 14 This is a schematic diagram of the arrangement structure of R / G / B color filters on the color filter substrate in this invention. Figure 15 This is a schematic diagram of the display device in the white state in this invention, as shown below. Figures 13 to 15 As shown, the present invention also provides a display device, including a display panel 30 and a backlight module 40, wherein the backlight module 40 is located below the display panel 30 and is used to provide a backlight source for the display panel 30.

[0078] The backlight module 40 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 40 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect.

[0079] The backlight module 40 includes a backlight source 41 and a privacy layer 43, which reduces the range of light emission angles. A brightness enhancement film 42 is also provided between the backlight source 41 and the privacy layer 43, increasing the brightness of the backlight module 40. The privacy layer 43 acts like a miniature venetian blind, blocking light with a large incident angle while allowing light with a smaller incident angle to pass through, thus reducing the range of light angles passing through the privacy layer 43. The privacy layer 43 includes multiple parallel light-blocking walls and light-transmitting holes located between adjacent light-blocking walls. Light-absorbing material is provided on both sides of the light-blocking walls. Alternatively, the backlight source 41 can be a light-collecting backlight, eliminating the need for a privacy layer 43; however, light-collecting backlights are more expensive than conventional backlights.

[0080] like Figures 13 to 15 As shown, this application also provides a display panel 30 for use in the display device described above. The display panel 30 includes a color filter substrate 31 and an array substrate 32 as described above. The color filter substrate 31 and the array substrate 32 are disposed opposite to each other, and a liquid crystal layer 33 is disposed between the color filter substrate 31 and the array substrate 32. The liquid crystal layer 33 preferably uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy. In the initial state, the positive liquid crystal molecules in the liquid crystal layer 33 are aligned parallel to the color filter substrate 31 and the array substrate 32, and the alignment direction of the positive liquid crystal molecules on the side closer to the color filter substrate 31 is parallel or antiparallel to the alignment direction of the positive liquid crystal molecules on the side closer to the array substrate 32. Of course, in other embodiments, the liquid crystal layer 33 may also use negative liquid crystal molecules, and the negative liquid crystal molecules in the liquid crystal layer 33 may be aligned perpendicular to the color filter substrate 31 and the array substrate 32, that is, similar to the alignment method of VA display mode.

[0081] The color filter substrate 31 has color resist layers 312 arranged in an array and black matrices 311 separating the color resist layers 312. The color resist layers 312 include red (R), green (G), and blue (B) color resist materials, and correspondingly form red (R), green (G), and blue (B) sub-pixel units. Figure 13 As shown, the color filters on the color filter substrate 31 are arranged in a conventional red (R), green (G), and blue (B) arrangement, that is, one column of red (R) color filters, one column of green (G) color filters, and one column of blue (B) color filters form a repeating cycle, and are arranged sequentially on the color filter substrate 31.

[0082] In this embodiment, a common electrode 321 is also provided on the side of the array substrate 32 facing the liquid crystal layer 33. The common electrode 321 and the pixel electrode 322 are located on different layers and are insulated from each other by an insulating layer. The common electrode 321 may be located above or below the pixel electrode 322. Figure 13 The diagram shows the common electrode 321 located below the pixel electrode 322. Preferably, the common electrode 321 is a planar electrode disposed across the entire surface, and the pixel electrode 322 is a block electrode disposed within each pixel unit or a slit electrode with multiple electrode strips, to form a fringe field switching (FFS) mode. Of course, in other embodiments, the pixel electrode 322 and the common electrode 321 may be located on the same layer, but they are insulated from each other. Both the pixel electrode 322 and the common electrode 321 may include multiple electrode strips, and the electrode strips of the pixel electrode 322 and the common electrode 321 are arranged alternately to form an in-plane switching (IPS) mode; or, in other embodiments, the array substrate 32 has a pixel electrode 322 on the side facing the liquid crystal layer 33, and the color filter substrate 31 has a common electrode 321 on the side facing the liquid crystal layer 33 to form a TN mode or a VA mode.

[0083] The color filter substrate 31 and the array substrate 32 can be made of materials such as glass, acrylic, and polycarbonate. The common electrode 321 and the pixel electrode 322 can be made of materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0084] The color filter substrate 31 is provided with an upper polarizer 51, and the array substrate 32 is provided with a lower polarizer 52. The light transmission axes of the upper polarizer 51 and the lower polarizer 52 are perpendicular to each other.

[0085] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, The array substrate is provided with multiple scan lines and multiple data lines. The multiple scan lines and multiple data lines are mutually insulated and cross each other to form multiple sub-pixel units (P) distributed in an array. Two adjacent data lines are respectively a first data line (21) and a second data line (22). The first data line (21) and the second data line (22) are arranged alternately. Two adjacent sub-pixel units (P) are respectively connected to different data lines. The array substrate is provided with multiple repeating unit areas, each repeating unit area having multiple columns of sub-pixel units (P), all the first data lines (21) in each repeating unit area are electrically connected to each other, and all the second data lines (22) in each repeating unit area are electrically connected to each other. The two adjacent scan lines are a first scan line (11) and a second scan line (12), which are arranged alternately. Each row of sub-pixel units (P) is provided with the first scan line (11) and the second scan line (12). The first scan line (11) and the second scan line (12) are provided between two adjacent rows of sub-pixel units (P). The first scan line (11) is located on the upper side of the corresponding row of sub-pixel units (P), and the second scan line (12) is located on the lower side of the corresponding row of sub-pixel units (P). Each row of sub-pixel units (P) is selectively electrically connected to the first scan line (11) and the second scan line (12). Within each repeating unit area, all sub-pixel units (P) connected to the same first data line (21) are connected to the first scan line (11) or the second scan line (12); all sub-pixel units (P) connected to the same second data line (22) are connected to the first scan line (11) or the second scan line (12); In the same row of sub-pixel units (P) within each repeating unit area, the sub-pixel units (P) connected by two adjacent first data lines (21) are respectively connected to different scan lines, and the sub-pixel units (P) connected by two adjacent second data lines (22) are respectively connected to different scan lines; In each row of sub-pixel units (P) within the repeating unit area, the odd-numbered sub-pixel units (P) connected by the first data lines (21) are electrically connected to the second scan line (12), and the even-numbered sub-pixel units (P) connected by the first data lines (21) are electrically connected to the first scan line (11); in each row of sub-pixel units (P) within the repeating unit area, the odd-numbered sub-pixel units (P) connected by the second data lines (22) are electrically connected to the second scan line (12), and the even-numbered sub-pixel units (P) connected by the second data lines (22) are electrically connected to the first scan line (11).

2. A display panel, characterized in that, The system includes a color filter substrate (31) and an array substrate (32) as described in claim 1. The color filter substrate (31) and the array substrate (32) are disposed opposite to each other. A liquid crystal layer (33) is disposed between the color filter substrate (31) and the array substrate (32). An upper polarizer (51) is disposed on the color filter substrate (31), and a lower polarizer (52) is disposed on the array substrate (32). The light transmission axes of the upper polarizer (51) and the lower polarizer (52) are perpendicular to each other.

3. A display device, characterized in that, Includes the display panel (30) as described in claim 2.

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