Display device

Abstract

Disclosed is a display device including a display panel including a first area and a second area, and a sensing module located on a rear side of the display panel. The first area includes a first pixel area displaying an image. The second area includes a second pixel area displaying an image and a transmission area transmitting light output by the sensing module. The second area is superposed with the sensing module. The second pixel area is superposed with a first layer blocking the light output by the sensing module. The transmission area is not superposed with the first layer.

Description

[0001] This application is a divisional application of the invention patent application filed on October 28, 2019, with application number "201911027896.1" and invention title "Display Device". Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] Light-emitting diode (LED) displays are self-emissive, meaning they do not require a separate light source, thus reducing the thickness and weight of the display. Furthermore, LED displays offer additional desirable characteristics such as low power consumption, high brightness, and high response time. Typically, an LED display comprises a substrate, multiple transistors mounted on the substrate, and light-emitting devices connected to the transistors. Summary of the Invention

[0004] An exemplary embodiment provides a display device including: a display panel including a first region and a second region; and a sensing module located on the rear side of the display panel. The first region includes a first pixel region for displaying an image. The second region is superimposed on the sensing module. The second region includes a second pixel region for displaying an image and a transmissive region for transmitting light output from the sensing module. The second pixel region is superimposed on a first layer that blocks light output from the sensing module, and the transmissive region is not superimposed on the first layer.

[0005] The second pixel region may include multiple transistors, and the first layer may be stacked with all the transistors.

[0006] The second pixel region may include multiple transistors, and the first layer may be stacked with some of the transistors.

[0007] The transmission area can be separated from the first layer in the plan view.

[0008] The first pixel region can be separated from the first layer in the planar diagram.

[0009] The first pixel area can be superimposed on the first layer.

[0010] The first layer can be overlaid on a portion of the first pixel region.

[0011] The first pixel region may include multiple transistors, and the first layer may be stacked with some of the transistors.

[0012] The second pixel region may include multiple transistors, and the first layer may be stacked with at least one of the transistors.

[0013] The first pixel region does not need to be superimposed on the first layer.

[0014] The first pixel region may include a first layer stacked with some of the transistors among a plurality of transistors, and the second pixel region may be stacked with more layers than the first pixel region.

[0015] The area occupied by the transmission region can be 20% to 90% of the second region.

[0016] The display panel may include a first substrate on which transistors are disposed, and the first layer may be located between the sensing module and the transistors.

[0017] Another embodiment provides a display device comprising: a display panel including a first region and a second region; and a sensing module located on the rear side of the display panel. The second region is superimposed on the sensing module. The first region includes a first pixel region for displaying an image. The second region includes a second pixel region for displaying an image and a transmissive region for transmitting light output from the sensing module. For the same region, the superposition percentage of the first layer in the first pixel region is different from the superposition percentage of the first layer in the second pixel region, and the first layer blocks the light output from the sensing module.

[0018] The transmission region may not be superimposed on the first layer.

[0019] The first pixel region may not overlap with the first layer, and at least a portion of the second pixel region may overlap with the first layer.

[0020] The entire second pixel area can be overlaid with the first layer.

[0021] A portion of the first pixel region can be superimposed on the first layer, and the entire second pixel region can be superimposed on the first layer.

[0022] The first layer superimposed on the first pixel region can receive a predetermined voltage. Attached Figure Description

[0023] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0024] Figure 1 A top view of a display device according to an exemplary embodiment is shown.

[0025] Figure 2 It shows relative to Figure 1 A sectional view of line II-II'.

[0026] Figure 3 A circuit diagram of the first pixel region according to an exemplary embodiment is shown.

[0027] Figure 4 It shows according to Figure 3 A top view of the first pixel region of an exemplary embodiment.

[0028] Figure 5 A circuit diagram of the second pixel region according to an exemplary embodiment is shown.

[0029] Figure 6 It shows according to Figure 5 A top view of the second pixel region of an exemplary embodiment.

[0030] Figure 7 It shows relative to Figure 6 A sectional view of line VII-VII'.

[0031] Figure 8 A top view of the transmission region according to an exemplary embodiment is shown.

[0032] Figure 9 A circuit diagram of the first pixel region according to an exemplary embodiment is shown.

[0033] Figure 10 It shows Figure 9 A top view of the first pixel region.

[0034] Figure 11 A circuit diagram of the first pixel region according to an exemplary embodiment is shown.

[0035] Figure 12 It shows Figure 11 A top view of the first pixel region.

[0036] Figure 13 A circuit diagram of the second pixel region according to an exemplary embodiment is shown.

[0037] Figure 14 It shows Figure 13 A top view of the second pixel region.

[0038] Figure 15 A circuit diagram of the second pixel region according to an exemplary embodiment is shown.

[0039] Figure 16 It shows Figure 15 A top view of the second pixel region. Detailed Implementation

[0040] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementation methods to those skilled in the art.

[0041] The accompanying drawings and descriptions are to be regarded as illustrative rather than restrictive in nature, and the same reference numerals denote the same elements throughout the specification.

[0042] For better understanding and ease of description, the dimensions and thicknesses of each structure shown in the accompanying drawings are arbitrarily illustrated. The thicknesses of layers, films, panels, regions, etc., are exaggerated in the drawings for clarity. The thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0043] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. The terms "on" or "above" refer to being located on or below the target portion, and the direction based on gravity does not necessarily indicate being located on the upper side of the target portion.

[0044] Unless explicitly stated otherwise, the word “includes” and its variations shall be understood to mean that the stated element is included, but not that any other element is excluded.

[0045] The phrase "on a plane" refers to viewing a part of the target from above, while the phrase "on a cross-section" refers to viewing a vertically cut section of the target from the side.

[0046] Throughout the specification, plan views represent views of sides parallel to two intersecting directions (e.g., first direction D1 and second direction D2), and sectional views represent views of sides cut in a direction perpendicular to the sides parallel to the first direction D1 and second direction D2 (e.g., third direction D3). Furthermore, when two constituent elements are superimposed on each other, it means that the two constituent elements are superimposed on each other in the third direction D3 (e.g., in a direction perpendicular to the upper side of the base).

[0047] Now refer to Figure 1 and Figure 2 A display device according to an exemplary embodiment is described. Figure 1 A top view of a display device according to an exemplary embodiment is shown. Figure 2 It shows relative to Figure 1 A sectional view of line II-II'.

[0048] Reference Figure 1 The display device 1000 according to an exemplary embodiment includes a display area. The display device 1000 can display an image across its entire front. The front of the display device 1000 may not include a border or a non-display area, or it may include a non-display area disposed on the edge of the display device 1000.

[0049] The display area may include a first area DA1 for displaying an image and a second area DA2 for displaying an image and having other functions. The second area DA2 may receive or transmit light with wavelengths different from the wavelength of the light of the displayed image much more than the first area DA1; that is, the second area DA2 may be more transparent for different wavelengths compared to the first area DA1.

[0050] In the plan view, the second region DA2 can be surrounded by the first region DA1 and can be located near the first side of the display device 1000. The second region DA2 can be disposed at various positions on the display device 1000, can have various planar forms, and can contact the first region DA1 on all sides, three sides, or two sides.

[0051] The first region DA1 includes a plurality of first pixel regions PX1. The second region DA2 may include a plurality of second pixel regions PX2 and a transmission region TA. In this specification, the first pixel region PX1, the second pixel region PX2, and the transmission region TA may represent the smallest region distinguished by signal lines extending in the first direction D1 and the second direction D2.

[0052] The first pixel region PX1 and the second pixel region PX2 may each include multiple transistors and light-emitting devices. Except for the difference in the stacking state of the first layer and the area occupied by the first layer, the actual arrangement of the first pixel region PX1 and the second pixel region PX2 according to the exemplary embodiment may be the same. The arrangement of the transistors, capacitors, and light-emitting devices included in the first pixel region PX1 and the second pixel region PX2 may be the same. A detailed arrangement of the first pixel region PX1 and the second pixel region PX2 will be described later.

[0053] For the same region, the area of ​​the first layer overlapping with the first pixel region PX1 can be different from the area of ​​the first layer overlapping with the second pixel region PX2. For example, the area of ​​the first layer overlapping with the first pixel region PX1 can be smaller than the area of ​​the first layer overlapping with the second pixel region PX2. In other words, the percentage of overlap of the first layer in the first pixel region PX1 and the second pixel region PX2 is different for the same region; for example, for the same region, the overlap in the second pixel region PX2 is larger than that in the first pixel region PX1. A detailed construction will be described later.

[0054] The proportion of the area used to display the image (i.e., the proportion of the area occupied by the second pixel region PX2 in the second region DA2) can be smaller than the proportion of the area occupied by the first pixel region PX1 in the first region DA1. In the first region DA1, multiple first pixel regions PX1 can be arranged in a matrix. In the second region DA2, multiple second pixel regions PX2 and transmission regions TA can be arranged alternately, or they can be arranged in various ways. The second region DA2 includes multiple transmission regions TA, therefore the proportion of the second pixel region PX2 can be smaller compared to the first region DA1, which has the same area.

[0055] The transmissive region TA may not include pixel circuitry (e.g., electrodes, transistors, or light-emitting devices). For example, the transmissive region TA may not include light-emitting devices and may be a non-emitting region.

[0056] For example, the area of ​​the transmissive region TA can be approximately 20% to 90% of the area of ​​the second region DA2. The second region DA2 includes the second pixel region PX2 and the transmissive region TA, so the second region DA2 can be partially transparent. At least for different wavelengths, the transmissive region TA has greater transmittance than the second pixel region PX2, and the second region DA2 has greater transmittance than the first region DA1.

[0057] Most light of different wavelengths (e.g., infrared light) incident on the transmission region TA can pass through the transmission region TA. The emitting layer is not located in the transmission region TA, therefore no image is displayed.

[0058] Reference Figure 1 and Figure 2 The display device 1000 according to an exemplary embodiment may include a sensing module 500 disposed on the rear side of the display panel 100. For example, the sensing module 500 may recognize specific patterns, such as biometric features such as fingerprints, irises, or faces.

[0059] The sensing module 500 can transmit light within a predetermined wavelength toward a target 600 disposed on the display panel 100, or it can receive light reflected from the target 600. The predetermined wavelength can be any wavelength other than visible light, which will be processed by the sensing module 500. Light within the predetermined wavelength can primarily pass through the transmission region TA disposed in the second region DA2. The light within the predetermined wavelength output by the sensing module 500 can be, for example, infrared light of approximately 900 nm to 1000 nm. In a plan view, the sensing module 500 can correspond to all or part of the second region DA2.

[0060] Now refer to Figures 3 to 8 The first pixel region, the second pixel region, and the transmissive region according to an exemplary embodiment are described in detail. Figure 3A circuit diagram of the first pixel region according to an exemplary embodiment is shown. Figure 4 A top view of the first pixel region according to an exemplary embodiment is shown. Figure 5 A circuit diagram of the second pixel region according to an exemplary embodiment is shown. Figure 6 A top view of the second pixel region according to an exemplary embodiment is shown. Figure 7 A cross-sectional view of the second pixel region according to an exemplary embodiment is shown. Figure 8 A top view of the transmission region according to an exemplary embodiment is shown.

[0061] Reference Figure 3 According to an exemplary embodiment, the first pixel region PX1 includes a plurality of transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, and light-emitting diodes (LEDs) connected to signal lines 127, 151, 152, 153, 158, 171, 172 and 741.

[0062] The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, a switching transistor connected to the first scan line 151 (i.e., the second transistor T2 and the third transistor T3), and other transistors (hereinafter, compensation transistors) for performing the operation of operating the light-emitting diode (LED). The compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0063] Multiple signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a first scan line 151, a second scan line 152, a transmit control line 153, a bypass control line 158, a data line 171, a drive voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may be part of the second scan line 152 or may be electrically connected to the second scan line 152.

[0064] The first scan line 151 is connected to the gate driver to transmit the scan signal (or first scan signal) Sn to the second transistor T2 and the third transistor T3. The second scan line 152 is connected to the gate driver to transmit the second scan signal Sn-1, applied to the first pixel region PX1 located in the forward direction, to the fourth transistor T4. The emission control line 153 is connected to the emission controller to transmit the emission control signal EM, used to control when the light-emitting diode (LED) emits light, to the fifth transistor T5 and the sixth transistor T6. The bypass control line 158 transmits the bypass signal GB to the seventh transistor T7.

[0065] Data line 171 transmits the data voltage Dm generated by the data driver, and the brightness of the light emitted by the light-emitting diode (LED) varies according to the data voltage Dm. Drive voltage line 172 applies the drive voltage ELVDD. Initialization voltage line 127 transmits the initialization voltage Vint used to initialize the drive transistor T1. Common voltage line 741 applies the common voltage ELVSS. Predetermined voltages can be applied to drive voltage line 172, initialization voltage line 127, and common voltage line 741.

[0066] The driving transistor T1 controls the current output according to the applied data voltage Dm. The output driving current Id is applied to the light-emitting diode (LED) to control the brightness of the LED according to the data voltage Dm. For this purpose, the first electrode S1 of the driving transistor T1 receives the driving voltage ELVDD. The first electrode S1 is connected to the driving voltage line 172 through the fifth transistor T5. The first electrode S1 of the driving transistor T1 is connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm. The second electrode D1 (output electrode) of the driving transistor T1 outputs current toward the LED. The second electrode D1 of the driving transistor T1 is connected to the anode of the LED through the sixth transistor T6. The gate electrode G1 of the driving transistor T1 is connected to one electrode (second storage electrode E2) of the storage capacitor Cst. The voltage at the gate electrode G1 varies according to the voltage stored in the storage capacitor Cst and is varied by the driving current Id output by the driving transistor T1.

[0067] The second transistor T2 receives the data voltage Dm. The second transistor T2 includes a gate electrode G2 connected to the first scan line 151, a first electrode S2 connected to the data line 171, and a second electrode D2 connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the first scan line 151, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0068] The third transistor T3 transmits the compensation voltage (the voltage of Dm+Vth) generated when the data voltage Dm passes through the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst. The third transistor T3 includes a gate electrode G3 connected to the first scan line 151, a first electrode S3 connected to the second electrode D1 of the driving transistor T1, and a second storage electrode E2 connected to both the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is turned on according to the scan signal Sn transmitted through the first scan line 151, connecting the gate electrode G1 and the second electrode D1 of the driving transistor T1, and connecting the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst.

[0069] The fourth transistor T4 initializes the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The fourth transistor T4 includes a gate electrode G4 connected to the second scan line 152, a first electrode S4 connected to the initialization voltage line 127, and a second storage electrode E2 connected to the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst according to the second scan signal Sn-1 received via the second scan line 152. Therefore, the gate voltage at the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 is initialized. The initialization voltage Vint has a low voltage value to turn on the driving transistor T1.

[0070] The fifth transistor T5 transmits the drive voltage ELVDD to the drive transistor T1. The fifth transistor T5 includes a gate electrode G5 connected to the emitter control line 153, a first electrode S5 connected to the drive voltage line 172, and a second electrode D5 connected to the first electrode S1 of the drive transistor T1.

[0071] The sixth transistor T6 transmits the drive current Id output by the driving transistor T1 to the light-emitting diode LED. The sixth transistor T6 includes a gate electrode G6 connected to the emission control line 153, a first electrode S6 connected to the second electrode D1 of the driving transistor T1, and a second electrode D6 connected to the anode of the light-emitting diode LED.

[0072] The fifth transistor T5 and the sixth transistor T6 are turned on by the emitter control signal EM received via emitter control line 153. When the drive voltage ELVDD is applied to the first electrode S1 of the drive transistor T1 through the fifth transistor T5, the drive transistor T1 outputs a drive current Id according to the voltage at the gate electrode G1 of the drive transistor T1 (i.e., the voltage at the second storage electrode E2 of the storage capacitor Cst). The output drive current Id is transmitted to the light-emitting diode LED through the sixth transistor T6. When the current Id... led When the current flows to the LED, the LED emits light.

[0073] The seventh transistor T7 initializes the anode of the light-emitting diode (LED). The seventh transistor T7 includes a gate electrode G7 connected to the bypass control line 158, a first electrode S7 connected to the anode of the LED, and a second electrode D7 connected to the initialization voltage line 127. The bypass control line 158 can be connected to the second scan line 152, and a signal with the same timing as the second scan signal Sn-1 is applied to the bypass signal GB. The bypass control line 158 may not be connected to the second scan line 152 and may transmit a signal different from the second scan signal Sn-1. When the seventh transistor T7 is turned on via the bypass signal GB, the initialization voltage Vint is applied to the anode of the LED to be initialized.

[0074] The storage capacitor Cst includes a first storage electrode E1 connected to the drive voltage line 172 and a second storage electrode E2 connected to the gate electrode G1 of the drive transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 determines the voltage at the gate electrode G1 of the drive transistor T1 and receives a compensation voltage (Dm+Vth) through the second electrode D3 of the third transistor T3 or an initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0075] The anode of the light-emitting diode (LED) is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7. The cathode of the LED is connected to the common voltage line 741 used to transmit the common voltage ELVSS.

[0076] In reference Figure 3 In the exemplary embodiment described, the circuitry of the first pixel region PX1 includes seven transistors T1 to T7 and one capacitor Cst. The number of transistors and capacitor and their connections are variable in various ways.

[0077] Now refer to Figure 4 Describes the detailed planar structure of the first pixel region PX1. (Refer to...) Figure 4 The first pixel region PX1 includes a first scan line 151 extending along the first direction D1 and transmitting a first scan signal Sn, a second scan line 152 for transmitting a second scan signal Sn-1, a transmission control line 153 for transmitting a transmission control signal EM, and an initialization voltage line 127 for transmitting an initialization voltage Vint. A bypass signal GB is transmitted through the second scan line 152.

[0078] The display device 1000 includes a data line 171 extending along a second direction D2 that intersects a first direction D1 and transmitting a data voltage Dm, and a drive voltage line 172 for transmitting a drive voltage ELVDD.

[0079] The display device 1000 includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light-emitting diode (LED).

[0080] The corresponding channels of driving transistors T1, T2, T3, T4, T5, T6, and T7 are disposed in a semiconductor layer 130 extending along a first direction D1 and a second direction D2. Furthermore, at least some of the first and second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are located on the semiconductor layer 130. Semiconductor layer (130; as shown) Figure 4 (As shown in the shaded area) can be formed to be bent in various ways. Semiconductor layer 130 may include polycrystalline semiconductors such as polycrystalline silicon or oxide semiconductors.

[0081] Semiconductor layer 130 includes a channel doped with n-type or p-type impurities and a first doped region and a second doped region disposed on corresponding sides of the channel and having a doping concentration greater than that of the channel. The first doped region and the second doped region correspond to the first electrode and the second electrode of a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, respectively. When one of the first doped region and the second doped region is a source region, the other can be a drain region. Furthermore, the region between the first electrode and the second electrode of different transistors can be doped in semiconductor layer 130, allowing the two transistors to be electrically connected to each other.

[0082] The corresponding channels of multiple transistors T1, T2, T3, T4, T5, T6, and T7 are stacked with the gate electrodes of transistors T1, T2, T3, T4, T5, T6, and T7, and are disposed between the first and second electrodes of transistors T1, T2, T3, T4, T5, T6, and T7. The multiple transistors T1, T2, T3, T4, T5, T6, and T7 can have substantially the same stacked structure. The driving transistor T1 will be described in detail, while the other transistors T2, T3, T4, T5, T6, and T7 will be described briefly.

[0083] The driving transistor T1 includes a channel and a first gate electrode 155. Figure 3The first electrode S1 and the second electrode D1 are described in the diagram. The channel of the driving transistor T1 is located between the first electrode S1 and the second electrode D1, and is superimposed on the first gate electrode 155 in the plan view. The channel is curved so that it can be formed as long in a limited area along the main direction in which the channel extends (e.g., the first direction D1). As the channel becomes longer, the driving range of the gate voltage (Vg) applied to the first gate electrode 155 of the driving transistor T1 increases, and the driving current Id increases continuously according to the gate voltage (Vg). As a result, the gray level of the light output by the light-emitting diode LED can be precisely controlled by changing the magnitude of the gate voltage (Vg), and the display quality of the display device 1000 can be improved. Furthermore, the channel extends in multiple directions instead of in one direction, thus offsetting the effects caused by directionality in the manufacturing process, and reducing the influence of process distribution as an advantage. Therefore, it is possible to prevent the degradation of display quality, such as stains (e.g., the difference in brightness between pixels when the characteristics of the driving transistor T1 vary according to the process distribution across different areas of the display device 1000), which can occur when the characteristics of the driving transistor T1 vary according to the process distribution across different areas of the display device 1000. In addition to the Ω shape shown, the above-described channel form can have various shapes.

[0084] The first gate electrode 155 is stacked with the channel in the plan view. The first electrode S1 and the second electrode D1 are located on corresponding sides of the channel. An extension of the storage line 126 is insulated from the first gate electrode 155 and disposed on the first gate electrode 155. The extension of the storage line 126 is stacked with the first gate electrode 155 in the plan view, and the second gate insulating layer 142 (see...) Figure 7 The storage capacitor Cst is located between storage line 126 and first gate electrode 155. An extension of storage line 126 is the first storage electrode of storage capacitor Cst. Figure 3 E1), and the first gate electrode 155 forms the second storage electrode ( Figure 3 (E2). Opening 56 is located in an extension of storage line 126, allowing the first gate electrode 155 to be connected to the first data connection member 71. In opening 56, the top side of the first gate electrode 155 is electrically connected to the first data connection member 71 via contact hole 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the first gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0085] The gate electrode of the second transistor T2 may be a part of the first scan line 151. The first electrode S2 of the second transistor T2 is connected to the data line 171 through the contact hole 62. The first electrode S2 and the second electrode D2 may be disposed on the semiconductor layer 130.

[0086] The third transistor T3 can be a dual-gate third transistor. A portion of the third transistor T3 extends along (e.g., perpendicular to each other) a first direction D1 and a second direction D2. The gate electrode of the third transistor T3 includes a portion of the first scan line 151 protruding along the second direction D2 and a portion of the first scan line 151 extending along the first direction D1. The aforementioned structure can be referred to as a dual-gate structure and can block the flow of leakage current. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through a contact hole 63.

[0087] The fourth transistor T4 can be a dual-gate fourth transistor T4 in which the second scan line 152 intersects with the semiconductor layer 130. The gate electrode of the fourth transistor T4 can be a portion of the second scan line 152. The second electrode D4 of the fourth transistor T4 is connected to the second electrode D3 of the third transistor T3. The aforementioned structure will be referred to as a dual-gate structure and blocks the flow of leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through a contact hole 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through a contact hole 63.

[0088] As described above, the dual-gate structure of the third transistor T3 and the fourth transistor T4 is used, thus blocking the electron movement path of the channel in the off state to effectively prevent leakage current from being generated.

[0089] The gate electrode of the fifth transistor T5 may be part of the emitter control line 153. The first electrode S5 of the fifth transistor T5 is connected to the drive voltage line 172 through the contact hole 67. The second electrode D5 is connected to the first electrode S1 of the drive transistor T1 through the semiconductor layer 130.

[0090] The gate electrode of the sixth transistor T6 may be part of the emitter control line 153. The second electrode D6 of the sixth transistor T6 is connected to the third data connection member 73 through the contact hole 69. The first electrode S6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0091] The gate electrode of the seventh transistor T7 can be part of the second scan line 152. The first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6. The second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0092] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 stacked on top of each other, and a second gate insulating layer 142 (see...). Figure 7The second gate insulating layer 142 is located between the first storage electrode E1 and the second storage electrode E2. The second storage electrode E2 corresponds to the first gate electrode 155 of the driving transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. Here, the second gate insulating layer 142 is a dielectric material, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. The first gate electrode 155 is used as the second storage electrode E2, so space can be obtained for forming the storage capacitor Cst in the space narrowed by the channel of the driving transistor T1 occupying a large area in the pixel.

[0093] The drive voltage line 172 is connected to the first storage electrode E1 through the contact hole 68. Therefore, the storage capacitor Cst stores the charge corresponding to the difference between the drive voltage ELVDD transmitted to the first storage electrode E1 through the drive voltage line 172 and the gate voltage (Vg) of the first gate electrode 155.

[0094] The second data connection member 72 is connected to the initialization voltage line 127 via the contact hole 64. The pixel electrode is connected to the third data connection member 73 via the contact hole 81.

[0095] A parasitic capacitor control pattern 79 can be disposed between the dual gate electrodes of the third transistor T3. The parasitic capacitor is disposed within the pixel, and its image quality characteristics change when the voltage applied to it varies. A drive voltage line 172 is connected to the parasitic capacitor control pattern 79 via a contact hole 66. This prevents changes in image quality characteristics caused by applying a drive voltage ELVDD, which is a constant DC voltage, to the parasitic capacitor. The parasitic capacitor control pattern 79 can be disposed in a region different from the area shown in the figures, and a voltage different from the drive voltage ELVDD can be applied.

[0096] The first end of the first data connection member 71 is connected to the first gate electrode 155 through the contact hole 61, and the second end of the first data connection member 71 is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0097] The first end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the second end of the second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64.

[0098] The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69.

[0099] Now refer to Figures 5 to 8 Describes a second region according to an exemplary embodiment. Figures 5 to 7The second pixel region of the second region is shown. Figure 8 The transmission region of the second area is shown.

[0100] According to an exemplary embodiment, the second pixel region PX2 may have the same pixel arrangement as the first pixel region PX1, but includes the first layer 30. (See also...) Figure 3 and Figure 4 The description provided for the first pixel region PX1 can be applied to the second pixel region PX2, so it will be omitted.

[0101] Figure 5 A circuit diagram is shown regarding the second pixel region PX2 having a first layer 30 superimposed on the second pixel region PX2. (Refer to...) Figure 5 and Figure 6 The first layer 30 can be disposed in front of the second pixel region PX2, for example, between the sensing module 500 and the transistors of the second pixel region PX2. Similar to the first pixel region PX1, the second pixel region PX2 includes seven transistors T1 to T7 and a capacitor Cst. According to an exemplary embodiment, the first layer 30 can be completely superimposed on the second pixel region PX2, for example, it can be superimposed on the seven transistors T1 to T7 and the capacitor Cst.

[0102] The first layer 30 is conductive and blocks light, such as infrared light, emitted from the sensing module 500. The first layer 30 may not receive any additional voltage, may have a predetermined voltage applied to it, or may be grounded. Applying a predetermined voltage prevents potential changes that occur when a specific charge is injected into the first layer 30.

[0103] Now refer to Figure 5 , Figure 6 and Figure 7 Describe the stacking structure of the second pixel region PX2.

[0104] The display panel 100 includes a first substrate 110. The first substrate 110 may include a plastic layer and a barrier layer. The plastic layer and the barrier layer may be stacked alternately.

[0105] The plastic layer may include one or a combination thereof, of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and poly(aryl ether sulfone). The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide, and is not limited thereto; the barrier layer may include any of the inorganic materials.

[0106] The first layer 30 can be disposed on the first substrate 110. The entire second pixel region PX2 can be stacked with the first layer 30. The first layer 30 is conductive and can include various conductive metals or semiconductor materials having conductive properties corresponding to various conductive metals. The first layer 30 can also block or absorb light output from the sensing module 500, such as infrared light.

[0107] The transmissive region TA can be set on all sides of the second pixel region PX2 (e.g., as shown in the image). Figure 1 As shown in the diagram (top, bottom, right, and left sides), the first layer 30 can be superimposed on corresponding second pixel regions PX2. For example, a single portion of the first layer 30 can correspond to a single second pixel region PX2, and another portion of the first layer 30 corresponding to another second pixel region PX2 can be separate from the single portion of the first layer 30. When multiple second pixel regions PX2 are adjacent (e.g., sharing a boundary), adjacent first layers 30 superimposed on adjacent second pixel regions PX2 can be connected.

[0108] The buffer layer 112 is located on the first layer 30. The buffer layer 112 may include inorganic insulating materials (such as silicon oxide, silicon nitride, aluminum oxide, etc.) or may include organic insulating materials (such as polyimide or acrylic, etc.).

[0109] The first and second electrodes of the semiconductor layer 130 including the channel and the multiple transistors T1, T2, T3, T4, T5, T6 and T7 are disposed on the buffer layer 112.

[0110] The first gate insulating layer 141 may cover the semiconductor layer 130. The first gate conductor, including the first gate electrode 155, the first scan line 151, the second scan line 152, and the emission control line 153, is located on the first gate insulating layer 141.

[0111] The second gate insulating layer 142 may cover the first gate conductor. The first gate insulating layer 141 and the second gate insulating layer 142 may include inorganic insulating materials or organic insulating materials such as silicon nitride, silicon oxide, and aluminum oxide.

[0112] A second gate conductor, including storage line 126, initialization voltage line 127, and parasitic capacitor control pattern 79, is disposed on the second gate insulating layer 142.

[0113] The interlayer insulating layer 160 may cover the second gate conductor. The interlayer insulating layer 160 may include inorganic or organic insulating materials such as silicon nitride, silicon oxide, or aluminum oxide.

[0114] The data conductors, including data line 171, drive voltage line 172, first data connection member 71, second data connection member 72, and third data connection member 73, are located on the interlayer insulating layer 160. The first data connection member 71 can be connected to the first gate electrode 155 through the contact hole 61.

[0115] The passivation layer 180 may cover the data conductor. The passivation layer 180 may be a planarization layer and may include organic or inorganic insulating materials.

[0116] The first electrode 191 is located on the passivation layer 180. The first electrode 191 passes through a contact hole 81 formed in the passivation layer 180 (see...). Figure 4 It is connected to the third data connection component 73.

[0117] A pixel defining layer or partition wall 350 is disposed on the passivation layer 180 and the first electrode 191. The partition wall 350 includes an opening 351 that overlaps with the first electrode 191 (e.g., exposing a large portion of the first electrode 191). An emitting layer 370 is disposed in the opening 351. A second electrode 270 is disposed on the emitting layer 370 and the partition wall 350, for example, along the sidewall of the opening 351 and the upper surface of the partition wall 350. The first electrode 191, the emitting layer 370, and the second electrode 270 form a light-emitting device LED. The first electrode 191 may be a pixel electrode, and the second electrode 270 may be a common electrode.

[0118] The pixel electrode can be the anode, serving as a hole injection electrode, and the common electrode can be the cathode, serving as an electron injection electrode. Alternatively, the pixel electrode can be the cathode, and the common electrode can be the anode. When holes and electrons are injected from the pixel electrode and the common electrode into the emitter layer, excitons generated by the combination of the injected holes and electrons transition from the excited state to the ground state to emit light.

[0119] The encapsulation layer 400 for protecting the LED light-emitting device may be located on the second electrode 270. The encapsulation layer 400 may be in contact with the second electrode 270 as shown, or it may be separate from the second electrode 270.

[0120] The encapsulation layer 400 may be a thin-film encapsulation layer on which inorganic and organic films (e.g., a three-layer structure having an inorganic film, an organic film, and an inorganic film) are stacked. According to an exemplary embodiment, a capping layer and a functional layer may be located between the second electrode 270 and the encapsulation layer 400.

[0121] The second pixel region PX2 can be stacked with an optical component (specifically, the sensing module 500 described above). The characteristics of transistors T1 to T7 included in the second pixel region PX2 are affected by infrared light output from the sensing module 500. According to an exemplary embodiment, the entire second pixel region PX2 can be stacked with a first layer 30. The first layer 30 blocks and obstructs the light output from the sensing module 500 to prevent the characteristics of the transistors in the second pixel region PX2 from being altered by the light (e.g., infrared light) output from the sensing module 500.

[0122] Reference Figure 8 The transmissive region TA may not include transistors and light-emitting devices. The transmissive region TA may include wiring for connecting adjacent second pixel regions PX2 within the second region DA2. For example, as... Figure 8 As shown, the transmissive region TA may include wiring, such as a first scan line 151, a second scan line 152, an emission control line 153, a storage line 126, an initialization voltage line 127, a data line 171, and / or a drive voltage line 172. The transmissive region TA may be manufactured using the same process as the first pixel region PX1 and the second pixel region PX2, and may not include some of the elements (e.g., semiconductor layers) in the second pixel region PX2.

[0123] Since the transmissive region TA does not include an additional semiconductor layer, it does not include a transistor. Furthermore, the transmissive region TA does not include any additional light-emitting devices, and therefore cannot display an image. According to an exemplary embodiment, the transmissive region TA may be stacked with a common electrode, or the common electrode may be removed from the transmissive region TA.

[0124] According to the exemplary embodiments described above, the first pixel region PX1 in the first region DA1 and the second pixel region PX2 in the second region DA2 can substantially include transistors, capacitors, and light-emitting devices arranged in a similar manner. The second pixel region PX2 may also include a first layer 30 stacked with a plurality of transistors and capacitors. The area of ​​the first layer 30 stacked with the second pixel region PX2 may differ from the area of ​​the first layer 30 stacked with the first pixel region PX1. For example, the first pixel region PX1 may not be stacked with the first layer 30, thereby preventing unnecessary load or coupling.

[0125] Light (e.g., infrared light) emitted from the rear side of the display panel 100 from the sensing module 500 will be incident on the second pixel region PX2, thereby affecting the characteristics of the transistors included in the second pixel region PX2. However, when the second pixel region PX2 includes a first layer 30 to block the light (e.g., infrared light) emitted from the sensing module 500, changes in the physical properties of the transistors caused by the light (e.g., infrared light) emitted from the sensing module 500 can be reduced or prevented.

[0126] Furthermore, the second region DA2 includes a transmissive region TA in addition to the second pixel region PX2, thus allowing for high light transmittance when entering and exiting the optical component (e.g., sensing module 500). Consequently, the recognition rate and sensing accuracy for targets to be identified by the optical component can be increased.

[0127] Now refer to Figures 9 to 12 A first pixel region is described according to an exemplary embodiment, set within a first region. A second pixel region according to an exemplary embodiment is compared with a reference. Figures 5 to 7 The provided description corresponds, and the transmission area is consistent with the reference. Figure 8 The provided description will be omitted.

[0128] Figure 9 A circuit diagram of the first pixel region according to an exemplary embodiment is shown. Figure 10 It shows Figure 9 A top view of the first pixel region. Figure 11 A circuit diagram of the first pixel region according to an exemplary embodiment is shown. Figure 12 It shows Figure 11 A top view of the first pixel region.

[0129] Reference Figure 9 and Figure 10 The first pixel region PX1 may include multiple transistors T1 to T7 and a capacitor Cst. A portion of the first pixel region PX1 may be stacked with the first layer 30. The first layer 30 is conductive and may include various conductive metals or semiconductor materials having conductive properties corresponding to various conductive metals.

[0130] The first layer 30 can be a layer used to block light (e.g., infrared light) output from the sensing module 500. Both infrared light and visible light can be incident on the first layer 30. The first layer 30 can transmit visible light and block infrared light.

[0131] The first layer 30 can be stacked with the driving transistor T1, the third transistor T3, and the compensation transistor T4. The first layer 30 can be stacked with the driving transistor T1, the third transistor T3, and the fourth transistor T4, which are largely affected by the leakage current in the first pixel region PX1. The first layer 30 is disposed in a partial region, thus preventing changes in the characteristics of the transistors caused by the transmission of infrared light, while substantially not reducing the transmittance of visible light.

[0132] According to an exemplary embodiment, the first layer 30 superimposed on the first pixel region PX1 may be connected to the first scan line 151, the data line 171, the emission control line 153 and / or the drive voltage line 172.

[0133] According to an exemplary embodiment, when the sensing module 500 is disposed on the rear side of the display panel 100, the light beam output by the sensing module 500 is partially input into the first region DA1 and the second region DA2. The characteristics of the transistors are altered by the infrared light, or leakage current is generated due to the infrared light. When the first pixel region PX1 includes a first layer 30 stacked with the transistor portion, leakage current can be reduced, image quality degradation caused by leakage current can be prevented, and changes in the physical properties of the transistors can be minimized.

[0134] In summary, the first pixel region PX1 can be stacked with the first layer 30. Specifically, the first layer 30 can be stacked with some of the transistors in the first pixel region PX1 whose physical properties are most likely to change due to infrared light.

[0135] In this configuration, the second pixel region PX2 may include a first layer 30 stacked with multiple transistors and capacitors. Regarding the second pixel region PX2, infrared light can be emitted from the rear side of the display panel 100, and the characteristics of the transistors are affected by the infrared light. However, the second pixel region PX2 includes the first layer 30 to prevent the transistors from being altered by the infrared light.

[0136] Furthermore, the second region DA2 includes a transmission region TA and a second pixel region PX2, thus the transmittance of the light beam output from and received by the optical component (specifically, the sensing module 500) can be high. Therefore, the recognition rate or sensing accuracy of the target to be identified by the optical component can be increased.

[0137] Reference Figure 11 and Figure 12 The first pixel region PX1 may include multiple transistors T1 to T7 and a capacitor Cst. A portion of the first pixel region PX1 may be stacked with the first layer 30. The first layer 30 is conductive and may include various conductive metals or semiconductor materials having conductive properties corresponding to various conductive metals.

[0138] The first layer 30 can block light output from the sensing module 500, such as infrared light. Both infrared and visible light can be incident on the first layer 30. The first layer 30 can transmit visible light and block infrared light.

[0139] The first layer 30 can be stacked with the driving transistor T1, the third transistor T3, the fourth transistor T4, and the seventh transistor T7. The first layer 30 can be stacked with the driving transistors T1, T3, T4, and T7, which are largely affected by leakage current in the first pixel region PX1. The first layer 30 is disposed in a portion of the first pixel region PX1, thus preventing changes in transistor characteristics due to infrared light without substantially reducing transmittance.

[0140] According to an exemplary embodiment, when the sensing module 500 is disposed on the rear side of the display panel 100, the light output by the sensing module 500 will partially incident on the first region DA1 and the second region DA2. The characteristics of the transistors may change due to the infrared light, or leakage current may be generated due to the infrared light.

[0141] However, the first pixel region PX1 includes a first layer 30 partially superimposed on the transistor, thereby reducing leakage current, preventing image quality degradation caused by leakage current, and minimizing changes in the physical properties of the transistor.

[0142] In summary, the first pixel region PX1 can be stacked with the first layer 30. Specifically, the first layer 30 can be stacked with some of the transistors among the multiple transistors included in the first pixel region PX1 that are most susceptible to changes in physical properties caused by infrared light.

[0143] Furthermore, the second pixel region PX2 may include a first layer 30 stacked with multiple transistors and capacitors. Regarding the second pixel region PX2, infrared light can be emitted from the rear side of the display panel 100, and the characteristics of the transistors are affected by the infrared light. However, the second pixel region PX2 includes a first layer 30 to prevent the physical properties of the transistors from being altered by the infrared light.

[0144] Furthermore, the second region DA2 includes a transmission region TA and a second pixel region PX2, thus the transmittance of the light beam output from the optical component (specifically, the sensing module 500) and the light beam incident on the optical component (specifically, the sensing module 500) can be high. Therefore, the recognition rate or sensing accuracy of the target to be identified by the optical component can be increased.

[0145] Now refer to Figures 13 to 16 Describes a second pixel region according to an exemplary embodiment. The first pixel region according to an exemplary embodiment is compared with a reference. Figure 3 and Figure 4 The provided description corresponds to the transmission area and reference. Figure 8 The provided description corresponds to this, and it will not be described further.

[0146] Figure 13 A circuit diagram of the second pixel region according to an exemplary embodiment is shown. Figure 14 It shows Figure 13 A top view of the second pixel region. Figure 15 A circuit diagram of the second pixel region according to an exemplary embodiment is shown. Figure 16 It shows Figure 15 A top view of the second pixel region.

[0147] Reference Figure 13 and Figure 14 According to an exemplary embodiment, the second pixel region PX2 may include a plurality of transistors T1 to T7 and a capacitor Cst. In this case, a portion of the second pixel region PX2 may be stacked with the first layer 30. The first layer 30 is conductive and may include various conductive metals or semiconductor materials having conductive properties corresponding to various conductive metals.

[0148] The first layer 30 blocks light, such as infrared light, output from the sensing module 500. Both infrared and visible light can be incident on the first layer 30. The first layer 30 can transmit visible light and block infrared light.

[0149] The first layer 30 can be stacked with the driving transistor T1, the third transistor T3, and the compensation transistor T4. The first layer 30 is stacked with the driving transistor T1, the third transistor T3, and the fourth transistor T4, which are largely affected by the leakage current in the second pixel region PX2, thereby preventing changes in the characteristics of the transistors caused by the transmission of infrared light, while essentially not reducing the transmittance of visible light.

[0150] In summary, a portion of the second pixel region PX2 according to the exemplary embodiment may be stacked with the first layer 30. Specifically, the first layer 30 may be stacked with some of the transistors among the plurality of transistors included in the second pixel region PX2 that are most susceptible to changes in physical properties caused by infrared light.

[0151] The first pixel region PX1 has a substantially the same arrangement as the second pixel region PX2, but it may not be superimposed on the first layer 30. Furthermore, the second region DA2 includes the transmissive region TA and the second pixel region PX2, thus allowing for high transmittance of the light beam output from the optical component (specifically, the sensing module 500). Therefore, the recognition rate or sensing accuracy for targets to be identified by the optical component can be increased.

[0152] Reference Figure 15and Figure 16 The second pixel region PX2 may include multiple transistors T1 to T7 and capacitor Cst.

[0153] In this case, a portion of the second pixel region PX2 can be stacked with the first layer 30. The first layer 30 is conductive and may include various conductive metals or semiconductor materials having conductive properties corresponding to various conductive metals.

[0154] The first layer 30 blocks light, such as infrared light, output from the sensing module 500. Both infrared and visible light can be incident on the first layer 30. The first layer 30 can transmit visible light and block infrared light.

[0155] According to an exemplary embodiment, the first layer 30, which is superimposed on the second pixel region PX2, can be superimposed on driving transistor T1, third transistor T3, fourth transistor T4, and seventh transistor T7. The first layer 30, being superimposed on driving transistor T1, third transistor T3, fourth transistor T4, and seventh transistor T7, which are largely affected by leakage current in the second pixel region PX2, prevents changes in transistor characteristics caused by infrared light transmission while substantially maintaining visible light transmittance.

[0156] In summary, a portion of the second pixel region PX2 can be stacked with the first layer 30. Specifically, the first layer 30 can be stacked with some of the transistors among the multiple transistors included in the second pixel region PX2 that are most susceptible to changes in physical properties caused by infrared light.

[0157] The first pixel region PX1 has a substantially the same arrangement as the second pixel region PX2, but it may not be superimposed on the first layer 30. Furthermore, the second region DA2 includes the second pixel region PX2 and the transmission region TA, thus allowing for high transmittance of the light beam output from the optical component (specifically, the sensing module 500). Therefore, the recognition rate or sensing accuracy for targets to be identified by the optical component can be increased.

[0158] When a first layer is included according to an exemplary embodiment, the load on a pixel region may increase, or signal distortion may occur due to coupling between the first layer and other signal wiring. However, when the first layer is disposed in a second pixel region superimposed on the sensing module and selectively disposed in the first pixel region according to an exemplary embodiment, the variation in image quality caused by infrared light is reduced in the second pixel region, and a predetermined image quality is provided in the first pixel region, thereby providing a display device with excellent display quality.

[0159] According to an exemplary embodiment, the display device includes a sensing module disposed on the rear side of the display panel, thereby providing a forward-facing display device. Furthermore, the pixel region superimposed on the sensing module includes a first layer that blocks light output by the sensing module, thereby minimizing image quality variations caused by light output by the sensing module and providing a display device with improved quality.

[0160] One or more embodiments may provide a forward display device including a sensing module disposed on the rear side of a display panel. One or more embodiments may prevent image quality variations caused by the sensing module by allowing the pixel region superimposed on the sensing module to include a first layer that blocks light output from the sensing module.

[0161] Example embodiments have been disclosed herein, and although specific terminology has been used, they are used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art as of the time of this application that features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly stated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, the display device comprising: The display panel includes a first area and a second area. The first region includes a first pixel region for displaying the image, and The second region includes a second pixel region for displaying the image and a transmission region for transmitting light output by the sensing module. The second pixel region includes: a first transistor; a second transistor electrically connected to the first transistor and electrically connected to the first scan line; and a third transistor electrically connected to the first scan line. The second pixel region includes a first layer that is stacked with the first transistor and the third transistor and blocks the light. In the planar view, the first layer is superimposed on the first scan line, and In the plan view, the first layer is separated from the second transistor.

2. The display device according to claim 1, wherein: The second pixel region includes a plurality of transistors, the plurality of transistors including the first transistor, the second transistor, and the third transistor. The first layer is stacked on a portion of the plurality of transistors, and The transmission region is not superimposed on the first layer.

3. The display device according to claim 1, further comprising: The sensing module is located on the rear side of the display panel.

4. The display device according to claim 1, wherein, In the plan view, the transmission region is separated from the first layer.

5. The display device according to claim 1, wherein, In the planar view, the first pixel region is separated from the first layer.

6. The display device according to claim 1, The second pixel region includes multiple first layers, and In the plan view, the plurality of first layers are separated from each other.

7. The display device according to claim 1, wherein: The first pixel region includes multiple transistors, and The first layer is stacked on a portion of the plurality of transistors.

8. The display device according to claim 7, wherein: The overlap percentage of the first layer in the first pixel region is different from that in the second pixel region, which are of the same area as the first pixel region and the second pixel region.

9. The display device according to claim 1, wherein: The first pixel region includes multiple transistors, and The first layer is not stacked with the plurality of transistors.

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