Clock synchronization method, device, computer readable storage medium, and system

Abstract

Embodiments of the present application disclose a clock synchronization method, device, computer readable storage medium and system. The method is applied to a clock synchronization device carrying a protocol stack, and the method comprises the following steps: when detecting that a first device acting as a master clock is in an abnormal state, sending a first application message carrying first device abnormal information to a second device acting as a slave clock, so that the second device switches the role in the protocol stack from the slave clock to the master clock based on the first application message; based on a current timestamp of the second device acting as the master clock, sending a first time synchronization message to the first device, so that the first device resumes a normal state after synchronization succeeds based on the first time synchronization message when working; when detecting that the first device is in the normal state, sending a first switching instruction to the first device, so that the first device switches the role in the protocol stack from the slave clock to the master clock based on the first switching instruction.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a clock synchronization method, device, computer-readable storage medium, and system. Background Technology

[0002] Clock synchronization is the process of providing a unified time scale for a distributed system (which includes multiple controllers) by manipulating certain operations on a local clock. With the increasing application of Ethernet clock synchronization technology in fields such as automotive, aerospace, and power, the systems being designed are becoming increasingly complex.

[0003] In related technologies, both the primary and backup clock devices are connected to networks A and B, respectively. This allows application devices accessing via both networks to receive Precision Timing Protocol (PTP) synchronization messages sent by the master clock on both networks. In this scheme, both the primary and backup clock devices include both an A protocol stack and a B protocol stack. Each device uses the A protocol stack when acting as the master clock and the B protocol stack when acting as the slave clock. Therefore, if the master clock fails, it must switch from master to slave, switching from the A protocol stack to the B protocol stack. Conversely, the other device must switch from slave to master, switching from the B protocol stack to the A protocol stack. Since the A and B protocol stacks belong to two different domains, this technology operates in a dual-domain system, involves two protocol stacks, and is logically complex and resource-intensive. Summary of the Invention

[0004] This invention provides a clock synchronization method, device, computer-readable storage medium, and system that simplifies logic and reduces resource consumption.

[0005] The technical solution of this invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a clock synchronization method. The method is applied to a clock synchronization device carrying a protocol stack. The clock synchronization device is connected to a first device and a second device, respectively. The clock synchronization device, the first device, and the second device use the same protocol stack. The method includes: when the first device, acting as the master clock, is detected to be in an abnormal state, sending a first application message carrying abnormal information of the first device to the second device, acting as a slave clock, causing the second device to switch its role in the protocol stack from slave clock to master clock based on the first application message; sending a first time synchronization message to the first device based on the current timestamp of the second device, acting as the master clock, causing the first device to resume its normal state after successful synchronization based on the first time synchronization message during operation; and sending a first switching instruction to the first device when the first device is detected to be in a normal state, causing the first device to switch its role in the protocol stack from slave clock to master clock based on the first switching instruction.

[0007] In this solution, only one protocol stack is needed to complete clock synchronization redundancy under a single domain. When the first device malfunctions, the first and second devices only need to change the roles of their protocol stacks and implement clock synchronization redundancy by sending application messages, which simplifies the logic and reduces resource consumption.

[0008] In some embodiments, when a first device acting as a master clock is detected to be in an abnormal state, sending a first application message carrying abnormal information of the first device to a second device acting as a slave clock includes: when a first device acting as a master clock is detected to be in the abnormal state, sending a first application message carrying abnormal information of the first device to a second device acting as a slave clock, and sending a second switching instruction to the first device, so that the first device will switch its role in the protocol stack from master clock to slave clock based on the second switching instruction.

[0009] In this scheme, when the first device acting as the master clock is detected to be in an abnormal state, the roles in the protocol stack are switched. The role of the first device in the protocol stack is switched from master clock to slave clock, and the role of the second device in the protocol stack is switched from slave clock to master clock. Clock redundancy is achieved by sending Ethernet packets in a single domain, which simplifies the logic and reduces resource consumption.

[0010] In some embodiments, the step of sending a first switching instruction to the first device when the first device is detected to be in a normal state includes: sending the first switching instruction to the first device when the first device is detected to be in a normal state, and sending a second application message carrying normal information of the first device to the second device, which is the master clock, so that the second device will switch its role in the protocol stack from master clock to slave clock based on the second application message.

[0011] In this scheme, when the first device, which is acting as a slave clock, is detected to be back in normal state (i.e., working normally), the roles in the protocol stack are switched again. The role of the first device in the protocol stack is switched from slave clock to master clock, and the role of the second device in the protocol stack is switched from master clock to slave clock. Clock redundancy is achieved by sending Ethernet packets in a single domain, which simplifies the logic and reduces resource consumption.

[0012] In some embodiments, the clock synchronization device includes a switch connected to the first device and the second device respectively; the switch sends a first application message carrying abnormal information of the first device to the second device, which is a slave clock; the method further includes: the switch switching from a first mode to a second mode based on the first application message; wherein, in the first mode, the first slave port of the switch is connected to the first device and the first master port of the switch is connected to the second device, and in the second mode, the second slave port of the switch is connected to the second device and the second master port of the switch is connected to the first device.

[0013] In this solution, a switch is used to realize the message transmission between various devices in the protocol stack, and the working mode of the switch (first mode and second mode) switches according to the application message to ensure successful transmission of Ethernet messages. This enables clock redundancy to be achieved by sending Ethernet messages in a single domain, simplifying the logic.

[0014] In some embodiments, the clock synchronization device includes a switch connected to the first device and the second device respectively; the switch sends a second application message carrying routine information of the first device to the second device, which serves as the master clock; the method further includes: the switch switching from a second mode to a first mode based on the second application message.

[0015] In this scheme, the protocol stack performs logical control over various devices using the same protocol, and the switch provides the transmission path for Ethernet packets between the protocol stack, the first device, and the second device. The switch's operating mode (first mode and second mode) switches according to the application packets to ensure successful transmission of Ethernet packets, thereby achieving clock redundancy in a single domain by sending Ethernet packets and simplifying the logic.

[0016] In some embodiments, the method further includes: sending a second time synchronization message to the second device based on the current timestamp of the first device that is being used as the master clock again, and sending a third time synchronization message to other devices, such that the second device performs time synchronization based on the second time synchronization message, and the other devices perform their respective time corrections based on the third time synchronization message.

[0017] In this scheme, the clock redundancy method only requires one protocol stack to achieve time synchronization between the second device and other devices. The logic is simple and reduces the resources consumed.

[0018] In some embodiments, the method further includes: reading the registers of the first device; and determining whether the first device is in an abnormal state based on the parameters stored in the registers that characterize the operating state of the first device.

[0019] In this solution, the registers of the first device are read, and based on the parameters stored in the registers that characterize the operating status of the first device, it is determined whether the first device is in an abnormal state. Then, when an abnormal state is determined, the role of the first device is switched, the role of the second device is switched, and the switch mode is switched, through a combination of protocol stack and Ethernet packets. This enables clock redundancy within a single domain, simplifies the logic, and reduces resource consumption.

[0020] In some embodiments, the first application message or the second application message includes a source address, a destination address, a working mode, and data; wherein, the source address represents the address of the device acting as the master clock; the destination address represents the address of the device acting as the slave clock; the working mode represents the working state of the device acting as the master clock, and the working state includes an abnormal state and a normal state; the data includes rules for determining the working state.

[0021] In this scheme, the first application message includes the address of the sending device and the address of the receiving device during message transmission, as well as the rules for judging the working status of the sending device. This allows for timely switching of the roles of the master and slave clocks in the protocol stack when the master clock malfunctions. Clock synchronization redundancy is achieved by sending application messages, simplifying the logic and reducing resource consumption.

[0022] In some embodiments, the first time synchronization message, the second time synchronization message, the third time synchronization message, the first application message, and the second application message are Ethernet messages on a single domain.

[0023] In this solution, the clock synchronization device, the first device, and the second device use the same protocol stack. This protocol stack supports the sending, receiving, and parsing of Ethernet packets (including the first time synchronization packet, the second time synchronization packet, the third time synchronization packet, the first application packet, and the second application packet). Clock redundancy is achieved by sending Ethernet packets, simplifying the logic.

[0024] In a second aspect, embodiments of the present invention provide a clock synchronization device, the device comprising: a memory for storing an executable computer program; and a processor for implementing the clock synchronization method described in the first aspect when executing the executable computer program stored in the memory.

[0025] Thirdly, embodiments of the present invention provide a computer-readable storage medium storing a computer program for implementing the clock synchronization method described in the first aspect when executed by a processor.

[0026] Fourthly, embodiments of the present invention provide a clock synchronization system, the system including a clock synchronization device carrying a protocol stack, a first device, and a second device. The clock synchronization device is connected to both the first device and the second device, and the clock synchronization device, the first device, and the second device use the same protocol stack. When the clock synchronization device detects that the first device, acting as the master clock, is in an abnormal state, it sends a first application message carrying abnormal information of the first device to the second device, acting as the slave clock. Based on the first application message, the second device switches its role in the protocol stack from slave clock to master clock. Based on the current timestamp of the second device acting as the master clock, the clock synchronization device sends a first time synchronization message to the first device. When the first device is working, it resumes its normal state after successful synchronization based on the first time synchronization message. When the clock synchronization device detects that the first device is in a normal state, it sends a first switching instruction to the first device. Based on the first switching instruction, the first device switches its role in the protocol stack from slave clock to master clock.

[0027] This invention provides a clock synchronization method, device, computer-readable storage medium, and system. According to the solution provided by this invention, the method is applied to a clock synchronization device carrying a protocol stack. The clock synchronization device is connected to a first device and a second device, respectively. The clock synchronization device, the first device, and the second device use the same protocol stack; that is, the clock synchronization device, the first device, and the second device are in the same domain system. When switching between master and slave clocks, since they use the same protocol stack, there is no need to switch domains. Under normal circumstances, the first device acts as the master clock, and the second device acts as a redundant clock (or slave clock). The first device sends time synchronization messages to the second device through the protocol stack to achieve time synchronization. When the first device, acting as the master clock, detects that it is in an abnormal state, its role in the protocol stack switches from master clock to slave clock. The method includes: when the clock synchronization device detects that the first device, acting as the master clock, is in an abnormal state, it sends a first application message carrying the abnormal information of the first device to the second device, acting as the slave clock. The second device parses the first application message, determines that the first device is in an abnormal state, and then switches its role in the protocol stack from slave clock to master clock. Based on the current timestamp of the second device acting as the master clock, the clock synchronization device sends a first time synchronization message to the first device, enabling the first device to perform its own time synchronization based on the first time synchronization message during operation, and restores its normal state after successful synchronization. When the clock synchronization device detects that the first device is in a normal state, it sends a first switching instruction to the first device, enabling the first device to switch its role in the protocol stack from slave clock to master clock based on the first switching instruction. Only one protocol stack is needed to complete clock synchronization redundancy under a single domain. When the first device is abnormal, the first device and the second device only need to change their roles in the protocol stack and implement clock synchronization redundancy by sending application messages, simplifying the logic and reducing resource consumption.

[0028] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the specification, serve to explain the technical solutions of the present invention.

[0030] Figure 1 A flowchart illustrating optional steps of a clock synchronization method provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of an application message format provided in an embodiment of the present invention;

[0032] Figure 3A flowchart illustrating optional steps of another clock synchronization method provided in an embodiment of the present invention;

[0033] Figure 4 A flowchart illustrating optional steps of another clock synchronization method provided in an embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram illustrating the message transmission relationship between controllers, provided as an embodiment of the present invention.

[0035] Figure 6 An optional flowchart of a single-domain clock synchronization redundancy method provided in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the composition structure of a clock synchronization device provided in an embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of an optional structure of a clock synchronization system provided in an embodiment of the present invention. Detailed Implementation

[0038] To gain a more detailed understanding of the features and technical content of the embodiments of the present invention, the implementation of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of the present invention.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the scope of the invention.

[0040] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] It should also be noted that the terms "first, second, third" used in the embodiments of the present invention are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein.

[0042] In this embodiment of the invention, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0043] Furthermore, in this embodiment of the invention, "multiple" means two or more, unless otherwise explicitly specified.

[0044] To better understand the clock synchronization method provided in the embodiments of the present invention, the application background and related technologies will be explained before introducing the technical solutions of the embodiments of the present invention.

[0045] With the increasing application of Ethernet clock synchronization technology in fields such as automotive, aerospace, and power, the systems being designed are becoming increasingly complex. This necessitates ensuring stability while simultaneously achieving time synchronization and accuracy, and considering resource consumption. Therefore, designing redundant clock synchronization systems has become an inevitable trend.

[0046] In related technologies, a non-homogeneous external high-precision clock and two internal clocks can be used as the master clock, backup clock, and third-party clock, respectively. Third-party clock arbitration is only used when the master and backup clocks are inconsistent. This can tolerate single-redundancy clock failures and achieve the purpose of "triple redundancy".

[0047] However, the above-mentioned technical solution of achieving clock synchronization by connecting both the primary clock device and the backup clock device to network A and network B is implemented in a dual-domain system, while the technical solution of achieving triple redundancy by using a primary clock, a backup clock, and a third-party clock is implemented in a multi-domain system. This not only makes the logic complex and difficult to implement, but also consumes a lot of resources and affects the system's sensitivity.

[0048] This invention provides a clock synchronization method. This method is applied to a clock synchronization device carrying a protocol stack. The clock synchronization device is connected to a first device and a second device, respectively. The clock synchronization device, the first device, and the second device use the same protocol stack, such as... Figure 1 As shown, Figure 1 This is a flowchart illustrating the steps of a clock synchronization method provided in an embodiment of the present invention. The clock synchronization method includes the following steps:

[0049] S101. When the first device, which is the master clock, is detected to be in an abnormal state, a first application message carrying the abnormal information of the first device is sent to the second device, which is the slave clock, so that the second device will switch its role in the protocol stack from slave clock to master clock based on the first application message.

[0050] In this embodiment of the invention, since the clock synchronization device, the first device, and the second device all use the same protocol stack—meaning they are in the same domain system—there is no need to switch domains when switching between the master and slave clocks. This protocol stack can be the General Precise Time Protocol (gPTP), a derivative of the PTP protocol, used to ensure that the time of all devices (also called nodes) in a local area network is completely consistent, with an error at the nanosecond (ns) level. All devices in a local area network use the master clock as a reference and synchronize their local clocks with the master's clock. Under normal circumstances, the first device acts as the master clock, and the second device acts as a redundant clock (or slave clock). The first device sends time synchronization messages to the second device through the protocol stack to achieve time synchronization. When the first device, acting as the master clock, detects that it is in an abnormal state, its role in the protocol stack switches from master clock to slave clock. The clock synchronization device, carrying the protocol stack, can read the working status of the first and second devices in the protocol stack, thereby enabling it to detect whether the first device is in an abnormal state. When the clock synchronization device detects that the first device, acting as the master clock, is in an abnormal state, it sends a first application message to the second device, acting as the slave clock. The first application message carries information about the first device's abnormality. The second device parses the first application message, determines that the first device is in an abnormal state, and then switches its role in the protocol stack from slave clock to master clock.

[0051] In this embodiment of the invention, the abnormal state represents the state in which the device is not working properly. The abnormal state can be any one or a combination of at least two of the following: disconnection, network disconnection, power failure, fault, restart. The gPTP protocol stack can determine whether the first device is abnormal by reading the registers of the first device.

[0052] For example, let's take controller A as the first device and controller B as the second device. Both controller A and controller B have only one gPTP protocol stack running. The entire logic control is executed by the device where the gPTP protocol stack resides (i.e., the clock synchronization device). Under normal circumstances, controller A, acting as the Master, sends time synchronization messages to controller B, and controller B, acting as the Slave, receives time synchronization messages. When controller A experiences an abnormal state (e.g., a restart), when the gPTP protocol stack detects this abnormality, it sends a command to controller A, causing controller A to switch from normal mode to abnormal mode. That is, its role in the gPTP protocol stack changes from Master to Slave. Then, the gPTP protocol stack sends an application message (i.e., the first application message) containing mode information to controller B. After receiving the mode information in the application message, controller B parses it. If it determines that controller A is in an abnormal state, controller B switches from normal mode to abnormal mode, that is, its role in the gPTP protocol stack changes from Slave to Master. In this scenario, controller A normally functions as the Master, and in its abnormal mode, it functions as the Slave; controller B normally functions as the Slave, and in its abnormal mode, it functions as the Master.

[0053] In some embodiments, the first application message includes a source address, a destination address, a working mode, and data; wherein, the source address represents the address of the device acting as the master clock; the destination address represents the address of the device acting as the slave clock; the working mode represents the working state of the device acting as the master clock, and the working state includes an abnormal state and a normal state; the data includes the rules for determining the working state.

[0054] In this embodiment of the invention, the application message format is as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of an application message format provided in an embodiment of the present invention. Taking the example of controller A sending an application message to controller B through the gPTP protocol stack, controller A acts as the master and controller B acts as the slave. The source address is the address of controller A, the destination address is the address of controller B, the mode is an abnormal state or a normal state, and the data can be the working state judgment rules. After the controller B parses the application message, it determines whether controller A is in an abnormal state or a normal state.

[0055] For example, the mode is "0" or "1", and the data represents the judgment rule: "0" represents a normal state, and "1" represents an abnormal state. The mode is "correct" or "incorrect", and the data represents the judgment rule: "correct" represents a normal state, and "incorrect" represents an abnormal state. The mode is "0x00" or "0x01", and the data represents the judgment rule: 0x00 represents a normal state, and 0x01 represents an abnormal state. This embodiment of the invention does not limit the representation of the mode and data, as long as controller B can determine whether controller A is in an abnormal state.

[0056] In this embodiment of the invention, the first application message includes the address of the sending device and the address of the receiving device during the message transmission process, as well as the judgment rules for the working status of the sending device, so that when the master clock is abnormal, the roles of the master and slave clocks in the protocol stack can be switched in time. The clock synchronization redundancy setting is realized by sending application messages, which simplifies the logic and reduces resource consumption.

[0057] S102. Based on the current timestamp of the second device, which serves as the master clock, a first time synchronization message is sent to the first device, so that the first device can resume its normal state after successful synchronization based on the first time synchronization message during operation.

[0058] In this embodiment of the invention, the clock synchronization device generates a first time synchronization message based on the current timestamp of the second device, which serves as the master clock, and sends the first time synchronization message to the first device. When the first device resumes normal operation, for example, by any one or at least two combinations of going online, powering on, connecting to the network, connecting, starting up, or restarting, it can receive the first time synchronization message and perform its own time synchronization based on the first time synchronization message. After successful time synchronization, it returns to its normal state.

[0059] For example, taking controller A as the first device and controller B as the second device, controller B acts as the master clock and sends a first time synchronization message to controller A based on the current timestamp information of controller B. After successful synchronization, controller A switches back to normal mode.

[0060] In some embodiments, the first time synchronization message and the first application message are Ethernet messages on a single domain.

[0061] In this embodiment of the invention, the clock synchronization device, the first device, and the second device use the same protocol stack, which supports the sending, receiving, and parsing of Ethernet packets. The packets sent between the first device and the second device through the protocol stack (e.g., the first time synchronization packet and the first application packet) are Ethernet packets.

[0062] S103. When the first device is detected to be in a normal state, a first switching instruction is sent to the first device, so that the first device will switch its role in the protocol stack from slave clock to master clock based on the first switching instruction.

[0063] In this embodiment of the invention, after successful synchronization, the first device switches back to normal mode operation. When the clock synchronization device detects that the first device is in normal mode, it sends a first switching instruction to the first device. Based on the first switching instruction, the first device switches its role in the protocol stack from slave clock to master clock.

[0064] For example, taking controller A as the first device and controller B as the second device, after successful synchronization, controller A switches back to normal mode. The gPTP protocol stack sends a first switching instruction to controller A. Based on the switching instruction, controller A's role in the gPTP protocol stack changes from Slave to Master.

[0065] This invention provides a clock redundancy method with simpler logic and lower resource consumption, requiring only one protocol stack. Controller A is used as the master clock device, and controller B as the redundant clock device. Application message notifications are sent to achieve in-vehicle Ethernet clock synchronization redundancy in a single-domain system, simplifying the logic and reducing resource consumption.

[0066] The clock synchronization method provided in this invention can be applied to fields such as automotive, aerospace, and power technologies. Taking automotive as an example, the gPTP protocol stack is used to synchronize the clocks of various devices in the automotive network. Because the clocks of each device operate independently, some applications require all devices to execute in a synchronized manner. For example, the task of playing audio and video may be implemented on different devices, so these two devices must have the same clock reference; otherwise, the picture and sound may not match. The clock synchronization method provided in this invention can be applied to automotive Ethernet clock synchronization systems. By creating a method to achieve clock synchronization redundancy settings in a single-domain system by sending application messages, it simplifies the logic and saves resources.

[0067] According to the solution provided in the embodiments of the present invention, this method is applied to a clock synchronization device carrying a protocol stack. The clock synchronization device is connected to a first device and a second device, respectively. The clock synchronization device, the first device, and the second device use the same protocol stack, that is, the clock synchronization device, the first device, and the second device are in the same domain system. When switching between the master clock and the slave clock, since they are using the same protocol stack, there is no need to switch domains. Under normal circumstances, the first device is used as the master clock, and the second device is used as a redundant clock (or slave clock). The first device sends time synchronization messages to the second device through the protocol stack to achieve time synchronization. When the first device, acting as the master clock, detects that it is in an abnormal state, its role in the protocol stack switches from master clock to slave clock. The method includes: when the clock synchronization device detects that the first device, acting as the master clock, is in an abnormal state, it sends a first application message carrying the abnormal information of the first device to the second device, acting as the slave clock. The second device parses the first application message, determines that the first device is in an abnormal state, and then switches its role in the protocol stack from slave clock to master clock. Based on the current timestamp of the second device acting as the master clock, the clock synchronization device sends a first time synchronization message to the first device, enabling the first device to perform its own time synchronization based on the first time synchronization message during operation, and restores its normal state after successful synchronization. When the clock synchronization device detects that the first device is in a normal state, it sends a first switching instruction to the first device, enabling the first device to switch its role in the protocol stack from slave clock to master clock based on the first switching instruction. Only one protocol stack is needed to complete clock synchronization redundancy under a single domain. When the first device is abnormal, the first device and the second device only need to change their roles in the protocol stack and implement clock synchronization redundancy by sending application messages, simplifying the logic and reducing resource consumption.

[0068] In some embodiments, the above Figure 1 S101 can also be implemented in the following way. When the first device, which is the master clock, is detected to be in an abnormal state, a first application message carrying the abnormal information of the first device is sent to the second device, which is the slave clock, and a second switching instruction is sent to the first device, so that the first device will switch its role in the protocol stack from master clock to slave clock based on the second switching instruction.

[0069] In this embodiment of the invention, when the gPTP protocol stack detects an anomaly in the first device, it sends a second switching instruction to the first device, causing the first device to switch from normal mode to an abnormal mode, that is, its role in the gPTP protocol stack changes from Master to Slave. Simultaneously, the gPTP protocol stack sends an application message (i.e., a first application message) containing mode information to the second device. After receiving the mode information of the application message, the second device parses it. If it determines that the first device is in an abnormal state, the second device switches from normal mode to an abnormal mode, that is, its role in the gPTP protocol stack changes from Slave to Master.

[0070] In this embodiment of the invention, when the protocol stack detects that the first device, which is the master clock, is in an abnormal state, the roles in the protocol stack are switched. The role of the first device in the gPTP protocol stack is switched from Master to Slave, and the role of the second device in the gPTP protocol stack is switched from Slave to Master. Clock redundancy is achieved by sending Ethernet packets in a single domain, which simplifies the logic and reduces resource consumption.

[0071] In some embodiments, the above Figure 1 S103 can also be implemented in the following way: When the first device is detected to be in a normal state, a first switching instruction is sent to the first device, and a second application message carrying the normal information of the first device is sent to the second device, which is the master clock, so that the second device will switch its role in the protocol stack from master clock to slave clock based on the second application message.

[0072] In this embodiment of the invention, when the gPTP protocol stack detects that the second device has returned to normal state, it sends a first switching instruction to it, causing the first device to switch from abnormal mode to normal mode, that is, its role in the gPTP protocol stack changes from Slave to Master. Simultaneously, the gPTP protocol stack sends an application message (i.e., a second application message) containing mode information to the second device. After receiving the mode information of the application message, the second device parses it. When it determines that the second device is in normal state, the second device switches from abnormal mode to normal mode, that is, its role in the gPTP protocol stack changes from Master to Slave.

[0073] In this embodiment of the invention, when the protocol stack detects that the first device, which is the slave clock, has returned to the normal state (i.e., normal operation), the roles in the protocol stack are switched again. The role of the first device in the gPTP protocol stack is switched from Slave to Master, and the role of the second device in the gPTP protocol stack is switched from Master to Slave. Clock redundancy is achieved by sending Ethernet packets in a single domain, which simplifies the logic and reduces resource consumption.

[0074] In some embodiments, the second application message is an Ethernet message on a single domain.

[0075] In some embodiments, the second application message includes a source address, a destination address, a working mode, and data; a description of the second application message can be found in the first application message described above, and will not be repeated here.

[0076] In some embodiments, in the above Figure 1 Prior to S101, the clock synchronization method also includes: reading the register of the first device; and determining whether the first device is in an abnormal state based on the parameters stored in the register that characterize the working state of the first device.

[0077] In this embodiment of the invention, the clock synchronization device carries a protocol stack and can read the operating status of the first and second devices in the protocol stack. The first and second devices have registers that store operating parameters, raw data, intermediate data, processing results, and operating status. When the first device detects an anomaly, it records this information in the register. Based on this, the clock synchronization device reads the first device's register and determines whether the first device is in an abnormal state based on the parameters stored in the register that characterize the first device's operating status. Furthermore, when an abnormal state is detected, the role of the first device is switched using the gPTP protocol stack combined with Ethernet packets, and the switch switches modes. This enables clock redundancy within a single domain, simplifies the logic, and reduces resource consumption.

[0078] In some embodiments, the clock synchronization device includes a switch, which is connected to a first device and a second device respectively. The step of sending the first application message can be implemented by sending a first application message carrying abnormal information of the first device to the second device, which is a slave clock, through the switch. Based on this, the clock synchronization method further includes the following step: the switch switches from a first mode to a second mode based on the first application message; wherein, in the first mode, the first slave port of the switch is connected to the first device and the first master port of the switch is connected to the second device, and in the second mode, the second slave port of the switch is connected to the second device and the second master port of the switch is connected to the first device.

[0079] In this embodiment of the invention, the message exchange between the first device, the second device, and the clock synchronization device is implemented through a switch. The switch can be regarded as a bridge for communication between devices, and the communication channel provided by the switch is from Master to Slave. The switch has many ports, and when the roles of the master clock and the slave clock change in the protocol stack, the port connections of the switch also change accordingly. The connection states of different ports can form different communication channels so that the master clock and the slave clock can send Ethernet messages through the communication channels.

[0080] In this embodiment of the invention, both the first mode and the second mode are master-to-slave clock switching. The switch has many ports (input and output interfaces), and mode switching ensures that Ethernet packets are switched from the master clock to the slave clock. When transmitting packets, the switch can switch its operating mode based on the application packet. For example, when transmitting a first application packet carrying information about a first device's abnormality, the switch switches from the first mode to the second mode based on the first application packet. That is, the end connected to the first device switches from Slave to Master, and the end connected to the second device switches from Master to Slave.

[0081] For example, taking controller A as the first device and controller B as the second device, under normal circumstances, controller A, acting as the Master, sends time synchronization messages to controller B, and controller B, acting as the Slave, receives the time synchronization messages. At this time, the switch operates in domain 0 (corresponding to the first mode), meaning the end connected to controller A is the Slave (corresponding to the first slave port), and the end connected to controller B is the Master (corresponding to the first master port). When the gPTP protocol stack detects an anomaly in controller A, it sends a command to switch controller A from normal mode to an abnormal mode, i.e., the gPTP protocol stack switches from Master to Slave. Then, the gPTP protocol stack sends an application message with mode information (corresponding to the first application message) to controller B. After receiving the mode information in the application message, controller B also switches from normal mode to an abnormal mode, i.e., the gPTP protocol stack switches from Slave to Master. Simultaneously, the switch switches from domain 0 to domain 1 (corresponding to switching from the first mode to the second mode), meaning the end connected to controller A is the Master, and the end connected to controller B is the Slave. The above-mentioned switch from domain0 to domain1 can be understood as a switch from mode 0 to mode 1 to ensure successful transmission of Ethernet packets.

[0082] It should be noted that the switch from Slave to Master for controller B and the switch switch from domain0 to domain1 can occur simultaneously or in any order. The switch acts as a bridge for protocol stack communication. The switch receives the first application message from the gPTP protocol stack and forwards it to controller B. During this process, the switch switches from domain0 to domain1 after receiving the first application message.

[0083] In this embodiment of the invention, a switch is used to realize the transmission of messages between various devices in the protocol stack, and the working mode of the switch (first mode and second mode) switches according to the application message to ensure successful transmission of Ethernet messages. This enables clock redundancy to be achieved in a single domain by sending Ethernet messages, which simplifies the logic and reduces resource consumption.

[0084] In some embodiments, the clock synchronization device includes a switch, which is connected to both the first device and the second device. The step of sending the second application message described above can be implemented by sending a second application message carrying the general information of the first device to the second device, which acts as the master clock, via the switch. Based on this, the clock synchronization method further includes the following step: the switch switches from a second mode to a first mode based on the second application message.

[0085] In this embodiment of the invention, the switch can switch its operating mode according to the application message when transmitting packets. For example, when transmitting a second application message carrying the general information of the first device, the switch switches from the second mode to the first mode based on the second application message. That is, the end connected to the first device switches from Master to Slave, and the end connected to the second device switches from Slave to Master.

[0086] For example, taking controller A as the first device and controller B as the second device, after controller A successfully synchronizes its time, it switches back to normal mode. The gPTP protocol stack sends a second application message to controller B. Upon receiving the second application message, controller B also switches back to normal mode, meaning its role in the protocol stack changes from Master to Slave. Simultaneously, the switch switches to domain0, meaning the end connected to controller A is the Slave, and the end connected to controller B is the Master.

[0087] The following will describe an exemplary application of the embodiments of the present invention in a practical application scenario.

[0088] like Figure 3 As shown, Figure 3The following is an optional flowchart of another clock synchronization method provided in an embodiment of the present invention. This clock synchronization method can be executed by a clock synchronization device and includes steps S201-S206.

[0089] S201. Read the register of the first device, and determine whether the first device is in an abnormal state based on the parameters stored in the register that characterize the working state of the first device.

[0090] S202. When the first device acting as the master clock is detected to be in an abnormal state, the switch sends a first application message carrying the abnormal information of the first device to the second device acting as the slave clock, so that the second device will switch its role in the protocol stack from slave clock to master clock based on the first application message; and sends a second switching instruction to the first device, so that the first device will switch its role in the protocol stack from master clock to slave clock based on the second switching instruction.

[0091] In this example, the implementation process and technical effects of S202 can be found in the above description of S101, and will not be repeated here.

[0092] S203, the switch switches from the first mode to the second mode based on the first application message.

[0093] It should be noted that the steps of sending the first application message to the second device and sending the second switching command to the first device via the switch are not sequential and can be executed simultaneously or in any order. Similarly, the steps of the second device switching from a slave clock to a master clock, the first device switching from a master clock to a slave clock, and the switch switching from the first mode to the second mode are not sequential and can be executed simultaneously or in any order. This embodiment of the invention does not impose any limitations on these steps.

[0094] S204. Based on the current timestamp of the second device, which serves as the master clock, a first time synchronization message is sent to the first device through the switch, so that the first device can resume its normal state after successful synchronization based on the first time synchronization message.

[0095] In this example, the implementation process and technical effect of S204 can be found in the description of S102 above, and will not be repeated here.

[0096] S205. When the first device is detected to be in a normal state, a first switching instruction is sent to the first device through the switch, so that the first device will switch its role in the protocol stack from slave clock to master clock based on the first switching instruction; and a second application message carrying the normal information of the first device is sent to the second device, which is the master clock, so that the second device will switch its role in the protocol stack from master clock to slave clock based on the second application message.

[0097] In this example, the implementation process and technical effect of S205 can be found in the description of S103 above, and will not be repeated here.

[0098] It should be noted that the steps of sending the first switching command to the first device and the second application message to the second device via the switch are not sequential and can be executed simultaneously or in any order. Similarly, the steps of the second device switching from master clock to slave clock, the first device switching from slave clock to master clock, and the switch switching from second mode to first mode are not sequential and can be executed simultaneously or in any order. This embodiment of the invention does not impose any limitations on these steps.

[0099] S206. The switch switches from the second mode to the first mode based on the second application message.

[0100] In this embodiment of the invention, the clock synchronization method involves a protocol stack, a first device, a second device, and a switch. The protocol stack performs logical control over various devices using the same protocol, and the switch provides the transmission path for Ethernet packets between the protocol stack, the first device, and the second device. In case of an anomaly, the switching between the master and slave clocks within a single domain is completed within the same protocol stack. Clock synchronization redundancy is achieved by sending application packets, simplifying the logic and reducing resource consumption.

[0101] In some embodiments, such as Figure 4 As shown, Figure 4 A flowchart illustrating optional steps of another clock synchronization method provided in this embodiment of the invention; based on the above... Figure 1 Following S103, the clock synchronization method further includes S104.

[0102] S104. Based on the current timestamp of the first device, which is now the master clock, a second time synchronization message is sent to the second device, and a third time synchronization message is sent to other devices, so that the second device performs time synchronization based on the second time synchronization message, and other devices perform their own time correction based on the third time synchronization message.

[0103] In this embodiment of the invention, after the first device becomes the master clock again, the clock synchronization device sends a second time synchronization message to the second device based on the current timestamp of the first device. The second device then performs time synchronization based on the second time synchronization message, thus restoring the time synchronization process to normal operation. During the period when the first device is in an abnormal state, other devices perform their respective tasks according to their own times. Only after the first device becomes the master clock again do the other devices receive the third time synchronization message sent by the first device to perform time synchronization. The number of other devices can be one, two, or more.

[0104] For example, taking controller A as the first device and controller B as the second device, controller A is used as the master clock device, and controller B is used as a redundant clock device. Controller A and controller B synchronize their time through a switch, and then synchronize with other controllers (the number of other controllers can be one, two, or more). After controller A successfully synchronizes, controller A re-acts as the master clock and sends a time synchronization message to controller B, while simultaneously synchronizing with other controllers.

[0105] It should be noted that the above S104 can also be in Figure 3 After S206 in the middle.

[0106] The clock redundancy method provided in this embodiment of the invention requires only one protocol stack, has simple logic, and reduces the resources consumed.

[0107] In some embodiments, the first time synchronization message, the second time synchronization message, the third time synchronization message, the first application message, and the second application message are Ethernet messages on a single domain.

[0108] Based on the above Figures 1-4 This invention provides a single-domain clock synchronization redundancy method. The message transmission relationship between various controllers is as follows: Figure 5 As shown, Figure 5 This diagram illustrates a message transmission relationship between controllers according to an embodiment of the present invention. This message transmission relationship is applicable to a clock synchronization redundancy system (also known as a clock synchronization system). The clock synchronization redundancy system includes controller A, controller B, a switch, and other controllers. Controller A and controller B each have a gPTP protocol stack, which can be switched as Master or Slave as needed for time synchronization. Real-world automotive Ethernet systems may include more nodes and links, resulting in a more complex ring network. Figure 5 This is merely a simplified illustration, and the embodiments of the present invention do not impose any limitations on it. The switch acts as a communication bridge between controller A, controller B, and other controllers. In the event of an anomaly, it completes the switching between the master and slave clocks within the same protocol stack, achieving clock synchronization redundancy by sending application messages. This simplifies the logic and reduces resource consumption.

[0109] The following will describe an exemplary application of the embodiments of the present invention in a practical application scenario.

[0110] Based on the above Figure 5 In a related clock synchronization redundancy system, this invention provides a clock redundancy method in a single-domain scenario, the flowchart of which is shown below. Figure 6 As shown, Figure 6This is an optional flowchart of a single-domain clock synchronization redundancy method provided in an embodiment of the present invention; since controller A is not abnormally restarted, it is normal time synchronization, and will not be described in detail here. The single-domain clock synchronization redundancy method includes S301-S305.

[0111] S301, Controller A restarts abnormally and sends an application message.

[0112] Controller A determines that it has restarted abnormally. The gPTP protocol stack detects this abnormal restart and sends an application message (corresponding to the first application message) to controller B. The application message format is as described above. Figure 2 As shown, 0x00 represents the normal mode, and 0x01 represents the abnormal mode;

[0113] S302, Controller and Switch switch roles.

[0114] Controller A switches its role from Master to Slave in the gPTP protocol stack. After receiving the application message and parsing the abnormal mode, controller B switches its role from Slave to Master in the gPTP protocol stack. At the same time, the switch switches from Domain0 to Domain1.

[0115] S303, Controller B synchronizes with Controller A and sends application messages.

[0116] The gPTP protocol stack uses the current timestamp of controller B as the synchronization time and sends a time synchronization message (corresponding to the first time synchronization message) to controller A. Controller A performs time synchronization. After controller A determines that time synchronization is successful, the gPTP protocol stack detects that controller A is working normally, i.e., in normal mode, and sends an application message in normal mode (corresponding to the second application message) to controller B.

[0117] S304, controller and switch role switching.

[0118] Switch controller A's gPTP protocol stack to normal mode. After receiving the application message, controller B also switches its gPTP protocol stack to normal mode. At the same time, the switch switches from Domain1 to Domain0.

[0119] S305, Controller A synchronizes with other controllers.

[0120] After controller B determines that time synchronization is successful, controller A acts as the master clock to synchronize time with other controllers. Then, to restore normal operation, controller A sends a time synchronization message to controller B.

[0121] The single-domain clock synchronization redundancy method provided in this invention completes the switching between the master clock and slave clock in a single domain within the same protocol stack. It achieves clock synchronization redundancy settings by sending application messages, simplifying the logic and reducing resource consumption.

[0122] In an embodiment of the present invention, Figure 7 This is a schematic diagram of the composition structure of the clock synchronization device proposed in an embodiment of the present invention, as shown below. Figure 7 As shown, the clock synchronization device 70 proposed in this embodiment of the invention includes a processor 701 and a memory 702 for storing executable computer programs. The processor 701 is used to implement the clock synchronization method provided in this embodiment of the invention when executing the executable computer program stored in the memory 702.

[0123] In some embodiments, the clock synchronization device 70 may further include a communication interface 703 and a bus 704 for connecting the processor 701, the memory 702 and the communication interface 703.

[0124] In this embodiment of the invention, the processor 701 can be at least one of the following: Application-Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that for different devices, the electronic device used to implement the above-mentioned processor function can also be other types, and this embodiment of the invention does not specifically limit the specific types.

[0125] In this embodiment of the invention, bus 704 is used to connect communication interface 703, processor 701 and memory 702 to realize mutual communication between these devices.

[0126] Memory 702 is used to store executable computer programs and data, including computer operation instructions. Memory 702 may include high-speed RAM and may also include non-volatile memory, such as at least two disk drives. In practical applications, the memory 702 may be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); or a combination of the above types of memory, and provides executable computer programs and data to processor 701.

[0127] Furthermore, in this embodiment, the functional modules can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.

[0128] If the integrated unit is implemented as a software functional module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method of this embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] This invention provides a computer-readable storage medium storing a computer program for implementing the clock synchronization method described in any of the above embodiments when executed by a processor.

[0130] For example, the program instructions corresponding to a clock synchronization method in this embodiment can be stored on storage media such as optical discs, hard disks, and USB flash drives. When the program instructions corresponding to a clock synchronization method in the storage medium are read or executed by an electronic device, the clock synchronization method as described in any of the above embodiments can be implemented.

[0131] To implement the clock synchronization method of this invention, this invention also provides a clock synchronization system, such as... Figure 8 As shown, Figure 8 This is a schematic diagram of an optional structure of a clock synchronization system provided in an embodiment of the present invention. The clock synchronization system 80 includes: a clock synchronization device 70 carrying a protocol stack, a first device 801, and a second device 802. The clock synchronization device 70 is connected to the first device 801 and the second device 802, respectively. The clock synchronization device 70, the first device 801, and the second device 802 use the same protocol stack. When the clock synchronization device 70 detects that the first device 801, which is the master clock, is in an abnormal state, it sends a first application carrying abnormal information of the first device to the second device 802, which is the slave clock. The message; the second device 802 will switch its role in the protocol stack from slave clock to master clock based on the first application message; the clock synchronization device 70 will send a first time synchronization message to the first device 801 based on the current timestamp of the second device 802 as the master clock; the first device 801 will resume its normal state after successful synchronization based on the first time synchronization message; when the clock synchronization device 70 detects that the first device 801 is in the normal state, it will send a first switching instruction to the first device 801; the first device 801 will switch its role in the protocol stack from slave clock to master clock based on the first switching instruction.

[0132] In some embodiments, the clock synchronization device 70 includes a switch, which is connected to a first device 801 and a second device 802 respectively; the switch sends a first application message carrying first device abnormality information to the second device 802, which is a slave clock; the switch switches from a first mode to a second mode based on the first application message; wherein, in the first mode, the first master port of the switch is connected to the first device 801 and the first slave port of the switch is connected to the second device 802, and in the second mode, the second master port of the switch is connected to the second device 802 and the second slave port of the switch is connected to the first device 801.

[0133] In some embodiments, the clock synchronization device 70 includes a switch, which is connected to a first device 801 and a second device 802 respectively; the switch sends a second application message carrying the general information of the first device to the second device 802, which serves as the master clock; the switch switches from a second mode to a first mode based on the second application message.

[0134] In some embodiments, when the clock synchronization device 70 detects that the first device 801, which is the master clock, is in an abnormal state, it sends a first application message carrying the abnormal information of the first device to the second device 802, which is the slave clock, and sends a second switching instruction to the first device 801; the second device 802 switches its role in the protocol stack from slave clock to master clock based on the first application message; the first device 801 switches its role in the protocol stack from master clock to slave clock based on the second switching instruction.

[0135] In some embodiments, when the clock synchronization device 70 detects that the first device 801 is in a normal state, it sends a first switching instruction to the first device 801 and sends a second application message carrying the normal information of the first device to the second device 802, which is the master clock; the first device 801 switches its role in the protocol stack from slave clock to master clock based on the first switching instruction; the second device 802 switches its role in the protocol stack from master clock to slave clock based on the second application message.

[0136] In some embodiments, clock synchronization device 70 sends a second time synchronization message to second device 802 based on the current timestamp of first device 801, which is now the master clock, and sends a third time synchronization message to other devices; second device 802 performs time synchronization based on the second time synchronization message; other devices perform their own time corrections based on the third time synchronization message.

[0137] In some embodiments, the clock synchronization device 70 reads the register of the first device 801; and determines whether the first device 801 is in an abnormal state based on the parameters stored in the register that characterize the working state of the first device.

[0138] It should be noted that the clock synchronization system provided in the above embodiments is only illustrated by the division of the program devices described above. In practical applications, the above processing can be assigned to different program devices as needed, that is, the internal structure of the system can be divided into different program devices to complete all or part of the processing described above. Furthermore, the clock synchronization system and clock synchronization method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process and beneficial effects are detailed in the method embodiments, which will not be repeated here. For technical details not disclosed in this system embodiment, please refer to the description of the method embodiments of the present invention for understanding.

[0139] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0140] This invention is described with reference to schematic and / or block diagrams illustrating the implementation of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the schematic and / or block diagrams can be implemented by computer program instructions, as well as combinations of blocks in the schematic and / or block diagrams. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the schematic and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0141] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in the implementation flow diagram. Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0142] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0143] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A clock synchronization method, characterized in that, The method is applied to a clock synchronization device carrying a protocol stack. The clock synchronization device is connected to a first device and a second device, respectively. The clock synchronization device, the first device, and the second device use the same protocol stack. The method includes: When an abnormal state is detected in the first device acting as the master clock, a second switching instruction is sent to the first device, causing the first device to switch its role in the protocol stack from master clock to slave clock based on the second switching instruction; simultaneously, a first application message carrying abnormal information of the first device is sent to the second device acting as the slave clock, causing the second device to switch its role in the protocol stack from slave clock to master clock based on the first application message; wherein, the first application message includes the address of the device acting as the master clock, the address of the device acting as the slave clock, and the working state of the device acting as the master clock, the working state including abnormal state and normal state; Based on the current timestamp of the second device, which acts as the master clock, a first time synchronization message is sent to the first device, so that the first device can resume its normal state after successful synchronization based on the first time synchronization message during operation. When the first device is detected to be in a normal state, a first switching instruction is sent to the first device, causing the first device to switch its role in the protocol stack from slave clock to master clock based on the first switching instruction.

2. The method according to claim 1, characterized in that, When the first device is detected to be in a normal state, sending a first switching command to the first device includes: When the first device is detected to be in a normal state, the first switching instruction is sent to the first device, and a second application message carrying the normal state information of the first device is sent to the second device, which is the master clock, so that the second device will switch its role in the protocol stack from master clock to slave clock based on the second application message.

3. The method according to any one of claims 1-2, characterized in that, The clock synchronization device includes a switch, which is connected to the first device and the second device respectively; Sending a first application message carrying first device error information to a second device acting as a slave clock includes: The switch sends a first application message carrying abnormal information of the first device to a second device acting as a slave clock. The method further includes: The switch switches from a first mode to a second mode based on the first application message; wherein, in the first mode, the first slave port of the switch is connected to the first device and the first master port of the switch is connected to the second device; in the second mode, the second slave port of the switch is connected to the second device and the second master port of the switch is connected to the first device.

4. The method according to claim 2, characterized in that, The clock synchronization device includes a switch, which is connected to the first device and the second device respectively; Sending a second application message carrying routine information of the first device to the second device, which acts as the master clock, includes: The switch sends a second application message carrying routine information of the first device to the second device, which acts as the master clock. The method further includes: The switch switches from the second mode to the first mode based on the second application message.

5. The method according to any one of claims 1-2, characterized in that, After the first device switches its role in the protocol stack from slave clock to master clock based on the first switching instruction, the method further includes: Based on the current timestamp of the first device, which is now acting as the master clock, a second time synchronization message is sent to the second device, and a third time synchronization message is sent to the other devices. This allows the second device to synchronize its time based on the second time synchronization message, and the other devices to perform their own time corrections based on the third time synchronization message.

6. The method according to any one of claims 1-2, characterized in that, Before sending a first application message carrying the abnormality information of the first device to the second device, which is the slave clock, when an abnormal state is detected in the first device acting as the master clock, the method further includes: Read the registers of the first device; Based on the parameters stored in the register that characterize the working state of the first device, it is determined whether the first device is in an abnormal state.

7. The method according to any one of claims 1-2, characterized in that, Both the first application message and the second application message include a source address, a destination address, a working mode, and data; Wherein, the source address represents the address of the device acting as the master clock; the destination address represents the address of the device acting as the slave clock; the operating mode represents the operating state of the device acting as the master clock, and the operating state includes abnormal state and normal state; the data includes the rules for judging the operating state.

8. The method according to any one of claims 1-2, characterized in that, The first time synchronization message, the second time synchronization message, the third time synchronization message, the first application message, and the second application message are Ethernet messages on a single domain.

9. A clock synchronization device, characterized in that, The device includes: Memory, used to store executable computer programs; A processor, when executing an executable computer program stored in the memory, implements the method according to any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The device contains a computer program that, when executed by a processor, implements the method described in any one of claims 1-8.

11. A clock synchronization system, characterized in that, The system includes a clock synchronization device carrying a protocol stack, a first device, and a second device. The clock synchronization device is connected to the first device and the second device respectively, and the clock synchronization device, the first device, and the second device use the same protocol stack. When the clock synchronization device detects that the first device, which serves as the master clock, is in an abnormal state, it sends a second switching command to the first device. The first device will switch its role in the protocol stack from master clock to slave clock based on the second switching instruction; Send a first application message carrying abnormal information of the first device to the second device, which is acting as a slave clock; The second device will switch its role in the protocol stack from slave clock to master clock based on the first application message; wherein, the first application message includes the address of the device as master clock, the address of the device as slave clock, and the working state of the device as master clock, the working state including abnormal state and normal state; The clock synchronization device sends a first time synchronization message to the first device based on the current timestamp of the second device, which serves as the master clock. When the first device is working, it resumes its normal state after successful synchronization based on the first time synchronization message; When the clock synchronization device detects that the first device is in a normal state, it sends a first switching command to the first device; Based on the first switching instruction, the first device will switch its role in the protocol stack from slave clock to master clock.

12. The system according to claim 11, characterized in that, The clock synchronization device includes a switch, which is connected to the first device and the second device respectively; The switch sends a first application message carrying abnormal information of the first device to a second device acting as a slave clock. The switch switches from a first mode to a second mode based on the first application message; wherein, in the first mode, the first master port of the switch is connected to the first device and the first slave port of the switch is connected to the second device, and in the second mode, the second master port of the switch is connected to the second device and the second slave port of the switch is connected to the first device.

13. The system according to claim 11, characterized in that, The clock synchronization device includes a switch, which is connected to the first device and the second device respectively; The switch sends a second application message carrying routine information of the first device to the second device, which acts as the master clock. The switch switches from the second mode to the first mode based on the second application message.

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