Semiconductor structure and method of forming the same
By introducing a barrier layer into the semiconductor structure, the coupling problem between the gate and drain is solved, the GIDL is reduced, the device performance and integration are improved, hydrogen accumulation is prevented, and higher memory integration is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-05-29
- Publication Date
- 2026-07-24
AI Technical Summary
In existing 3D memories, coupling can easily occur between the gate layer and drain of the memory cell, leading to increased GIDL, which affects device performance and limits the miniaturization of memory devices.
Introducing a barrier layer into the semiconductor structure increases the distance between the gate and the drain, and prevents hydrogen accumulation, thereby reducing leakage current.
It effectively reduces the coupling between the gate and drain, decreases the GIDL, improves the device's performance and integration, and prevents the accumulation of hydrogen in the channel.
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Figure CN116744676B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is widely used in smart devices due to its small size, high transfer speed, and high integration. As terminal devices continue to shrink, the size of memory is also shrinking. CAA (Channel All Around) technology, as a type of 3D memory, breaks down the barriers of planar memory, allowing memory structures to evolve in three-dimensional space and improving memory integration.
[0003] Currently, 3D memories can arrange multiple memory cells in a direction perpendicular to the substrate. However, due to limitations in memory size and fabrication process, coupling can easily occur between the gate layer and drain in the memory cell, leading to an increase in GIDL (Gate-induced Drain Leakage) and affecting the overall performance of the device.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] In view of this, a semiconductor structure is provided that reduces the coupling between the drain and the gate, decreases the GIDL, and prevents hydrogen from accumulating in the channel, thereby reducing leakage current.
[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.
[0007] According to one aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: a substrate;
[0008] A first film structure is formed on the substrate. The first film structure includes a plurality of first semiconductor layers, a dielectric layer, and a second semiconductor layer. The plurality of first semiconductor layers are spaced apart on the substrate. The dielectric layer fills the gaps between the plurality of first semiconductor layers and covers the top surface of the first semiconductor layers.
[0009] A barrier layer, wherein the barrier layer is located on the top surface of the first film structure;
[0010] A via, which passes through the barrier layer, the second semiconductor layer and the dielectric layer to expose the first semiconductor layer, and the via corresponds one-to-one with the first semiconductor layer;
[0011] The second film layer structure includes a channel layer, a gate dielectric layer and a gate layer sequentially disposed along a direction away from the substrate. The channel layer and the gate dielectric layer are disposed within the channel hole and extend to the top surface of the barrier layer. The gate layer covers the gate dielectric layer and fills the channel hole.
[0012] In some embodiments of this disclosure, based on the foregoing scheme, the first semiconductor layer and the second semiconductor layer are indium gallium zinc oxide film layers.
[0013] In some embodiments of this disclosure, based on the foregoing scheme, the channel layer is made of the same material as the first semiconductor layer and / or the second semiconductor layer.
[0014] In some embodiments of this disclosure, based on the foregoing scheme, the gate layer includes a first gate layer and a second gate layer stacked together, wherein the work functions of the first gate layer and the second gate layer are different.
[0015] In some embodiments of this disclosure, based on the foregoing scheme, the barrier layer includes any one or more of silicon, nitrogen, boron, and carbon elements.
[0016] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: providing a substrate;
[0017] A first film structure is formed on the substrate. The first film structure includes a plurality of first semiconductor layers, a dielectric layer, and a second semiconductor layer sequentially formed on the substrate. The plurality of first semiconductor layers are spaced apart on the substrate. The dielectric layer fills the gaps between the plurality of first semiconductor layers and covers the top surface of the first semiconductor layers.
[0018] A barrier layer is formed on the second semiconductor layer;
[0019] The barrier layer and the first film layer structure are etched to form a plurality of channel holes, which pass through the barrier layer, the second semiconductor layer and the dielectric layer to expose the first semiconductor layer, and the channel holes correspond one-to-one with the first semiconductor layer;
[0020] A second film structure is formed, the second film structure including a channel layer, a gate dielectric layer and a gate layer disposed sequentially along the direction away from the substrate, the channel layer and the gate dielectric layer being formed conformally in the channel hole and extending to the top surface of the barrier layer, the gate layer covering the gate dielectric layer and filling the channel hole.
[0021] In some embodiments of this disclosure, after forming the second film structure based on the foregoing scheme, the method further includes:
[0022] Using the barrier layer as an etch stop layer, the second film structure is etched so that the side surfaces of the channel layer, the gate dielectric layer, and the gate layer are flush with each other in a direction perpendicular to the substrate, thereby forming a plurality of semiconductor structures, each of which corresponds one-to-one with the channel via.
[0023] In some embodiments of this disclosure, based on the foregoing scheme, the method further includes:
[0024] After the first semiconductor layer is formed, the first semiconductor layer is subjected to heat treatment;
[0025] After the second semiconductor layer is formed, the second semiconductor layer is subjected to heat treatment.
[0026] In some embodiments of this disclosure, based on the foregoing scheme, the first semiconductor layer and the second semiconductor layer are indium gallium zinc oxide film layers.
[0027] In some embodiments of this disclosure, based on the foregoing scheme, the channel layer is made of the same material as the first semiconductor layer and / or the second semiconductor layer.
[0028] This disclosure provides a semiconductor structure including a substrate, a first film layer structure and a second film layer structure disposed on the substrate, and a barrier layer disposed between the first film layer structure and the second film layer structure. On the one hand, by setting the barrier layer, the distance between the gate and the drain can be increased, the coupling effect between the gate and the drain can be reduced, and the gate-induced drain current can be reduced. On the other hand, by setting the barrier layer, external hydrogen elements can be prevented from accumulating in the channel, reducing leakage current. Thirdly, the barrier layer can serve as an etch stop layer during the device formation process to prevent over-etching of the film layer.
[0029] This disclosure also provides a method for forming a semiconductor structure, which involves forming a first film structure and a second film structure on a substrate, and forming a barrier layer between the first film structure and the second film structure to increase the distance between the gate and the drain in the device, reduce the coupling between the gate and the drain, and reduce the gate-induced drain current; the barrier layer can serve as an etch stop layer during the device formation process to prevent over-etching of the film layer; this formation method is simple and easy to implement.
[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0032] Figure 1 This is a three-dimensional cross-sectional view of an existing storage unit in an exemplary embodiment of the present disclosure.
[0033] Figure 2 This is a schematic diagram of a conventional memory cell structure in an exemplary embodiment of the present disclosure.
[0034] Figures 3-5 This is a schematic diagram of a conventional storage cell formation process in an exemplary embodiment of the present disclosure.
[0035] Figure 6 In exemplary embodiments of this disclosure Figure 5 A top-view structural diagram of the provided storage unit.
[0036] Figure 7 This is a flowchart illustrating a method for forming a storage cell in the prior art, as shown in an exemplary embodiment of this disclosure.
[0037] Figure 8 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0038] Figures 9-19 This is a schematic diagram of the formation process of a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0039] Figure 20 In exemplary embodiments of this disclosure Figure 19 A cross-sectional view of the semiconductor structure along the AA direction.
[0040] Figure 21 This is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.
[0041] Figure 22 This is a flowchart of a method for forming a first semiconductor layer according to an exemplary embodiment of the present disclosure.
[0042] The reference numerals in the attached figures are explained as follows:
[0043] 100: Substrate; 200: First film layer structure; 210: First semiconductor layer; 211: Intermediate film layer; 212: Spacing hole; 220: Dielectric layer; 230: Second semiconductor layer; 300: Barrier layer; 400: Channel hole; 500: Second film layer structure; 510: Channel layer; 520: Gate dielectric layer; 530: Gate layer; 531: First gate layer; 532: Second gate layer; 600: Fill layer; 20: MIM structure; 30: Via; 40: Channel; 50: Isolation layer; 60: Gate electrode layer. Detailed Implementation
[0044] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0045] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0046] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0047] In related technologies, indium gallium zinc oxide (IGZO) is a novel semiconductor material that can be used as a film layer material in thin-film transistors (TFTs). Compared to amorphous silicon, it has higher electron mobility, which can improve the information transmission capacity of the device. In 3D DRAM, the traditional memory structure of one transistor + one capacitor is limited by the large area occupied by the capacitor, which restricts the critical dimensions of the device and limits its density. To improve this situation, a capacitor-free DRAM structure based on indium gallium zinc oxide (IGZO) is proposed. This capacitor-free memory architecture, composed of two indium gallium zinc oxide (IGZO) thin-film transistors (TFTs), significantly improves the structural density of the memory, increases the integration level of the device, and reduces the structural size of the device.
[0048] Currently, the structure of dynamic random access memory is as follows: Figure 1-7 As shown, its formation process includes:
[0049] Step S101: As Figure 2 As shown, a MIM (Metal Insulator Metal) structure 20 is formed on the substrate 100;
[0050] Step S102: As Figure 3 As shown, a via 30 is formed on the MIM structure 20;
[0051] Step S103: As Figure 4 As shown, a channel 40, an isolation layer 50, and a gate electrode layer 60 are sequentially formed in the via 30;
[0052] Step S104: As Figure 5 As shown, the channel 40, the isolation layer 50 and the gate electrode layer 60 are etched to expose the upper metal layer in the MIM structure 20, forming multiple isolated memory cells.
[0053] The memory device formed through steps S101 to S104 has a large coupling effect between the drain (source) and the gate due to the small distance between them. This results in a large parasitic capacitance and a large gate-induced drain current (GIDL). In addition, the drain (source) in the memory device is directly exposed to the external environment, which can easily cause contamination during subsequent processing. Furthermore, during the manufacturing process, the channel 40, the isolation layer 50, and the gate electrode layer 60 located on the upper metal layer need to be etched. During the etching process, the structure of the upper metal layer can easily be damaged, thereby affecting the performance of the drain (source) in the device and the overall performance of the device.
[0054] Based on this, the present disclosure provides a semiconductor structure, such as... Figures 8-20 As shown, the semiconductor structure includes: a substrate 100, a first film structure 200, a barrier layer 300, a channel hole 400, and a second film structure 500.
[0055] The first film structure 200 is formed on the substrate 100 and includes a plurality of first semiconductor layers 210, a dielectric layer 220, and a second semiconductor layer 230. The plurality of first semiconductor layers 210 are spaced apart on the substrate 100, and the dielectric layer 220 fills the gaps between the plurality of first semiconductor layers 210 and covers the top surface of the first semiconductor layers 210. A barrier layer 300 is located on the top surface of the first film structure 200. A channel via 400 passes through the barrier layer 300 and the second semiconductor layer 230. The body layer 230 and the dielectric layer 220 expose the first semiconductor layer 210, and the channel hole 400 corresponds one-to-one with the first semiconductor layer 210; the second film layer structure 500 includes a channel layer 510, a gate dielectric layer 520 and a gate layer 530 sequentially disposed along the direction away from the substrate 100. The channel layer 510 and the gate dielectric layer 520 are disposed conformally in the channel hole 400 and extend to the top surface of the barrier layer 300. The gate layer 530 covers the gate dielectric layer 520 and fills the channel hole 400.
[0056] The semiconductor structure disclosed herein includes a substrate 100, a first film structure 200 and a second film structure 500 disposed on the substrate 100, and a barrier layer 300 disposed between the first film structure 200 and the second film structure 500. By disposing of the barrier layer 300, the distance between the gate and the drain can be increased, the coupling between the gate and the drain can be reduced, and the gate-induced drain current can be reduced. By disposing of the barrier layer 300, external hydrogen elements can be prevented from accumulating in the channel, reducing leakage current. The barrier layer 300 can also serve as an etch stop layer during the device formation process to prevent over-etching of the film.
[0057] The various parts of the semiconductor structure provided in the embodiments of this disclosure will now be described in detail:
[0058] In the embodiments provided in this disclosure, the semiconductor structure includes a substrate 100. For example... Figure 9As shown, substrate 100 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), gallium phosphide (GaP), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), zinc telluride (ZnTe), or cadmium sulfide (CdS). The embodiments provided in this disclosure are illustrated using a substrate 100 comprising silicon (Si) ions as an example. Of course, for other types of substrates, corresponding modifications or improvements can be made to the embodiments of this disclosure, all of which are within the protection scope of this disclosure, and this disclosure does not specifically limit them.
[0059] In the embodiments provided in this disclosure, such as Figure 12 As shown, a first film structure 200 is formed on a substrate 100. The first film structure 200 includes a first semiconductor layer 210, a dielectric layer 220, and a second semiconductor layer 230. There can be multiple first semiconductor layers 210, which are spaced apart on the substrate 100. The dielectric layer 220 fills the gaps between the multiple first semiconductor layers 210 and covers the top surface of the first semiconductor layers 210. The second semiconductor layer 230 is formed on the surface of the dielectric layer 220.
[0060] The first film structure 200 includes a first semiconductor layer 210. For example... Figure 10 As shown, forming a first semiconductor layer 210 on a substrate 100 includes: forming an intermediate film layer 211 on the substrate 100, the intermediate film layer 211 covering the surface of the substrate 100; etching the intermediate film layer 211 to form a plurality of spacer holes 212 on the intermediate film layer 211, each spacer hole 212 exposing the surface of the substrate 100 to form a plurality of first semiconductor layers 210, adjacent first semiconductor layers 210 being separated by spacer holes 212.
[0061] In this disclosure, there can be multiple first semiconductor layers 210, which are spaced apart on the substrate 100. For example, to fully utilize the surface of the substrate 100, the multiple first semiconductor layers 210 can be uniformly arranged in an array on the substrate 100. This disclosure does not impose specific limitations on the number and arrangement of the first semiconductor layers 210, which can be selected according to the actual structural design requirements of the device.
[0062] The first semiconductor layer 210 may include an oxide semiconductor material, for example, a film formed of an oxide semiconductor material such as indium gallium zinc oxide (IGZO). The first semiconductor layer 210 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD) (such as magnetron sputtering deposition) or other deposition methods.
[0063] The oxide layer deposited on the substrate 100 is a semiconductor. When the first semiconductor layer 210 serves as the source (drain) of a device, it needs to be converted from a semiconductor to a conductor. Therefore, after the first semiconductor layer 210 is formed on the substrate 100, it needs to be heat-treated. For example, the first semiconductor layer 210 can be thermally annealed to convert it from a semiconductor to a conductor. Of course, the heat treatment of the first semiconductor layer 210 can also include other forms of heat treatment besides thermal annealing to achieve the purpose of converting the first semiconductor layer 210 into a conductor.
[0064] The heat treatment temperature can be from 200°C to 600°C, for example, 200°C, 300°C, 400°C, 500°C, or 600°C. The heat treatment time can be from 0.5 min to 3 min, for example, 0.5 min, 1 min, 1.5 min, 2 min, 2.5 min, or 3.5 min. In some embodiments, the first semiconductor layer 210 can be thermally annealed at 400°C for 1 min to transform the first semiconductor layer 210 into a conductor. Of course, the above embodiments are merely illustrative, and the heat treatment of the first semiconductor layer 210 in this disclosure includes, but is not limited to, the above embodiments. Modifications or combinations thereof are all covered within this disclosure.
[0065] The first film structure 200 includes a dielectric layer 220. For example... Figure 11 As shown, the dielectric layer 220 fills the gaps between the plurality of first semiconductor layers 210 and covers the top surface of the first semiconductor layers 210. The dielectric layer 220 is formed on the plurality of first semiconductor layers 210 to isolate the plurality of first semiconductor layers 210 from each other and to isolate the first semiconductor layer 210 from the second semiconductor layer 230.
[0066] The dielectric layer 220 can be an oxide layer or a low-dielectric material layer or a combination thereof, for example, it can be any one or a combination of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), or spin-coated glass (SOG).
[0067] The dielectric layer 220 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.
[0068] The first film structure 200 includes a second semiconductor layer 230. For example... Figure 12 As shown, a second semiconductor layer 230 is formed on the surface of the dielectric layer 220. The second semiconductor layer 230 may include an oxide semiconductor material, for example, a film formed of an oxide semiconductor material such as indium gallium zinc oxide (IGZO). The second semiconductor layer 230 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD) (such as magnetron sputtering deposition), or other deposition methods.
[0069] When the second semiconductor layer 230 serves as the drain (source) electrode of the device, it is necessary to convert the semiconductor into a conductor. Therefore, after forming the second semiconductor layer 230 on the dielectric layer 220, the second semiconductor layer 230 needs to be heat-treated. For example, the second semiconductor layer 230 can be thermally annealed to convert it from a semiconductor into a conductor. Of course, the heat treatment of the second semiconductor layer 230 can also include other forms of heat treatment besides thermal annealing to achieve the purpose of converting the second semiconductor layer 230 into a conductor.
[0070] The heat treatment temperature can be from 200°C to 600°C, for example, 200°C, 300°C, 400°C, 500°C, or 600°C. The heat treatment time can be from 0.5 min to 3 min, for example, 0.5 min, 1 min, 1.5 min, 2 min, 2.5 min, or 3.5 min. In some embodiments, the second semiconductor layer 230 can be thermally annealed at 400°C for 1 min to transform the second semiconductor layer 230 into a conductor. Of course, the above embodiments are merely illustrative, and the heat treatment of the second semiconductor layer 230 disclosed herein includes, but is not limited to, the above embodiments; variations or combinations thereof are all covered within this disclosure.
[0071] In this disclosure, the first semiconductor layer 210 and the second semiconductor layer 230 can be made of the same material, for example, both the first semiconductor layer 210 and the second semiconductor layer 230 can be made of indium gallium zinc oxide (IGZO). Of course, the first semiconductor layer 210 and the second semiconductor layer 230 can also be made of different oxide materials, such as indium zinc oxide (IZO), zinc tin oxide (ZTO) or other materials suitable for use as source and drain electrodes of the device.
[0072] In the embodiments provided in this disclosure, such as Figure 13 As shown, a barrier layer 300 is formed on the surface of the second semiconductor layer 230. The barrier layer 300 may include any one or more of silicon, nitrogen, boron, and carbon. For example, the barrier layer 300 may be silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOC), silicon boron nitride (SiBN), or other forms of compounds.
[0073] The barrier layer 300 can be formed on the second semiconductor layer 230 by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PEVCD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.
[0074] In the embodiments provided in this disclosure, the semiconductor structure includes a channel hole 400. For example... Figure 14 As shown, the channel via 400 passes through the barrier layer 300, the second semiconductor layer 230, and the dielectric layer 220 to expose the first semiconductor layer 210. The channel via 400 corresponds one-to-one with the first semiconductor layer 210. Forming the channel via 400 includes etching the barrier layer 300, the second semiconductor layer 230, and the dielectric layer 220 along a direction perpendicular to the substrate 100 to expose the first semiconductor layer 210.
[0075] The bottom surface of the channel hole 400 can be flush with the top surface of the first semiconductor layer 210; or the bottom surface of the channel hole 400 can be located inside the first semiconductor layer 210. That is, during etching, the first semiconductor layer 210 is partially etched in a direction perpendicular to the substrate 100 to ensure that the first semiconductor layer 210 can be fully exposed, thus ensuring sufficient contact between the second film structure 500 and the first semiconductor layer 210, thereby improving the performance of the device.
[0076] In some embodiments, the projection of the channel hole 400 on the substrate 100 may coincide with the projection of the first semiconductor layer 210 on the substrate 100, or the projection of the channel hole 400 on the substrate 100 may be located within the projection of the first semiconductor layer 210 on the substrate 100, so as to ensure the positional relationship between the channel hole 400 and the first semiconductor layer 210, and avoid semiconductor structure defects caused by the opening of the channel hole 400 being located outside the first semiconductor layer 210 due to over-etching.
[0077] In the embodiments provided in this disclosure, such as Figure 18 As shown, the semiconductor structure includes a second film structure 500. The second film structure 500 includes a channel layer 510, a gate dielectric layer 520, and a gate layer 530 sequentially disposed along a direction away from the substrate 100. The channel layer 510 and the gate dielectric layer 520 are conformally disposed within the channel hole 400 and extend to the top surface of the barrier layer 300. The gate layer 530 covers the gate dielectric layer 520 and fills the channel hole 400.
[0078] Among them, such as Figures 15-18 As shown, after forming the channel hole 400, a channel layer 510 can be formed simultaneously on the inner wall of the channel hole 400 and the top surface of the barrier layer 300, and a gate dielectric layer 520 is formed conformally on the channel layer 510, and a gate layer 530 is formed on the gate dielectric layer 520, so that the gate layer 530 fills the channel hole 400.
[0079] The channel layer 510 is made of the same material as the first semiconductor layer 210 and / or the second semiconductor layer 230. When the first semiconductor layer 210 and the second semiconductor layer 230 are made of the same material, the channel layer 510 may be made of the same material as the first semiconductor layer 210 and the second semiconductor layer 230. When the first semiconductor layer 210 and the second semiconductor layer 230 are made of different materials, the channel layer 510 may be made of the same material as the first semiconductor layer 210 or the channel layer 510 may be made of the same material as the second semiconductor layer 230.
[0080] The channel layer 510 may include an oxide semiconductor, such as tin oxide (SnO), zinc oxide (ZnO), zinc tin oxide (ZTO), gallium oxide (GaO), indium oxide (InO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). In some embodiments, when the first semiconductor layer 210 and the second semiconductor layer 230 are made of the same material, the channel layer 510 can be made of the same material as the first semiconductor layer 210 and the second semiconductor layer 230, making the first semiconductor layer 210, the channel layer 510 and the second semiconductor layer 230 an integrated material. This solves the problem of high contact resistance between heterogeneous materials, reduces contact resistance, and improves device performance. For example, when the first semiconductor layer 210 and the second semiconductor layer 230 are both indium gallium zinc oxide (IGZO), the channel layer 510 can also be indium gallium zinc oxide (IGZO), making the first semiconductor layer 210, the channel layer 510 and the second semiconductor layer 230 homogeneous materials. Since all three are indium gallium zinc oxide (IGZO) films, the cutoff current of the device is reduced, and the device's data retention capability is improved.
[0081] The channel layer 510 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.
[0082] like Figure 16 As shown, the gate dielectric layer 520 is formed conformally on the surface of the channel layer 510 away from the substrate 100. The gate dielectric layer 520 may include a silicon oxide layer, a high dielectric constant material layer, or a combination thereof. For example, the high dielectric constant material layer may include any one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO), zirconium oxide (ZrO2), thallium oxide (Ta2O5), titanium oxide (TiO2), strontium titanate (SrTiO3), or barium strontium titanate (BaSrTiO3). The gate dielectric layer 520 may be formed on the channel layer 510 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.
[0083] A gate layer 530 is formed on the surface of the gate dielectric layer 520 away from the substrate 100. The gate layer 530 includes a stacked first gate layer 531 and a second gate layer 532, the work functions of which are different. Figure 17 As shown, the first gate layer 531 is located within the channel hole 400, and the first gate layer 531 at least fills a portion of the channel hole 400. The first gate layer 531 is used to form a gate. After forming the gate dielectric layer 520, forming the first gate layer 531 includes: forming a first gate film layer on the surface of the gate dielectric layer 520; removing the first gate film layer located outside the channel hole 400 and a portion of the first gate film layer located inside the channel hole 400 to form the first gate layer 531, the top surface of the first gate layer 531 being lower than the opening of the channel hole 400.
[0084] The first gate layer 531 may include a material with a high work function, such as any one or more of titanium nitride (TiN), aluminum titanium alloy (TiAl), tantalum nitride (TaN), tungsten (W), cobalt (Co), nickel (Ni), or iridium (Ir). The first gate layer 531 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.
[0085] like Figure 18 As shown, the gate layer 530 further includes a second gate layer 532, which covers the top surface of the first gate layer 531, fills the channel via 400, and extends to the gate dielectric layer 520. Forming the second gate layer 532 after forming the first gate layer 531 includes forming a second gate film layer on the surface jointly formed by the first gate layer 531 and the gate dielectric layer 520, thereby forming the second gate layer 532.
[0086] The work function of the second gate layer 532 differs from that of the first gate layer 531. In some embodiments, the work function of the second gate layer 532 may be lower than that of the first gate layer 531. The second gate layer 532 may include a material with a low work function, such as aluminum nitride (AlN). x Lanthanum oxide (LaO) or other materials with low work functions.
[0087] It should be noted that the gate layer 530 provided in the above embodiments of this disclosure includes a first gate layer 531 and a second gate layer 532 with different work functions. Of course, in practical applications, the gate layer 530 may include multiple gate layers with different work functions. The gate formed by this structure can improve the gate-induced drain current (GIDL), reduce the contact resistance, reduce the peak current when the device is off, and improve the performance of the device.
[0088] After the second film layer structure 500 is formed, the multiple semiconductor structures are in a non-isolated state. Therefore, the second film layer structure 500 needs to be etched to isolate the multiple semiconductor structures. Figure 19 As shown, forming multiple semiconductor structures includes: using the barrier layer 300 as an etch stop layer, etching the second film layer structure 500 so that the sides of the channel layer 510, the gate dielectric layer 520 and the gate layer 530 are flush in a direction perpendicular to the substrate 100, thereby forming multiple semiconductor structures, each corresponding to a channel hole 400.
[0089] It should be noted that the fact that the sides of the channel layer 510, the gate dielectric layer 520, and the gate layer 530 are flush with each other in the direction perpendicular to the substrate 100 means that the sides formed by the channel layer 510, the gate dielectric layer 520, and the gate layer 530 are perpendicular to the substrate 100. Of course, the perpendicularity here can be perpendicular in the strict sense, that is, the sides are at 90° to the substrate 100. However, in the actual structure, due to the manufacturing process, the sides may not be perpendicular to the substrate 100. The specific angle between the two can be determined according to the actual manufacturing process, and this disclosure does not make a specific limitation.
[0090] After multiple semiconductor structures are formed, a filling layer 600 can be formed on the top surface of the multiple semiconductor structures. The top surface of the filling layer 600 can be flush with the top surface of the gate layer 530, such as... Figure 8 As shown. For example, after forming multiple semiconductor structures, a fill layer 600 is formed on the surface jointly formed by the gate layer 530 and the barrier layer 300; the fill layer 600 is etched so that the top surface of the fill layer 600 is flush with the top surface of the gate layer 530 to expose the gate layer, thus forming the final semiconductor structure. The fill layer 600 can be an oxide film layer, for example, it can be an insulating material such as silicon oxide (SiO2).
[0091] The semiconductor structure disclosed herein includes a substrate 100, a first film structure 200 and a second film structure 500 disposed on the substrate 100, and a barrier layer 300 disposed between the first film structure 200 and the second film structure 500. By disposing of the barrier layer 300, the distance between the gate and the drain can be increased, the coupling between the gate and the drain can be reduced, and the gate-induced drain current can be reduced. By disposing of the barrier layer 300, external hydrogen elements can be prevented from accumulating in the channel, reducing leakage current. The barrier layer 300 can also serve as an etch stop layer during the device formation process to prevent over-etching of the film.
[0092] This disclosure also provides a method for forming a semiconductor structure, such as... Figure 21 As shown, combined with Figures 8-20 The formation method includes steps S100 to S500.
[0093] Wherein, step S100: providing substrate 100;
[0094] Step S200: A first film structure 200 is formed on the substrate 100. The first film structure 200 includes a plurality of first semiconductor layers 210, a dielectric layer 220 and a second semiconductor layer 230 sequentially formed on the substrate 100. The plurality of first semiconductor layers 210 are spaced apart on the substrate 100. The dielectric layer 220 fills the gaps between the plurality of first semiconductor layers 210 and covers the top surface of the first semiconductor layers 210.
[0095] Step S300: Form a barrier layer 300 on the second semiconductor layer 230;
[0096] Step S400: Etch the barrier layer 300 and the first film structure 200 to form a plurality of channel holes 400. The channel holes 400 pass through the barrier layer 300, the second semiconductor layer 230 and the dielectric layer 220 to expose the first semiconductor layer 210. The channel holes 400 correspond one-to-one with the first semiconductor layer 210.
[0097] Step S500: Form a second film structure 500. The second film structure 500 includes a channel layer 510, a gate dielectric layer 520 and a gate layer 530 sequentially disposed along a direction away from the substrate 100. The channel layer 510 and the gate dielectric layer 520 are formed conformally within the channel hole 400 and extend to the top surface of the barrier layer 300. The gate layer 530 covers the gate dielectric layer 520 and fills the channel hole 400.
[0098] The semiconductor structure formation method disclosed herein involves forming a first film structure 200 and a second film structure 500 on a substrate 100, and forming a barrier layer 300 between the first film structure 200 and the second film structure 500 to increase the distance between the gate and drain in the device, reduce the coupling between the gate and drain, and reduce the gate-induced drain current. The barrier layer 300 can serve as an etch stop layer during the device formation process to prevent over-etching of the film. The barrier layer 300 can also prevent leakage caused by the accumulation of external hydrogen elements in the device, thereby improving the performance of the device.
[0099] The steps of the method for forming a semiconductor structure provided in the embodiments of this disclosure will be described in detail below:
[0100] In steps S100 to S200, such as Figures 9-11As shown, a substrate 100 is provided; a first film structure 200 is formed on the substrate 100. The first film structure 200 includes a plurality of first semiconductor layers 210, a dielectric layer 220 and a second semiconductor layer 230 sequentially formed on the substrate 100. The plurality of first semiconductor layers 210 are spaced apart on the substrate 100, and the dielectric layer 220 fills the gaps between the plurality of first semiconductor layers 210 and covers the top surface of the first semiconductor layers 210.
[0101] The material and structure of the substrate 100 have been described in the above semiconductor structure section and will not be repeated here.
[0102] The first film structure 200 includes a first semiconductor layer 210. The first semiconductor layer 210 is formed on the substrate 100, such as... Figure 22 As shown, combined with Figure 10 As shown, it includes:
[0103] Step S201: An intermediate film layer 211 is formed on the substrate 100, and the intermediate film layer 211 covers the surface of the substrate 100;
[0104] Step S202: Etch the intermediate film layer 211 to form a plurality of spacer holes 212 on the intermediate film layer 211, each spacer hole 212 exposing the surface of the substrate 100 to form a plurality of first semiconductor layers 210, with adjacent first semiconductor layers 210 separated by spacer holes 212.
[0105] Step S203: Perform heat treatment on the plurality of first semiconductor layers 210 to make the first semiconductor layers 210 conductive.
[0106] There can be multiple first semiconductor layers 210, which are spaced apart on the substrate 100. For example, to make full use of the surface of the substrate 100, multiple first semiconductor layers 210 can be uniformly arranged in an array on the substrate 100. This disclosure does not impose specific limitations on the number and arrangement of the first semiconductor layers 210, which can be selected according to the actual structural design requirements of the device.
[0107] The first semiconductor layer 210 may include an oxide semiconductor material, for example, a film formed of an oxide semiconductor material such as indium gallium zinc oxide (IGZO). The first semiconductor layer 210 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD) (such as magnetron sputtering deposition) or other deposition methods.
[0108] The oxide layer deposited on the substrate 100 is a semiconductor. When the first semiconductor layer 210 serves as the source (drain) of a device, it needs to be converted from a semiconductor to a conductor to make the first semiconductor layer 210 conductive. Therefore, after the first semiconductor layer 210 is formed on the substrate 100, it needs to be heat-treated. For example, the first semiconductor layer 210 can be thermally annealed to change it from a semiconductor to a conductor. Of course, the heat treatment of the first semiconductor layer 210 can also include other forms of heat treatment besides thermal annealing to achieve the purpose of converting the first semiconductor layer 210 into a conductor.
[0109] The temperature for heat treatment of the first semiconductor layer 210 can be between 200°C and 600°C, for example, 200°C, 300°C, 400°C, 500°C, or 600°C. The heat treatment time can be between 0.5 min and 3 min, for example, 0.5 min, 1 min, 1.5 min, 2 min, 2.5 min, or 3.5 min. In some embodiments, the first semiconductor layer 210 can be heat-annealed at 400°C for 1 min to transform it into a conductor. Of course, the above embodiments are merely illustrative, and the heat treatment of the first semiconductor layer 210 disclosed herein includes, but is not limited to, the above embodiments; variations or combinations thereof are covered within this disclosure.
[0110] The first film structure 200 includes a dielectric layer 220. The method of forming the dielectric layer 220, as well as its materials and structure, are as described in the above embodiments and will not be repeated here.
[0111] The first film structure 200 includes a second semiconductor layer 230. The second semiconductor layer 230 is formed on the surface of the dielectric layer. The second semiconductor layer 230 may include an oxide semiconductor material, for example, a film formed from an oxide semiconductor material such as indium gallium zinc oxide (IGZO). The second semiconductor layer 230 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD) (such as magnetron sputtering deposition), or other deposition methods.
[0112] When the second semiconductor layer 230 serves as the drain (source) electrode of the device, it is necessary to convert the semiconductor into a conductor. Therefore, after forming the second semiconductor layer 230 on the dielectric layer, it needs to undergo heat treatment. For example, the second semiconductor layer 230 can be thermally annealed to transform it from a semiconductor into a conductor. Of course, the heat treatment of the second semiconductor layer 230 can also include other forms of heat treatment besides thermal annealing to achieve the purpose of transforming the second semiconductor layer 230 into a conductor.
[0113] The temperature for heat treatment of the second semiconductor layer 230 can be between 200°C and 600°C, for example, 200°C, 300°C, 400°C, 500°C, or 600°C. The heat treatment time can be between 0.5 min and 3 min, for example, 0.5 min, 1 min, 1.5 min, 2 min, 2.5 min, or 3.5 min. In some embodiments, the second semiconductor layer 230 can be heat-annealed at 400°C for 1 min to transform it into a conductor. Of course, the above embodiments are merely illustrative, and the heat treatment of the second semiconductor layer 230 disclosed herein includes, but is not limited to, the above embodiments; variations or combinations thereof are covered within this disclosure.
[0114] In this disclosure, the first semiconductor layer 210 and the second semiconductor layer 230 can be made of the same material, for example, both the first semiconductor layer 210 and the second semiconductor layer 230 can be made of indium gallium zinc oxide (IGZO). Of course, the first semiconductor layer 210 and the second semiconductor layer 230 can also be made of different oxide materials, such as indium zinc oxide (IZO), zinc tin oxide (ZTO) or other materials suitable for use as source and drain electrodes of the device.
[0115] In steps S300 to S400, such as Figures 13-14 As shown, a barrier layer 300 is formed on the second semiconductor layer 230; the barrier layer 300 and the first film layer structure 200 are etched to form a plurality of channel holes 400. The channel holes 400 pass through the barrier layer 300, the second semiconductor layer 230 and the dielectric layer to expose the first semiconductor layer 210. The channel holes 400 correspond one-to-one with the first semiconductor layer 210.
[0116] A barrier layer 300 is formed on the surface of the second semiconductor layer 230. The barrier layer 300 may include any one or more of silicon, nitrogen, boron, and carbon. For example, the barrier layer 300 may be silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon boron nitride (SiBN), or other forms of compounds.
[0117] The barrier layer 300 can be formed on the second semiconductor layer 230 by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PEVCD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.
[0118] The semiconductor structure includes a channel via 400. The channel via 400 passes through the barrier layer 300, the second semiconductor layer 230, and the dielectric layer 220 to expose the first semiconductor layer 210. Each channel via 400 corresponds to one of the first semiconductor layers 210. Forming the channel via 400 includes etching the barrier layer 300, the second semiconductor layer 230, and the dielectric layer 220 along a direction perpendicular to the substrate 100 to expose the first semiconductor layer 210. The formation process and structure of the channel via 400 are as described in the above embodiments and will not be repeated here.
[0119] In step S500, such as Figures 15-18 As shown, a second film structure 500 is formed. The second film structure 500 includes a channel layer 510, a gate dielectric layer 520 and a gate layer 530 sequentially disposed along a direction away from the substrate 100. The channel layer 510 and the gate dielectric layer 520 are formed conformally within the channel hole 400 and extend to the top surface of the barrier layer 300. The gate layer 530 covers the gate dielectric layer 520 and fills the channel hole 400.
[0120] The channel layer 510 is made of the same material as the first semiconductor layer 210 and / or the second semiconductor layer 230. When the first semiconductor layer 210 and the second semiconductor layer 230 are made of the same material, the channel layer 510 may be made of the same material as the first semiconductor layer 210 and the second semiconductor layer 230. When the first semiconductor layer 210 and the second semiconductor layer 230 are made of different materials, the channel layer 510 may be made of the same material as the first semiconductor layer 210 or the channel layer 510 may be made of the same material as the second semiconductor layer 230.
[0121] The channel layer 510 may include an oxide semiconductor, such as tin oxide (SnO), zinc oxide (ZnO), zinc tin oxide (ZTO), gallium oxide (GaO), indium oxide (InO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). In some embodiments, when the first semiconductor layer 210 and the second semiconductor layer 230 are made of the same material, the channel layer 510 can be made of the same material as the first semiconductor layer 210 and the second semiconductor layer 230, making the first semiconductor layer 210, the channel layer 510 and the second semiconductor layer 230 an integrated material. This solves the problem of high contact resistance between heterogeneous materials, reduces contact resistance, and improves device performance. For example, when the first semiconductor layer 210 and the second semiconductor layer 230 are both indium gallium zinc oxide (IGZO), the channel layer 510 can also be indium gallium zinc oxide (IGZO), making the first semiconductor layer 210, the channel layer 510 and the second semiconductor layer 230 homogeneous materials. Since all three are indium gallium zinc oxide (IGZO) films, the cutoff current of the device is reduced, and the device's data retention capability is improved.
[0122] The channel layer 510 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.
[0123] The formation method, structure, and materials of the gate dielectric layer 520 are as described in the above embodiments, and will not be repeated here.
[0124] A gate layer 530 is formed on the surface of the gate dielectric layer 520 away from the substrate 100. The gate layer 530 includes a stacked first gate layer 531 and a second gate layer 532, the first gate layer 531 and the second gate layer 532 having different work functions. Figure 17 As shown, the first gate layer 531 is located within the channel hole 400, and the first gate layer 531 at least fills a portion of the channel hole 400. The first gate layer 531 is used to form a gate. After forming the gate dielectric layer 520, forming the first gate layer 531 includes: forming a first gate film layer on the surface of the gate dielectric layer 520; removing the first gate film layer located outside the channel hole 400 and a portion of the first gate film layer located inside the channel hole 400 to form the first gate layer 531, the top surface of the first gate layer 531 being lower than the opening of the channel hole 400.
[0125] The first gate layer 531 may include a material with a high work function, such as any one or more of titanium nitride (TiN), aluminum titanium alloy (TiAl), tantalum nitride (TaN), tungsten (W), cobalt (Co), nickel (Ni), or iridium (Ir). The first gate layer 531 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition methods.
[0126] like Figure 18 As shown, the gate layer 530 further includes a second gate layer 532, which covers the top surface of the first gate layer 531, fills the channel via 400, and extends to the gate dielectric layer 520. Forming the second gate layer 532 after forming the first gate layer 531 includes forming a second gate film layer on the surface jointly formed by the first gate layer 531 and the gate dielectric layer 520, thereby forming the second gate layer 532.
[0127] The work function of the second gate layer 532 differs from that of the first gate layer 531. In some embodiments, the work function of the second gate layer 532 may be lower than that of the first gate layer 531. The second gate layer 532 may include a material with a low work function, such as aluminum nitride (AlN). x Lanthanum oxide (LaO) or other materials with low work functions.
[0128] It should be noted that the gate layer 530 provided in the above embodiments of this disclosure includes a first gate layer 531 and a second gate layer 532 with different work functions. Of course, in practical applications, the gate layer 530 may include multiple gate layers with different work functions. The gate formed by this structure can improve the gate-induced drain current (GIDL), reduce the contact resistance, reduce the peak current when the device is off, and improve the performance of the device.
[0129] like Figure 19 As shown, after forming the second film structure 500, the method further includes: using the barrier layer 300 as an etch stop layer to etch the second film structure 500 so that the sides of the channel layer 510, the gate dielectric layer 520 and the gate layer 530 are flush in a direction perpendicular to the substrate 100, so as to form a plurality of semiconductor structures, each corresponding to a channel hole 400.
[0130] It should be noted that the fact that the sides of the channel layer 510, the gate dielectric layer 520, and the gate layer 530 are flush with each other in the direction perpendicular to the substrate 100 means that the sides formed by the channel layer 510, the gate dielectric layer 520, and the gate layer 530 are perpendicular to the substrate 100. Of course, the perpendicularity here can be perpendicular in the strict sense, that is, the sides are at 90° to the substrate 100. However, in the actual structure, due to the manufacturing process, the sides may not be perpendicular to the substrate 100. The specific angle between the two can be determined according to the actual manufacturing process, and this disclosure does not make a specific limitation.
[0131] The semiconductor structure formation method disclosed herein involves forming a first film structure 200 and a second film structure 500 on a substrate 100, and forming a barrier layer 300 between the first film structure 200 and the second film structure 500 to increase the distance between the gate and drain in the device, reduce the coupling between the gate and drain, and reduce the gate-induced drain current. The barrier layer 300 can serve as an etch stop layer during the device formation process to prevent over-etching of the film. The barrier layer 300 can also prevent leakage caused by the accumulation of external hydrogen elements in the device, thereby improving the performance of the device.
[0132] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0133] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; A first film structure is formed on the substrate. The first film structure includes a plurality of first semiconductor layers, a dielectric layer, and a second semiconductor layer. The plurality of first semiconductor layers are spaced apart on the substrate. The dielectric layer fills the gaps between the plurality of first semiconductor layers and covers the top surface of the first semiconductor layers. A barrier layer, wherein the barrier layer is located on the top surface of the first film structure; A via, which passes through the barrier layer, the second semiconductor layer and the dielectric layer to expose the first semiconductor layer, and the via corresponds one-to-one with the first semiconductor layer; The second film layer structure includes a channel layer, a gate dielectric layer and a gate layer sequentially disposed along a direction away from the substrate. The channel layer and the gate dielectric layer are disposed within the channel hole and extend to the top surface of the barrier layer. The gate layer covers the gate dielectric layer and fills the channel hole.
2. The semiconductor structure according to claim 1, characterized in that, The first semiconductor layer and the second semiconductor layer are indium gallium zinc oxide film layers.
3. The semiconductor structure according to claim 1, characterized in that, The channel layer is made of the same material as the first semiconductor layer and / or the second semiconductor layer.
4. The semiconductor structure according to claim 1, characterized in that, The gate layer includes a first gate layer and a second gate layer stacked together, and the first gate layer and the second gate layer have different work functions.
5. The semiconductor structure according to claim 1, characterized in that, The barrier layer comprises one or more of the elements silicon, nitrogen, boron, and carbon.
6. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first film structure is formed on the substrate. The first film structure includes a plurality of first semiconductor layers, a dielectric layer, and a second semiconductor layer sequentially formed on the substrate. The plurality of first semiconductor layers are spaced apart on the substrate. The dielectric layer fills the gaps between the plurality of first semiconductor layers and covers the top surface of the first semiconductor layers. A barrier layer is formed on the second semiconductor layer; The barrier layer and the first film layer structure are etched to form a plurality of channel holes, which pass through the barrier layer, the second semiconductor layer and the dielectric layer to expose the first semiconductor layer, and the channel holes correspond one-to-one with the first semiconductor layer; A second film structure is formed, the second film structure including a channel layer, a gate dielectric layer and a gate layer disposed sequentially along the direction away from the substrate, the channel layer and the gate dielectric layer being formed conformally in the channel hole and extending to the top surface of the barrier layer, the gate layer covering the gate dielectric layer and filling the channel hole.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, After forming the second film structure, the method further includes: Using the barrier layer as an etch stop layer, the second film structure is etched so that the side surfaces of the channel layer, the gate dielectric layer, and the gate layer are flush with each other in a direction perpendicular to the substrate, thereby forming a plurality of semiconductor structures, each of which corresponds one-to-one with the channel via.
8. The method for forming a semiconductor structure according to claim 6, characterized in that, The method further includes: After the first semiconductor layer is formed, the first semiconductor layer is subjected to heat treatment; After the second semiconductor layer is formed, the second semiconductor layer is subjected to heat treatment.
9. The method for forming a semiconductor structure according to claim 6, characterized in that, The first semiconductor layer and the second semiconductor layer are indium gallium zinc oxide film layers.
10. The method for forming a semiconductor structure according to claim 6, characterized in that, The channel layer is made of the same material as the first semiconductor layer and / or the second semiconductor layer.