Image sensor, working method thereof, and electronic device

Abstract

The present application provides an image sensor, a working method thereof, and an electronic device. A bit line module is provided, and in a first state, a low-gain reset signal is sampled into a first equivalent capacitor; in a second state, a high-gain reset signal and a high-gain image signal are sampled and outputted in sequence through a second gain output bit line; when the second state returns to the first state, the low-gain reset signal sampled in the first equivalent capacitor is outputted through the first gain output bit line, and then the low-gain image signal is sampled and outputted through the first gain output bit line; at the same time, a gain output selection circuit is connected to a matching readout circuit to achieve effective image quantization; while achieving a high dynamic range of the image sensor, the cost and size of the image sensor are reduced; because there is no need to sample and hold the output of the pixel circuit to reduce the KT / C noise of the circuit, the circuit noise level is lower, further improving the performance of the image sensor.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to an image sensor, a working method thereof, and an electronic device. Background Art

[0002] Dynamic range is a key factor in image sensor imaging quality. A high dynamic range allows for the output of scene image information across a wider range of light intensities, resulting in richer image detail. Typically, an image sensor outputs a dynamic range of approximately 60-70dB. In typical natural environment applications, the required dynamic range to capture both highlights and shadows is approximately 100dB. In image sensor design, there are several ways to improve dynamic range. For example, further increasing the full-well charge capacity of the pixel circuit can achieve a larger dynamic range, or by synthesizing multiple frames of image data.

[0003] The dual conversion gain (DCG) mode is primarily used in image sensors. It increases conversion gain by using a smaller integrating capacitor under low illumination conditions to improve sensitivity. It also increases dynamic range by using a larger integrating capacitor under high illumination conditions to increase stored charge. Because the dual conversion gain mode uses a multi-frame synthesis approach to achieve high dynamic range, the multi-frame readout process has time lags, resulting in smearing in the resulting composite image and high circuit readout noise. Improving the dynamic range of image sensors, reducing pixel circuit noise, and simultaneously reducing the quantization circuit area are key challenges in current designs. Summary of the Invention

[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide an image sensor, a working method thereof, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides an image sensor, comprising:

[0006] The pixel circuit has two states. In the first state, it outputs a low-gain reset signal or a low-gain image signal. In the second state, it outputs a high-gain reset signal or a high-gain image signal. The pixel circuit is configured to sequentially output a low-gain reset signal, a high-gain reset signal, a high-gain image signal, and a low-gain image signal. A bit line module is connected to the pixel circuit. The bit line module includes a first gain output bit line and a second gain output bit line. The first gain output bit line includes a first equivalent capacitor, and the second gain output bit line includes a second equivalent capacitor. The bit line module is configured to sample the low-gain reset signal to the first equivalent capacitor in the first state of the pixel circuit, and sample the high-gain reset signal to the first equivalent capacitor in the second state of the pixel circuit. and the high-gain image signal are sampled and outputted in sequence through the second gain output bit line; when the pixel circuit is restored from the second state to the first state, the low-gain reset signal sampled in the first equivalent capacitor is outputted through the first gain output bit line, and then the low-gain image signal is sampled and outputted through the first gain output bit line; a readout circuit is connected to the bit line module, and the readout circuit has two states: in the first state, the high-gain reset signal and the high-gain image signal are received in sequence and quantized respectively to obtain an effective image signal quantization value under high gain; in the second state, the low-gain reset signal and the low-gain image signal are received in sequence and quantized respectively to obtain an effective image signal quantization value under low gain.

[0007] In one possible implementation, the pixel circuit includes a photosensitive element, a reset transistor, a transfer transistor, a source follower transistor, a dual conversion gain transistor, and a row selection module, wherein the row selection module includes a low-gain row selection switch and a high-gain row selection switch, and the low-gain row selection switch and the high-gain row selection switch are connected in parallel; a first end of the low-gain row selection switch is connected to the output end of the source follower transistor, and a second end of the low-gain row selection switch is connected to the first equivalent capacitor; the low-gain row selection switch is used to sample the low-gain reset signal to the first equivalent capacitor in the first state of the pixel circuit and to sample the low-gain reset signal from the pixel circuit to the first equivalent capacitor. When the second state of the pixel circuit is restored to the first state, the high-gain reset signal and the high-gain image signal are output through the first gain output bit line, and after the pixel circuit is restored to the first state from the second state, the low-gain image signal is transmitted from the pixel circuit to the first equivalent capacitor and output through the first gain output bit line; the first end of the high-gain row selection switch is connected to the output end of the source follower transistor, and the second end of the high-gain row selection switch is connected to the second equivalent capacitor; the high-gain row selection switch is used to transmit the high-gain reset signal and the high-gain image signal in sequence to the second equivalent capacitor and output them through the second gain output bit line in the second state of the pixel circuit.

[0008] In one possible implementation, the bit line module further includes a source follower current source, a low gain bit line selection switch, and a high gain bit line selection switch; the first end of the low gain bit line selection switch is connected to the source follower current source, the second end of the low gain bit line selection switch is connected to the first gain output bit line, and the low gain bit line selection switch is used to select the source follower current source to provide an operating current for the first gain output bit line; the first end of the high gain bit line selection switch is connected to the source follower current source, the second end of the high gain bit line selection switch is connected to the second gain output bit line, and the high gain bit line selection switch is used to select the source follower current source to provide an operating current for the second gain output bit line.

[0009] In one possible implementation, the readout circuit includes a gain quantization selection circuit, a comparison circuit, a counter, and a memory connected in sequence. The gain quantization selection circuit is configured to, in a first state of the readout circuit, sequentially connect the high-gain reset signal and the high-gain image signal to the comparison circuit; and the gain quantization selection circuit is further configured to, in a second state of the readout circuit, sequentially connect the low-gain reset signal and the low-gain image signal to the comparison circuit.

[0010] In one possible implementation, when the readout circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the high-gain reset signal and output a first comparison signal; the counter is configured to count when receiving the first comparison signal, and record a first counting result when the ramp voltage and the high-gain reset signal overlap; when the readout circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage and the high-gain image signal and output a second comparison signal; the counter is configured to count in the opposite direction starting from the first counting result when receiving the second comparison signal, and output a second counting result when the ramp voltage and the high-gain image signal overlap, the second counting result being the difference between the quantization result of the high-gain image signal and the quantization result of the high-gain reset signal; the memory is configured to store the second counting result and use the second counting result as the effective value under the high gain. image quantization value; when the readout circuit quantizes the low-gain reset signal, the comparison circuit is configured to compare the ramp voltage and the low-gain reset signal and output a third comparison signal; the counter is configured to count when receiving the third comparison signal, and record a third counting result when the ramp voltage and the low-gain reset signal overlap; when the readout circuit quantizes the low-gain image signal, the comparison circuit is configured to compare the ramp voltage and the low-gain image signal and output a fourth comparison signal; the counter is configured to count in a reverse direction starting from the third counting result when receiving the fourth comparison signal, and output a fourth counting result when the ramp voltage and the low-gain image signal overlap, the fourth counting result being the difference between the quantization result of the low-gain image signal and the quantization result of the low-gain reset signal; the memory is configured to store the fourth counting result and use the fourth counting result as the effective image quantization value at the low gain.

[0011] In one possible implementation, the comparison circuit includes a comparator, a first capacitor, a second capacitor, a first clear switch, and a second clear switch; the non-inverting input of the comparator is connected to the ramp voltage through the first capacitor, and the inverting input of the comparator is connected to the gain quantization selection circuit through the second capacitor; the non-inverting input of the comparator is connected to the first end of the first clear switch, and the inverting input of the comparator is connected to the first end of the second clear switch; the non-inverting output of the comparator is connected to the second end of the first clear switch, and the first inverting output of the comparator is connected to the second end of the second clear switch.

[0012] In a possible implementation, the first capacitor is a variable capacitor.

[0013] In a possible implementation, the slope of the ramp voltage is adjustable.

[0014] In one possible implementation, the gain quantization selection circuit includes a high-gain quantization switch and a low-gain quantization switch; a first end of the high-gain quantization switch is connected to the second gain output bit line to serve as a high-gain reset signal input end and a high-gain image signal input end of the gain quantization selection circuit; a first end of the low-gain quantization switch is connected to the first gain output bit line to serve as a low-gain reset signal input end and a low-gain image signal input end of the gain quantization selection circuit; a second end of the high-gain quantization switch and a second end of the low-gain quantization switch are connected in parallel to a first end of the second capacitor, and a second end of the second capacitor is connected to an inverting input end of the comparator.

[0015] In a second aspect, embodiments of the present application further provide an image sensor operating method, which is applied to the aforementioned image sensor and includes the following steps:

[0016] The low-gain row selection switch and the low-gain bit line selection switch are turned on to sample the low-gain reset signal output by the pixel circuit to the first equivalent capacitor; the high-gain row selection switch and the high-gain bit line selection switch are turned on to transmit the high-gain reset signal output by the pixel circuit to the second equivalent capacitor and output it through the second gain output bit line; the ramp voltage is connected to the non-inverting input terminal of the comparator, the high-gain quantization switch is turned on to couple the high-gain reset signal to the inverting input terminal of the comparator through the second capacitor, and the readout circuit quantizes the high-gain reset signal to obtain the quantized value of the high-gain reset signal; the high-gain row selection switch and the high-gain bit line selection switch are turned on to transmit the high-gain image signal output by the pixel circuit to the second gain output bit line and output it; the ramp voltage is connected to the non-inverting input terminal of the comparator, the high-gain quantization switch is turned on to couple the high-gain image signal to the inverting input terminal of the comparator through the second capacitor, and the readout circuit quantizes the high-gain reset signal to obtain the quantized value of the high-gain reset signal The image signal is quantized to obtain a difference between a quantized value of the high-gain reset signal and a quantized value of the high-gain image signal, that is, to obtain a high-gain effective image quantized value; the ramp voltage is connected to the non-inverting input terminal of the comparator, the low-gain quantization switch signal is input, the low-gain quantization switch is turned on, the low-gain reset signal is coupled to the inverting input terminal of the comparator via the second capacitor, and the readout circuit quantizes the low-gain reset signal to obtain a low-gain reset signal quantized value; the low-gain row selection switch and the low-gain bit line selection switch are turned on, the low-gain image signal is transmitted to the first equivalent capacitor and outputted via the first gain output bit line; the ramp voltage is connected to the non-inverting input terminal of the comparator, the low-gain quantization switch is turned on, the low-gain image signal is coupled to the inverting input terminal of the comparator via the second capacitor, and the readout circuit quantizes the low-gain image signal to obtain a difference between a quantized value of the low-gain reset signal and a quantized value of the low-gain image signal, that is, to obtain a low-gain effective image quantized value.

[0017] In a possible implementation, the reset transistor is turned on before the low-gain row selection switch and the low-gain bit line selection switch are turned on.

[0018] In one possible implementation, before the low-gain reset signal or the low-gain image signal is connected to the first gain output bit line, the dual-conversion gain transistor is turned on; before the high-gain reset signal and the high-gain image signal are connected to the second gain output bit line, the dual-conversion gain transistor is turned off.

[0019] In a possible implementation, the step of quantizing the high-gain reset signal, the high-gain image signal, the low-gain image signal, and the low-gain reset signal by the readout circuit includes:

[0020] When the ramp voltage decreases, the comparison circuit compares the ramp voltage with the high-gain reset signal and outputs the first comparison signal; when the counter receives the first comparison signal, it counts, and when the ramp voltage and the high-gain reset signal overlap, it records the first counting result and resets the ramp voltage; when the ramp voltage decreases, the comparison circuit compares the ramp voltage with the high-gain image signal and outputs the second comparison signal; when the counter receives the second comparison signal, it counts in the opposite direction from the first counting result, and when the ramp voltage and the high-gain image signal overlap, it records the second counting result and resets the ramp voltage, the second counting result being the difference between the quantization result of the high-gain reset signal and the quantization result of the high-gain image signal; the memory is configured to store the second counting result and store the second counting result as is the high-gain effective image quantization value; when the ramp voltage decreases, the comparison circuit compares the ramp voltage with the low-gain reset signal and outputs the third comparison signal; when the counter receives the third comparison signal, it counts, and when the ramp voltage and the low-gain reset signal overlap, it records the third counting result and resets the ramp voltage; when the ramp voltage decreases, the comparison circuit compares the ramp voltage with the low-gain image signal and outputs the fourth comparison signal; when the counter receives the fourth comparison signal, it counts in the opposite direction from the third counting result, and when the ramp voltage and the high-gain image signal overlap, it records the fourth counting result and resets the ramp voltage; the memory is configured to store the fourth counting result, which is the difference between the quantization result of the high-gain reset signal and the quantization result of the high-gain image signal.

[0021] In a possible implementation, before the readout circuit quantizes the high-gain reset signal and before the readout circuit quantizes the low-gain image signal, the first clear switch and the second clear switch are simultaneously turned on to clear and reset the comparator.

[0022] In a third aspect, an embodiment of the present application further provides an electronic device comprising the above-mentioned image sensor.

[0023] An image sensor, operating method thereof, and electronic device provided by embodiments of the present application include a bitline module. In a first state, a low-gain reset signal is sampled into a first equivalent capacitor. In a second state, a high-gain reset signal and a high-gain image signal are sequentially sampled and outputted via a second gain output bitline. When the second state returns to the first state, the low-gain reset signal sampled in the first equivalent capacitor is outputted via the first gain output bitline, followed by the low-gain image signal sampled and outputted via the first gain output bitline. Simultaneously, a gain output selection circuit is connected to a matching readout circuit to achieve effective image quantization. While achieving a high dynamic range for the image sensor, the cost and size of the image sensor are reduced. Because the pixel circuit output does not need to be sampled and held to reduce the circuit's KT / C noise, the circuit noise level is lower, further improving image sensor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of the structure of the image sensor provided in this application;

[0026] Figure 2 A circuit diagram of the image sensor provided in this application;

[0027] Figure 3 This is a circuit timing diagram of the image sensor provided in this application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0029] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0030] As mentioned in the background technology section, in the existing technology, the dual conversion gain mode requires increasing the gain with a smaller integral capacitor under low illumination conditions to improve sensitivity; and increasing the stored charge with a larger integral capacitor under high illumination conditions to reduce the gain to improve the dynamic range. In a pixel circuit including a dual conversion gain mode, a high-gain reset signal, a high-gain image signal, a low-gain reset signal, and a low-gain image signal are typically sequentially output to the readout circuit during signal readout. Therefore, in the prior art, when the readout circuit performs signal readout, two or more analog-to-digital conversion circuits are typically designed to quantize the reset signal and image signal at low gain, and the reset signal and image signal at high gain, respectively, to ensure the dynamic range of the image sensor. However, the use of two or more analog-to-digital conversion circuits requires the use of a high dynamic range synthesized by multiple frames, resulting in a time difference in the reading process, a tailing phenomenon in the final synthesized image, and high circuit read noise. Furthermore, since two or more analog-to-digital conversion circuits actually occupy a large circuit area, as pixel functions become increasingly rich, the size of the photosensitive element is typically increased when designing an image sensor. Furthermore, the use of large-scale analog-to-digital conversion circuits on this basis results in an excessively large quantization circuit area.

[0031] Based on the above technical problems, the present application provides an image sensor, which at least includes a pixel circuit 11, a bit line module 12 and a readout circuit 13. Figure 1 and Figure 2 , specifically:

[0032] The pixel circuit 11 has two states. In the first state, it outputs a low-gain reset signal lcg_rst or a low-gain image signal lcg_sig. In the second state, it outputs a high-gain reset signal hcg_rst or a high-gain image signal hcg_sig. The pixel circuit 11 is configured to sequentially output the low-gain reset signal lcg_rst, the high-gain reset signal hcg_rst, the high-gain image signal hcg_sig, and the low-gain image signal lcg_sig.

[0033] The bitline module 12 is connected to the pixel circuit 11 and includes a first gain output bitline Pixout_1 and a second gain output bitline Pixout_h. The first gain output bitline Pixout_1 includes a first equivalent capacitor Cb11, and the second gain output bitline Pixout_h includes a second equivalent capacitor Cblh. The bitline module 12 is configured to sample the low-gain reset signal lcg_rst into the first equivalent capacitor Cb11 when the pixel circuit 11 is in a first state. The bitline module 12 is configured to sample and output the high-gain reset signal hcg_rst and the high-gain image signal hcg_sig sequentially through the second gain output bitline Pixout_h when the pixel circuit 11 is in a second state. The bitline module 12 is also configured to output the low-gain reset signal lcg_rst sampled in the first equivalent capacitor Cb11 through the first gain output bitline Pixout_1, and then sample and output the low-gain image signal lcg_sig through the first gain output bitline Pixout_1 when the pixel circuit 11 returns to the first state from the second state.

[0034] It is understandable that the first equivalent capacitor Cbll may be inherent in the first gain output bit line Pixout_1 or parasitic, or may be added in the form of device capacitance. A first end of the first equivalent capacitor Cbll is connected to the first gain output bit line Pixout_1, and a second end of the first equivalent capacitor Cbll is connected to the ground signal. On the one hand, the first equivalent capacitor Cbll is used to sample the low-gain reset signal lcg_rst transmitted by the pixel circuit 11. When the readout circuit 13 is in an operating state, the first equivalent capacitor Cbll directly outputs the low-gain reset signal lcg_rst to the first gain output bit line Pixout_1 without being further turned on through the pixel circuit 11. On the other hand, the pixel circuit 11 outputs a low-gain image signal lcg_sig. The aforementioned low-gain image signal lcg_sig is transmitted to the first equivalent capacitor Cbll, causing its potential to change. At this time, the potentials of the first end and the second end of the first equivalent capacitor Cbll are different, so charging and discharging are performed, thereby causing the low gain to be reset. The image signal lcg_sig is output through the first gain output bit line Pixout_1. It is also understandable that the second equivalent capacitor Cblh may be inherent to the second gain output bit line Pixout_1 or parasitic, or may be added in the form of device capacitance. A first end of the second equivalent capacitor Cblh is connected to the second gain output bit line Pixout_h, and a second end of the second equivalent capacitor Cblh is connected to the ground signal. The pixel circuit 11 outputs a high-gain reset signal hcg_rst and a high-gain image signal hcg_sig. The high-gain reset signal hcg_rst and the high-gain image signal hcg_sig are transmitted to the second equivalent capacitor Cblh, causing its potential to change. At this time, the potentials of the first end and the second end of the second equivalent capacitor Cblh are different, so a discharge operation is performed, thereby causing the high-gain reset signal hcg_rst and the high-gain image signal hcg_sig to be output through the second gain output bit line Pixout_h.

[0035] The readout circuit 13 is connected to the bit line module 12. The readout circuit 13 has two states. In the first state, the high-gain reset signal hcg_rst and the high-gain image signal hcg_sig are received in sequence and quantized respectively to obtain the effective image signal quantization value under high gain; in the second state, the low-gain reset signal lcg_rst and the low-gain image signal lcg_sig are received in sequence and quantized respectively to obtain the effective image signal quantization value under low gain.

[0036] In the image sensor provided in the present application, the pixel circuit 11 includes a photosensitive element PD, a reset transistor RST, a transfer transistor TX, a source follower transistor SF, a dual conversion gain transistor DCG and a row selection module, the row selection module includes a low gain row selection switch LRS and a high gain row selection switch HRS, and the low gain row selection switch LRS and the high gain row selection switch HRS are connected in parallel.

[0037] Optionally, in some embodiments, the pixel circuit 11 further includes a dual conversion gain capacitor Cdcg.

[0038] Furthermore, the drain of the reset transistor RST and the drain of the source-follower transistor SF are commonly connected to the first power supply PIXVDD, the source of the reset transistor RST is connected to the first end of the dual conversion gain capacitor Cdcg and the drain of the dual conversion gain transistor DCG, the source of the dual conversion gain transistor DCG, the gate of the source-follower transistor SF, and the source of the transfer transistor TX are commonly connected to the floating diffusion point FD, the drain of the transfer transistor TX is connected to the negative electrode of the photosensitive element PD, the source-follower transistor SF amplifies and outputs the low-gain reset signal lcg_rst, the high-gain image signal hcg_sig, the high-gain reset signal hcg_rst, and the low-gain image signal lcg_sig in sequence through its source, the gate of the reset transistor RST is connected to the reset signal rst, the gate of the dual conversion gain transistor DCG is connected to the conversion gain control signal dcg, the gate of the transfer transistor TX is connected to the control signal tx, the second end of the dual conversion gain capacitor Cdcg is connected to the power supply VC, and the positive electrode of the photosensitive element PD is connected to the power ground.

[0039] A first end of the low-gain row select switch LRS is connected to the source follower transistor SF, and a second end of the low-gain row select switch LRS is connected to the first equivalent capacitor Cbll. The low-gain row select switch LRS is controlled by the low-gain row select signal lcg_rowsel. The low-gain row select switch LRS is turned on under the control of the low-gain row select signal lcg_rowsel, and is used to sample the low-gain reset signal lcg_rst to the first equivalent capacitor Cbll in the first state and restore it to the first state in the second state and output it through the first gain output bit line Pixout_1, and transmit the low-gain image signal lcg_sig from the pixel circuit 11 after the second state is restored to the first state. to the first equivalent capacitor Cbll and output through the first gain output bit line Pixout_l; a first end of the high gain row select switch HRS is connected to the source follower transistor SF, and a second end of the high gain row select switch HRS is connected to the second equivalent capacitor Cblh; the high gain row select switch HRS is controlled by the high gain row select signal hcg_rowsel, and the high gain row select switch HRS is turned on under the control of the high gain row select signal hcg_rowsel, and is used to transmit the high gain reset signal hcg_rst and the high gain image signal hcg_sig in sequence to the second equivalent capacitor Cblh and output through the second gain output bit line Pixout_h in the second state.

[0040] The bit line module 12 further includes a source follower current source CC, a low gain bit line selection switch LBS, and a high gain bit line selection switch HBS; a first end of the low gain bit line selection switch LBS is connected to the source follower current source CC, and a second end of the low gain bit line selection switch LBS is connected to the first gain output bit line Pixout_1, in other words, the second end of the low gain row selection switch LRS is connected in series with the first end of the first equivalent capacitor Cbll, the low gain bit line selection switch LBS is controlled by the low gain bit line selection signal lcg_bl_sel, and the low gain bit line selection switch LBS is used to A first-gain output bit line Pixout_1 provides operating current. A first end of a high-gain bit line select switch HBS is connected to a source-follower current source CC, and a second end of the high-gain bit line select switch HBS is connected to a second-gain output bit line Pixout_h. In other words, the second end of the high-gain row select switch HRS and the first end of the second equivalent capacitor Cblh are connected in series. The high-gain bit line select switch HBS is controlled by a high-gain bit line select signal hcg_bl_sel and is used to provide operating current for the second-gain output bit line Pixout_h.

[0041] Specifically, if Figure 2As shown, the function of the source follower current source module is to provide operating current for the first gain output bit line Pixout_l and the second gain output bit line Pixout_h; in the embodiment of the present application, by sequentially turning on and off the low gain bit line selection signal lcg_bl_sel and the low gain row selection signal lcg_rowsel, the high gain bit line selection signal hcg_bl_sel and the high gain row selection signal hcg_rowsel, the low gain reset signal lcg_rst can be sampled to the first equivalent capacitor Cbll, and the low gain image signal lcg_sig can be driven to The first gain output bit line Pixout_l transmits the high gain image signal hcg_sig and the high gain reset signal hcg_rst to the second gain output bit line Pixout_h. Then, when the readout circuit 13 is turned on, the low gain reset signal lcg_rst and the low gain image signal lcg_sig are transmitted by the first gain output bit line Pixout_l, and the high gain reset signal hcg_rst and the high gain image signal hcg_sig are transmitted by the second gain output bit line Pixout_h, and enter the readout circuit 13 for signal comparison and quantization.

[0042] The readout circuit 13 includes a gain quantization selection circuit 131, a comparison circuit 132, a counter 133, and a memory 134, which are connected in sequence. The gain quantization selection circuit 131 is configured to sequentially connect the high-gain reset signal hcg_rst and the high-gain image signal hcg_sig to the comparison circuit 132 in a first state. The gain quantization selection circuit 131 is also configured to sequentially connect the low-gain reset signal lcg_rst and the low-gain image signal lcg_sig to the comparison circuit 132 in a second state.

[0043] In the first state and the second state of the readout circuit, the comparison circuit 132 uses the ramp voltage vramp as a reference value and compares it with the voltage values ​​of the high-gain reset signal hcg_rst and the high-gain image signal hcg_sig, and the low-gain reset signal lcg_rst and the low-gain image signal lcg_sig, respectively, obtains corresponding comparison results, stores them in the memory 134 as counting results, obtains and outputs the low-gain effective image quantization value and the high-gain effective image quantization value, specifically:

[0044] When the readout circuit 13 quantizes the high-gain reset signal hcg_rst, the comparison circuit 132 is configured to compare the ramp voltage vramp with the high-gain reset signal hcg_rst and output a first comparison signal; the counter 133 is configured to count when receiving the first comparison signal, specifically, the counting direction is downward, and when the ramp voltage vramp and the high-gain reset signal hcg_rst overlap, the first counting result is recorded; when the readout circuit 13 quantizes the high-gain image signal hcg_sig, the comparison circuit 132 is configured to compare the ramp voltage vramp with the high-gain reset signal hcg_rst. The counter 133 is configured to, when receiving the second comparison signal, start counting in the opposite direction from the first counting result, specifically, the counting direction is upward, and when the ramp voltage vramp and the high gain image signal hcg_sig overlap, output a second counting result, which is the difference between the quantization results of the high gain image signal hcg_sig and the high gain reset signal hcg_rst; the memory 134 is configured to store the second counting result and use the second counting result as the effective image quantization value under high gain When the readout circuit 13 quantizes the low gain reset signal lcg_rst, the comparison circuit 132 is configured to compare the ramp voltage vramp with the low gain reset signal lcg_rst and output a third comparison signal; the counter 133 is configured to count when receiving the third comparison signal, specifically, the counting direction is downward, and when the ramp voltage vramp and the low gain reset signal lcg_rst overlap, the third counting result is recorded; when the readout circuit 13 quantizes the low gain reset signal lcg_rst, the comparison circuit 132 is configured to compare the ramp voltage vramp and the low gain reset signal lcg_rst The counter 133 is configured to, when receiving the fourth comparison signal, start counting in the opposite direction from the third counting result, specifically, the counting direction is upward, and when the ramp voltage vramp and the low-gain image signal lcg_sig overlap, output a fourth counting result, which is the difference between the quantization result of the low-gain image signal lcg_sig and the low-gain reset signal lcg_rst; the memory 134 is configured to store the fourth counting result and use the fourth counting result as the effective image quantization value under low gain.

[0045] The readout circuit 13 includes a comparator, a first capacitor C1, a second capacitor C2, a first clearing switch CAZ1 and a second clearing switch CAZ2;

[0046] The non-inverting input terminal of the comparator is connected to the ramp voltage vramp through the first capacitor C1, and the inverting input terminal of the comparator is connected to the gain quantization selection circuit 131 through the second capacitor C2; the non-inverting input terminal of the comparator is connected to the first end of the first clear switch CAZ1, the inverting input terminal of the comparator is connected to the first end of the second clear switch CAZ2, the first non-inverting output terminal of the comparator is connected to the second end of the first clear switch CAZ1, and the first inverting output terminal of the comparator is connected to the second end of the second clear switch CAZ2.

[0047] In some embodiments, the comparator includes a first input terminal Vinp connected to the non-inverting input terminal of the comparator, a second input terminal Vinn connected to the inverting input terminal of the comparator, and also includes a first gain output bit line Vop1 and a second gain output bit line Von1 respectively connected to the first clear switch CAZ1 and the second clear switch CAZ2. In addition, in the comparison circuit 132, the comparator is connected to the counter 133 through the third output terminal Vout.

[0048] Optionally, the first capacitor C1 is a variable capacitor, and adjusting the variable capacitor can further improve the circuit gain.

[0049] Optionally, the slope of the ramp voltage vramp is adjustable; in particular, in the process of quantizing the output of the pixel circuit 11, the slopes of the low-gain ramp voltage and the high-gain ramp voltage can be set to different, thereby further improving the circuit gain and further increasing the dynamic range of the image sensor.

[0050] The gain quantization selection circuit 131 also includes a high-gain quantization switch HEN and a low-gain quantization switch LEN; the high-gain quantization switch HEN is controlled by a high-gain quantization switch signal hcg_en, and a first end of the high-gain quantization switch HEN is connected to the second gain output bit line Pixout_h to serve as a high-gain reset signal hcg_rst input end of the readout circuit 13 and a high-gain image signal hcg_sig input end of the readout circuit 13; the low-gain quantization switch LEN is controlled by a low-gain quantization switch signal lcg_en, and a first end of the low-gain quantization switch LEN is connected to the first gain output bit line Pixout_l to serve as a low-gain reset signal lcg_rst input end of the readout circuit 13 and a low-gain image signal lcg_sig input end of the readout circuit 13; the second end of the high-gain quantization switch HEN and the second end of the low-gain quantization switch LEN are connected in parallel to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the inverting input end of the comparator.

[0051] It can be understood that, through the high-gain quantization switch HEN receiving the high-gain quantization switch signal hcg_en and the low-gain quantization switch LEN receiving the low-gain quantization switch signal lcg_en in the readout circuit 13, the second gain output bit line Pixout_h and the first gain output bit line Pixout_l are respectively connected to the second capacitor C2 at different times, thereby respectively coupling the high-gain reset signal hcg_rst and the high-gain image signal hcg_sig to the inverting input terminal of the comparison circuit 132 through the second gain output bit line Pixout_h and the second capacitor C2, and coupling the low-gain reset signal lcg_rst and the low-gain image signal lcg_sig to the inverting input terminal of the comparison circuit 132 through the first gain output bit line Pixout_l and the second capacitor C2.

[0052] It can be understood that the low-gain bit line selection switch LBS, the high-gain bit line selection switch HBS, the low-gain row selection switch LRS, the high-gain row selection switch HRS, the high-gain quantization switch HEN, the low-gain quantization switch LEN, the first clear switch CAZ1 and the second clear switch CAZ2 are all fully-controlled switching devices. As an optional implementation, they can also be MOS tubes. The embodiment of the present application does not impose any specific restrictions on the switch type.

[0053] like Figure 2 As shown, it can be understood that each column of pixel units includes two output bit lines, namely a first output bit line Pixout_1 and a second output bit line Pixout_h.

[0054] In addition, the present application also provides an image sensor working method, which is applied to the above-mentioned image sensor. Figure 3 yes Figure 2 The timing control diagram of the image sensor is described in detail below:

[0055] Input the low gain row selection signal lcg_rowsel and the low gain bit line selection signal lcg_bl_sel, turn on the low gain row selection switch LRS and the low gain bit line selection switch LBS, and sample the low gain reset signal lcg_rst output by the pixel circuit 11 to the first equivalent capacitor Cbll of the first output bit line Pixout_1. Figure 3 :

[0056] At time t0, the reset signal rst is set to a low level, the low-gain row selection signal lcg_rowsel is set to a high level, the low-gain bit line selection signal lcg_bl_sel is set to a high level, the first gain output bit line Pixout_1, the source follower transistor SF, and the source follower current source CC are turned on, and the low-gain reset signal lcg_rst is obtained;

[0057] At time t1, the low-gain bit line selection signal lcg_bl_sel is set to a low level, and the first-gain output bit line Pixout_1, the source-follower transistor SF, and the source-follower current source CC are disconnected;

[0058] At time t2, the low-gain row selection signal lcg_rowsel is set to a low level, and the aforementioned low-gain reset signal lcg_rst is sampled to the equivalent capacitor of the first gain output bit line Pixout_1, that is, the first equivalent capacitor Cb11.

[0059] The high gain row selection signal hcg_rowsel and the high gain bit line selection signal hcg_bl_sel are input, the high gain row selection switch HRS and the high gain bit line selection switch HBS are turned on, and the high gain reset signal hcg_rst and the high gain image signal hcg_sig output by the pixel circuit 11 are transmitted to the second gain output bit line Pixout_h and output.

[0060] Specifically, it is first transmitted to the second equivalent capacitor Cblh, and then connected to the second gain output bit line Pixout_h output; the first clear switch CAZ1 and the second clear switch CAZ2 are turned on to clear and reset the comparator; the readout circuit 13 quantizes the high gain reset signal hcg_rst, and refers to Figure 3 :

[0061] At time t3, the high-gain row select signal hcg_rowsel is set to a high level, the high-gain row select switch HRS is turned on, the high-gain bit line select signal hcg_bl_sel is set to a high level, the high-gain bit line select switch HBS is turned on, the second gain output bit line Pixout_h, the source-follower transistor SF and the source-follower current source CC are turned on, the comparator clear signal cmp_az is connected, the first clear switch CAZ1 and the second clear switch CAZ2 are turned on, the first input terminal Vinp of the comparator and the first gain output bit line Vop1 are shorted together, the second input terminal Vinn and the second gain output bit line Von1 are shorted together, and the comparator clear signal cmp_az clears the comparator; the dual conversion gain signal dcg is set to a high level, the dual conversion gain transistor DCG is turned on, and at this time the second gain output bit line Pixout_h receives the high gain reset signal hcg_rst.

[0062] At time t4, the high-gain quantization switch signal hcg_en is set to a high level, the high-gain quantization switch HEN is turned on, and the second gain output bit line Pixout_h is connected to the comparator;

[0063] At time t5, the comparator clear switch signal cmp_az is turned off, and the first clear switch CAZ1 and the second clear switch CAZ2 are turned off.

[0064] The ramp voltage vramp is connected to the non-inverting input terminal of the comparator, the high-gain quantization switch signal hcg_en is input, the high-gain quantization switch HEN is turned on, and the high-gain reset signal hcg_rst is coupled to the inverting input terminal of the comparator through the second capacitor C2. The readout circuit 13 quantizes the high-gain reset signal hcg_rst to obtain a quantized value of the high-gain reset signal. Specifically, during the quantization of the high-gain reset signal lcg_rst, the ramp voltage vramp decreases, the comparison circuit 132 compares the ramp voltage vramp with the high-gain reset signal hcg_rst, and outputs a first comparison signal. The counter 133 starts counting, and when the ramp voltage vramp and the high-gain reset signal hcg_rst overlap, the first counting result is recorded, the ramp voltage vramp is reset, and the high-gain reset signal hcg_rst is output. Figure 3 :

[0065] At time t6, the ramp voltage vramp begins to decrease, and the comparison circuit 132 compares the ramp voltage vramp with the high-gain reset signal hcg_rst and outputs a first comparison signal; the count enable signal count_en of the counter 133 counts when receiving the first comparison signal, and when the ramp voltage vramp and the high-gain reset signal hcg_rst overlap, the first counting result is recorded and the high-gain reset signal hcg_rst is output.

[0066] Specifically, the ramp voltage vramp and the second gain output bit line Pixout_h are respectively coupled to the non-inverting input terminal of the comparator through capacitors, corresponding to the first input terminal Vinp and the second input terminal Vinn of the comparator, respectively. When the first input terminal Vinp and the second input terminal Vinn overlap, the comparator outputs 0. At this time, the counter 133 stops counting and obtains a reset signal under high gain.

[0067] At time t7, the high-gain reset signal hcg_rst is quantized and the ramp voltage vramp is reset.

[0068] Input the high-gain row selection signal hcg_rowsel and the high-gain bit line selection signal hcg_bl_sel, turn on the low-gain row selection switch HRS and the low-gain bit line selection switch HBS, and transmit the high-gain image signal hcg_sig output by the pixel circuit to the second gain output bit line Pixout_h for output;

[0069] The aforementioned ramp voltage vramp is connected to the non-inverting input terminal of the comparator, and the high-gain quantization switch signal hcg_en is input to turn on the high-gain quantization switch HEN, and the high-gain image signal hcg_sig is coupled to the inverting input terminal of the comparator through the second capacitor C2. The readout circuit 13 quantizes the high-gain image signal hcg_sig to obtain the difference between the quantization value of the high-gain reset signal and the quantization value of the high-gain image signal, that is, the high-gain effective image quantization value.

[0070] Specifically, in the step of quantizing the high-gain image signal hcg_sig, the ramp voltage vramp decreases, and the comparison circuit 132 compares the ramp voltage vramp with the high-gain image signal hcg_sig and outputs a second comparison signal; when the counter 133 receives the second comparison signal, it starts counting in the opposite direction from the first counting result, and when the ramp voltage vramp and the high-gain image signal hcg_sig overlap, it records the second counting result and resets the ramp voltage vramp. The second counting result is the difference between the quantization result of the high-gain reset signal hcg_rst and the quantization result of the high-gain image signal hcg_sig; the memory 134 is configured to store the second counting result and use the second counting result as the high-gain effective image quantization value; refer to Figure 3 :

[0071] From time t8 to t9, the transmission control signal tx is set to a high level, the transmission transistor TX is turned on, and the image signal begins to be transmitted. The second gain output bit line Pixout_h is coupled to the second input terminal Vinn of the comparator through the second capacitor C2, and the image signal is transmitted to the comparator to obtain a high-gain image signal hcg_sig.

[0072] At time t10, the ramp voltage vramp decreases again. The comparison circuit 132 compares the ramp voltage vramp with the high-gain image signal hcg_sig and outputs a second comparison signal. When the count enable count_en is enabled, that is, when the counter 133 receives the second comparison signal, it starts counting in the opposite direction from the first count result. The ramp voltage vramp and the second gain output bit line Pixout_h are coupled to the first input terminal Vinp and the second input terminal Vinn of the comparator via the first capacitor C1 and the second capacitor C2, respectively. When the first input terminal Vinp and the second input terminal Vinn overlap, the comparator outputs 0. At this time, the counter 133 stops counting and obtains the second count result. The memory 134 stores the second count result and obtains the difference between the high-gain image signal and the reset signal. This difference is the high-gain effective image quantization value.

[0073] At time t11, the quantization of the high-gain image signal hcg_sig is completed, and the ramp voltage vramp is reset and begins to return to the reference state.

[0074] At time t12, the high gain row selection signal hcg_rowsel is set to a low level, the high gain row selection switch HRS is disconnected, the high gain bit line selection signal hcg_bl_sel is set to a low level, the high gain bit line selection switch HBS is disconnected, the high gain quantization switch signal hcg_en is set to a low level, the high gain quantization switch HEN is disconnected, the second gain output bit line Pixout_h, the source follower transistor SF and the source follower current source CC are disconnected, and the second gain output bit line Pixout_h is disconnected from the comparator.

[0075] Since the low-gain reset signal lcg_rst is sampled to the equivalent capacitor of the first gain output bit line Pixout_1, i.e., the first equivalent capacitor Cb1, at time t2, the low-gain reset signal lcg_rst can be discharged through the first equivalent capacitor Cb1 when the low-gain reset signal lcg_rst is quantized. When the switch control circuit 13 is turned on, the low-gain reset signal lcg_rst is output through the first gain output bit line Pixout_1. After the low-gain quantization switch signal lcg_en is input, the low-gain quantization switch LEN is turned on, and the comparator is reset, the low-gain reset signal lcg_rst is coupled to the inverting input terminal of the comparator through the second capacitor C2. Figure 3 :

[0076] At time t13, the dual conversion gain signal dcg is set to a high level, the dual conversion gain transistor DCG is turned on, the comparator clear switch signal cmp_az is connected, the first clear switch CAZ1 and the second clear switch CAZ2 are turned on, the first input terminal Vinp of the comparator and the first gain output bit line Vop1 are shorted together, and the second input terminal Vinn of the comparator and the second gain output bit line Von1 are shorted together, thus clearing and resetting the comparator.

[0077] At time t14, the low gain quantization switch signal lcg_en is set to a high level, the low gain quantization switch LEN is turned on, and the low gain reset signal lcg_rst stored on the equivalent capacitor of the first gain output bit line Pixout_1, i.e., the first equivalent capacitor Cb11, is coupled to the second input terminal Vinn of the comparator through the second capacitor C2.

[0078] At time t15 , the comparator clear switch signal cmp_az is turned off, and the first clear switch CAZ1 and the second clear switch CAZ2 are turned off.

[0079] The ramp voltage vramp is connected to the non-inverting input of the comparator, and the readout circuit 13 quantizes the low-gain reset signal lcg_rst to obtain a quantized value of the low-gain reset signal. Specifically, during the quantization of the low-gain reset signal lcg_rst, the ramp voltage vramp decreases, and the comparison circuit 132 compares the ramp voltage vramp with the low-gain reset signal lcg_rst and outputs a third comparison signal. The counter 133 counts upon receiving the third comparison signal, and when the ramp voltage vramp and the low-gain reset signal lcg_rst overlap, the counter 133 records the third count result and resets the ramp voltage vramp. Figure 3 :

[0080] At time t16, the ramp voltage vramp begins to decrease. The comparator circuit 132 compares the ramp voltage vramp with the low-gain reset signal lcg_rst and outputs a third comparison signal. The counter 133 begins counting when the count enable signal count_en is enabled. The ramp voltage vramp and the first gain output bit line Pixout_1 are coupled to the first input terminal Vinp and the second input terminal Vinn of the comparator via the first capacitor C1 and the second capacitor C2, respectively. When the first input terminal Vinp and the second input terminal Vinn overlap, the comparator outputs 0. At this time, the counter 133 stops counting and obtains the third count result, thereby obtaining the low-gain reset signal lcg_rst.

[0081] At time t17, the low-gain reset signal lcg_rst is quantized, and the ramp voltage vramp is reset and returns to the reference state;

[0082] A low-gain row select signal lcg_rowsel and a low-gain bit line select signal lcg_bl_sel are input, the low-gain row select switch LRS and the low-gain output select transistor LBS are turned on, and the low-gain image signal lcg_sig is transmitted to the first gain output bit line Pixout_1 for sampling and output. The ramp voltage vramp is connected to the non-inverting input terminal of the comparator, and a low-gain quantization switch signal lcg_en is input, the low-gain quantization switch LEN is turned on, and the low-gain image signal lcg_sig is coupled to the inverting input terminal of the comparator via the second capacitor C2. The readout circuit 13 quantizes the low-gain image signal lcg_sig to obtain the difference between the quantization value of the low-gain reset signal and the quantization value of the low-gain image signal, that is, the low-gain effective image quantization value. Specifically, in the quantization step of the low-gain image signal lcg_sig, the ramp voltage vramp decreases again, and the comparison circuit 132 compares the ramp voltage vramp with the low-gain image signal lcg_sig and outputs a fourth comparison signal. When the counter 133 receives the fourth comparison signal, it starts counting in the opposite direction from the third counting result. When the ramp voltage vramp overlaps with the high-gain image signal hcg_sig, it records the fourth counting result and resets the ramp voltage vramp. The fourth counting result is the difference between the quantization result of the high-gain reset signal hcg_rst and the quantization result of the high-gain image signal hcg_sig. Figure 3 :

[0083] At time t18, the low gain row select signal lcg_rowsel is set to a high level, the low gain row select switch LRS is turned on, the low gain bit line select signal lcg_bl_sel is set to a high level, the low gain output select transistor LBS is turned on, and the first gain output bit line Pixout_1 and the source follower current source CC are connected.

[0084] From t19 to t20, the transmission control signal tx is set to a high level, the transmission transistor TX is turned on, and the image signal begins to be transmitted. The first gain output bit line Pixout_1 is coupled to the second input terminal Vinn of the comparator through the second capacitor C2 to obtain a low gain image signal lcg_sig.

[0085] At time t21, the ramp voltage vramp decreases again. The comparator circuit 132 compares the ramp voltage vramp with the low-gain image signal lcg_sig and outputs a fourth comparison signal. When the count enable signal count_en is input, the counter 133 starts counting in the opposite direction from the third count result. The ramp voltage vramp and the first gain output bit line Pixout_1 are coupled to the first input terminal Vinp and the second input terminal Vinn of the comparator via the first capacitor C1 and the second capacitor C2, respectively. When the ramp voltage vramp and the high-gain image signal hcg_sig overlap, in other words, when the first input terminal Vinp and the second input terminal Vinn overlap, the comparator outputs 0. At this time, the counter 133 stops counting. The memory 134 stores the fourth count result, obtaining the difference between the image signal at low gain and the reset signal. This difference is the relevant valid image quantization value obtained at low gain.

[0086] At time t22, the quantization of the low-gain image signal lcg_sig is completed, and the ramp voltage vramp is reset and returns to the reference state.

[0087] In the working method of the image sensor provided in the present application, within one quantization cycle, the low-gain reset signal lcg_rst, the high-gain reset signal hcg_rst, the high-gain image signal hcg_sig, and the low-gain image signal lcg_sig are read sequentially, and the analog-to-digital conversion circuit in the readout circuit quantizes the above signals to achieve high dynamic range output of the image sensor.

[0088] In addition, the present application also provides an electronic device including the aforementioned image sensor.

[0089] In summary, the image sensor and its operating method provided by the present application include a bitline module 12. In a first state, a low-gain reset signal lcg_rst is sampled into a first equivalent capacitor Cb11. In a second state, a high-gain reset signal hcg_rst and a high-gain image signal hcg_sig are sequentially sampled and outputted via a second gain output bitline Pixout_h. Furthermore, after the second state returns to the first state, the low-gain reset signal lcg_rst sampled in the first equivalent capacitor Cb11 is outputted via a first gain output bitline Pixout_1, and the low-gain image signal lcg_sig is subsequently sampled and outputted via the first gain output bitline Pixout_1. Simultaneously, the bitline module 12 is connected to a corresponding readout circuit 13 to achieve effective image quantization. This achieves a high dynamic range for the image sensor while reducing cost and size. Because the pixel circuit output does not need to be sampled and held to reduce the circuit's KT / C noise, the circuit noise level is lower, further improving image sensor performance.

[0090] The embodiments described above are only some of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of protection of the present application, but merely represents selected embodiments of the present application. Based on this, the scope of protection of the present application shall be based on the scope of protection of the claims. In addition, based on the embodiments of the present application, all other embodiments that can be obtained by those skilled in the art without making creative work should fall within the scope of protection of the present application.

Claims

1. An image sensor, characterized in that: include: A pixel circuit having two states: in a first state, outputting a low-gain reset signal or a low-gain image signal; and in a second state, outputting a high-gain reset signal or a high-gain image signal; the pixel circuit being configured to sequentially output a low-gain reset signal, a high-gain reset signal, a high-gain image signal, and a low-gain image signal; a bitline module connected to the pixel circuit, the bitline module comprising a first gain output bitline and a second gain output bitline, the first gain output bitline comprising a first equivalent capacitor, and the second gain output bitline comprising a second equivalent capacitor; the bitline module being configured to sample the low-gain reset signal to the first equivalent capacitor in a first state of the pixel circuit, and to sample and output the high-gain reset signal and the high-gain image signal in sequence through the second gain output bitline in a second state of the pixel circuit; and when the pixel circuit returns from the second state to the first state, output the low-gain reset signal sampled in the first equivalent capacitor through the first gain output bitline, and then sample and output the low-gain image signal through the first gain output bitline; A readout circuit is connected to the bit line module. The readout circuit has two states. In a first state, the readout circuit sequentially receives the high-gain reset signal and the high-gain image signal and quantizes them respectively to obtain an effective image signal quantization value under high gain. In a second state, the readout circuit sequentially receives the low-gain reset signal and the low-gain image signal and quantizes them respectively to obtain an effective image signal quantization value under low gain.

2. The image sensor according to claim 1, wherein The pixel circuit includes a photosensitive element, a reset transistor, a transfer transistor, a source follower transistor, a dual conversion gain transistor and a row selection module, wherein the row selection module includes a low gain row selection switch and a high gain row selection switch, and the low gain row selection switch and the high gain row selection switch are connected in parallel; A first end of the low-gain row selection switch is connected to the output end of the source follower transistor, and a second end of the low-gain row selection switch is connected to the first equivalent capacitor; the low-gain row selection switch is used to sample the low-gain reset signal to the first equivalent capacitor in the first state of the pixel circuit and output it through the first gain output bit line when the pixel circuit is restored from the second state to the first state, and to transmit the low-gain image signal from the pixel circuit to the first equivalent capacitor and output it through the first gain output bit line after the pixel circuit is restored from the second state to the first state; The first end of the high-gain row selection switch is connected to the output end of the source follower transistor, and the second end of the high-gain row selection switch is connected to the second equivalent capacitor; the high-gain row selection switch is used to transmit the high-gain reset signal and the high-gain image signal to the second equivalent capacitor in sequence in the second state of the pixel circuit and output them through the second gain output bit line.

3. The image sensor according to claim 1, wherein The bit line module further includes a source follower current source, a low gain bit line selection switch and a high gain bit line selection switch; A first end of the low-gain bit line selection switch is connected to the source follower current source, a second end of the low-gain bit line selection switch is connected to the first gain output bit line, and the low-gain bit line selection switch is used to select the source follower current source to provide an operating current for the first gain output bit line; The first end of the high-gain bit line selection switch is connected to the source follower current source, the second end of the high-gain bit line selection switch is connected to the second gain output bit line, and the high-gain bit line selection switch is used to select the source follower current source to provide an operating current for the second gain output bit line.

4. The image sensor according to claim 1, wherein The readout circuit includes a gain quantization selection circuit, a comparison circuit, a counter, and a memory connected in sequence, wherein the gain quantization selection circuit is configured to sequentially connect the high gain reset signal and the high gain image signal to the comparison circuit in a first state of the readout circuit; The gain quantization selection circuit is further configured to sequentially connect the low-gain reset signal and the low-gain image signal to the comparison circuit in the second state of the readout circuit.

5. The image sensor according to claim 4, wherein: When the readout circuit quantizes the high-gain reset signal, the comparison circuit is configured to compare the ramp voltage with the high-gain reset signal and output a first comparison signal; the counter is configured to count when receiving the first comparison signal, and record a first counting result when the ramp voltage and the high-gain reset signal overlap; When the readout circuit quantizes the high-gain image signal, the comparison circuit is configured to compare the ramp voltage with the high-gain image signal and output a second comparison signal; the counter is configured to count in a reverse direction from the first counting result upon receiving the second comparison signal, and output a second counting result when the ramp voltage and the high-gain image signal overlap, the second counting result being the difference between the quantization result of the high-gain image signal and the quantization result of the high-gain reset signal; The memory is configured to store the second counting result and use the second counting result as the effective image quantization value under the high gain; When the readout circuit quantizes the low-gain reset signal, the comparison circuit is configured to compare the ramp voltage with the low-gain reset signal and output a third comparison signal; the counter is configured to count when receiving the third comparison signal, and record a third counting result when the ramp voltage and the low-gain reset signal overlap; When the readout circuit quantizes the low-gain image signal, the comparison circuit is configured to compare the ramp voltage with the low-gain image signal and output a fourth comparison signal; the counter is configured to count in a reverse direction from the third counting result upon receiving the fourth comparison signal, and output a fourth counting result when the ramp voltage and the low-gain image signal overlap, the fourth counting result being the difference between the quantization result of the low-gain image signal and the quantization result of the low-gain reset signal; The memory is configured to store the fourth counting result and use the fourth counting result as the effective image quantization value under the low gain.

6. The image sensor according to claim 4, wherein: The comparison circuit includes a comparator, a first capacitor, a second capacitor, a first clearing switch and a second clearing switch; The non-inverting input terminal of the comparator is connected to the ramp voltage through the first capacitor, and the inverting input terminal of the comparator is connected to the gain quantization selection circuit through the second capacitor; The non-phase input terminal of the comparator is connected to the first end of the first clear switch, and the inverting input terminal of the comparator is connected to the first end of the second clear switch; the non-phase output terminal of the comparator is connected to the second end of the first clear switch, and the first inverting output terminal of the comparator is connected to the second end of the second clear switch.

7. The image sensor according to claim 6, wherein: The first capacitor is a variable capacitor.

8. The image sensor according to claim 6, wherein: The slope of the ramp voltage is adjustable.

9. The image sensor according to claim 6, wherein: The gain quantization selection circuit includes a high gain quantization switch and a low gain quantization switch; A first end of the high-gain quantization switch is connected to the second gain output bit line to serve as a high-gain reset signal input end of the gain quantization selection circuit and a high-gain image signal input end of the gain quantization selection circuit; A first end of the low-gain quantization switch is connected to the first gain output bit line to serve as a low-gain reset signal input end of the gain quantization selection circuit and a low-gain image signal input end of the gain quantization selection circuit; The second end of the high-gain quantization switch and the second end of the low-gain quantization switch are connected in parallel to the first end of the second capacitor, and the second end of the second capacitor is connected to the inverting input end of the comparator.

10. A method for operating an image sensor, applied to the image sensor according to any one of claims 1 to 9, characterized in that: The following steps are involved: The pixel circuit includes a photosensitive element, a reset transistor, a transfer transistor, a source follower transistor, a dual conversion gain transistor and a row selection module, and the row selection module includes a low gain row selection switch and a high gain row selection switch. The bit line module also includes a source follower current source, a low gain bit line selection switch and a high gain bit line selection switch. The readout circuit includes a gain quantization selection circuit, a comparison circuit, a counter and a memory connected in sequence. The comparison circuit includes a comparator, a first capacitor, a second capacitor, a first clear switch and a second clear switch. The gain quantization selection circuit includes a high gain quantization switch and a low gain quantization switch. Turning on the low-gain row selection switch and the low-gain bit line selection switch to sample the low-gain reset signal output by the pixel circuit to the first equivalent capacitor; Turning on the high-gain row selection switch and the high-gain bit line selection switch to transmit the high-gain reset signal output by the pixel circuit to the second equivalent capacitor and output it through the second gain output bit line; Connecting the ramp voltage to the non-inverting input terminal of the comparator, turning on the high-gain quantization switch, coupling the high-gain reset signal to the inverting input terminal of the comparator through the second capacitor, and causing the readout circuit to quantize the high-gain reset signal to obtain a quantized value of the high-gain reset signal; Turning on the high-gain row selection switch and the high-gain bit line selection switch to transmit the high-gain image signal output by the pixel circuit to the second gain output bit line for output; Connecting the ramp voltage to the non-inverting input terminal of the comparator, turning on the high-gain quantization switch, coupling the high-gain image signal to the inverting input terminal of the comparator via the second capacitor, and causing the readout circuit to quantize the high-gain image signal to obtain a difference between a quantized value of the high-gain reset signal and a quantized value of the high-gain image signal, that is, obtaining an effective image quantized value under high gain; Connecting the ramp voltage to the non-inverting input terminal of the comparator, inputting the low-gain quantization switch signal, turning on the low-gain quantization switch, coupling the low-gain reset signal to the inverting input terminal of the comparator via the second capacitor, and causing the readout circuit to quantize the low-gain reset signal to obtain a quantized value of the low-gain reset signal; Turning on the low-gain row selection switch and the low-gain bit line selection switch to transmit the low-gain image signal to the first equivalent capacitor and output it through the first gain output bit line; The ramp voltage is connected to the non-inverting input terminal of the comparator, the low-gain quantization switch is turned on, the low-gain image signal is coupled to the inverting input terminal of the comparator via the second capacitor, and the readout circuit quantizes the low-gain image signal to obtain the difference between the quantization value of the low-gain reset signal and the quantization value of the low-gain image signal, that is, the effective image quantization value under the low gain condition is obtained.

11. The operating method of the image sensor according to claim 10, wherein: The reset transistor is turned on before the low-gain row selection switch and the low-gain bit line selection switch are turned on.

12. The operating method of the image sensor according to claim 10, wherein: Before the low-gain reset signal or the low-gain image signal is connected to the first gain output bit line, the dual-conversion gain transistor is turned on; before the high-gain reset signal and the high-gain image signal are connected to the second gain output bit line, the dual-conversion gain transistor is turned off.

13. The operating method of the image sensor according to claim 10, wherein: The step of quantizing the high-gain reset signal, the high-gain image signal, the low-gain image signal, and the low-gain reset signal by the readout circuit includes: The ramp voltage decreases, the comparison circuit compares the ramp voltage with the high-gain reset signal, and outputs a first comparison signal; The counter counts when receiving the first comparison signal, and records a first counting result and resets the ramp voltage when the ramp voltage and the high-gain reset signal overlap; The ramp voltage decreases, and the comparison circuit compares the ramp voltage with the high-gain image signal and outputs a second comparison signal; The counter starts counting in a reverse direction from the first counting result when receiving the second comparison signal, and records a second counting result and resets the ramp voltage when the ramp voltage and the high-gain image signal overlap, wherein the second counting result is a difference between a quantization result of the high-gain reset signal and a quantization result of the high-gain image signal; The memory is configured to store the second counting result and use the second counting result as the high-gain effective image quantization value; The ramp voltage decreases, the comparison circuit compares the ramp voltage with the low-gain reset signal, and outputs a third comparison signal; The counter counts when receiving the third comparison signal, and records a third counting result and resets the ramp voltage when the ramp voltage and the low-gain reset signal overlap; The ramp voltage decreases, and the comparison circuit compares the ramp voltage with the low-gain image signal and outputs a fourth comparison signal; When receiving the fourth comparison signal, the counter starts counting in the opposite direction from the third counting result, and when the ramp voltage and the high-gain image signal overlap, the counter records a fourth counting result and resets the ramp voltage. The memory is configured to store the fourth counting result, which is the difference between a quantization result of the high-gain reset signal and a quantization result of the high-gain image signal.

14. The operating method of the image sensor according to claim 13, wherein: Before the readout circuit quantizes the high-gain reset signal and before the readout circuit quantizes the low-gain image signal, the first clear switch and the second clear switch are turned on simultaneously to clear and reset the comparator.

15. An electronic device comprising the image sensor according to any one of claims 1 to 9.

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