Driving control circuit, gate driving circuit, display substrate and display device

Abstract

A drive control circuit includes an input circuit (10), a first output circuit (11), and a second output circuit (12). The first output circuit (11) is electrically connected to the input circuit (10) and a first output terminal (OUT1), and is configured to output a first output signal from the first output terminal (OUT1) under control of the input circuit (11). The second output circuit (12) is electrically connected to the input circuit (10) and a second output terminal (OUT2), or is electrically connected to the first output terminal (OUT1) and the second output terminal (OUT2), and is configured to output a second output signal from the second output terminal (OUT2) under control of the input circuit (10) or the first output terminal (OUT1). The first output signal is different from the second output signal.

Description

TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, the technical field of display, in particular to a driving control circuit, a gate driving circuit, a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present application provide a driving control circuit, a gate driving circuit, a display substrate and a display device.

[0005] In one aspect, the embodiments of the present application provide a driving control circuit, comprising: an input circuit, a first output circuit and a second output circuit. The first output circuit is electrically connected with the input circuit and a first output terminal, and is configured to output a first output signal from the first output terminal under the control of the input circuit. The second output circuit is electrically connected with the input circuit and a second output terminal, or is electrically connected with the first output terminal and the second output terminal, and is configured to output a second output signal from the second output terminal under the control of the input circuit or the first output terminal. The first output signal and the second output signal are different in at least one of the following: the absolute value of the voltage of the active level, the polarity of the active level, the duration of the active level within a frame duration, and the voltage fluctuation stage continuous after the active level.

[0006] In another aspect, the embodiments of the present application provide a gate driving circuit, comprising a plurality of cascaded driving control circuits as described above. The signal input terminal of the first stage driving control circuit is electrically connected with a start signal line, and the signal input terminal of the i+1 stage driving control circuit is electrically connected with the first output terminal of the i stage driving control circuit, where i is an integer greater than 0.

[0007] In another aspect, the embodiments of the present disclosure provide a display substrate, comprising a display area and a non-display area located at a periphery of the display area, the non-display area being provided with a gate drive circuit, the gate drive circuit comprising a plurality of cascaded drive control circuits, the drive control circuit comprising an input circuit, a first output circuit and a second output circuit; the first output circuit being electrically connected with the input circuit, and the second output circuit being electrically connected with the input circuit or the first output circuit. In a first direction, the input circuit is located between the first output circuit and the second output circuit, or the second output circuit is located between the input circuit and the first output circuit.

[0008] In another aspect, the embodiments of the present disclosure provide a display device comprising the display substrate as described above.

[0009] Other aspects can become apparent from the following drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of one or more components in the drawings do not reflect the true proportion, and the purpose is only to schematically illustrate the present disclosure.

[0011] Figure 1 Structure schematic diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0012] Figure 2 Equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0013] Figure 3 Working timing diagram of the drive control circuit provided; Figure 2

[0014] Another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure; Figure 4

[0015] Working timing diagram of the drive control circuit provided; Figure 5 Figure 4 Another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure;

[0016] Figure 6 Working timing diagram of the drive control circuit provided;

[0017] Figure 7 Figure 6

[0018] Figure 8 ​​​Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0019] Figure 9 For Figure 8 The working timing diagram of the drive control circuit provided;

[0020] Figure 10 Another structural schematic diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0021] Figure 11 Another structural schematic diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0022] Figure 12 Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0023] Figure 13 For Figure 12 The working timing diagram of the drive control circuit provided;

[0024] Figure 14 Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0025] Figure 15 For Figure 14 The working timing diagram of the drive control circuit provided;

[0026] Figure 16 Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0027] Figure 17 For Figure 16 The working timing diagram of the drive control circuit provided;

[0028] Figure 18 Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0029] Figure 19 Another structural schematic diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0030] Figure 20 Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0031] Figure 21 For Figure 20 The working timing diagram of the drive control circuit provided;

[0032] Figure 22 Another equivalent circuit diagram of the drive control circuit of at least one of the embodiments of the present disclosure;

[0033] Figure 23 For Figure 22 A timing diagram of the driving control circuit is provided;

[0034] Figure 24 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure;

[0035] Figure 25 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure;

[0036] Figure 26 For Figure 25 A timing diagram of the driving control circuit is provided;

[0037] Figure 27 Another structural schematic diagram of the driving control circuit of at least one embodiment of the present disclosure;

[0038] Figure 28 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure;

[0039] Figure 29 For Figure 28 A timing diagram of the driving control circuit is provided;

[0040] Figure 30 An equivalent circuit diagram of the pixel circuit of at least one embodiment of the present disclosure;

[0041] Figure 31 For Figure 30 A timing diagram of the pixel circuit is provided;

[0042] Figure 32 A schematic diagram of the gate driving circuit of at least one embodiment of the present disclosure;

[0043] Figure 33 A top view of the driving control circuit of at least one embodiment of the present disclosure;

[0044] Figure 34 For Figure 33 A partial cross-sectional schematic diagram in the direction of P-P';

[0045] Figure 35A For Figure 33 A top view of the driving control circuit after forming the first semiconductor layer;

[0046] Figure 35B For Figure 33 A top view of the driving control circuit after forming the first conductive layer;

[0047] Figure 35C For Figure 33 A top view of the driving control circuit after forming the second semiconductor layer;

[0048] Figure 35D Figure 1 is a top view of a drive control circuit in accordance with an embodiment of the present disclosure; Figure 33 Figure 2 is a top view of the drive control circuit of Figure 1 after formation of a second conductive layer;

[0049] Figure 35E Figure 3 is a top view of the drive control circuit of Figure 1 after formation of a first semiconductor layer; Figure 33 Figure 4 is a top view of the drive control circuit of Figure 1 after formation of a fourth insulating layer;

[0050] Figure 35F Figure 5 is a top view of the drive control circuit of Figure 1 after formation of a third conductive layer; Figure 33 Figure 6 is a top view of the drive control circuit of Figure 1 after formation of a fifth insulating layer;

[0051] Figure 35G Figure 7 is a top view of a drive control circuit in accordance with another embodiment of the present disclosure; Figure 33 Figure 8 is a top view of the drive control circuit of Figure 7 after formation of a second semiconductor layer;

[0052] Figure 36 Figure 9 is a top view of a drive control circuit in accordance with another embodiment of the present disclosure;

[0053] Figure 37 Figure 10 is a top view of the drive control circuit of Figure 9 after formation of a first conductive layer; Figure 36 Figure 11 is a cross-sectional view along the Q-Q' direction of the drive control circuit of Figure 9;

[0054] Figure 38A Figure 12 is a top view of the drive control circuit of Figure 9 after formation of a second semiconductor layer; Figure 36 Figure 13 is a top view of the drive control circuit of Figure 9 after formation of a second conductive layer;

[0055] Figure 38B Figure 14 is a top view of the drive control circuit of Figure 9 after formation of a first insulating layer; Figure 36 Figure 15 is a top view of the drive control circuit of Figure 9 after formation of a third conductive layer;

[0056] Figure 38C Figure 16 is a top view of the drive control circuit of Figure 9 after formation of a second insulating layer; Figure 36 Figure 17 is a top view of the drive control circuit of Figure 9 after formation of a fourth semiconductor layer;

[0057] Figure 38D Figure 18 is a top view of the drive control circuit of Figure 9 after formation of a third insulating layer; Figure 36 Figure 19 is a top view of the drive control circuit of Figure 9 after formation of a fifth conductive layer;

[0058] Figure 38E Figure 20 is a top view of the drive control circuit of Figure 9 after formation of a fourth insulating layer; Figure 36 Figure 21 is a top view of the drive control circuit of Figure 9 after formation of a sixth semiconductor layer;

[0059] Figure 38F Figure 22 is a top view of the drive control circuit of Figure 9 after formation of a fifth insulating layer; Figure 36 Figure 23 is a top view of the drive control circuit of Figure 9 after formation of a sixth conductive layer;

[0060] Figure 38G Figure 24 is a top view of the drive control circuit of Figure 9 after formation of a sixth insulating layer; Figure 36 Figure 25 is a top view of a drive control circuit in accordance with another embodiment of the present disclosure;

[0061] Figure 39 Figure 26 is a top view of the drive control circuit of Figure 25 after formation of a first conductive layer;

[0062] Figure 40 for Figure 39 A partial cross-sectional view along the R-R' direction;

[0063] Figure 41A for Figure 39 A top view of the drive control circuit after the first semiconductor layer has been formed;

[0064] Figure 41B for Figure 39 A top view of the drive control circuit after the first conductive layer has been formed;

[0065] Figure 41C for Figure 39 A top view of the drive control circuit after the second semiconductor layer is formed;

[0066] Figure 41D for Figure 39 A top view of the drive control circuit after the second conductive layer has been formed;

[0067] Figure 41E for Figure 39 A top view of the drive control circuit after the fourth insulating layer has been formed;

[0068] Figure 41F for Figure 39 A top view of the drive control circuit after the third conductive layer has been formed;

[0069] Figure 41G for Figure 39 A top view of the drive control circuit after the fifth insulating layer has been formed;

[0070] Figure 42A This is a top view of a cascaded drive control circuit according to at least one embodiment of the present disclosure;

[0071] Figure 42B for Figure 42A A top view of the drive control circuit after the first conductive layer has been formed;

[0072] Figure 43 Another top view of a cascaded drive control circuit according to at least one embodiment of the present disclosure;

[0073] Figure 44 This is another top view of the drive control circuit of at least one embodiment of the present disclosure;

[0074] Figure 45 for Figure 44 A partial cross-sectional view along the U-U' direction;

[0075] Figure 46A for Figure 44 A top view of the drive control circuit after the first semiconductor layer has been formed;

[0076] Figure 46B FIG. 1 is a schematic view of a display device according to an embodiment of the present disclosure. Figure 44 FIG. 2 is a top view of a drive control circuit after formation of a first conductive layer in the display device of FIG. 1.

[0077] Figure 46C FIG. 3 is a top view of a drive control circuit after formation of a second semiconductor layer in the display device of FIG. 1. Figure 44 FIG. 4 is a top view of a drive control circuit after formation of a second conductive layer in the display device of FIG. 1.

[0078] Figure 46D FIG. 5 is a top view of a drive control circuit after formation of a third semiconductor layer in the display device of FIG. 1. Figure 44 FIG. 6 is a top view of a drive control circuit after formation of a third conductive layer in the display device of FIG. 1.

[0079] Figure 46E FIG. 7 is a top view of a drive control circuit after formation of a fourth insulating layer in the display device of FIG. 1. Figure 44 FIG. 8 is a top view of a drive control circuit after formation of a fourth conductive layer in the display device of FIG. 1.

[0080] Figure 46F FIG. 9 is a top view of a drive control circuit after formation of a fifth insulating layer in the display device of FIG. 1. Figure 44 FIG. 10 is a top view of a drive control circuit after formation of a fifth conductive layer in the display device of FIG. 1.

[0081] Figure 46G FIG. 11 is a schematic view of a display device according to an embodiment of the present disclosure. Figure 44 FIG. 12 is a schematic view of a display device according to an embodiment of the present disclosure.

[0082] Figure 47 DETAILED DESCRIPTION

[0083] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced to be one or more forms. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. Embodiments in the present disclosure and features in the embodiments can be combined with each other as long as there is no contradiction.

[0084] In the drawings, the size, the thickness, or the region of one or a plurality of constituent elements, a layer, or the like is sometimes exaggerated for the sake of clarity. Thus, one embodiment of the present disclosure is not necessarily limited to such a size, and the shape or the size of one or a plurality of components in the drawings do not reflect the actual one. Furthermore, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shape or the value shown in the drawings.

[0085] The ordinal numbers "first", "second", "third", and the like in the present disclosure are used for the purpose of avoiding confusion with the constituent elements, and are not used to limit the number. "A plurality of" in the present disclosure indicates two or more.

[0086] ​In the present disclosure, words of a positional relation or a positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation, and are used only for the convenience of description and simplification of the description, and thus are not intended to indicate or imply that the device or the element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which the components are described. Therefore, the words described in the specification are not limited, and can be appropriately replaced according to the situation.

[0087] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connected", and "connection" are to be construed broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate member, or connected inside two elements. Those skilled in the art can understand the meaning of the above terms in the present disclosure according to the situation. Among them, "electrically connected" includes the case where the components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the connected components. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.

[0088] In the present disclosure, a transistor refers to an element including at least a gate electrode (gate), a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0089] In the present disclosure, in order to distinguish two poles of a transistor other than the gate electrode, one of the poles is referred to as a first pole, and the other pole is referred to as a second pole, the first pole can be a source electrode or a drain electrode, and the second pole can be a drain electrode or a source electrode, and in addition, the gate electrode of the transistor is referred to as a control pole. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in the circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0090] In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of -10° or more and 10° or less, and thus can include a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and 100° or less, and thus can include a state in which the angle is 85° or more and 95° or less.

[0091] In the present disclosure, "film" and "layer" can be exchanged with each other. For example, "conductive layer" can be sometimes replaced with "conductive film". Similarly, "insulating film" can be sometimes replaced with "insulating layer".

[0092] In the present disclosure, "about", "approximately", and "approximately" mean not strictly limited to the limit, and allow for a range of process and measurement errors.

[0093] In the present disclosure, the effective level includes the level of turning on the transistor. For example, the effective level of turning on the P-type transistor is low, and the effective level of turning on the N-type transistor is high.

[0094] In some example embodiments, the display substrate can include a display area and a non-display area. For example, the non-display area can be located at the periphery of the display area. However, the present embodiment is not limited thereto. The display area includes at least a plurality of pixel circuits arranged regularly, a plurality of gate lines (e.g., including scan lines, reset control lines, and light emission control lines) extending in a first direction, a plurality of data lines extending in a second direction, and a power supply line. The first direction and the second direction are in the same plane, and the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.

[0095] In some example embodiments, the non-display area is provided with a gate drive circuit, and the gate drive circuit includes a plurality of cascaded drive control circuits, which can be configured to provide a gate drive signal to the pixel circuit of the display area.

[0096] The present embodiment provides a drive control circuit, which includes an input circuit, a first output circuit, and a second output circuit. The first output circuit is electrically connected with the input circuit and a first output terminal, and is configured to output a first output signal from the first output terminal under the control of the input circuit. The second output circuit is electrically connected with the input circuit and a second output terminal, or is electrically connected with the first output terminal and the second output terminal, and is configured to output a second output signal from the second output terminal under the control of the input circuit or the first output terminal. At least one of the first output signal and the second output signal is different from the following: the absolute value of the voltage of the effective level, the polarity of the effective level, the duration of the effective level within a frame duration, and the voltage fluctuation phase continuous after the effective level.

[0097] In some example embodiments, the active level of the first output signal and the active level of the second output signal have opposite polarities. In some examples, the active level of the first output signal can be configured to turn on a P-type transistor and the active level of the second output signal can be configured to turn on an N-type transistor. However, the present embodiments are not limited thereto. For example, the active levels of the first output signal and the second output signal can both be configured to turn on an N-type transistor or a P-type transistor.

[0098] In some example embodiments, the active level duration of the first output signal within a frame duration can be different from the active level duration of the second output signal within a frame duration. For example, the active level duration of the first output signal within a frame duration can be less than or equal to the active level duration of the second output signal within a frame duration. However, the present embodiments are not limited thereto.

[0099] In some example embodiments, the first output signal has a voltage fluctuation phase that is continuous after the active level, and the voltage fluctuation duration is less than the active level duration. The second output signal does not have a voltage fluctuation phase that is continuous after the active level. That is, the voltage fluctuation duration of the second output signal that is continuous after the active level is zero. However, the present embodiments are not limited thereto. For example, the voltage fluctuation duration of the first output signal and the second output signal that is continuous after the active level can both be zero.

[0100] In some example embodiments, the first output signal and the second output signal have opposite phases. For example, the active levels of the first output signal and the second output signal have opposite polarities, and the active level duration of the first output signal within a frame duration and the active level duration of the second output signal within a frame duration are substantially the same. In some examples, the voltage absolute value of the active level of the first output signal and the voltage absolute value of the active level of the second output signal can be substantially the same. However, the present embodiments are not limited thereto. For example, the voltage absolute value of the active level of the first output signal can be different from the voltage absolute value of the active level of the second output signal.

[0101] In some example embodiments, the active levels of the first output signal and the second output signal can have the same polarity, and the active level duration of the first output signal within a frame duration can be different from the active level duration of the second output signal within a frame duration. For example, the active levels of the first output signal and the second output signal can be configured to turn on an N-type transistor, and the active level duration of the first output signal within a frame duration can be greater than the active level duration of the second output signal within a frame duration. However, the present embodiments are not limited thereto.

[0102] In the embodiment, the first output signal is different from the second output signal. The driving control circuit of the embodiment can provide two different output signals, and can meet the requirements of different types of pixel circuits for the gate driving signal, thereby improving the performance of the pixel circuit. In addition, the number of circuits in the non-display area can be reduced, thereby facilitating the realization of a narrow frame display substrate.

[0103] Figure 1 A structural schematic diagram of a driving control circuit of at least one embodiment of the present disclosure is shown. As shown in the figure, the driving control circuit provided in the example can include an input circuit 10, a first output circuit 11, and a second output circuit 12. The first output circuit 11 is electrically connected with the input circuit 10 and a first output end OUT1, and is configured to output a first output signal from the first output end OUT1 under the control of the input circuit 10. The second output circuit 12 is electrically connected with the first output end OUT1 and a second output end OUT2, and is configured to output a second output signal from the second output end OUT2 under the control of the first output end OUT1. Figure 1

[0104] In some example embodiments, the second output circuit 12 can include at least one inverting sub-circuit. The inverting sub-circuit is electrically connected with the first output end, the second output end, a first power supply line, and a second power supply line, and is configured to control the second output end to output a first power supply signal provided by the first power supply line or a second power supply signal provided by the second power supply line under the control of the first output end. The effective level of the first power supply signal and the second power supply signal are different in polarity. The first output circuit 11 can include at least one inverting sub-circuit, which is electrically connected with the input circuit and the first output end.

[0105] In some example embodiments, the inverting sub-circuit can include a first semiconductor type transistor and a second semiconductor type transistor, and the transistor types of the first semiconductor type transistor and the second semiconductor type transistor are different. The first electrode of the first semiconductor type transistor is electrically connected with the first power supply line, and the first electrode of the second semiconductor type transistor is electrically connected with the second power supply line. The effective level of the first power supply signal provided by the first power supply line is opposite in polarity to the effective level of turning on the first semiconductor type transistor, and the effective level of the second power supply signal provided by the second power supply line is opposite in polarity to the effective level of turning on the second semiconductor type transistor. In some examples, the first semiconductor type transistor can be a P-type transistor, and the second semiconductor type transistor can be an N-type transistor. The N-type transistor can be realized by doping, or can directly use an oxide as an active layer without doping. However, the embodiment is not limited in this regard.

[0106] Figure 2 An equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure is shown. Figure 3 An equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure is shown.​ Figure 2 A timing chart of the driving control circuit is provided.

[0107] In some example embodiments, as shown in FIG. 1, an input circuit 10 is electrically connected with a signal input terminal INPUT, a first clock terminal CK, a second clock terminal CB, a first power line VGH, a second power line VGL, a first node N1 and a second node N2, and is configured to control the potentials of the first node N1 and the second node N2 under the control of the signal input terminal INPUT, the first clock terminal CK and the second clock terminal CB. A first output circuit 11 is electrically connected with the first power line VGH, the second clock terminal CB, a first output terminal OUT1, the first node N1 and the second node N2, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the first node N1 and the second node N2. A second output circuit 12 is electrically connected with the first power line VGH, the second power line VGL, the first output terminal OUT1 and a second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the first output terminal OUT1. Figure 2 In some example embodiments, as shown in FIG. 2, the input circuit 10 includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The first output circuit 11 includes a third transistor T3, an eighth transistor T8, a first capacitor C1 and a second capacitor C2. The second output circuit 12 includes a ninth transistor T9 and a tenth transistor T10.

[0108] Figure 2 In some example embodiments, as shown in FIG. 3, the input circuit 10 includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The first output circuit 11 includes a third transistor T3, an eighth transistor T8, a first capacitor C1 and a second capacitor C2. The second output circuit 12 includes a ninth transistor T9 and a tenth transistor T10.

[0109] In some example embodiments, as shown in FIG. 4, the input circuit 10 includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The first output circuit 11 includes a third transistor T3, an eighth transistor T8, a first capacitor C1 and a second capacitor C2. The second output circuit 12 includes a ninth transistor T9 and a tenth transistor T10. Figure 2 ​As shown, the control electrode of the first transistor T1 is electrically connected with the first clock end CK, the first electrode of the first transistor T1 is electrically connected with the second power supply line VGL, and the second electrode of the first transistor T1 is electrically connected with the second node N2. The control electrode of the second transistor T2 is electrically connected with the first clock end CK, the first electrode of the second transistor T2 is electrically connected with the signal input end INPUT, and the second electrode of the second transistor T2 is electrically connected with the third node N3. The control electrode of the third transistor T3 is electrically connected with the second node N2, the first electrode of the third transistor T3 is electrically connected with the first power supply line VGH, and the second electrode of the third transistor T3 is electrically connected with the first output end OUT1. The control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first power supply line VGH, and the second electrode of the fourth transistor T4 is electrically connected with the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected with the second clock end CB, and the second electrode of the fifth transistor T5 is electrically connected with the third node N3. The control electrode of the sixth transistor T6 is electrically connected with the second power supply line VGL, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the first node N1. The control electrode of the seventh transistor T7 is electrically connected with the third node N3, the first electrode of the seventh transistor T7 is electrically connected with the first clock end CK, and the second electrode of the seventh transistor T7 is electrically connected with the second node N2. The control electrode of the eighth transistor T8 is electrically connected with the first node N1, the first electrode of the eighth transistor T8 is electrically connected with the second clock end CB, and the second electrode of the eighth transistor T8 is electrically connected with the first output end OUT1. The control electrode of the ninth transistor T9 is electrically connected with the first output end OUT1, the first electrode of the ninth transistor T9 is electrically connected with the first power supply line VGH, and the second electrode of the ninth transistor T9 is electrically connected with the second output end OUT2. The control electrode of the tenth transistor T10 is electrically connected with the first output end OUT1, the first electrode of the tenth transistor T10 is electrically connected with the second power supply line VGL, and the second electrode of the tenth transistor T10 is electrically connected with the second output end OUT2. The first electrode plate of the first capacitor C1 is electrically connected with the second node N2, and the second electrode plate of the first capacitor C1 is electrically connected with the first power supply line VGH. The first electrode plate of the second capacitor C2 is electrically connected with the first node N1, and the second electrode plate of the second capacitor C2 is electrically connected with the first output end OUT1.

[0110] In the present example, the first node N1 is the connection point of the sixth transistor T6, the eighth transistor T8 and the second capacitor C2. The second node N2 is the connection point of the first transistor T1, the seventh transistor T7, the fourth transistor T4, the third transistor T3 and the first capacitor C1. The third node N3 is the connection point of the second transistor T2, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7.

[0111] In the present example, the first node N1 and the second node N2 are both output control nodes. The ninth transistor T9 is a first output transistor, and the tenth transistor T10 is a second output transistor.

[0112] In the embodiments of the present disclosure, the first power line VGH continuously provides a first power signal, and the second power line VGL continuously provides a second power signal. The effective level of the first power signal can be a high level, and the effective level of the second power signal can be a low level. The absolute value of the voltage of the effective level of the first power signal and the absolute value of the voltage of the effective level of the second power signal can be substantially the same. However, the present embodiments are not limited in this regard.

[0113] In the embodiments of the present disclosure, the first clock terminal CK can provide a first clock signal, and the second clock terminal CB can provide a second clock signal. The first clock signal and the second clock signal are both pulse signals. For example, the duty cycles of the first clock signal and the second clock signal can be substantially the same, and the first clock signal and the second clock signal are not low at the same time. The duty cycle refers to the proportion of the high level time in a pulse period (including the high level time and the low level time).

[0114] In some example embodiments, the first transistor T1 to the ninth transistor T9 can be first semiconductor type transistors. The tenth transistor T10 can be a second semiconductor type transistor. The transistor types of the first semiconductor type transistors and the second semiconductor type transistor are opposite. For example, the first transistor T1 to the ninth transistor T9 can be P-type transistors, and the tenth transistor T10 can be an N-type transistor. In some examples, the P-type transistor can be a low temperature poly-silicon (LTPS) thin film transistor, and the N-type transistor can be an oxide thin film transistor, such as an indium gallium zinc oxide (IGZO) thin film transistor. In addition, the present embodiments can select a thin film transistor of a bottom gate structure or a thin film transistor of a top gate structure, or can adopt a thin film transistor of a bottom gate plus top gate structure, as long as the switching function can be achieved. However, the present embodiments are not limited in this regard.

[0115] Reference will now be made to Figure 3 The working process of the first stage driving control circuit is taken as an example for illustration Figure 2The working process of the driving control circuit is shown. The signal input end INPUT of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit of the embodiment can include: 10 transistor units (i.e., the first transistor T1 to the tenth transistor T10), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 2 power supply ends (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH can continuously provide a high-level first power supply signal, and the second power supply line VGL can continuously provide a low-level second power supply signal.

[0116] As shown in Figure 3 the working process of the driving control circuit of the present example can include the following stages.

[0117] In the first stage S11, the first clock end CK provides a low-level signal, the second clock end CB provides a high-level signal, and the signal input end INPUT provides a low-level signal.

[0118] The first clock end CK provides a low-level signal, and the first transistor T1 and the second transistor T2 are turned on. The low-level signal provided by the signal input end INPUT is transmitted to the third node N3 via the turned-on second transistor T2, and then transmitted to the first node N1 via the turned-on sixth transistor T6, so that the third node N3 and the first node N1 are at a low potential. The seventh transistor T7 and the eighth transistor T8 are turned on. The high-level signal provided by the second clock end CB is transmitted to the first output end OUT1 via the turned-on eighth transistor T8. The low-level second power supply signal provided by the second power supply line VGL is transmitted to the second node N2 via the turned-on first transistor T1, and the low-level signal provided by the first clock end CK is transmitted to the second node N2 via the turned-on seventh transistor T7, so that the second node N2 is at a low potential. The fourth transistor T4 and the third transistor T3 are turned on. The second clock end CB provides a high-level signal, and the fifth transistor T5 is cut off. The high-level first power supply signal provided by the first power supply line VGH is transmitted to the first output end OUT1 via the turned-on third transistor T3. The first output end OUT1 outputs a high-level signal. The ninth transistor T9 is cut off, the tenth transistor T10 is turned on, and the low-level second power supply signal provided by the second power supply line VGL is transmitted to the second output end OUT2 via the turned-on tenth transistor T10. The second output end OUT2 outputs a low-level signal.

[0119] In the second stage S12, the first clock end CK provides a high-level signal, the second clock end CB provides a low-level signal, and the signal input end INPUT provides a high-level signal.

[0120] The first clock end CK provides a high level signal, the first transistor T1 and the second transistor T2 are turned off. The sixth transistor T6 is turned on. The third node N3 and the first node N1 keep low potential. The seventh transistor T7 and the eighth transistor T8 are turned on. The high level signal provided by the first clock end CK is transmitted to the second node N2 through the turned-on seventh transistor T7, so that the second node N2 is at high potential. The fourth transistor T4 and the third transistor T3 are turned off. The second clock end CB provides a low level signal, and the fifth transistor T5 is turned on. The low level signal provided by the second clock end CB is transmitted to the first output end OUT1 through the turned-on eighth transistor T8. The first output end OUT1 outputs a low level signal. The ninth transistor T9 is turned on, the tenth transistor T10 is turned off, and the high level first power signal provided by the first power supply line VGH is transmitted to the second output end OUT2 through the turned-on ninth transistor T9. The second output end OUT2 outputs a high level signal.

[0121] In the third stage S13, the first clock end CK provides a low level signal, the second clock end CB provides a high level signal, and the signal input end INPUT provides a high level signal.

[0122] The first clock end CK provides a low level signal, and the first transistor T1 and the second transistor T2 are turned on. The high level signal provided by the signal input end INPUT is transmitted to the third node N3 through the turned-on second transistor T2, and then transmitted to the first node N1 through the turned-on sixth transistor T6, so that the third node N3 and the first node N1 are at high potential. The seventh transistor T7 and the eighth transistor T8 are turned off. The low level second power signal provided by the second power supply line VGL is transmitted to the second node N2 through the turned-on first transistor T1, so that the second node N2 is at low potential. The fourth transistor T4 and the third transistor T3 are turned on. The second clock end CB provides a high level signal, and the fifth transistor T5 is turned off. The high level first power signal provided by the first power supply line VGH is transmitted to the first output end OUT1 through the turned-on third transistor T3. The first output end OUT1 outputs a high level signal. The ninth transistor T9 is turned off, the tenth transistor T10 is turned on, and the low level second power signal provided by the second power supply line VGL is transmitted to the second output end OUT2 through the turned-on tenth transistor T10. The second output end OUT2 outputs a low level signal.

[0123] In the fourth stage S14, the first clock end CK provides a high level signal, the second clock end CB provides a low level signal, and the signal input end INPUT provides a high level signal.

[0124] The first clock terminal CK provides a high level signal, the first transistor T1 and the second transistor T2 are turned off. The sixth transistor T6 is turned on. The third node N3 and the first node N1 keep high potential. The seventh transistor T7 and the eighth transistor T8 are turned off. The second node N2 keeps low potential, the third transistor T3 and the fourth transistor T4 are turned on. The second clock terminal CB provides a low level signal, the fifth transistor T5 is turned on. The high level first power signal provided by the first power supply line VGH is transmitted to the third node N3 via the turned-on fourth transistor T4 and the fifth transistor T5, so that the third node N3 keeps at high potential. The high level first power signal provided by the first power supply line VGH is transmitted to the first output terminal OUT1 via the turned-on third transistor T3. The first output terminal OUT1 outputs a high level signal. The ninth transistor T9 is turned off, the tenth transistor T10 is turned on, and the low level second power signal provided by the second power supply line VGL is transmitted to the second output terminal OUT2 via the turned-on tenth transistor T10. The second output terminal OUT2 outputs a low level signal.

[0125] After the fourth stage S14, the third stage S13 and the fourth stage S14 can be repeated until the signal input terminal INPUT inputs a low level signal, and then the first stage S11 is started again.

[0126] According to the working process of the driving control circuit, in the second stage S12, the first output terminal OUT1 outputs a low level signal, and the second output terminal OUT2 outputs a high level signal; in the remaining stages, the first output terminal OUT1 outputs a high level signal, and the second output terminal OUT2 outputs a low level signal. The phase of the first output signal output by the first output terminal OUT1 is opposite to the phase of the second output signal output by the second output terminal OUT2. The effective level of the first output signal can be low level, and the effective level of the second output signal can be high level. In a frame, the time length of the effective level of the first output signal can be substantially the same as the time length of the effective level of the second output signal. The absolute value of the voltage of the effective level of the first output signal and the absolute value of the voltage of the effective level of the second output signal are substantially the same.

[0127] In the present exemplary embodiment, the second output circuit 12 includes an inverting sub-circuit. The inverting sub-circuit includes the ninth transistor T9 and the tenth transistor T10. The effective level (i.e. high level) of the first power signal is opposite to the effective level (i.e. low level) for turning on the ninth transistor T9, and the effective level (i.e. low level) of the second power signal is opposite to the effective level (i.e. high level) for turning on the tenth transistor T10. The inverting sub-circuit can perform inverting processing on the first output signal output by the first output terminal OUT1 to obtain the second output signal.

[0128] In some exemplary embodiments, the first output signal provided by the first output terminal OUT1 can be configured to turn on the P-type transistor in the pixel circuit, and the second output signal provided by the second output terminal OUT2 can be configured to turn on the N-type transistor in the pixel circuit. For example, the first output signal can be provided as a scan signal to the P-type transistor in the pixel circuit, and the second output signal can be provided as a scan signal to the N-type transistor in the pixel circuit. In some examples, the first output signal provided by the first output terminal of the current stage drive control circuit can be transmitted to the signal input terminal of the next stage drive control circuit as an input signal for the next stage drive control circuit. However, this embodiment is not limited in this respect.

[0129] Figure 4 This is another equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. Figure 5 for Figure 4 The provided timing diagram for the drive control circuit.

[0130] In some exemplary implementations, such as Figure 4 As shown, the drive control circuit of this exemplary embodiment includes an input circuit 10, a first output circuit 11, and a second output circuit 12. The input circuit 10 is electrically connected to a signal input terminal INPUT, a first control terminal NX, a first clock terminal CK, a second clock terminal CB, a first power line VGH, a second power line VGL, a fourth node N4, and a fifth node N5, and is configured to control the potentials of the fourth node N4 and the fifth node N5 under the control of the signal input terminal INPUT, the first control terminal NX, the first clock terminal CK, and the second clock terminal CB. The first output circuit 11 is electrically connected to the first power line VGH, the second power line VGL, the fourth node N4, the fifth node N5, and the first output terminal OUT1, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the fourth node N4 and the fifth node N5. The second output circuit 12 is electrically connected to the first power line VGH, the second power line VGL, the first output terminal OUT1, and the second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the first output terminal OUT1.

[0131] In some exemplary implementations, such as Figure 4As shown, the input circuit 10 can include a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, a thirty-fourth transistor T34, a thirty-fifth transistor T35, a thirty-sixth transistor T36, a thirty-seventh transistor T37, a thirty-eighth transistor T38, a forty-first transistor T41, a forty-second transistor T42, a forty-third transistor T43, a fourth capacitor C4, and a fifth capacitor C5. The first output circuit 11 can include a thirty-ninth transistor T39, a fortieth transistor T40, and a third capacitor C3. The second output circuit 12 can include a forty-fourth transistor T44 and a forty-fifth transistor T45.

[0132] In some example embodiments, as Figure 4As shown, the control electrode of the thirty-first transistor T31 is electrically connected with the first clock end CK, the first electrode of the thirty-first transistor T31 is electrically connected with the signal input end INPUT, and the second electrode of the thirty-first transistor T31 is electrically connected with the seventh node N7. The control electrode of the thirty-second transistor T32 is electrically connected with the seventh node N7, the first electrode of the thirty-second transistor T32 is electrically connected with the first clock end CK, and the second electrode of the thirty-second transistor T32 is electrically connected with the sixth node N6. The control electrode of the thirty-third transistor T33 is electrically connected with the first clock end CK, the first electrode of the thirty-third transistor T33 is electrically connected with the second power supply line VGL, and the second electrode of the thirty-third transistor T33 is electrically connected with the sixth node N6. The control electrode of the thirty-fourth transistor T34 is electrically connected with the fifth node N5, the first electrode of the thirty-fourth transistor T34 is electrically connected with the second clock end CB, and the second electrode of the thirty-fourth transistor T34 is electrically connected with the second electrode of the thirty-fifth transistor T35. The control electrode of the thirty-fifth transistor T35 is electrically connected with the sixth node N6, and the first electrode of the thirty-fifth transistor T35 is electrically connected with the first power supply line VGH. The control electrode of the thirty-sixth transistor T36 is electrically connected with the eighth node N8, the first electrode of the thirty-sixth transistor T36 is electrically connected with the second clock end CB, and the second electrode of the thirty-sixth transistor T36 is electrically connected with the first electrode of the thirty-seventh transistor T37. The control electrode of the thirty-seventh transistor T37 is electrically connected with the second clock end CB, and the second electrode of the thirty-seventh transistor T37 is electrically connected with the fourth node N4. The control electrode of the thirty-eighth transistor T38 is electrically connected with the seventh node N7, the first electrode of the thirty-eighth transistor T38 is electrically connected with the first power supply line VGH, and the second electrode of the thirty-eighth transistor T38 is electrically connected with the fourth node N4. The control electrode of the thirty-ninth transistor T39 is electrically connected with the fourth node N4, the first electrode of the thirty-ninth transistor T39 is electrically connected with the first power supply line VGH, and the second electrode of the thirty-ninth transistor T39 is electrically connected with the first output end OUT1. The control electrode of the fortieth transistor T40 is electrically connected with the fifth node N5, the first electrode of the fortieth transistor T40 is electrically connected with the second power supply line VGL, and the second electrode of the fortieth transistor T40 is electrically connected with the first output end OUT1. The control electrode of the forty-first transistor T41 is electrically connected with the second power supply line VGL, the first electrode of the forty-first transistor T41 is electrically connected with the sixth node N6, and the second electrode of the forty-first transistor T41 is electrically connected with the eighth node N8. The control electrode of the forty-second transistor T42 is electrically connected with the second power supply line VGL, the first electrode of the forty-second transistor T42 is electrically connected with the seventh node N7, and the second electrode of the forty-second transistor T42 is electrically connected with the fifth node N5. The control electrode of the forty-third transistor T43 is electrically connected with the first control end NX, the first electrode of the forty-third transistor T43 is electrically connected with the first power supply line VGH, and the second electrode of the forty-third transistor T43 is electrically connected with the seventh node N7.A control electrode of the forty-fourth transistor T44 is electrically connected with the first output terminal OUT1, a first electrode of the forty-fourth transistor T44 is electrically connected with the first power supply line VGH, and a second electrode of the forty-fourth transistor T44 is electrically connected with the second output terminal OUT2. A control electrode of the forty-fifth transistor T45 is electrically connected with the first output terminal OUT1, a first electrode of the forty-fifth transistor T45 is electrically connected with the second power supply line VGL, and a second electrode of the forty-fifth transistor T45 is electrically connected with the second output terminal OUT2. A first plate of the third capacitor C3 is electrically connected with the fourth node N4, and a second plate of the third capacitor C3 is electrically connected with the first power supply line VGH. A first plate of the fourth capacitor C4 is electrically connected with the fifth node N5, and a second plate of the fourth capacitor C4 is electrically connected with the second electrode of the thirty-fifth transistor T35. A first plate of the fifth capacitor C5 is electrically connected with the eighth node N8, and a second plate of the fifth capacitor C5 is electrically connected with the first electrode of the thirty-seventh transistor T37.

[0133] In the present example, the fourth node N4 is a connection point of the thirty-seventh transistor T37, the thirty-eighth transistor T38, the thirty-ninth transistor T39 and the third capacitor C3. The fifth node N5 is a connection point of the thirty-fourth transistor T34, the fortieth transistor T40, the forty-second transistor T42 and the fourth capacitor C4. The sixth node N6 is a connection point of the thirty-second transistor T32, the thirty-third transistor T33, the thirty-fifth transistor T35 and the forty-first transistor T41. The seventh node N7 is a connection point of the thirty-first transistor T31, the thirty-second transistor T32, the forty-second transistor T42, the thirty-eighth transistor T38 and the forty-third transistor T43. The eighth node N8 is a connection point of the thirty-sixth transistor T36, the forty-first transistor T41 and the fifth capacitor C5.

[0134] In the present example, the fourth node N4 and the fifth node N5 are output control nodes. The forty-fourth transistor T44 is a first output transistor, and the forty-fifth transistor T45 is a second output transistor.

[0135] In some example embodiments, the thirty-first transistor T31 to the forty-fourth transistor T44 can be first semiconductor type transistors, for example, P-type transistors, and the forty-fifth transistor T45 can be a second semiconductor type transistor, for example, an N-type transistor. For example, the P-type transistors can be LTPS thin film transistors, and the N-type transistor can be an oxide thin film transistor, such as an IGZO thin film transistor. However, the present embodiments are not limited thereto.

[0136] Reference will now be made to Figure 5 with reference to the working process of the first stage driving control circuit as an example Figure 4The working process of the driving control circuit is shown. The signal input end INPUT of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit of the embodiment can include 15 transistor units (i.e., the thirty-first transistor T31 to the forty-fifth transistor T45), 3 capacitor units (i.e., the third capacitor C3 to the fifth capacitor C5), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 2 power supply ends (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH can continuously provide a high-level first power supply signal, and the second power supply line VGL can continuously provide a low-level second power supply signal.

[0137] In the present exemplary embodiment, during a normal display period, the first control end NX continuously provides a high-level signal, so that the forty-third transistor T43 is turned off and has no effect on the potential of the seventh node N7. During a non-normal display period (e.g., before displaying the first frame, or a blanking stage, etc.), the first control end NX can provide a low-level signal, so that the forty-third transistor T43 is turned on and transmits the high-level first power supply signal provided by the first power supply line VGH to the seventh node N7. In this way, the seventh node N7 and the fifth node N5 can be at a high potential, the forty-first transistor T40 is turned off, and the first output end OUT1 cannot output an effective low-level signal, thereby preventing the occurrence of screen flickering or mis-emission during the non-normal display period.

[0138] As shown in Figure 5 The normal display period of the driving control circuit of the present exemplary embodiment can include the following stages. In the first stage S21 to the seventh stage S27, the first control end NX provides a high-level signal, and the forty-third transistor T43 is turned off.

[0139] In the first stage S21, the first clock end CK provides a high-level signal, the second clock end CB provides a low-level signal, and the signal input end INPUT provides a low-level signal.

[0140] The first clock end CK provides a high level signal, the thirty-first transistor T31 and the thirty-third transistor T33 are turned off, the forty-second transistor T42 is turned on, the seventh node N7 and the fifth node N5 keep the low level of the last stage, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned on. The high level signal provided by the first clock end CK is transmitted to the sixth node N6 through the turned-on thirty-second transistor T32, the forty-first transistor T41 is turned on, the sixth node N6 and the eighth node N8 are at high level, the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned off. The low level signal provided by the second clock end CB is transmitted to the second plate of the fourth capacitor C4 through the turned-on thirty-fourth transistor T34, and the first plate (i.e. the fifth node N5) of the fourth capacitor C4 keeps a lower potential due to the capacitor retention effect. The thirty-eighth transistor T38 is turned on, so that the potential of the fourth node N4 is pulled up to high level, and the thirty-ninth transistor T39 is turned off. The fortieth transistor T40 is turned on, so that the first output end OUT1 outputs the low level second power signal provided by the first power supply line VGL. The forty-fourth transistor T44 is turned on, the forty-fifth transistor T45 is turned off, and the second output end OUT2 outputs the high level first power signal provided by the first power supply line VGH.

[0141] In the second stage S22, the first clock end CK provides a low level signal, the second clock end CB provides a high level signal, and the signal input end INPUT provides a high level signal.

[0142] The first clock end CK provides a low level signal, and the thirty-first transistor T31 and the thirty-third transistor T33 are turned on. The turned-on thirty-first transistor T31 transmits the high level signal provided by the signal input end INPUT to the seventh node N7, and the forty-second transistor T42 is turned on, so that the potential of the seventh node N7 and the fifth node N5 is pulled up. The thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The turned-on thirty-third transistor T33 transmits the low level second power supply signal provided by the second power supply line VGL to the sixth node N6, and the forty-first transistor T41 is turned on, so that the sixth node N6 and the eighth node N8 are at low potential, and the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The high level first power supply signal provided by the first power supply line VGH is transmitted to the second plate of the fourth capacitor C4 through the turned-on thirty-fifth transistor T35, and the first plate (i.e. the fifth node N5) of the fourth capacitor C4 keeps stable high level under the jumping action of the fourth capacitor C4. The second clock end CB inputs a high level signal, the thirty-seventh transistor T37 is turned off, the fourth node N4 keeps the high potential provided by the first power supply line VGH under the storage action of the third capacitor C3, and the thirty-ninth transistor T39 is turned off. Since the thirty-ninth transistor T39 and the fortieth transistor T40 are both turned off, the first output end OUT1 keeps the previous low level output. The forty-fourth transistor T44 is turned on, the forty-fifth transistor T45 is turned off, and the second output end OUT2 outputs the high level first power supply signal provided by the first power supply line VGH.

[0143] In the third stage S23, the first clock end CK inputs a high level signal, the second clock end CB inputs a low level signal, and the signal input end INPUT inputs a high level signal.

[0144] The first clock end CK inputs a high level signal, the thirty-first transistor T31 and the thirty-third transistor T33 are turned off, the forty-second transistor T42 is turned on, and the seventh node N7 and the fifth node N5 keep the high level of the previous stage. The thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The forty-first transistor T41 is turned on, the sixth node N6 and the eighth node N8 keep low level, and the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The first power supply line VGH provides a high level first power supply signal which is transmitted to the second plate of the fourth capacitor C4 through the turned-on thirty-fifth transistor T35, so that the fifth node N5 keeps stable high level. The second clock end CB inputs a low level signal, the thirty-seventh transistor T37 is turned on, the low level signal provided by the second clock end CB is transmitted to the fourth node N4 through the turned-on thirty-sixth transistor T36 and the thirty-seventh transistor T37, the thirty-ninth transistor T39 is turned on, and the first output end OUT1 outputs the high level first power supply signal provided by the first power supply line VGH. The forty-fourth transistor T44 is turned off, the forty-fifth transistor T45 is turned on, and the second output end OUT2 outputs the low level second power supply signal provided by the second power supply line VGL.

[0145] In the fourth stage S24, the first clock end CK inputs a low level signal, the second clock end CB inputs a high level signal, and the signal input end INPUT inputs a high level signal.

[0146] The first clock end CK inputs a low level signal, and the thirty-first transistor T31 and the thirty-third transistor T33 are turned on. The thirty-first transistor T31 transmits the high level signal input by the signal input end INPUT to the seventh node N7, the forty-second transistor T42 is turned on, and the seventh node N7 and the fifth node N5 are at high level. The thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The thirty-third transistor T33 transmits the low level signal provided by the second power supply line to the sixth node N6, the forty-first transistor T41 is turned on, the sixth node N6 and the eighth node N8 are at low level, and the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The second clock end CB inputs a high level signal, the thirty-seventh transistor T37 is turned off, the fourth node N4 keeps the low level of the previous stage under the storage action of the third capacitor C3, the thirty-ninth transistor T39 is turned on, and the first output end OUT1 outputs the high level first power supply signal provided by the first power supply line VGH. The forty-fourth transistor T44 is turned off, the forty-fifth transistor T45 is turned on, and the second output end OUT2 outputs the low level second power supply signal provided by the second power supply line VGL.

[0147] In the fifth stage S25, the first clock end CK inputs a high level signal, the second clock end CB inputs a low level signal, and the signal input end INPUT inputs a low level signal.

[0148] The first clock end CK inputs a high level signal, the thirty-first transistor T31 and the thirty-third transistor T33 are turned off, the forty-second transistor T42 is turned on, and the seventh node N7 and the fifth node N5 keep the high level of the previous stage. The thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The forty-first transistor T41 is turned on, the sixth node N6 and the eighth node N8 keep the low level, and the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The second clock end CB inputs a low level signal, and the thirty-seventh transistor T37 is turned on. The turned-on thirty-sixth transistor T36 and the thirty-seventh transistor T37 transmit the low level signal provided by the second clock end CB to the fourth node N4, the thirty-ninth transistor T39 is turned on, and the first output end OUT1 outputs the high level first power signal provided by the first power supply line VGH. The forty-fourth transistor T44 is turned off, the forty-fifth transistor T45 is turned on, and the second output end OUT2 outputs the low level second power signal provided by the second power supply line VGL.

[0149] In the sixth stage S26, the first clock end CK inputs a low level signal, the second clock end CB inputs a high level signal, and the signal input end INPUT inputs a low level signal.

[0150] The first clock end CK inputs a low level signal, and the thirty-first transistor T31 and the thirty-third transistor T33 are turned on. The forty-second transistor T42 is turned on, and the potential of the seventh node N7 and the fifth node N5 is pulled low. The thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned on. The turned-on thirty-eighth transistor T38 transmits the high level signal provided by the first power supply line VGH to the fourth node N4, and the thirty-ninth transistor T39 is turned off. The turned-on fortieth transistor T40 transmits the low level signal provided by the second power supply line VGL to the first output end OUT1. The turned-on thirty-second transistor T32 transmits the low level signal provided by the first clock end CK to the sixth node N6, and the forty-first transistor T41 is turned on. The sixth node N6 and the eighth node N8 are at the low level, and the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The second clock end CB inputs a high level signal, and the thirty-seventh transistor T37 is turned off. The forty-fourth transistor T44 is turned on, the forty-fifth transistor T45 is turned off, and the second output end OUT2 outputs the high level signal provided by the first power supply line VGH.

[0151] In the seventh stage S27, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a low level signal.

[0152] The first clock terminal CK inputs a high level signal, and the thirty-first transistor T31 and the thirty-third transistor T33 are turned off. The forty-second transistor T42 is turned on, and the seventh node N7 and the fifth node N5 keep the low level of the previous stage. The thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned on. The turned-on thirty-second transistor T32 transmits the high level signal provided by the first clock terminal CK to the sixth node N6, the forty-first transistor T41 is turned on, and the potential of the sixth node N6 and the eighth node N8 is pulled high. The thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned off. The turned-on thirty-eighth transistor T38 transmits the high level signal provided by the first power supply line VGH to the fourth node N4, and the thirty-ninth transistor T39 is turned off. The fortieth transistor T40 is turned on, and outputs the low level signal provided by the second power supply line VGL to the first output terminal OUT1. The forty-fourth transistor T44 is turned on, the forty-fifth transistor T45 is turned off, and the second output terminal OUT2 outputs the high level signal provided by the first power supply line VGH.

[0153] After the seventh stage S27, the sixth stage S26 and the seventh stage t27 can be repeated until the signal input terminal INPUT inputs a high level signal, and then restart from the second stage S22.

[0154] According to the working process of the above-mentioned driving control circuit, in the third stage S23 to the fifth stage S25, the first output terminal OUT1 can output a high level signal, and the second output terminal OUT2 outputs a low level signal. In the remaining stages, the first output terminal OUT1 outputs a low level signal, and the second output terminal OUT2 outputs a high level signal. The phase of the first output signal provided by the first output terminal OUT1 and the phase of the second output signal provided by the second output terminal OUT2 are opposite. The effective level of the first output signal is low, and the effective level of the second output signal is high. In a frame, the duration of the effective level of the first output signal and the duration of the effective level of the second output signal can be substantially the same. The absolute value of the voltage of the effective level of the first output signal and the absolute value of the voltage of the effective level of the second output signal can be substantially the same.

[0155] In the present exemplary embodiment, the second output circuit 12 can include an inverting sub-circuit including the forty-fourth transistor T44 and the forty-fifth transistor T45. The active level (i.e., high level) of the first power supply signal is opposite to the active level (i.e., low level) for turning on the forty-fourth transistor T44, and the active level (i.e., low level) of the second power supply signal is opposite to the active level (i.e., high level) for turning on the forty-fifth transistor T45. The inverting sub-circuit can invert the first output signal output by the first output terminal OUT1 to obtain the second output signal.

[0156] In some exemplary embodiments, the first output signal provided by the first output terminal OUT1 can be configured to turn on the N-type transistor in the pixel circuit, and the second output signal provided by the second output terminal OUT2 can be configured to turn on the P-type transistor in the pixel circuit. In some examples, the first output signal and the second output signal can be transmitted to the pixel circuit as the light emitting control signal through the light emitting control line, or can be transmitted to the pixel circuit as the scanning signal through the scanning line. In some examples, the first output signal provided by the first output terminal of the present stage of the driving control circuit can be transmitted to the signal input terminal of the next stage of the driving control circuit as the input signal of the next stage of the driving control circuit. However, the present embodiment is not limited thereto.

[0157] In some other exemplary embodiments, the forty-first transistor T41 and the forty-second transistor T42 in the driving control circuit 10 can be omitted, i.e., the fifth node N5 and the seventh node N7 are directly electrically connected, and the eighth node N8 and the sixth node N6 are directly electrically connected. However, the present embodiment is not limited thereto. Figure 4

[0158] Figure 6 Another equivalent circuit diagram of the driving control circuit for at least one embodiment of the present disclosure. Figure 7 Another equivalent circuit diagram of the driving control circuit for at least one embodiment of the present disclosure. Figure 6 A timing diagram of the driving control circuit.

[0159] In some exemplary embodiments, as described above, the first output signal provided by the first output terminal OUT1 can be configured to turn on the N-type transistor in the pixel circuit, and the second output signal provided by the second output terminal OUT2 can be configured to turn on the P-type transistor in the pixel circuit. In some examples, the first output signal and the second output signal can be transmitted to the pixel circuit as the light emitting control signal through the light emitting control line, or can be transmitted to the pixel circuit as the scanning signal through the scanning line. In some examples, the first output signal provided by the first output terminal of the present stage of the driving control circuit can be transmitted to the signal input terminal of the next stage of the driving control circuit as the input signal of the next stage of the driving control circuit. However, the present embodiment is not limited thereto. Figure 6 ​As shown, the driving control circuit of the present exemplary embodiment includes an input circuit 10, a first output circuit 11, and a second output circuit 12. The input circuit 10 is electrically connected with a signal input terminal INPUT, a first clock terminal CK, a second clock terminal CB, a first power supply line VGH, a second power supply line VGL, a ninth node N9, and a tenth node N10, and is configured to control the potentials of the ninth node N9 and the tenth node N10 under the control of the signal input terminal INPUT, the first clock terminal CK, and the second clock terminal CB. The first output circuit 11 is electrically connected with the first power supply line VGH, the second power supply line VGL, the ninth node N9, the tenth node N10, and a first output terminal OUT1, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the ninth node N9 and the tenth node N10. The second output circuit 12 is electrically connected with the first power supply line VGH, the second power supply line VGL, the first output terminal OUT1, and a second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the first output terminal OUT1.

[0160] As shown, the input circuit 10 can include a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, a fifty-fourth transistor T54, a fifty-fifth transistor T55, a fifty-sixth transistor T56, a fifty-seventh transistor T57, a fifty-eighth transistor T58, a sixty-first transistor T61, a sixty-second transistor T62, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. The first output circuit 11 can include a fifty-ninth transistor T59 and a sixtieth transistor T60. The second output circuit 12 can include a sixty-third transistor T63 and a sixty-fourth transistor T64. Figure 6

[0161] As shown, the input circuit 10 can include a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53, a fifty-fourth transistor T54, a fifty-fifth transistor T55, a fifty-sixth transistor T56, a fifty-seventh transistor T57, a fifty-eighth transistor T58, a sixty-first transistor T61, a sixty-second transistor T62, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. The first output circuit 11 can include a fifty-ninth transistor T59 and a sixtieth transistor T60. The second output circuit 12 can include a sixty-third transistor T63 and a sixty-fourth transistor T64. Figure 6 ​As shown, the control electrode of the fifty-first transistor T51 is electrically connected with the first clock end CK, the first electrode of the fifty-first transistor T51 is electrically connected with the signal input end INPUT, and the second electrode of the fifty-first transistor T51 is electrically connected with the eleventh node N11. The control electrode of the fifty-second transistor T52 is electrically connected with the eleventh node N11, the first electrode of the fifty-second transistor T52 is electrically connected with the first clock end CK, and the second electrode of the fifty-second transistor T52 is electrically connected with the twelfth node N12. The control electrode of the fifty-third transistor T53 is electrically connected with the first clock end CK, the first electrode of the fifty-third transistor T53 is electrically connected with the second power supply line VGL, and the second electrode of the fifty-third transistor T53 is electrically connected with the twelfth node N12. The control electrode of the fifty-fourth transistor T54 is electrically connected with the second clock end CB, the first electrode of the fifty-fourth transistor T54 is electrically connected with the second electrode of the fifty-fifth transistor T55, and the second electrode of the fifty-fourth transistor T54 is electrically connected with the eleventh node N11. The control electrode of the fifty-fifth transistor T55 is electrically connected with the twelfth node N12, and the first electrode of the fifty-fifth transistor T55 is electrically connected with the first power supply line VGH. The control electrode of the fifty-sixth transistor T56 is electrically connected with the thirteenth node N13, the first electrode of the fifty-sixth transistor T56 is electrically connected with the second clock end CB, and the second electrode of the fifty-sixth transistor T56 is electrically connected with the first electrode of the fifty-seventh transistor T57. The control electrode of the fifty-seventh transistor T57 is electrically connected with the second clock end CB, and the second electrode of the fifty-seventh transistor T57 is electrically connected with the tenth node N10. The control electrode of the fifty-eighth transistor T58 is electrically connected with the eleventh node N11, the first electrode of the fifty-eighth transistor T58 is electrically connected with the first power supply line VGH, and the second electrode of the fifty-eighth transistor T58 is electrically connected with the tenth node N10. The control electrode of the fifty-ninth transistor T59 is electrically connected with the tenth node N10, the first electrode of the fifty-ninth transistor T59 is electrically connected with the first power supply line VGH, and the second electrode of the fifty-ninth transistor T59 is electrically connected with the first output end OUT1. The control electrode of the sixtieth transistor T60 is electrically connected with the ninth node N9, the first electrode of the sixtieth transistor T60 is electrically connected with the second power supply line VGL, and the second electrode of the sixtieth transistor T60 is electrically connected with the first output end OUT1. The control electrode of the sixty-first transistor T61 is electrically connected with the second power supply line VGL, the first electrode of the sixty-first transistor T61 is electrically connected with the twelfth node N12, and the second electrode of the sixty-first transistor T61 is electrically connected with the thirteenth node N13. The control electrode of the sixty-second transistor T62 is electrically connected with the second power supply line VGL, the first electrode of the sixty-second transistor T62 is electrically connected with the eleventh node N11, and the second electrode of the sixty-second transistor T62 is electrically connected with the ninth node N9.A control electrode of the sixty-third transistor T63 is electrically connected with the first output terminal OUT1, a first electrode of the sixty-third transistor T63 is electrically connected with the first power supply line VGH, and a second electrode of the sixty-third transistor T63 is electrically connected with the second output terminal OUT2. A control electrode of the sixty-fourth transistor T64 is electrically connected with the first output terminal OUT1, a first electrode of the sixty-fourth transistor T64 is electrically connected with the second power supply line VGL, and a second electrode of the sixty-fourth transistor T64 is electrically connected with the second output terminal OUT2. A first electrode plate of the sixth capacitor C6 is electrically connected with the tenth node N10, and a second electrode plate of the sixth capacitor C6 is electrically connected with the first power supply line VGH. A first electrode plate of the seventh capacitor C7 is electrically connected with the second clock terminal CB, and a second electrode plate of the seventh capacitor C7 is electrically connected with the ninth node N9. A first electrode plate of the eighth capacitor C8 is electrically connected with the thirteenth node N13, and a second electrode plate of the eighth capacitor C8 is electrically connected with the first electrode of the fifty-seventh transistor T57.

[0162] In the present example, the ninth node N9 is a connection point of the sixty-second transistor T62, the sixtieth transistor T60 and the seventh capacitor C7. The tenth node N10 is a connection point of the fifty-seventh transistor T57, the fifty-eighth transistor T58, the fifty-ninth transistor T59 and the sixth capacitor C6. The eleventh node N11 is a connection point of the fifty-first transistor T51, the fifty-second transistor T52, the fifty-fourth transistor T54, the fifty-eighth transistor T58 and the sixty-second transistor T62. The twelfth node N12 is a connection point of the fifty-second transistor T52, the fifty-third transistor T53, the fifty-fifth transistor T55 and the sixty-first transistor T61. The thirteenth node N13 is a connection point of the fifty-sixth transistor T56, the sixty-first transistor T61 and the eighth capacitor C8.

[0163] In the present example, the ninth node N9 and the tenth node N10 are output control nodes. The sixty-third transistor T63 is a first output transistor, and the sixty-fourth transistor T64 is a second output transistor.

[0164] In some example embodiments, the fifty-first transistor T51 to the sixty-third transistor T63 can be first semiconductor type transistors, for example, can be P-type transistors; and the sixty-fourth transistor T64 can be a second semiconductor type transistor, for example, can be an N-type transistor. For example, the P-type transistor can be an LTPS thin film transistor, and the N-type transistor can be an oxide thin film transistor, such as an IGZO thin film transistor. However, the present embodiments are not limited thereto.

[0165] Reference will now be made to Figure 7 The working process of the first stage driving control circuit will be described by way of example Figure 6The working process of the driving control circuit is shown. The signal input end INPUT of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit of the embodiment includes 14 transistor units (i.e., the fifty-first transistor T51 to the sixty-fourth transistor T64), 3 capacitor units (i.e., the sixth capacitor C6 to the eighth capacitor C8), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 2 power supply ends (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH can continuously provide a high-level first power supply signal, and the second power supply line VGL can continuously provide a low-level second power supply signal.

[0166] As shown in Figure 7 The working process of the driving control circuit of the embodiment can include the following stages.

[0167] In the first stage S31, the signal input end INPUT provides a high-level signal, the first clock end CK provides a low-level signal, and the second clock end CB provides a high-level signal.

[0168] The first clock end CK provides a low-level signal, the fifty-first transistor T51 and the fifty-fifth transistor T53 are turned on, the sixty-second transistor T62 is turned on, the eleventh node N11 and the ninth node N9 are at a high potential, and the fifty-second transistor T52, the fifty-eighth transistor T58, and the sixtieth transistor T60 are turned off. The low-level signal provided by the second power supply line VGL is transmitted to the twelfth node N12 via the turned-on fifty-third transistor T53, and the sixty-first transistor T61 is turned on, the twelfth node N12 and the thirteenth node N13 are at a low potential, and the fifty-fifth transistor T55 and the fifty-sixth transistor T56 are turned on. The second clock end CB provides a high-level signal, and the fifty-fourth transistor T54 and the fifty-seventh transistor T57 are turned off. The tenth node N10 keeps the high level of the previous stage, and the fifty-ninth transistor T59 is turned off. Since the fifty-ninth transistor T59 and the sixtieth transistor T60 are both turned off, the first output end OUT1 keeps the low-level signal output before. The sixty-third transistor T63 is turned on, the sixty-fourth transistor T64 is turned off, and the second output end OUT2 outputs the high-level signal provided by the first power supply line VGH.

[0169] In the second stage S32, the signal input end INPUT provides a high-level signal, the first clock end CK provides a high-level signal, and the second clock end CB provides a low-level signal.

[0170] The second clock end CB provides a low level signal, the fifty-fourth transistor T54 and the fifty-seventh transistor T57 are turned on. The first clock end CK provides a high level signal, the fifty-first transistor T51 and the fifty-third transistor T53 are turned off, the twelfth node N12 and the thirteenth node N13 keep the low potential of the previous stage under the storage effect of the eighth capacitor C8. The fifty-fifth transistor T55 and the fifty-sixth transistor T56 are turned on. The high level signal provided by the first power supply line VGH is transmitted to the eleventh node N11 through the turned-on fifty-fifth transistor T55 and the fifty-fourth transistor T54, so that the potential of the eleventh node N11 and the ninth node N9 is pulled up. The fifty-second transistor T52, the fifty-eighth transistor T58 and the sixtieth transistor T60 are turned off. The low level signal provided by the second clock end CB is transmitted to the tenth node N10 through the turned-on fifty-sixth transistor T56 and the fifty-seventh transistor T57, so that the tenth node N10 is at a low potential, the fifty-ninth transistor T59 is turned on, and the first output end OUT1 outputs a high level signal. The sixty-third transistor T63 is turned off, the sixty-fourth transistor T64 is turned on, and the second output end OUT2 outputs a low level signal.

[0171] In the third stage S33, the signal input end INPUT provides a high level signal, the first clock end CK provides a low level signal, and the second clock end CB provides a high level signal.

[0172] The first clock end CK provides a low level signal, the fifty-first transistor T51 and the fifty-third transistor T53 are turned on, the ninth node N9 and the eleventh node N11 are at a high potential, and the fifty-second transistor T52, the fifty-eighth transistor T58 and the sixtieth transistor T60 are turned off. The twelfth node N12 and the thirteenth node T13 are at a low potential, and the fifty-fifth transistor T55 and the fifty-sixth transistor T56 are turned on. The second clock end CB provides a high level signal, and the fifty-fourth transistor T54 and the fifty-seventh transistor T57 are turned off. The tenth node N10 keeps the low potential of the previous stage, the fifty-ninth transistor T59 is turned on, the first output end OUT1 outputs a high level signal, the sixty-third transistor T63 is turned off, the sixty-fourth transistor T64 is turned on, and the second output end OUT2 outputs a low level signal.

[0173] In the fourth stage S24, the signal input end INPUT provides a low level signal, the first clock end CK provides a high level signal, and the second clock end CB provides a low level signal.

[0174] The second clock end CB provides a low level signal, the fifty-fourth transistor T54 and the fifty-seventh transistor T57 are turned on. The first clock end CK provides a high level signal, the fifty-first transistor T51 and the fifty-third transistor T53 are turned off, the ninth node N9 and the eleventh node N11 keep the high potential of the last stage under the storage effect of the seventh capacitor C7, the fifty-second transistor T52, the fifty-eighth transistor T58 and the sixtieth transistor T60 are turned off. The twelfth node N12 and the thirteenth node N13 keep the low potential under the storage effect of the eighth capacitor C8, the fifty-fifth transistor T55 and the fifty-sixth transistor T56 are turned on. The low level signal provided by the second clock end CB is transmitted to the tenth node N10 through the turned-on fifty-sixth transistor T56 and the fifty-seventh transistor T57, so that the tenth node N10 is at the low potential, the fifty-ninth transistor T59 is turned on, and the first output end OUT1 outputs the high level signal. The sixty-third transistor T63 is turned off, the sixty-fourth transistor T64 is turned on, and the second output end OUT2 outputs the low level signal.

[0175] In the fifth stage S35, the signal input end INPUT provides a low level signal, the first clock end CK provides a low level signal, and the second clock end CB provides a high level signal.

[0176] The first clock end CK provides a low level signal, the fifty-first transistor T51 and the fifty-third transistor T53 are turned on, and the ninth node N9 and the eleventh node N11 are at the low potential. The fifty-second transistor T52, the fifty-eighth transistor T58 and the sixtieth transistor T60 are turned on. The twelfth node N12 and the thirteenth node N13 are at the low potential, and the fifty-fifth transistor T55 and the fifty-sixth transistor T56 are turned on. The second clock end CB provides a high level signal, and the fifty-fourth transistor T54 and the fifty-seventh transistor T57 are turned off. The tenth node N10 is at the high potential, and the fifty-ninth transistor T59 is turned off. The first output end OUT1 outputs the low level signal. The sixty-third transistor T63 is turned on, the sixty-fourth transistor T64 is turned off, and the second output end OUT2 outputs the high level signal.

[0177] In the sixth stage S36, the signal input end INPUT provides a low level signal, the first clock end CK provides a high level signal, and the second clock end CB provides a low level signal.

[0178] The first clock terminal CK provides a high level signal, the fifty-first transistor T51 and the fifty-third transistor T53 are turned off, the ninth node N9 and the eleventh node N11 keep low potential, the fifty-second transistor T52, the fifty-eighth transistor T58 and the sixtieth transistor T60 are turned on. The twelfth node N12 and the thirteenth node N13 are at high potential, the fifty-fifth transistor T55 and the fifty-sixth transistor T56 are turned off. The second clock terminal CB provides a low level signal, the fifty-fourth transistor T54 and the fifty-seventh transistor T57 are turned on. The tenth node N10 is at high potential, the fifty-ninth transistor T59 is turned off. The first output terminal OUT1 outputs a low level signal. The sixty-third transistor T63 is turned on, the sixty-fourth transistor T64 is turned off, and the second output terminal OUT2 outputs a high level signal.

[0179] After the sixth stage S36, the fifth stage S35 and the sixth stage S36 can be repeated until the signal input terminal INPUT inputs a high level signal, and then restart from the first stage S31.

[0180] According to the working process of the above driving control circuit, in the second stage S32 to the fourth stage S34, the first output terminal OUT1 can output a high level signal, and the second output terminal OUT2 outputs a low level signal; in the remaining stages, the first output terminal OUT1 outputs a low level signal, and the second output terminal OUT2 outputs a high level signal. The phase of the first output signal provided by the first output terminal OUT1 and the phase of the second output signal provided by the second output terminal OUT2 are opposite. The effective level of the first output signal is low level, and the effective level of the second output signal is high level. In a frame time, the effective level time of the first output signal and the effective level time of the second output signal can be substantially the same. The absolute value of the voltage of the effective level of the first output signal and the absolute value of the voltage of the effective level of the second output signal can be substantially the same.

[0181] In the present exemplary embodiment, the second output circuit 12 can include an inverting sub-circuit, which can include the sixty-third transistor T63 and the sixty-fourth transistor T64. The effective level (i.e. high level) of the first power supply signal is opposite in polarity to the effective level (i.e. low level) for turning on the sixty-third transistor T63, and the effective level (i.e. low level) of the second power supply signal is opposite in polarity to the effective level (i.e. high level) for turning on the sixty-fourth transistor T64. The inverting sub-circuit inverts the first output signal output by the first output terminal OUT1 to obtain the second output signal.

[0182] In some example embodiments, the first output signal provided by the first output terminal OUT1 can be configured to turn on the N-type transistor in the pixel circuit, and the second output signal provided by the second output terminal OUT2 can be configured to turn on the P-type transistor in the pixel circuit. In some examples, the first output signal and the second output signal can be transmitted to the pixel circuit as the light-emitting control signal through the light-emitting control line. In some examples, the first output signal provided by the first output terminal of the current stage of the driving control circuit can be transmitted to the signal input terminal of the next stage of the driving control circuit as the input signal of the next stage of the driving control circuit. However, the present embodiment is not limited thereto.

[0183] In some other example embodiments, Figure 6 The sixty-first transistor T61 and the sixty-second transistor T62 in the signal input terminal INPUT can be omitted, i.e., the eleventh node N11 and the ninth node N9 can be directly electrically connected, and the twelfth node N12 and the thirteenth node N13 can be directly electrically connected. However, the present embodiment is not limited thereto.

[0184] Figure 8 Another equivalent circuit diagram of the driving control circuit for at least one embodiment of the present disclosure. Figure 9 Another equivalent circuit diagram of the driving control circuit for at least one embodiment of the present disclosure. Figure 8 A working timing diagram of the driving control circuit provided.

[0185] In some example embodiments, as shown in Figure 8 The input circuit 10 is electrically connected with the signal input terminal INPUT, the first clock terminal CK, the second clock terminal CB, the first power line VGH, the second power line VGL, and the fourteenth node N14, and is configured to control the potential of the fourteenth node N14 under the control of the signal input terminal INPUT, the first clock terminal CK, and the second clock terminal CB. The first output circuit 11 is electrically connected with the fourteenth node N14, the first output terminal OUT1, the first power line VGH, and the second power line VGL, and is configured to control the first output terminal OUT1 to output the first output signal under the control of the fourteenth node N14. The second output circuit 12 is electrically connected with the signal input terminal INPUT, the first output terminal OUT1, and the second output terminal OUT2, and is configured to control the second output terminal OUT2 to output the second output signal under the control of the first output terminal OUT1 and the signal input terminal INPUT.

[0186] In some example embodiments, as shown in Figure 8 The input circuit 10 can include the seventy-first transistor T71 to the seventy-fourth transistor T74, the seventy-seventh transistor T77 to the eightieth transistor T80. The first output circuit 11 can include the seventy-fifth transistor T75 and the seventy-sixth transistor T76. The second output circuit 12 can include the eighty-first transistor T81 to the eighty-sixth transistor T86.

[0187] In some example embodiments, as Figure 8As shown, the control electrode of the seventy-first transistor T71 is electrically connected with the second clock terminal CB, the first electrode of the seventy-first transistor T71 is electrically connected with the first power supply line VGH, and the second electrode of the seventy-first transistor T71 is electrically connected with the first electrode of the seventy-second transistor T72. The control electrode of the seventy-second transistor T72 is electrically connected with the signal input terminal INPUT, and the second electrode of the seventy-second transistor T72 is electrically connected with the fourteenth node N14. The control electrode of the seventy-third transistor T73 is electrically connected with the signal input terminal INPUT, the first electrode of the seventy-third transistor T73 is electrically connected with the second electrode of the seventy-fourth transistor T74, and the second electrode of the seventy-third transistor T73 is electrically connected with the fourteenth node N14. The control electrode of the seventy-fourth transistor T74 is electrically connected with the first clock terminal CK, and the first electrode of the seventy-fourth transistor T74 is electrically connected with the second power supply line VGL. The control electrode of the seventy-fifth transistor T75 is electrically connected with the fourteenth node N14, the first electrode of the seventy-fifth transistor T75 is electrically connected with the first power supply line VGH, and the second electrode of the seventy-fifth transistor T75 is electrically connected with the first output terminal OUT1. The control electrode of the seventy-sixth transistor T76 is electrically connected with the fourteenth node N14, the first electrode of the seventy-sixth transistor T76 is electrically connected with the second power supply line VGL, and the second electrode of the seventy-sixth transistor T76 is electrically connected with the first output terminal OUT1. The control electrode of the seventy-seventh transistor T77 is electrically connected with the first clock terminal CK, the first electrode of the seventy-seventh transistor T77 is electrically connected with the first power supply line VGH, and the second electrode of the seventy-seventh transistor T77 is electrically connected with the first electrode of the seventy-eighth transistor T78. The control electrode of the seventy-eighth transistor T78 is electrically connected with the first output terminal OUT1, and the second electrode of the seventy-eighth transistor T78 is electrically connected with the fourteenth node N14. The control electrode of the seventy-ninth transistor T79 is electrically connected with the first output terminal OUT1, the first electrode of the seventy-ninth transistor T79 is electrically connected with the second electrode of the eightieth transistor T80, and the second electrode of the seventy-ninth transistor T79 is electrically connected with the fourteenth node N14. The control electrode of the eightieth transistor T80 is electrically connected with the second clock terminal CB, and the first electrode of the eightieth transistor T80 is electrically connected with the second power supply line VGL. The control electrode of the eighty-first transistor T81 is electrically connected with the first output terminal OUT1, the first electrode of the eighty-first transistor T81 is electrically connected with the first power supply line VGH, and the second electrode of the eighty-first transistor T81 is electrically connected with the fifteenth node N15. The control electrode of the eighty-second transistor T82 is electrically connected with the signal input terminal INPUT, the first electrode of the eighty-second transistor T82 is electrically connected with the first power supply line VGH, and the second electrode of the eighty-second transistor T82 is electrically connected with the fifteenth node N15. The control electrode of the eighty-third transistor T83 is electrically connected with the signal input terminal INPUT, the first electrode of the eighty-third transistor T83 is electrically connected with the second electrode of the eighty-fourth transistor T84, and the second electrode of the eighty-third transistor T83 is electrically connected with the fifteenth node N15.The control electrode of the eighty-fourth transistor T84 is electrically connected with the first output terminal OUT1, and the first electrode of the eighty-fourth transistor T84 is electrically connected with the second power supply line VGL. The control electrode of the eighty-fifth transistor T85 is electrically connected with the fifteenth node N15, the first electrode of the eighty-fifth transistor T85 is electrically connected with the first power supply line VGH, and the second electrode of the eighty-fifth transistor T85 is electrically connected with the second output terminal OUT2. The control electrode of the eighty-sixth transistor T86 is electrically connected with the fifteenth node N15, the first electrode of the eighty-sixth transistor T86 is electrically connected with the second power supply line VGL, and the second electrode of the eighty-sixth transistor T86 is electrically connected with the second output terminal OUT2.

[0188] In the present example, the fourteenth node N14 is the connection point of the seventy-second transistor T72, the seventy-third transistor T73, the seventy-fifth transistor T75, the seventy-sixth transistor T76, the seventy-eighth transistor T78 and the seventy-ninth transistor T79. The fifteenth node N15 is the connection point of the eighty-first transistor T81, the eighty-second transistor T82, the eighty-third transistor T83, the eighty-fifth transistor T85 and the eighty-sixth transistor T86.

[0189] In the present example, the fourteenth node N14 is an output control node. The first output circuit 11 can include one inverting sub-circuit, and the second output circuit 12 can include three inverting sub-circuits. However, the present embodiment is not limited thereto.

[0190] In some examples, the seventy-first transistor T71, the seventy-second transistor T72, the seventy-fifth transistor T75, the seventy-seventh transistor T77, the seventy-eighth transistor T78, the eighty-first transistor T81, the eighty-second transistor T82 and the eighty-fifth transistor T85 can be first semiconductor type transistors, for example, can be P-type transistors. The seventy-third transistor T73, the seventy-fourth transistor T74, the seventy-sixth transistor T76, the seventy-ninth transistor T79, the eightieth transistor T80, the eighty-third transistor T83, the eighty-fourth transistor T84 and the eighty-sixth transistor T86 can be second semiconductor type transistors, for example, can be N-type transistors. For example, the P-type transistors can be LTPS thin film transistors, and the N-type transistors can be oxide thin film transistors, such as IGZO thin film transistors. However, the present embodiment is not limited thereto.

[0191] Reference will now be made to the following Figure 9 Description Figure 8The working process of the driving control circuit is shown. The signal input end of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit of the embodiment includes 16 transistor units (i.e., the seventy-first transistor T71 to the eighty-sixth transistor T86), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 2 power supply ends (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH can continuously provide a high-level first power supply signal, and the second power supply line VGL can continuously provide a low-level second power supply signal.

[0192] As shown in Figure 9 The working process of the driving control circuit of the embodiment can include the following stages.

[0193] In the first stage S101, the signal input end INPUT provides a high-level signal, the first clock end CK provides a low-level signal, and the second clock end CB provides a high-level signal.

[0194] The seventy-first transistor T71, the seventy-second transistor T72, and the seventy-fourth transistor T74 are turned off, the seventy-third transistor T73 is turned on, the fourteenth node N14 maintains the high voltage of the previous stage, the seventy-sixth transistor T76 is turned on, and the seventy-fifth transistor T75 is turned off. The first output end OUT1 outputs a low-level signal. The seventy-seventh transistor T77, the seventy-eighth transistor T78, and the eightieth transistor T80 are turned on, the seventy-ninth transistor T79 is turned off, and the fourteenth node N14 is maintained at a high voltage. The eighty-first transistor T81 is turned on, the eighty-fourth transistor T84 is turned off, the eighty-second transistor T82 is turned off, the eighty-third transistor T83 is turned on, and the fifteenth node N15 is at a high voltage. The eighty-fifth transistor T85 is turned off, the eighty-sixth transistor T86 is turned on, and the second output end OUT2 outputs a low-level signal.

[0195] In the second stage S102, the signal input end INPUT provides a high-level signal, the first clock end CK provides a high-level signal, and the second clock end CB provides a low-level signal.

[0196] The seventy-second transistor T72 is turned on, the seventy-first transistor T71 is turned off, the seventy-third transistor T73 is turned off, the seventy-fourth transistor T74 is turned off, and the fourteenth node N14 keeps low. The seventy-fifth transistor T75 is turned on, the seventy-sixth transistor T76 is turned off, and the first output terminal OUT1 outputs high signal. The seventy-ninth transistor T79 is turned on, the eightieth transistor T80 is turned on, the seventy-eighth transistor T78 is turned off, the seventy-seventh transistor T77 is turned on, and the fourteenth node N14 keeps low. The eighty-first transistor T81 is turned off, the eighty-fourth transistor T84 is turned on, the eighty-second transistor T82 is turned on, the eighty-third transistor T83 is turned off, and the fifteenth node N15 keeps high. The eighty-fifth transistor T85 is turned off, the eighty-sixth transistor T86 is turned on, and the second output terminal OUT2 outputs low signal.

[0197] In the third stage S103, the signal input terminal INPUT provides low signal, the first clock terminal CK provides low signal, and the second clock terminal CB provides high signal.

[0198] The seventy-second transistor T72 is turned on, the seventy-first transistor T71 is turned off, the seventy-third transistor T73 is turned off, the seventy-fourth transistor T74 is turned off, and the fourteenth node N14 keeps low. The seventy-fifth transistor T75 is turned on, the seventy-sixth transistor T76 is turned off, and the first output terminal OUT1 outputs high signal. The seventy-ninth transistor T79 is turned on, the eightieth transistor T80 is turned on, the seventy-eighth transistor T78 is turned off, the seventy-seventh transistor T77 is turned on, and the fourteenth node N14 keeps low. The eighty-first transistor T81 is turned off, the eighty-fourth transistor T84 is turned on, the eighty-second transistor T82 is turned on, the eighty-third transistor T83 is turned off, and the fifteenth node N15 keeps high. The eighty-fifth transistor T85 is turned off, the eighty-sixth transistor T86 is turned on, and the second output terminal OUT2 outputs low signal.

[0199] In the fourth stage S104, the signal input terminal INPUT provides low signal, the first clock terminal CK provides high signal, and the second clock terminal CB provides low signal.

[0200] The seventy-second transistor T72 is turned on, the seventy-first transistor T71 is turned off, the seventy-third transistor T73 and the seventy-fourth transistor T74 are turned off, and the fourteenth node N14 maintains a high level. The seventy-fifth transistor T75 is turned off, the seventy-sixth transistor T76 is turned on, and the first output terminal OUT1 outputs a low level signal. The seventy-eighth transistor T78 is turned on, the seventy-ninth transistor T79 is turned off, the seventy-seventh transistor T77 is turned on, the eightieth transistor T80 is turned on, and the fourteenth node N14 maintains a high level. The eighty-first transistor T81 is turned on, the eighty-fourth transistor T84 is turned off, the eighty-second transistor T82 is turned on, the eighty-third transistor T83 is turned off, and the fifteenth node N15 maintains a high level. The eighty-fifth transistor T85 is turned off, the eighty-sixth transistor T86 is turned on, and the second output terminal OUT2 outputs a low level signal.

[0201] In the fifth stage S105, the signal input terminal INPUT provides a low level signal, the first clock terminal CK provides a low level signal, and the second clock terminal CB provides a high level signal.

[0202] The seventy-second transistor T72 is turned on, the seventy-first transistor T71 is turned off, the seventy-third transistor T73 and the seventy-fourth transistor T74 are turned off, and the fourteenth node N14 maintains a high level. The seventy-fifth transistor T75 is turned off, the seventy-sixth transistor T76 is turned on, and the first output terminal OUT1 outputs a low level signal. The seventy-eighth transistor T78 is turned on, the seventy-ninth transistor T79 is turned off, the seventy-seventh transistor T77 is turned on, the eightieth transistor T80 is turned on, and the fourteenth node N14 maintains a high level. The eighty-first transistor T81 is turned on, the eighty-fourth transistor T84 is turned off, the eighty-second transistor T82 is turned on, the eighty-third transistor T83 is turned off, and the fifteenth node N15 maintains a high level. The eighty-fifth transistor T85 is turned off, the eighty-sixth transistor T86 is turned on, and the second output terminal OUT2 outputs a low level signal.

[0203] According to the working process of the driving control circuit, the first output terminal OUT1 outputs a high level signal in the second stage S102 and the third stage S103, and outputs a low level signal in the other stages. The second output terminal OUT2 outputs a high level signal in the second stage S102, and outputs a low level signal in the other stages. In the example, the effective levels of the first output signal and the second output signal have the same polarity, for example, the effective levels of the first output signal and the second output signal are high levels. The voltage absolute values of the effective levels of the first output signal and the second output signal can be substantially the same. The effective level duration of the first output signal in a frame duration is greater than the effective level duration of the second output signal in a frame duration. For example, the effective level duration of the first output signal in a frame duration can be greater than or equal to 1.5 times the effective level duration of the second output signal in a frame duration. However, the present embodiment is not limited thereto.

[0204] In some exemplary embodiments, the first output signal provided by the first output terminal OUT1 can be configured to turn on the N-type transistor in the pixel circuit that requires a shorter driving time, and the second output signal provided by the second output terminal OUT2 can be configured to turn on the N-type transistor in the pixel circuit that requires a longer driving time. For example, the first and second output signals can be used as scan signals and transmitted to the pixel circuit through scan lines. In some examples, the first output signal provided by the first output terminal of the current stage drive control circuit can be transmitted to the signal input terminal of the next stage drive control circuit as the input signal of the next stage drive control circuit. However, this embodiment is not limited in this respect.

[0205] In other examples, Figure 8 In the drive control circuit shown, a third output terminal can be provided that is directly electrically connected to the fifteenth node N15, thereby obtaining a third output signal that is out of phase with the second output signal. However, this embodiment is not limited to this.

[0206] Figure 10 This is another schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. Figure 10 As shown, the drive control circuit of this embodiment may include: an input circuit 10, a first output circuit 11, and a second output circuit 12. The first output circuit 11 is electrically connected to the input circuit 10 and a first output terminal OUT1, and is configured to output a first output signal from the first output terminal OUT1 under the control of the input circuit 10. The second output circuit 12 is electrically connected to the input circuit 10 and a second output terminal OUT2, and is configured to output a second output signal from the second output terminal OUT2 under the control of the input circuit 10.

[0207] In some exemplary embodiments, the polarity of the effective levels of the first output signal and the second output signal, and the duration of the effective levels within one frame, may be different, while the absolute values ​​of the effective voltage levels may be the same. For example, the effective level of the first output signal may be high, the effective level of the second output signal may be low, and the duration of the effective level of the first output signal may be longer than the duration of the effective level of the second output signal. In other examples, the polarity of the effective levels of the first output signal and the duration of the effective levels within one frame may be the same, while the absolute values ​​of the effective voltage levels may be different. However, this embodiment is not limited in this respect.

[0208] Figure 11 This is another schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. Figure 11As shown, the input circuit 10 is electrically connected with the first output control node OP1 and the second output control node OP2. The first output circuit 11 is electrically connected with the first output control node OP1, the second output control node OP2 and the first output terminal OUT1, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the first output control node OP1 and the second output control node OP2. The second output circuit 12 is electrically connected with the first output control node OP1 and the second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the first output control node OP1.

[0209] Figure 12 An equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. Figure 13 An equivalent circuit diagram of the drive control circuit of at least one embodiment of the present disclosure. Figure 12 A working timing diagram of the drive control circuit.

[0210] In some example embodiments, as shown in Figure 12 The drive control circuit can include an input circuit 10, a first output circuit 11 and a second output circuit 12. The input circuit 10 is electrically connected with a signal input terminal INPUT, a first clock terminal CK, a second clock terminal CK, a first power line VGH, a second power line VGL, a first node N1 and a second node N2, and is configured to control the potentials of the first node N1 and the second node N2 under the control of the signal input terminal INPUT, the first clock terminal CK and the second clock terminal CB. The first output circuit 11 is electrically connected with the first power line VGH, the second clock terminal CB, a first output terminal OUT1, the first node N1 and the second node N2, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the first node N1 and the second node N2. The second output circuit 12 is electrically connected with the first power line VGH, a third power line VGH', the second node N2 and a second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the second node N2.

[0211] In some example embodiments, as shown in Figure 12 The input circuit 10 can include a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. The first output circuit 11 includes a third transistor T3, an eighth transistor T8, a first capacitor C1 and a second capacitor C2. The second output circuit 12 includes an eleventh transistor T11 and a twelfth transistor T12. The structure and connection relationship of the input circuit 10 and the first output circuit 11 of the present example can refer to the description of the input circuit 10 and the first output circuit 11 in the embodiment shown in Figure 2

[0212] ​In some exemplary implementations, such as Figure 12 As shown, the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the second power supply line VGL, and the second electrode of the eleventh transistor T11 is electrically connected to the second output terminal OUT2. The control electrode of the twelfth transistor T12 is electrically connected to the second node N2, the first electrode of the twelfth transistor T12 is electrically connected to the third power supply line VGH', and the second electrode of the twelfth transistor T12 is electrically connected to the second output terminal OUT2.

[0213] In this example, the first node N1 is the connection point of the sixth transistor T6, the eighth transistor T8, and the second capacitor C2. The second node N2 is the connection point of the first transistor T1, the seventh transistor T7, the fourth transistor T4, the third transistor T3, the first capacitor C1, the eleventh transistor T11, and the twelfth transistor T12. The third node N3 is the connection point of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0214] In this example, the first node N1 and the second node N2 are output control nodes. Specifically, the first node N1 is the second output control node, and the second node N2 is the first output control node. The eleventh transistor T11 is the first output transistor, and the twelfth transistor T12 is the second output transistor.

[0215] In this embodiment, a first power line VGH continuously provides a first power signal, a second power line VGL continuously provides a second power signal, and a third power line VGH' continuously provides a third power signal. The effective levels of the first and third power signals can be high, and the effective level of the second power signal can be low. The absolute voltage values ​​of the effective levels of the first and second power signals can be approximately the same, and the absolute voltage value of the effective level of the third power signal is greater than the absolute voltage value of the effective level of the first power signal. However, this embodiment is not limited in this respect.

[0216] In some examples, the first transistor T1 through the eighth transistor T8 and the eleventh transistor T11 can be first semiconductor transistors, and the twelfth transistor T12 can be a second semiconductor transistor. The transistor types of the first semiconductor transistor and the second semiconductor transistor are opposite. For example, the first transistor T1 through the eighth transistor T8 and the eleventh transistor T11 can be P-type transistors, and the twelfth transistor T12 can be an N-type transistor. In some examples, the P-type transistor can be an LTPS thin-film transistor, and the N-type transistor can be an oxide thin-film transistor. However, this embodiment is not limited in this respect.

[0217] The following reference Figure 13The working process of the driving control circuit is described. The working process of the first-stage driving control circuit is taken as an example for description. The signal input end INPUT of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit in this embodiment can include: 10 transistor units (i.e., the first transistor T1 to the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12), 2 capacitor units (i.e., the first capacitor C1 and the second capacitor C2), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 3 power supply ends (i.e., the first power supply line VGH, the second power supply line VGL, and the third power supply line VGH').

[0218] As shown in FIG. 4, the working process of the driving control circuit in this example can include the following stages. Figure 13

[0219] In the first stage S41, the first clock end CK provides a low-level signal, the second clock end CB provides a high-level signal, and the signal input end INPUT provides a low-level signal.

[0220] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned on; and the fifth transistor T5 is turned off. The third node N3 and the first node N1 are at a low potential, and the second node N2 is at a low potential. The first output end OUT1 outputs a high-level signal. The eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, and the second output end OUT2 outputs a low-level signal provided by the second power supply line VGL.

[0221] In the second stage S42, the first clock end CK provides a high-level signal, the second clock end CB provides a low-level signal, and the signal input end INPUT provides a high-level signal.

[0222] The sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the fifth transistor T5 are turned on; and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. The third node N3 and the first node N1 remain at a low potential. The second node N2 is at a high potential. The first output end OUT1 outputs a low-level signal provided by the second clock end CB. The eleventh transistor T11 is turned off, the twelfth transistor T12 is turned on, and the second output end OUT2 outputs a high-potential third power supply signal provided by the third power supply line VGH'.

[0223] In the third stage S43, the first clock end CK provides a low-level signal, the second clock end CB provides a high-level signal, and the signal input end INPUT provides a high-level signal. ​

[0224] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are turned on; the seventh transistor T7, the eighth transistor T8 and the fifth transistor T5 are turned off. The third node N3 and the first node N1 are at high potential. The second node N2 is at low potential. The first output terminal OUT1 outputs a high level signal. The eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, and the second output terminal OUT2 outputs a low level signal provided by the second power supply line VGL.

[0225] In the fourth stage S44, the first clock terminal CK provides a high level signal, the second clock terminal CB provides a low level signal, and the signal input terminal INPUT provides a high level signal.

[0226] The third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on; the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 are turned off. The third node N3 and the first node N1 remain at high potential, and the second node N2 remains at low potential. The first output terminal OUT1 outputs a high level signal. The eleventh transistor T11 is turned on, the twelfth transistor T12 is turned off, and the second output terminal OUT2 outputs a low level signal provided by the second power supply line VGL.

[0227] After the fourth stage S44, the third stage S43 and the fourth stage S44 can be repeated until the signal input terminal INPUT provides a low level signal, and then the process starts again from the first stage S41.

[0228] According to the above working process, in the second stage S42, the first output terminal OUT1 outputs a low level signal, the second node N2 is at high potential, and the second output terminal OUT2 outputs a high level third power supply signal provided by the third power supply line. The voltage value of the high level signal output by the second output terminal OUT2 is greater than the voltage value of the high potential of the second node N2. In the remaining stages, the first output terminal OUT1 outputs a high level signal, the second node N2 is at low potential, and the second output terminal OUT2 outputs a low level signal provided by the second power supply line. In this example, the effective level of the first output signal is low level, and the effective level time length in a frame is approximately the same as the low level time length of the second clock signal provided by the second clock terminal CB in a pulse. The effective level of the second output signal is high level, and the effective level time length in a frame is approximately the same as the high level time length of the first clock signal provided by the first clock terminal CK in a pulse.

[0229] In the present example, the polarities of the active levels of the first output signal and the second output signal are opposite. The active level durations of the first output signal and the second output signal in a frame duration are different, and the active level duration of the second output signal can be greater than that of the first output signal. The absolute values of the voltages of the active levels of the first output signal and the second output signal are different, and the absolute value of the voltage of the active level of the second output signal can be greater than that of the first output signal.

[0230] In the present example, the first output signal provided by the first output terminal OUT1 can be configured to turn on the P-type transistor in the pixel circuit (i.e., the active level of the first output signal is low), and the second output signal provided by the second output terminal OUT2 can be configured to turn on the N-type transistor in the pixel circuit (i.e., the active level of the second output signal is high). For example, the first output signal and the second output signal can be transmitted to the pixel circuit as a scanning signal through a scanning line. In some examples, the first output signal provided by the first output terminal of the present stage driving control circuit can be transmitted to the signal input terminal of the next stage driving control circuit as the input signal of the next stage driving control circuit. However, the present embodiment is not limited thereto.

[0231] In the present example, the active level (i.e., low) of the second power signal provided by the second power supply line VGL is of the same polarity as the active level (i.e., low) of the eleventh transistor T11, and the active level (i.e., high) of the third power signal is of the same polarity as the active level (i.e., high) of the twelfth transistor T12. The present example can achieve stable output of the second output signal by connecting the second output circuit 12 at the second node N2 (i.e., the first output control node) to obtain the second output signal, thereby achieving the driving control circuit to provide two different output signals.

[0232] Figure 14 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Figure 15 For Figure 14 The working timing diagram of the driving control circuit provided.

[0233] In some example embodiments, as Figure 14As shown, the drive control circuit includes an input circuit 10, a first output circuit 11, and a second output circuit 12. The input circuit 10 is electrically connected with a signal input terminal INPUT, a first clock terminal CK, a second clock terminal CB, a first power line VGH, a second power line VGL, a twenty-first node N21, and a twenty-second node N22, and is configured to control the potentials of the twenty-first node N21 and the twenty-second node N22 under the control of the signal input terminal INPUT, the first clock terminal CK, and the second clock terminal CB. The first output circuit 11 is electrically connected with the first power line VGH, the second clock terminal CB, a first output terminal OUT1, the twenty-first node N21, and the twenty-second node N22, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the twenty-first node N21 and the twenty-second node N22. The second output circuit 12 is electrically connected with the first power line VGH, a third power line VGH', the twenty-second node N22, and a second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the twenty-second node N22.

[0234] In some example embodiments, as shown in FIG. 1, the input circuit 10 can include a twenty-first transistor T21, a twenty-second transistor T22, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, and a twenty-seventh transistor T27. The first output circuit 11 can include a twenty-third transistor T23, a twenty-eighth transistor T28, an eleventh capacitor C11, and a twelfth capacitor C12. The second output circuit 12 can include a thirteenth transistor T13 and a fourteenth transistor T14. Figure 14 In some example embodiments, as shown in FIG. 1, the input circuit 10 can include a twenty-first transistor T21, a twenty-second transistor T22, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, and a twenty-seventh transistor T27. The first output circuit 11 can include a twenty-third transistor T23, a twenty-eighth transistor T28, an eleventh capacitor C11, and a twelfth capacitor C12. The second output circuit 12 can include a thirteenth transistor T13 and a fourteenth transistor T14.

[0235] Figure 14 ​As shown, the control electrode of the twenty-first transistor T21 is electrically connected with the twenty-third node N23, the first electrode of the twenty-first transistor T21 is electrically connected with the second power supply line VGL, and the second electrode of the twenty-first transistor T21 is electrically connected with the twenty-second node N22. The control electrode of the twenty-second transistor T22 is electrically connected with the first clock terminal CK, the first electrode of the twenty-second transistor T22 is electrically connected with the signal input terminal INPUT, and the second electrode of the twenty-second transistor T22 is electrically connected with the twenty-third node N23. The control electrode of the twenty-third transistor T23 is electrically connected with the twenty-second node N22, the first electrode of the twenty-third transistor T23 is electrically connected with the first power supply line VGH, and the second electrode of the twenty-third transistor T23 is electrically connected with the first output terminal OUT1. The control electrode of the twenty-fourth transistor T24 is electrically connected with the twenty-second node N22, the first electrode of the twenty-fourth transistor T24 is electrically connected with the first power supply line VGH, and the second electrode of the twenty-fourth transistor T24 is electrically connected with the first electrode of the twenty-fifth transistor T25. The control electrode of the twenty-fifth transistor T25 is electrically connected with the second clock terminal CB, and the second electrode of the twenty-fifth transistor T25 is electrically connected with the twenty-third node N23. The control electrode of the twenty-sixth transistor T26 is electrically connected with the first power supply line VGL, the first electrode of the twenty-sixth transistor T26 is electrically connected with the twenty-third node N23, and the second electrode of the twenty-sixth transistor T26 is electrically connected with the twenty-first node N21. The control electrode of the twenty-seventh transistor T27 is electrically connected with the twenty-third node N23, the first electrode of the twenty-seventh transistor T27 is electrically connected with the first power supply line VGH, and the second electrode of the twenty-seventh transistor T27 is electrically connected with the twenty-second node N22. The control electrode of the twenty-eighth transistor T28 is electrically connected with the twenty-first node N21, the first electrode of the twenty-eighth transistor T28 is electrically connected with the second clock terminal CB, and the second electrode of the twenty-eighth transistor T28 is electrically connected with the first output terminal OUT1. The control electrode of the thirteenth transistor T13 is electrically connected with the twenty-second node N22, the first electrode of the thirteenth transistor T13 is electrically connected with the second power supply line VGL, and the second electrode of the thirteenth transistor T13 is electrically connected with the second output terminal OUT2. The control electrode of the fourteenth transistor T14 is electrically connected with the twenty-second node N22, the first electrode of the fourteenth transistor T14 is electrically connected with the third power supply line VGH', and the second electrode of the fourteenth transistor T14 is electrically connected with the second output terminal OUT2. The first electrode plate of the eleventh capacitor C11 is electrically connected with the twenty-second node N22, and the second electrode plate of the eleventh capacitor C11 is electrically connected with the first power supply line VGH. The second electrode plate of the twelfth capacitor C12 is electrically connected with the twenty-first node N21, and the second electrode plate of the twelfth capacitor C12 is electrically connected with the first output terminal OUT1.

[0236] In this example, node 21 N21 is the connection point of transistors 26 T26, 28 T28, and 12 C12. Node 22 N22 is the connection point of transistors 21 T21, 27 T27, 24 T24, 23 T23, 11 C11, 13 T13, and 14 T14. Node 23 N23 is the connection point of transistors 22 T22, 25 T25, 26 T26, 27 T27, and 21 T21.

[0237] In this example, the twenty-first node N21 and the twenty-second node N22 are output control nodes. Specifically, the twenty-second node N22 is the first output control node, and the twenty-first node N21 is the second output control node. The thirteenth transistor T13 is the first output transistor, and the fourteenth transistor T14 is the second output transistor.

[0238] In some examples, the twenty-first transistor T21 and the fourteenth transistor T14 can be second semiconductor type transistors, such as N-type transistors. The twenty-second transistors T22 to T28 and the thirteenth transistor T13 can be first semiconductor type transistors, such as P-type transistors. However, this embodiment is not limited in this respect.

[0239] The following reference Figure 15 The operation of the drive control circuit is explained below. The operation of the first-stage drive control circuit is described as an example. The signal input terminal INPUT of the first-stage drive control circuit can be electrically connected to the start signal line. The drive control circuit in this embodiment may include: 10 transistor units (i.e., transistors T21 to T28, transistor T13, and transistor T14), 2 capacitor units (i.e., capacitor C11 and capacitor C12), 3 input terminals (i.e., first clock terminal CK, second clock terminal CB, and signal input terminal INPUT), 2 output terminals (i.e., first output terminal OUT1 and second output terminal OUT2), and 3 power supply terminals (i.e., first power supply line VGH, second power supply line VGL, and third power supply line VGH').

[0240] like Figure 15 As shown, the operation of the drive control circuit in this example may include the following stages.

[0241] In the first stage S51, the first clock terminal CK inputs a low-level signal, the second clock terminal CB inputs a high-level signal, and the signal input terminal INPUT inputs a low-level signal.

[0242] The first clock end CK inputs a low level signal, the twenty-second transistor T22 is turned on, in addition, the twenty-sixth transistor T26 is turned on, the twenty-third node N23 and the twenty-first node N21 are at low potential, the twenty-seventh transistor T27 and the twenty-eighth transistor T28 are turned on, and the twenty-first transistor T21 is cut off. The first output end OUT1 outputs a high level signal provided by the second clock end CB. The high level signal provided by the first power supply line VGH is transmitted to the twenty-second node N22 through the turned-on twenty-seventh transistor T27, so that the twenty-second node N22 is at high potential, and the twenty-third transistor T23 and the twenty-fourth transistor T24 are cut off. The second clock end CB provides a high level signal, and the twenty-fifth transistor T25 is cut off. The twenty-second node N22 is at high potential, the fourteenth transistor T14 is turned on, the thirteenth transistor T13 is cut off, and the second output end OUT2 outputs a high level third power signal provided by the third power supply line VGH'.

[0243] In the second stage S52, the first clock end CK inputs a high level signal, the second clock end CB inputs a low level signal, and the signal input end INPUT inputs a high level signal.

[0244] The first clock end CK inputs a high level signal, the twenty-second transistor T22 is cut off, the twenty-third node N23 and the twenty-first node N21 maintain the low level of the previous stage, the twenty-seventh transistor T27 and the twenty-eighth transistor T28 are turned on, and the twenty-first transistor T21 is cut off. The first output end OUT1 outputs a low level signal provided by the second clock end CB. The high level signal provided by the first power supply line VGH is transmitted to the twenty-second node N22 through the turned-on twenty-seventh transistor T27, so that the twenty-second node N22 is at high potential, the fourteenth transistor T14 is turned on, the thirteenth transistor T13, the twenty-third transistor T23 and the twenty-fourth transistor T24 are cut off. The second output end OUT2 outputs a high level third power signal provided by the third power supply line VGH'. The second clock end CB provides a low level signal, and the twenty-fifth transistor T25 is turned on.

[0245] In the third stage S53, the first clock end CK inputs a low level signal, the second clock end CB inputs a high level signal, and the signal input end INPUT inputs a high level signal.

[0246] The first clock terminal CK inputs a low level signal, the twenty-second transistor T22 is turned on, the twenty-third node N23 and the twenty-first node N21 are at high potential, the twenty-eighth transistor T28 and the twenty-seventh transistor T27 are cut off, and the twenty-first transistor T21 is turned on. The low level signal provided by the second power supply line VGL is transmitted to the twenty-second node N22 through the turned-on twenty-first transistor T21, so that the twenty-second node N22 is at low potential, the twenty-third transistor T23, the twenty-fourth transistor T24 and the thirteenth transistor T13 are turned on, and the fourteenth transistor T14 is cut off. The first output terminal OUT1 outputs the high level signal provided by the first power supply line VGH. The second output terminal OUT2 outputs the low level signal provided by the second power supply line VGL. The second clock terminal CB provides a high level signal, and the twenty-fifth transistor T25 is cut off.

[0247] In the fourth stage S54, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a high level signal.

[0248] The first clock terminal CK inputs a high level signal, the twenty-second transistor T22 is cut off, the twenty-third node N23 and the twenty-first node N21 maintain the high potential in the last stage, the twenty-eighth transistor T28 and the twenty-seventh transistor T27 are cut off, and the twenty-first transistor T21 is turned on. The twenty-second node N22 is at low potential, the thirteenth transistor T13, the twenty-fourth transistor T24 and the twenty-third transistor T23 are turned on, and the fourteenth transistor T14 is cut off. The second clock terminal CB provides a low level signal, and the twenty-fifth transistor T25 is turned on. The high level signal provided by the first power supply line VGH can be transmitted to the twenty-third node N23 through the turned-on twenty-fourth transistor T24 and the twenty-fifth transistor T25, so as to ensure that the twenty-third node N23 maintains high potential. The first output terminal OUT1 outputs the high level first power supply signal provided by the first power supply line VGH. The second output terminal OUT2 outputs the low level second power supply signal provided by the second power supply line VGL.

[0249] After the fourth stage S54, the third stage S53 and the fourth stage S54 can be repeated until the signal input terminal INPUT provides a low level signal, and then the first stage S51 is started again.

[0250] According to the above working process, in the second stage S52, the first output terminal OUT1 outputs a low level signal, and in the remaining stages, the first output terminal OUT1 outputs a high level signal. In the first stage S51 and the second stage S52, the twenty-second node N22 is at high potential, and the second output terminal OUT2 outputs the high level signal provided by the third power supply line, and in the remaining stages, the twenty-second node N22 is at low potential, and the second output terminal OUT2 outputs the low level signal provided by the second power supply line.

[0251] In the present example, the active level of the first output signal and the active level of the second output signal are opposite in polarity, for example, the active level of the first output signal is low and the active level of the second output signal is high. The active level duration of the first output signal and the active level duration of the second output signal are different in a frame duration, wherein the active level duration of the second output signal can be greater than 1.5 times the active level duration of the first output signal. The absolute value of the voltage of the active level of the first output signal and the absolute value of the voltage of the active level of the second output signal are different, wherein the absolute value of the voltage of the active level of the second output signal can be greater than the absolute value of the voltage of the active level of the first output signal. However, the present embodiment is not limited thereto. For example, the absolute value of the voltage of the active level of the first output signal and the absolute value of the voltage of the active level of the second output signal can be substantially the same.

[0252] In the present example, the first output signal provided by the first output terminal OUT1 can be configured to turn on the P-type transistor in the pixel circuit (i.e., the active level of the first output signal is low), and the second output signal provided by the second output terminal OUT2 can be configured to turn on the N-type transistor in the pixel circuit (i.e., the active level of the second output signal is high). For example, the first output signal and the second output signal can be transmitted to the pixel circuit as a scanning signal through a scanning line. In some examples, the first output signal provided by the first output terminal of the present stage driving control circuit can be transmitted to the signal input terminal of the next stage driving control circuit as the input signal of the next stage driving control circuit. However, the present embodiment is not limited thereto.

[0253] In the present example, the active level of the second power signal provided by the second power supply line VGL (i.e., low) is the same in polarity as the active level of the thirteenth transistor T13 (i.e., low), and the active level of the third power signal (i.e., high) is the same in polarity as the active level of the fourteenth transistor T14 (i.e., high). The present example can achieve stable output of the second output signal by connecting the second output circuit 12 at the twenty-second node N22 (i.e., the first output control node) to obtain the second output signal, thereby achieving the driving control circuit to provide two different output signals.

[0254] Figure 16 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Figure 17 For Figure 16 The working timing diagram of the driving control circuit provided. As Figure 16 shown, the second output circuit 12 is electrically connected with the fourth node N4 and the second output terminal OUT2, and is configured to control the second output terminal OUT2 to output the second output signal under the control of the fourth node N4.

[0255] In some example embodiments, as shown in Figure 16 The input circuit 10 can include a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, a thirty-fourth transistor T34, a thirty-fifth transistor T35, a thirty-sixth transistor T36, a thirty-seventh transistor T37, a thirty-eighth transistor T38, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5. The first output circuit 11 can include a thirty-ninth transistor T39 and a fortieth transistor T40. The second output circuit 12 can include a forty-sixth transistor T46 and a forty-seventh transistor T47.

[0256] In the present example, the fourth node N4 is a connection point of the thirty-seventh transistor T37, the thirty-eighth transistor T38, the thirty-ninth transistor T39, the third capacitor C3, the forty-sixth transistor T46, and the forty-seventh transistor T47. The fifth node N5 is a connection point of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38, the fortieth transistor T40, and the fourth capacitor C4. The sixth node N6 is a connection point of the thirty-second transistor T32, the thirty-third transistor T33, the thirty-fifth transistor T35, the thirty-sixth transistor T36, and the fifth capacitor C5.

[0257] In some examples, as shown in Figure 16 The control electrode of the forty-sixth transistor T46 is electrically connected to the fourth node N4, the first electrode of the forty-sixth transistor T46 is electrically connected to the first power supply line VGH, and the second electrode of the forty-sixth transistor T46 is electrically connected to the second output terminal OUT2. The control electrode of the forty-seventh transistor T47 is electrically connected to the fourth node N4, the first electrode of the forty-seventh transistor T47 is electrically connected to the second power supply line VGL, and the second electrode of the forty-seventh transistor T47 is electrically connected to the second output terminal OUT2. The connection relationship of the transistors and the connection relationship of the capacitors of the input circuit 10 and the first output circuit 11 can refer to the description of the equivalent circuit of the embodiment shown in Figure 4

[0258] In the present example, the fourth node N4 and the fifth node N5 are output control nodes. For example, the fourth node N4 is a first output control node, and the fifth node N5 is a second output control node. The forty-sixth transistor T46 is a first output transistor, and the forty-seventh transistor T47 is a second output transistor.

[0259] ​In this example, transistors 31 through 40, and 46, can be first-type semiconductor transistors, such as P-type transistors. Transistor 47 can be a second-type semiconductor transistor, such as an N-type transistor. However, this embodiment is not limited to this.

[0260] The following reference Figure 17 Taking the operation of the first-stage drive control circuit as an example, the following explanation is provided. Figure 16 The diagram illustrates the operation of the drive control circuit. The signal input terminal INPUT of the first-stage drive control circuit can be electrically connected to the start signal line. The drive control circuit in this embodiment may include: 12 transistor units (i.e., transistors T31 to T40, T46, and T47), 3 capacitor units (i.e., capacitors C3 to C5), 3 input terminals (i.e., the first clock terminal CK, the second clock terminal CB, and the signal input terminal INPUT), 2 output terminals (i.e., the first output terminal OUT1 and the second output terminal OUT2), and 2 power supply terminals (i.e., the first power line VGH and the second power line VGL). The first power line VGH can continuously provide a high-level first power signal, and the second power line VGL can continuously provide a low-level second power signal.

[0261] like Figure 17 As shown, the operation of the drive control circuit in this example may include the following stages.

[0262] In the first stage S61, the first clock terminal CK inputs a low-level signal, the second clock terminal CB inputs a high-level signal, and the signal input terminal INPUT inputs a high-level signal.

[0263] Transistors T31 (31) and T33 (33) are turned on, node N5 is at a high potential, and transistors T32 (32), T34 (34), T38 (38), and T40 (40) are turned off. Node N6 is at a low potential, and transistors T35 (35) and T36 (36) are turned on. The second clock input CB is high, and transistor T37 (37) is turned off. Node N4 maintains the high potential from the previous stage, transistors T39 (39) and T46 (46) are turned off, and transistor T47 (47) is turned on. The first output terminal OUT1 maintains the previous low-level output, and the second output terminal OUT2 outputs the low-level signal provided by the second power supply line VGL.

[0264] In the second stage S62, the first clock terminal CK inputs a high-level signal, the second clock terminal CB inputs a low-level signal, and the signal input terminal INPUT inputs a high-level signal.

[0265] The thirty-first transistor T31 and the thirty-third transistor T33 are turned on, the fifth node N5 is at high potential, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The sixth node N6 is at low potential, the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The second clock end CB inputs a high level signal, and the thirty-seventh transistor T37 is turned off. The fourth node N4 keeps low potential, the thirty-ninth transistor T39 and the forty-sixth transistor T46 are turned on, and the forty-seventh transistor T47 is turned off. The first output end OUT1 outputs a high level signal, and the second output end OUT2 outputs a high level signal.

[0266] In the third stage S63, the first clock end CK inputs a low level signal, the second clock end CB inputs a high level signal, and the signal input end INPUT inputs a high level signal.

[0267] The thirty-first transistor T31 and the thirty-third transistor T33 are turned on, the fifth node N5 is at high potential, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The sixth node N6 is at low potential, the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The second clock end CB inputs a high level signal, and the thirty-seventh transistor T37 is turned off. The fourth node N4 keeps low potential, the thirty-ninth transistor T39 and the forty-sixth transistor T46 are turned on, and the forty-seventh transistor T47 is turned off. The first output end OUT1 outputs a high level signal, and the second output end OUT2 outputs a high level signal.

[0268] In the fourth stage S64, the first clock end CK inputs a high level signal, the second clock end CB inputs a low level signal, and the signal input end INPUT inputs a low level signal.

[0269] The thirty-first transistor T31 and the thirty-third transistor T33 are turned off, the fifth node N5 is at high potential, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned off. The sixth node N6 keeps low potential, the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are turned on. The second clock end CB provides a low level signal, and the thirty-seventh transistor T37 is turned on. The fourth node N4 is at low potential, the thirty-ninth transistor T39 and the forty-sixth transistor T46 are turned on, and the forty-seventh transistor T47 is turned off. The first output end OUT1 and the second output end OUT2 both output a high level signal.

[0270] In the fifth stage S65, the first clock end CK inputs a low level signal, the second clock end CB inputs a high level signal, and the signal input end INPUT inputs a low level signal.

[0271] The thirty-first transistor T31 and the thirty-third transistor T33 are turned on, the fifth node N5 is at low potential, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned on. The sixth node N6 is at low potential, the thirty-fifth transistor T35 and the thirty-sixth transistor T63 are turned on. The thirty-seventh transistor T37 is cut off. The fourth node N4 is at high potential, the thirty-ninth transistor T39 and the forty-sixth transistor T46 are cut off, and the forty-seventh transistor T47 is turned on. The second output terminal OUT2 outputs a low level signal. Since the fortieth transistor T40 has threshold loss in transmitting the low level signal, the second power supply signal cannot be completely output to the first output terminal OUT1. The voltage value of the output signal of the first output terminal OUT1 in this stage is less than the voltage value of the first power supply signal and greater than the voltage value of the second power supply signal.

[0272] In the sixth stage S66, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a low level signal.

[0273] The thirty-first transistor T31 and the thirty-third transistor T33 are cut off, the fifth node N5 remains at low potential, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38 and the fortieth transistor T40 are turned on, and the first output terminal OUT1 outputs a low level signal. The sixth node N6 is at high potential, the thirty-fifth transistor T35 and the thirty-sixth transistor T36 are cut off. The thirty-seventh transistor T37 is turned on. The fourth node N4 is at high potential, the thirty-ninth transistor T39 and the forty-sixth transistor T46 are cut off, the forty-seventh transistor T47 is turned on, and the second output terminal OUT2 outputs a low level signal.

[0274] According to the operation process of the driving control circuit, in the second stage S62 to the fourth stage S64, the first output terminal OUT1 and the second output terminal OUT2 can output high level signals, and in the fifth stage S65, the first output terminal OUT1 outputs a first voltage signal, and the voltage value of the first voltage signal is less than the voltage value of the first power supply signal and greater than the voltage value of the second power supply signal. The stage in which the first output terminal OUT1 outputs the first voltage signal can be referred to as a voltage fluctuation stage, and the time length of the first output terminal OUT1 outputting the first voltage signal can be referred to as a voltage fluctuation time length. In the present example, the effective level of the first output signal provided by the first output terminal OUT1 and the effective level of the second output signal provided by the second output terminal OUT2 have the same polarity, that is, both are high level effective. The effective level time length of the first output signal in a frame time length and the effective level time length of the second output signal in a frame time length can be substantially the same. The first output signal has a voltage fluctuation stage after the effective level, and the effective level time length of the first output signal is greater than the voltage fluctuation time length. The second output signal does not have a voltage fluctuation stage. Compared with the first output signal, the second output signal in the present example can eliminate the voltage fluctuation of the first output signal, thereby improving the performance of the output signal of the driving control circuit.

[0275] In the present example, the second output circuit 12 can include an inverting sub-circuit, which can include a forty-sixth transistor T46 and a forty-seventh transistor T47. The effective level (i.e., high level) of the first power supply signal and the effective level (i.e., low level) for turning on the forty-sixth transistor T46 have opposite polarities, and the effective level (i.e., low level) of the second power supply signal and the effective level (i.e., high level) for turning on the forty-seventh transistor T47 have opposite polarities. The inverting sub-circuit can perform inverting processing on the signal of the fourth node N4 to obtain the second output signal.

[0276] In some example embodiments, the first output signal provided by the first output terminal OUT1 and the second output signal provided by the second output terminal OUT2 can be configured to turn on the N-type transistor in the pixel circuit. In some examples, the first output signal can be transmitted to the pixel circuit as a light emitting control signal through a light emitting control line; and the second output signal can be transmitted to the pixel circuit as a reset control signal through a reset control line to control the anode of the light emitting element to be reset. In some examples, the first output signal provided by the first output terminal of the present stage driving control circuit can be transmitted to the signal input terminal of the next stage driving control circuit as the input signal of the next stage driving control circuit. However, the present embodiment is not limited thereto.

[0277] Figure 18 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Compared with the driving control circuit shown in FIG. 8, Figure 16 the driving control circuit shown in FIG. 9, Figure 18The input circuit 10 of the drive control circuit shown may further include a forty-first transistor T41 and a forty-second transistor T42. The forty-second transistor T42 is connected between the fifth node N5 and the seventh node N7, configured to stabilize the potential of the seventh node N7; the forty-first transistor T41 is connected between the sixth node N6 and the eighth node N8, configured to stabilize the potential of the sixth node N6. The connection relationship between the transistors and capacitors of the input circuit 10 and the first output circuit 11 of this embodiment can be referred to... Figure 4 The description of the drive control circuit shown can be found in the following section. For the structure of the second output circuit 12, please refer to... Figure 16 The relevant descriptions of the drive control circuit shown are omitted here. Regarding... Figure 18 The operating timing sequence of the drive control circuit shown can be referred to Figure 17 The explanation is already provided, so it will not be repeated here.

[0278] Figure 19 This is another schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. Figure 19 As shown, the input circuit 10 may include an input sub-circuit 101 and a control sub-circuit 102. The input sub-circuit 101 is electrically connected to the signal input terminal INPUT, the first clock terminal CK, and the first control node CP1, and is configured to control the potential of the first control node CP1 under the control of the signal input terminal INPUT and the first clock terminal CK. The control sub-circuit 102 is electrically connected to at least the first control node CP1, the first power line VGH, the second power line VGL, the first output control node OP1, and the second output control node OP2, and is configured to control the potential of the first output control node OP1 and the second output control node OP2 under the control of the first control node CP1. The first output circuit 11 is electrically connected to the first output control node OP1, the second output control node OP2, and the first output terminal OUT1, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the first output control node OP1 and the second output control node OP2. The second output circuit 12 is electrically connected to the first control node CP1 and the second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a second output signal under the control of the first control node CP1.

[0279] Figure 20 This is an equivalent circuit diagram of a drive control circuit according to at least one embodiment of the present disclosure. Figure 21 for Figure 20 The provided timing diagram of the drive control circuit.

[0280] In some exemplary implementations, such as Figure 20As shown, the input sub-circuit 101 can include a twenty-second transistor T22. The control sub-circuit 102 can include a twenty-first transistor T21, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26 and a twenty-seventh transistor T27. The first output circuit 11 can include a twenty-third transistor T23, a twenty-eighth transistor T28, an eleventh capacitor C11 and a twelfth capacitor C12. The second output circuit 12 can include a fifteenth transistor T15 and a sixteenth transistor T16. The structures and connection relationships of the input circuit 10 and the first output circuit 11 can refer to the description of the driving control circuit as shown in FIG. 1, which will not be repeated here. Figure 14 The description of the driving control circuit as shown in FIG. 1 will not be repeated here.

[0281] In some examples, as shown in FIG. 2, the first electrode of the twenty-first transistor T21 is electrically connected with the first node N1, the second electrode of the twenty-first transistor T21 is electrically connected with the twenty-second node N22, and the control electrode of the twenty-first transistor T21 is electrically connected with the twenty-first node N21. Figure 20 As shown, the control electrode of the fifteenth transistor T15 is electrically connected with the twenty-third node N23, the first electrode of the fifteenth transistor T15 is electrically connected with the third power supply line VGH', and the second electrode of the fifteenth transistor T15 is electrically connected with the second output terminal OUT2. The control electrode of the sixteenth transistor T16 is electrically connected with the twenty-third node N23, the first electrode of the sixteenth transistor T16 is electrically connected with the second power supply line VGL, and the second electrode of the sixteenth transistor T16 is electrically connected with the second output terminal OUT2.

[0282] In the present example, the twenty-first node N21 is the connection point of the twenty-sixth transistor T26, the twenty-eighth transistor T28 and the twelfth capacitor C12. The twenty-second node N22 is the connection point of the twenty-first transistor T21, the twenty-seventh transistor T27, the twenty-fourth transistor T24, the twenty-third transistor T23 and the eleventh capacitor C11. The twenty-third node N23 is the connection point of the twenty-second transistor T22, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, the twenty-first transistor T21, the fifteenth transistor T15 and the sixteenth transistor T16.

[0283] In the present example, the twenty-first node N21 and the twenty-second node N22 can be output control nodes. The twenty-third node N23 can be a first control node. The fifteenth transistor T15 is a first output transistor, and the sixteenth transistor T16 is a second output transistor.

[0284] In some examples, the twenty-first transistor T21 and the sixteenth transistor T16 can be second semiconductor type transistors, for example, can be N-type transistors. The twenty-second transistor T22 to the twenty-eighth transistor T28 and the fifteenth transistor T15 can be first semiconductor type transistors, for example, can be P-type transistors. However, the present embodiment is not limited thereto.

[0285] The following will be described with reference to Figure 21The operation of the drive control circuit is explained below. The operation of the first-stage drive control circuit is described as an example. The signal input terminal INPUT of the first-stage drive control circuit can be electrically connected to the start signal line. The drive control circuit in this embodiment may include: 10 transistor units (i.e., transistors T21 to T28, transistor T15, and transistor T16), 2 capacitor units (i.e., capacitor C11 and capacitor C12), 3 input terminals (i.e., first clock terminal CK, second clock terminal CB, and signal input terminal INPUT), 2 output terminals (i.e., first output terminal OUT1 and second output terminal OUT2), and 3 power supply terminals (i.e., first power supply line VGH, second power supply line VGL, and third power supply line VGH').

[0286] like Figure 21 As shown, the operation of the drive control circuit in this example may include the following stages.

[0287] In the first stage S71, the first clock terminal CK inputs a low-level signal, the second clock terminal CB inputs a high-level signal, and the signal input terminal INPUT inputs a low-level signal.

[0288] Transistors T22 (22), T26 (26), T27 (27), T28 (28), and T15 (15) are turned on. Transistors T21 (21), T23 (23), T24 (24), T25 (25), and T16 (16) are turned off. Nodes N23 (23) and N21 (21) are at a low potential, and node N22 (22) is at a high potential. The first output terminal OUT1 outputs a high-level signal, and the second output terminal OUT2 outputs a high-level signal provided by the third power line VGH'.

[0289] In the second stage S72, the first clock terminal CK inputs a high-level signal, the second clock terminal CB inputs a low-level signal, and the signal input terminal INPUT inputs a high-level signal.

[0290] Transistors T21 (21), T22 (22), T24 (24), T23 (23), and T16 (16) are off; transistors T25 (25), T26 (26), T27 (27), T28 (28), and T15 (15) are on. Nodes N23 (23) and N21 (21) are at low potential, and node N22 (22) is at high potential. Output terminal OUT1 outputs a low-level signal, and output terminal OUT2 outputs a high-level signal provided by the third power line VGH'.

[0291] In the third stage S73, the first clock terminal CK inputs a low level signal, the second clock terminal CB inputs a high level signal, and the signal input terminal INPUT inputs a high level signal.

[0292] The twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-sixth transistor T26 and the sixteenth transistor T16 are turned on, and the twenty-fifth transistor T25, the twenty-seventh transistor T27, the twenty-eighth transistor T28 and the fifteenth transistor T15 are turned off. The twenty-third node N23 and the twenty-first node N21 are at high potential, and the twenty-second node N22 is at low potential. The first output terminal OUT1 outputs a high level signal, and the second output terminal OUT2 outputs a low level signal.

[0293] In the fourth stage S74, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a high level signal.

[0294] The twenty-second transistor T22, the twenty-seventh transistor T27, the twenty-eighth transistor T28 and the fifteenth transistor T15 are turned off, and the twenty-first transistor T21, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25, the twenty-sixth transistor T26 and the sixteenth transistor T16 are turned on.

[0295] The twenty-third node N23 and the twenty-first node N21 are at high potential, and the twenty-second node N22 is at low potential. The first output terminal OUT1 outputs a high level first power signal provided by the first power line VGH. The second output terminal OUT2 outputs a low level second power signal provided by the second power line VGL.

[0296] According to the above working process, it can be known that in the first stage S71 and the second stage S72, the second output terminal OUT2 outputs a high level signal provided by the third power line VGH', and outputs a low level signal in the remaining stages. The first output terminal OUT1 outputs a low level signal in the second stage S72, and outputs a high level signal in the remaining stages.

[0297] In the example, the active level of the first output signal and the active level of the second output signal are opposite in polarity, for example, the active level of the first output signal is low and the active level of the second output signal is low. The active level duration of the first output signal and the active level duration of the second output signal are different in a frame duration. The active level duration of the second output signal can be greater than the active level duration of the first output signal, for example, the active level duration of the second output signal can be 1.5 times greater than the active level duration of the first output signal. The voltage absolute value of the active level of the first output signal and the voltage absolute value of the active level of the second output signal are different, wherein the voltage absolute value of the active level of the second output signal can be greater than the voltage absolute value of the active level of the first output signal. However, the present embodiment is not limited thereto. For example, the voltage absolute value of the active level of the first output signal and the voltage absolute value of the active level of the second output signal can be substantially the same.

[0298] In the example, the first output signal provided by the first output terminal OUT1 can be configured to turn on the P-type transistor in the pixel circuit (i.e., the active level of the first output signal is low), and the second output signal provided by the second output terminal OUT2 can be configured to turn on the N-type transistor in the pixel circuit (i.e., the active level of the second output signal is high). In some examples, the first output signal and the second output signal can be transmitted to the pixel circuit as a scanning signal through a scanning line. In some examples, the first output signal provided by the first output terminal of the present stage driving control circuit can be transmitted to the signal input terminal of the next stage driving control circuit as an input signal of the next stage driving control circuit. However, the present embodiment is not limited thereto.

[0299] In the example, the active level of the second power signal provided by the second power supply line VGL (i.e., low) is opposite in polarity to the active level of the sixteenth transistor T16 (i.e., high), and the active level of the third power signal (i.e., high) is opposite in polarity to the active level of the fifteenth transistor T15 (i.e., low). The second output circuit 12 can include an inverting sub-circuit, which can include the fifteenth transistor T15 and the sixteenth transistor T16. The inverting sub-circuit can invert the signal of the twenty-third node N23 (i.e., the first control node) and output a second output signal, thereby realizing the driving control circuit to provide two different output signals.

[0300] Figure 22 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Figure 23 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Figure 22 The working timing diagram of the driving control circuit provided. As Figure 22As shown, the input sub-circuit 101 can include a thirty-first transistor T31. The control sub-circuit 102 can include: a thirty-second transistor T32 to a thirty-eighth transistor T38, a third capacitor C3 to a fifth capacitor C5. The first output circuit 11 can include: a thirty-ninth transistor T39 and a fortieth transistor T40. The second output circuit 12 can include: a forty-eighth transistor T48 and a forty-ninth transistor T49.

[0301] In the present example, the fourth node N4 is a connection point of the thirty-seventh transistor T37, the thirty-eighth transistor T38, the thirty-ninth transistor T39 and the third capacitor C3. The fifth node N5 is a connection point of the thirty-first transistor T31, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38, the fortieth transistor T40, the forty-eighth transistor T48, the forty-ninth transistor T49 and the fourth capacitor C4. The sixth node N6 is a connection point of the thirty-second transistor T32, the thirty-third transistor T33, the thirty-fifth transistor T35, the thirty-sixth transistor T36 and the fifth capacitor C5. The connection relationship of the transistors and the capacitors of the input circuit 10 and the first output circuit 11 can refer to the description of the equivalent circuit of the embodiment shown in FIG. 2, which will not be repeated here. Figure 4 The description of the equivalent circuit of the embodiment shown in FIG. 2 is omitted here.

[0302] In some examples, as shown in FIG. 3, the input sub-circuit 101 can include a thirty-first transistor T31. The control sub-circuit 102 can include: a thirty-second transistor T32 to a thirty-eighth transistor T38, a third capacitor C3 to a fifth capacitor C5. The first output circuit 11 can include: a thirty-ninth transistor T39 and a fortieth transistor T40. The second output circuit 12 can include: a forty-eighth transistor T48 and a forty-ninth transistor T49. Figure 22 As shown, the control electrode of the forty-eighth transistor T48 is electrically connected with the fifth node N5, the first electrode of the forty-eighth transistor T48 is electrically connected with the first power supply line VGH, and the second electrode of the forty-eighth transistor T48 is electrically connected with the second output terminal OUT2. The control electrode of the forty-ninth transistor T49 is electrically connected with the fifth node N5, the first electrode of the forty-ninth transistor T49 is electrically connected with the second power supply line VGL, and the second electrode of the forty-ninth transistor T49 is electrically connected with the second output terminal OUT2.

[0303] In the present example, the fourth node N4 and the fifth node N5 are output control nodes. The fifth node N5 is also a first control node. The forty-eighth transistor T48 is a first output transistor, and the forty-ninth transistor T49 is a second output transistor.

[0304] In the present example, the thirty-first transistor T31 to the fortieth transistor T40 and the forty-eighth transistor T48 can be first semiconductor type transistors, for example, P-type transistors. The forty-ninth transistor T49 can be a second semiconductor type transistor, for example, an N-type transistor. However, the present embodiment is not limited thereto.

[0305] The working process of the first stage driving control circuit will be described below Figure 23 as an example Figure 22The working process of the driving control circuit is shown. The signal input end INPUT of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit of the embodiment can include: 12 transistor units (i.e., the thirty-first transistor T31 to the fortieth transistor T40, the forty-eighth transistor T48, and the forty-ninth transistor T49), 3 capacitor units (i.e., the third capacitor C3 to the fifth capacitor C5), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 2 power supply ends (i.e., the first power supply line VGH and the second power supply line VGL). The first power supply line VGH can continuously provide a high-level first power supply signal, and the second power supply line VGL can continuously provide a low-level second power supply signal.

[0306] As shown in Figure 23 The working process of the driving control circuit of the embodiment can include the following stages.

[0307] In the first stage S81, the first clock end CK inputs a low-level signal, the second clock end CB inputs a high-level signal, and the signal input end INPUT inputs a high-level signal.

[0308] The thirty-first transistor T31, the thirty-third transistor T33, the thirty-fifth transistor T35, the thirty-sixth transistor T36, and the forty-ninth transistor T49 are turned on, and the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-seventh transistor T37, the thirty-eighth transistor T38, the thirty-ninth transistor T39, the fortieth transistor T40, and the forty-eighth transistor T48 are turned off. The fifth node N5 is at a high potential, the sixth node N6 is at a low potential, and the fourth node N4 is at a high potential. The first output end OUT1 outputs a low-level signal, and the second output end OUT2 outputs a low-level signal.

[0309] In the second stage S82, the first clock end CK inputs a high-level signal, the second clock end CB inputs a low-level signal, and the signal input end INPUT inputs a high-level signal.

[0310] The thirty-first transistor T31, the thirty-third transistor T33, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38, the fortieth transistor T40, and the forty-eighth transistor T48 are turned off, and the thirty-fifth transistor T35, the thirty-sixth transistor T36, the thirty-seventh transistor T37, the thirty-ninth transistor T39, and the forty-ninth transistor T49 are turned on. The fifth node N5 is at a high potential, the sixth node N6 is at a low potential, and the fourth node N4 is at a low potential. The first output end OUT1 outputs a high-level signal, and the second output end OUT2 outputs a low-level signal.

[0311] In the third stage S83, the first clock terminal CK inputs a low level signal, the second clock terminal CB inputs a high level signal, and the signal input terminal INPUT inputs a high level signal.

[0312] The thirty-first transistor T31, the thirty-third transistor T33, the thirty-fifth transistor T35, the thirty-sixth transistor T36, the thirty-ninth transistor T39 and the forty-ninth transistor T49 are turned on, and the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-seventh transistor T37, the thirty-eighth transistor T38, the fortieth transistor T40 and the forty-eighth transistor T48 are turned off. The fifth node N5 is at a high potential, the sixth node N6 is at a low potential, and the fourth node N4 is at a low potential. The first output terminal OUT1 outputs a high level signal, and the second output terminal OUT2 outputs a low level signal.

[0313] In the fourth stage S84, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a low level signal.

[0314] The thirty-first transistor T31, the thirty-third transistor T33, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-eighth transistor T38, the fortieth transistor T40 and the forty-eighth transistor T48 are turned off, and the thirty-fifth transistor T35, the thirty-sixth transistor T36, the thirty-seventh transistor T37, the thirty-ninth transistor T39 and the forty-ninth transistor T49 are turned on. The fifth node N5 is at a high potential, the sixth node N6 is at a low potential, and the fourth node N4 is at a low potential. The first output terminal OUT1 outputs a high level signal, and the second output terminal OUT2 outputs a low level signal.

[0315] In the fifth stage S85, the first clock terminal CK inputs a low level signal, the second clock terminal CB inputs a high level signal, and the signal input terminal INPUT inputs a low level signal.

[0316] The thirty-first transistor T31, the thirty-third transistor T33, the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-fifth transistor T35, the thirty-sixth transistor T63, the thirty-eighth transistor T38, the fortieth transistor T40 and the forty-eighth transistor T48 are turned on, and the thirty-seventh transistor T37, the thirty-ninth transistor T39 and the forty-ninth transistor T49 are turned off. The fifth node N5 is at a low potential, the sixth node N6 is at a low potential, and the fourth node N4 is at a high potential. Since the fortieth transistor T40 has threshold loss in transmitting a low level signal, the second power signal cannot be completely output to the first output terminal OUT1. The output signal of the first output terminal OUT1 in this stage has a voltage value smaller than that of the first power signal and larger than that of the second power signal. The second output terminal OUT2 outputs a high level signal.

[0317] In the sixth stage S86, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a low level signal.

[0318] The thirty-first transistor T31, the thirty-third transistor T33, the thirty-fifth transistor T35, the thirty-sixth transistor T36, the thirty-ninth transistor T39 and the forty-ninth transistor T49 are turned off, and the thirty-second transistor T32, the thirty-fourth transistor T34, the thirty-seventh transistor T37, the thirty-eighth transistor T38, the fortieth transistor T40 and the forty-eighth transistor T48 are turned on. The fifth node N5 is at a low potential, the sixth node N6 is at a high potential, and the fourth node N4 is at a high potential. The first output terminal OUT1 and the second output terminal OUT2 output low level signals.

[0319] According to the working process of the driving control circuit, the first output terminal OUT1 outputs a high level signal in the second stage S82 to the fourth stage S84 and outputs the first voltage signal in the fifth stage S85. The second output terminal OUT2 outputs a low level signal in the first stage S81 to the fourth stage S84 and outputs a high level signal in the remaining stages.

[0320] In the present example, the polarities of the active levels of the first output signal and the second output signal are opposite, for example, the active level of the first output signal is a high level and the active level of the second output signal is a low level. The duration of the active level of the first output signal in a frame duration can be less than the duration of the active level of the second output signal in a frame duration. The absolute values of the voltages of the active levels of the first output signal and the second output signal can be substantially the same. The first output signal has a continuous voltage fluctuation stage after the active level, and the duration of the voltage fluctuation is less than the duration of the active level. The second output signal does not have a voltage fluctuation stage after the active level.

[0321] In the present example, the second output circuit 12 can include an inverting sub-circuit including the forty-eighth transistor T48 and the forty-ninth transistor T49. The polarity of the active level (i.e., high level) of the first power supply signal is opposite to the polarity of the active level (i.e., low level) for turning on the forty-eighth transistor T48, and the polarity of the active level (i.e., low level) of the second power supply signal is opposite to the polarity of the active level (i.e., high level) for turning on the forty-ninth transistor T49. The inverting sub-circuit can perform inverting processing on the signal of the fifth node N5 to obtain the second output signal.

[0322] In some example embodiments, the first output signal provided by the first output terminal OUT1 can be configured to turn on the N-type transistor in the pixel circuit. The second output signal provided by the second output terminal OUT2 can be configured to turn on the P-type transistor in the pixel circuit. In some examples, the first output signal can be transmitted to the pixel circuit as a light emitting control signal through a light emitting control line; the second output signal can be transmitted to the pixel circuit as a reset control signal through a reset control line to control the reset of the anode of the light emitting element. In some examples, the first output signal provided by the first output terminal of the current stage of the driving control circuit can be transmitted to the signal input terminal of the next stage of the driving control circuit as the input signal of the next stage of the driving control circuit. However, the present embodiment is not limited thereto.

[0323] Figure 24 Another equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Compared with the driving control circuit shown in Figure 22 Figure 24 The input circuit 10 of the driving control circuit shown in FIG. 10 can further include a forty-first transistor T41 and a forty-second transistor T42. The forty-second transistor T42 is connected between the fifth node N5 and the seventh node N7 and is configured to stabilize the potential of the seventh node N7. The forty-first transistor T41 is connected between the sixth node N6 and the eighth node N8 and is configured to stabilize the potential of the sixth node N6. The structure of the input circuit and the first output circuit of the driving control circuit of the present embodiment can refer to the related description of the driving control circuit shown in Figure 4 Figure 22 The structure of the second output circuit of the driving control circuit of the present embodiment can refer to the related description of the driving control circuit shown in Figure 24 The working timing of the driving control circuit shown in FIG. 10 can refer to the description of Figure 23 , and thus will not be repeated here.

[0324] Figure 25 An equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Figure 26 The working timing of the driving control circuit provided in Figure 25

[0325] In some example embodiments, as Figure 25 ​​​As shown, the input sub-circuit 101 can include a twenty-second transistor T22. The control sub-circuit 102 can include a twenty-fourth transistor T24, a twenty-fifth transistor T25 and a twenty-sixth transistor T26. The first output circuit 11 can include a twenty-third transistor T23, a twenty-eighth transistor T28, an eleventh capacitor C11 and a twelfth capacitor C12. The second output circuit 12 can include a twenty-first transistor T21 and a twenty-seventh transistor T27. The connection relationship of the twenty-first transistor T21 to the twenty-eighth transistor T28, the eleventh capacitor C11 and the twelfth capacitor C12 can refer to the description of the driving control circuit shown in FIG. 2, which will not be repeated here. Figure 12 The description of the driving control circuit shown in FIG. 2 will not be repeated here.

[0326] In this example, the twenty-first node N21 is the connection point of the twenty-sixth transistor T26, the twenty-eighth transistor T28 and the twelfth capacitor C12. The twenty-second node N22 is the connection point of the twenty-first transistor T21, the twenty-seventh transistor T27, the twenty-fourth transistor T24, the twenty-third transistor T23 and the eleventh capacitor C11. The twenty-third node N23 is the connection point of the twenty-second transistor T22, the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27 and the twenty-first transistor T21.

[0327] In this example, the twenty-first node N21 and the twenty-second node N22 can be output control nodes. The twenty-second node N22 is the first output control node, and the twenty-first node N21 is the second output control node. The twenty-third node N23 can be the first control node. The second output end OUT2 can be directly electrically connected with the twenty-second node N22. The twenty-seventh transistor T27 can be the first output transistor, and the twenty-first transistor T21 can be the second output transistor.

[0328] In some examples, the twenty-first transistor T21 can be a second semiconductor type transistor, for example, an N-type transistor. The twenty-second transistor T22 to the twenty-eighth transistor T28 can be a first semiconductor type transistor, for example, a P-type transistor. However, the present embodiment is not limited thereto.

[0329] Reference will be made to Figure 26The working process of the driving control circuit is described. The working process of the first-stage driving control circuit is taken as an example for description. The signal input end INPUT of the first-stage driving control circuit can be electrically connected with the start signal line. The driving control circuit in this embodiment can include: 8 transistor units (i.e., the twenty-first transistor T21 to the twenty-eighth transistor T28), 2 capacitor units (i.e., the eleventh capacitor C11 and the twelfth capacitor C12), 3 input ends (i.e., the first clock end CK, the second clock end CB, and the signal input end INPUT), 2 output ends (i.e., the first output end OUT1 and the second output end OUT2), and 2 power supply ends (i.e., the first power supply line VGH and the second power supply line VGL).

[0330] As shown in FIG. 9, the working process of the driving control circuit in this example can include the following stages. Figure 26

[0331] In the first stage S91, the first clock end CK inputs a low-level signal, the second clock end CB inputs a high-level signal, and the signal input end INPUT inputs a low-level signal.

[0332] The twenty-second transistor T22, the twenty-sixth transistor T26, the twenty-seventh transistor T27, and the twenty-eighth transistor T28 are turned on. The twenty-first transistor T21, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 are turned off. The twenty-third node N23 and the twenty-first node N21 are at a low potential, and the twenty-second node N22 is at a high potential. The first output end OUT1 outputs a high-level signal, and the second output end OUT2 outputs a high-level signal.

[0333] In the second stage S92, the first clock end CK inputs a high-level signal, the second clock end CB inputs a low-level signal, and the signal input end INPUT inputs a high-level signal.

[0334] The twenty-first transistor T21, the twenty-second transistor T22, the twenty-fourth transistor T24, and the twenty-third transistor T23 are turned off, and the twenty-fifth transistor T25, the twenty-sixth transistor T26, the twenty-seventh transistor T27, and the twenty-eighth transistor T28 are turned on. The twenty-third node N23 and the twenty-first node N21 are at a low potential, and the twenty-second node N22 is at a high potential. The first output end OUT1 outputs a low-level signal, and the second output end OUT2 outputs a high-level signal.

[0335] In the third stage S93, the first clock end CK inputs a low-level signal, the second clock end CB inputs a high-level signal, and the signal input end INPUT inputs a high-level signal.

[0336] ​The twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are turned on, and the twenty-fifth transistor T25, the twenty-seventh transistor T27 and the twenty-eighth transistor T28 are turned off. The twenty-third node N23 and the twenty-first node N21 are at high level, and the twenty-second node N22 is at low level. The first output terminal OUT1 outputs a high level signal, and the second output terminal OUT2 outputs a low level signal.

[0337] In the fourth stage S94, the first clock terminal CK inputs a high level signal, the second clock terminal CB inputs a low level signal, and the signal input terminal INPUT inputs a high level signal.

[0338] The twenty-second transistor T22, the twenty-seventh transistor T27 and the twenty-eighth transistor T28 are turned off, and the twenty-first transistor T21, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-fifth transistor T25 and the twenty-sixth transistor T26 are turned on. The twenty-third node N23 and the twenty-first node N21 are at high level, and the twenty-second node N22 is at low level. The first output terminal OUT1 outputs a high level signal. The second output terminal OUT2 outputs a low level signal.

[0339] According to the above working process, the second output terminal OUT2 outputs a high level signal in the first stage S91 and the second stage S92, and outputs a low level signal in the remaining stages. The first output terminal OUT1 outputs a low level signal in the second stage S92, and outputs a high level signal in the remaining stages.

[0340] In the present example, the polarities of the effective levels of the first output signal and the second output signal are opposite, for example, the effective level of the first output signal is low level, and the effective level of the second output signal is high level. The effective level time lengths of the first output signal and the second output signal in a frame are different. The effective level time length of the second output signal can be greater than 1.5 times the effective level time length of the first output signal. The absolute values of the voltages of the effective levels of the first output signal and the second output signal can be substantially the same.

[0341] In this example, the first output signal provided by the first output terminal OUT1 can be configured to enable the P-type transistor in the pixel circuit (i.e., the effective level of the first output signal is low), and the second output signal provided by the second output terminal OUT2 can be configured to enable the N-type transistor in the pixel circuit (i.e., the effective level of the second output signal is high). In some examples, the first and second output signals can be transmitted to the pixel circuit as scan signals. In some examples, the first output signal provided by the first output terminal of this stage of the drive control circuit can be transmitted to the signal input terminal of the next stage of the drive control circuit as the input signal of the next stage of the drive control circuit. However, this embodiment is not limited in this respect.

[0342] In this exemplary embodiment, the second output circuit 12 may include an inverting sub-circuit, which may include a twenty-first transistor T21 and a twenty-seventh transistor T27. The effective level (i.e., low level) of the second power supply signal provided by the second power supply line VGL is opposite in polarity to the effective level (i.e., high level) of the twenty-first transistor T21, and opposite in polarity to the effective level (i.e., low level) of the twenty-seventh transistor T27. In this example, by connecting the second output terminal at the twenty-second node N22, the signal at the twenty-third node N23 (i.e., the first control node) can be inverted and output to obtain the second output signal, thereby enabling the drive control circuit to provide two different output signals.

[0343] Figure 27 This is another schematic diagram of the drive control circuit according to at least one embodiment of the present disclosure. Figure 27As shown, the driving control circuit of the embodiment can include an input circuit 10, a first output circuit 11, a second output circuit 12, and a third output circuit 13. The input circuit 10 can include an input sub-circuit 101 and a control sub-circuit 102. The input sub-circuit 101 is electrically connected with a signal input terminal INPUT, a first clock terminal CK, and a first control node CP1, and is configured to control the potential of the first control node CP1 under the control of the signal input terminal INPUT and the first clock terminal CK. The control sub-circuit 102 is electrically connected with the first control node CP1, a first power line VGH, a second power line VGL, a first output control node OP1, and a second output control node OP2, and is configured to control the potentials of the first output control node OP1 and the second output control node OP2 under the control of the first control node CP1. The first output circuit 11 is electrically connected with the first output control node OP1, the second output control node OP2, and a first output terminal OUT1, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the first output control node OP1 and the second output control node OP2. The second output circuit 12 is electrically connected with the first control node CP1 and a second output terminal OUT2, and is configured to control the second output terminal OUT2 to output a third output signal under the control of the first control node CP1. The third output circuit 13 is electrically connected with the first control node CP1 and a third output terminal OUT3, and is configured to control the third output terminal OUT3 to output a third output signal under the control of the first control node CP1. The first output signal, the second output signal, and the third output signal are all different. However, the embodiment is not limited thereto. In other examples, the third output circuit can be electrically connected with the first output control node and the third output terminal, and be configured to control the third output terminal to output the third output signal under the control of the first output control node. Alternatively, the third output circuit can be electrically connected with the first output terminal and the third output terminal, and be configured to control the third output terminal to output the third output signal under the control of the first output terminal.

[0344] Figure 28 An equivalent circuit diagram of the driving control circuit of at least one embodiment of the present disclosure. Figure 29 As Figure 28 A working timing diagram of the driving control circuit.

[0345] In some example embodiments, as Figure 28As shown in the figure, the input sub-circuit 101 can include a twenty-second transistor T22. The control sub-circuit 102 can include a twenty-fourth transistor T24, a twenty-fifth transistor T25 and a twenty-sixth transistor T26. The first output circuit 11 can include a twenty-third transistor T23, a twenty-eighth transistor T28, an eleventh capacitor C11 and a twelfth capacitor C12. The second output circuit 12 can include a fifteenth transistor T15 and a sixteenth transistor T16. The third output circuit 13 can include a twenty-first transistor T21 and a twenty-seventh transistor T27.

[0346] The connection relationship of the transistors and the capacitors of the driving control circuit of the present embodiment can refer to the description of the driving control circuit as shown in the figure, which will not be repeated here. Figure 20 The connection relationship of the transistors and the capacitors of the driving control circuit of the present embodiment can refer to the description of the driving control circuit as shown in the figure, which will not be repeated here.

[0347] In the present example, the twenty-first node N21 and the twenty-second node N22 can be output control nodes. The twenty-second node N22 is a first output control node, and the twenty-first node N21 is a second output control node. The twenty-third node N23 can be a first control node. The third output terminal OUT3 is directly electrically connected with the twenty-second node N22. The fifteenth transistor T15 is a first output transistor, and the sixteenth transistor T16 is a second output transistor.

[0348] In some examples, the twenty-first transistor T21 and the sixteenth transistor T16 can be second semiconductor type transistors, for example, N-type transistors. The twenty-second transistor T22 to the twenty-eighth transistor T28 and the fifteenth transistor T15 can be first semiconductor type transistors, for example, P-type transistors. However, the present embodiment is not limited thereto.

[0349] As shown in the figure, the working process of the driving control transistor of the present embodiment can refer to the description of the working process of Figure 29 and Figure 20 , which will not be repeated here. Figure 21 As shown in the figure, in the first stage S71 and the second stage S72, the second output terminal OUT2 and the third output terminal OUT3 both output high-level signals, and output low-level signals in the remaining stages. The first output terminal OUT1 outputs a low-level signal in the second stage S72, and outputs a high-level signal in the remaining stages.

[0350] Figure 29

[0351] ​​In the example, the active level of the first output signal and the second output signal are opposite in polarity, and the active level of the second output signal and the third output signal are the same in polarity. For example, the active level of the first output signal is low, and the active level of the second output signal and the third output signal are high. The active level duration of the first output signal and the second output signal in a frame duration is different, and the active level duration of the second output signal can be greater than 1.5 times the active level duration of the first output signal. The voltage absolute value of the active level of the first output signal and the second output signal is different, and the voltage absolute value of the active level of the second output signal can be greater than the voltage absolute value of the active level of the first output signal. The voltage absolute value of the active level of the second output signal and the third output signal is different, and the voltage absolute value of the active level of the second output signal can be greater than the voltage absolute value of the active level of the third output signal. The active level duration of the second output signal and the third output signal in a frame duration can be substantially the same.

[0352] In the example, the first output signal provided by the first output terminal OUT1 can be configured to turn on the P-type transistor in the pixel circuit (i.e., the active level of the first output signal is low), and the second output signal provided by the second output terminal OUT2 and the third output signal provided by the third output terminal OUT3 can be configured to turn on the N-type transistor in the pixel circuit (i.e., the active level of the second output signal and the third output signal is high). In some examples, the first output signal provided by the first output terminal of the current stage driving control circuit can be transmitted to the signal input terminal of the next stage driving control circuit as the input signal of the next stage driving control circuit. However, the present embodiment is not limited thereto.

[0353] In the example, the second output circuit 12 can include an inverting sub-circuit which can include the fifteenth transistor T15 and the sixteenth transistor T16, and can implement inverting processing on the signal of the twenty-third node N23 (i.e., the first control node). The third output circuit 13 can include an inverting sub-circuit which can include the twenty-first transistor T21 and the twenty-seventh transistor T27, and can implement inverting processing on the signal of the twenty-third node N23 (i.e., the first control node). The present example can implement a driving control circuit outputting three different signals, and can meet the driving requirements of different types of pixel circuits.

[0354] The above driving control circuit provided by the present embodiment can be combined as needed to implement a driving control circuit outputting at least two different signals, thereby meeting the driving requirements of different types of pixel circuits. The present embodiment is not limited thereto.

[0355] Figure 30This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Figure 31 for Figure 30 The provided pixel circuit timing diagram is shown. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited thereto.

[0356] In some exemplary implementations, such as Figure 30 As shown, the pixel circuit in this example includes six switching transistors (M1, M2, M4 through M7), one driving transistor M3, and one storage capacitor Cst. The six switching transistors are, respectively, a data write transistor M4, a threshold compensation transistor M2, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a first reset transistor M1, and a second reset transistor M7. The light-emitting element EL includes an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0357] In some exemplary embodiments, the driving transistor and the six switching transistors can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the driving transistor and the six switching transistors may include both P-type and N-type transistors.

[0358] In some exemplary embodiments, the driving transistor and the six switching transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OPT TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0359] In some exemplary implementations, such as Figure 30As shown, the fourth power line VDD is configured to provide a constant high level signal to the pixel circuit, and the fifth power line VSS is configured to provide a constant low potential signal to the pixel circuit. The scan line GL is configured to provide a scan signal SCAN to the pixel circuit, the data line DL is configured to provide a data signal DATA to the pixel circuit, the light-emitting control line EML is configured to provide a light-emitting control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, in the nth row of pixel circuits, the first reset control line RST1 can be electrically connected with the scan line GL of the (n-1)th row of pixel circuits to be input with the scan signal SCAN(n-1), i.e., the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected with the scan line GL of the nth row of pixel circuits to be input with the scan signal SCAN(n), i.e., the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected with the nth row of pixel circuits and the first reset control line RST1 electrically connected with the (n+1)th row of pixel circuits can be an integral structure. Here, n is an integer. In this way, the signal lines of the display substrate can be reduced, and a narrow frame design of the display substrate can be achieved. However, the present embodiment is not limited in this regard.

[0360] In some example embodiments, the first initial signal line INIT1 is configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 is configured to provide a second initial signal to the pixel circuit. The first initial signal and the second initial signal can be the same or different in size. For example, the first initial signal and the second initial signal can be constant voltage signals, which can be, for example, between the first voltage signal and the second voltage signal, but are not limited thereto.

[0361] In some example embodiments, as Figure 30As shown, the gate of data writing transistor M4 is electrically connected to scan line GL, the first terminal of data writing transistor M4 is electrically connected to data line DL, and the second terminal of data writing transistor M4 is electrically connected to the first terminal of driving transistor M3. The gate of threshold compensation transistor M2 is electrically connected to scan line GL, the first terminal of threshold compensation transistor M2 is electrically connected to the gate of driving transistor M3, and the second terminal of threshold compensation transistor M2 is electrically connected to the second terminal of driving transistor M3. The gate of first light-emitting control transistor M5 is electrically connected to light-emitting control line EML, the first terminal of first light-emitting control transistor M5 is electrically connected to fourth power line VDD, and the second terminal of first light-emitting control transistor M5 is electrically connected to the first terminal of driving transistor M3. The gate of second light-emitting control transistor M6 is electrically connected to light-emitting control line EML, the first terminal of second light-emitting control transistor M6 is electrically connected to the second terminal of driving transistor M3, and the second terminal of second light-emitting control transistor M6 is electrically connected to the anode of light-emitting element EL. The first reset transistor M1 is electrically connected to the gate of the driving transistor M3 and configured to reset the gate of the driving transistor M3. The second reset transistor M7 is electrically connected to the anode of the light-emitting element EL and configured to reset the anode of the light-emitting element EL. The gate of the first reset transistor M1 is electrically connected to the first reset control line RST1, the first terminal of the first reset transistor M1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first reset transistor M1 is electrically connected to the gate of the driving transistor M3. The gate of the second reset transistor M7 is electrically connected to the second reset control line RST2, the first terminal of the second reset transistor M7 is electrically connected to the second initial signal line INIT2, and the second terminal of the second reset transistor M7 is electrically connected to the anode of the light-emitting element EL. The first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M3, and the second plate of the storage capacitor Cst is electrically connected to the fourth power supply line VDD.

[0362] In this example, the first pixel node P1 is the connection point of the storage capacitor Cst, the first reset transistor M1, the driving transistor M3 and the threshold compensation transistor M2; the second pixel node P2 is the connection point of the first light-emitting control transistor M5, the data writing transistor M4 and the driving transistor M3; the third pixel node P3 is the connection point of the driving transistor M3, the threshold compensation transistor M2 and the second light-emitting control transistor M6; and the fourth pixel node P4 is the connection point of the second light-emitting control transistor M6, the second reset transistor M7 and the light-emitting element EL.

[0363] The following reference Figure 31 right Figure 30 The working process of the pixel circuit is illustrated below. Figure 30 The pixel circuit shown is illustrated using P-type transistors as an example.

[0364] In some example embodiments, as shown in FIG. 1, the working process of the pixel circuit in a frame display period includes a first stage S111, a second stage S112 and a third stage S113. Figure 31

[0365] The first stage S111 is called a reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, the first reset transistor M1 is turned on, the first initial signal provided by the first initial signal line INIT1 is provided to the first pixel node P1, the first pixel node P1 is initialized, and the original data voltage in the storage capacitor Cst is cleared. The scan signal SCAN provided by the scan line GL is a high-level signal, the emission control signal EM provided by the emission control line EML is a high-level signal, the data write transistor M4, the threshold compensation transistor M2, the first emission control transistor M5 and the second emission control transistor M6 are disconnected, the second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, the second reset transistor M7 is turned on, and the second initial signal provided by the second initial signal line INIT2 is provided to the fourth pixel node P4 to reset the anode of the light emitting element EL. In this stage, the light emitting element EL does not emit light.

[0366] ​In the second stage S112, referred to as a data writing stage or a threshold compensation stage, the scan signal SCAN provided by the scan line GL is a low-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the emission control signal EM provided by the emission control line EML are high-level signals, and the data signal DATA is output by the data line DL. In this stage, the first plate of the storage capacitor Cst is at a low level, so the driving transistor M3 is turned on. The scan signal SCAN is a low-level signal, which turns on the threshold compensation transistor M2 and the data writing transistor M4. The threshold compensation transistor M2 and the data writing transistor M4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first pixel node P1 through the second pixel node P2, the turned-on driving transistor M3, the third pixel node P3, and the turned-on threshold compensation transistor M2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor M3 is charged into the storage capacitor Cst, so that the voltage of the first plate of the storage capacitor Cst (i.e., the first pixel node P1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the driving transistor M3. The second reset control signal provided by the second reset control line RST2 is a low-level signal, the second reset transistor M7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light emitting element EL, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage in the anode of the light emitting element EL is emptied, the initialization is completed, and it is ensured that the light emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, so that the first reset transistor M1 is disconnected. The emission control signal EM provided by the emission control signal line EML is a high-level signal, so that the first emission control transistor M5 and the second emission control transistor M6 are disconnected.

[0367] In the third stage S113, referred to as an emission stage, the emission control signal EM provided by the emission control signal line EML is a low-level signal, the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The emission control signal EM provided by the emission control signal line EML is a low-level signal, which turns on the first emission control transistor M5 and the second emission control transistor M6, the high-level signal output by the first power supply line PL1 is provided to the anode of the light emitting element EL through the turned-on first emission control transistor M5, the driving transistor M3, and the second emission control transistor M6 to provide a driving voltage to the anode of the light emitting element EL, and the light emitting element EL is driven to emit light. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the second reset transistor M7 is turned off.

[0368] In the driving process of the pixel circuit, the driving current flowing through the driving transistor M3 is determined by the voltage difference between the gate and the first electrode of the driving transistor M3. Since the voltage of the first pixel node P1 is Vdata-|Vth|, the driving current of the driving transistor M3 is:

[0369] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0370] wherein I is the driving current flowing through the driving transistor M3, that is, the driving current of the light emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor M3, Vth is the threshold voltage of the driving transistor M3, Vdata is the data voltage output by the data line DL, and VDD is the high level signal output by the first power supply line VDD.

[0371] It can be seen from the above formula that the current flowing through the light emitting element EL is independent of the threshold voltage of the driving transistor M3. Therefore, the pixel circuit of the embodiment can compensate the threshold voltage of the driving transistor M3 well.

[0372] In some examples, Figure 4 or Figure 6 the first output signal of the driving control circuit shown in Figure 30 may be provided as a light emitting control signal to the pixel circuit shown in Figure 4 or Figure 6 the second output signal of the driving control circuit shown in Figure 30 may be provided as a second reset control signal to the pixel circuit shown in Figure 30 In other examples, the threshold compensation transistor M2 of the pixel circuit shown in Figure 2 or Figure 12 the first output signal of the driving control circuit shown in Figure 2 or Figure 12 may be configured to turn on the data writing transistor M4 in the pixel circuit. In other examples, Figure 30 the second reset transistor M7 of the pixel circuit shown in Figure 16 or Figure 18 the first output signal of the driving control circuit shown in Figure 16 or Figure 18The second output signal of the driving control circuit shown can be provided to the pixel circuit as a second reset control signal. In other examples, Figure 30 The first light emitting control transistor and the second light emitting control transistor of the pixel circuit shown can be N-type transistors, Figure 22 Or Figure 24 The first output signal of the driving control circuit shown can be provided to the pixel circuit as a light emitting control signal, Figure 22 Or Figure 24 The second output signal shown can be provided to the pixel circuit as a second reset control signal. However, the present embodiment is not limited in this regard.

[0373] The present disclosure also provides a gate driving circuit including a plurality of cascaded driving control circuits.

[0374] Figure 32 A schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure. As Figure 32 The gate driving circuit provided by the present example embodiment can include a plurality of cascaded driving control circuits GOA, as

[0375] In the present example implementation, as Figure 32 The signal input end INPUT of the first driving control circuit GOA(1) is connected to the start signal line STV, and the signal input end of the (i+1)th driving control circuit GOA(i+1) is electrically connected to the first output end of the ith driving control circuit GOA(i). Here, i is an integer greater than 0.

[0376] In some example implementations, the first clock end CK of the plurality of driving control circuits is electrically connected to the first clock signal line CKL and configured to receive a first clock signal; and the second clock end CB is electrically connected to the second clock signal line CBL and configured to receive a second clock signal. The first clock signal and the second clock signal can both be pulse signals. For example, the duty cycles of the first clock signal and the second clock signal can be substantially the same, and the first clock signal and the second clock signal are not low at the same time. The plurality of driving control circuits are also respectively electrically connected to the second power supply line VGL that continuously provides a low-level signal and the first power supply line VGH that continuously provides a high-level signal. However, the present embodiment is not limited in this regard.

[0377] In some example embodiments, the first clock terminal CK of the kth-stage driving control circuit is electrically connected with the first clock signal line CKL, and the second clock terminal CB is electrically connected with the second clock signal line CBL; the first clock terminal CK of the k+1th-stage driving control circuit is electrically connected with the second clock signal line CBL, and the second clock terminal CB is electrically connected with the first clock signal line CKL. Wherein, k is equal to 2n or 2n-1, and n is an integer greater than 0. Two cascaded driving control circuits of the gate driving circuit of the present example can serve as a minimum period repetition unit to drive two rows of sub-pixels of the display area. However, the present embodiment is not limited thereto.

[0378] Figure 33 A top view of the driving control circuit of at least one embodiment of the present disclosure. Figure 34 A top view of the driving control circuit of at least one embodiment of the present disclosure. Figure 33 A partial cross-sectional view along the P-P' direction. The equivalent circuit of the driving control circuit of the present example can be as shown in Figure 2 In the present example embodiment, the first transistor T1 to the ninth transistor T9 in the driving control circuit are taken as P-type transistors and low-temperature polysilicon thin film transistors, and the tenth transistor T10 is taken as an N-type transistor and an oxide thin film transistor. However, the present embodiment is not limited thereto.

[0379] In some example embodiments, as shown in Figure 33 In the plane parallel to the display substrate, the second output circuit is located between the second power line VGL and the input circuit in the first direction X, the first output circuit and the first power line VGH are located on the side of the input circuit away from the second input circuit in the first direction X, and the clock signal line (for example, including the first clock signal line CKL and the second clock signal line CBL) is located on the side of the second power line VGL away from the second output circuit in the first direction X. In other words, the clock signal line, the second power line VGL, the second output circuit, the input circuit and the first output circuit are arranged in sequence along the first direction X. Wherein, the first clock signal line CKL can be located between the second clock signal line CBL and the second power line VGL. The first power line VGH overlaps with the first output circuit in the orthographic projection of the substrate. However, the present embodiment is not limited thereto.

[0380] In some example embodiments, as shown in Figure 33As shown, in a plane parallel to the display substrate, the ninth transistor T9 and the tenth transistor T10 of the second output circuit can be arranged in the second direction Y in sequence. The third transistor T3 and the eighth transistor T8 of the first output circuit can be arranged in the second direction Y in sequence. The first capacitor C1 and the second capacitor C2 can be arranged in the second direction Y in sequence, and the first power supply line VGH has an overlap with the first capacitor C1 and the second capacitor C2 in the orthographic projection of the substrate. The third transistor T3 and the first capacitor C1 are adjacent in the first direction X, and the eighth transistor T8 and the second capacitor C2 are adjacent in the first direction X. The seventh transistor T7 of the input circuit is located between the first transistor T1 and the second transistor T2 in the first direction X, and the first transistor T1 is adjacent to the ninth transistor T9 and the tenth transistor T10 of the second output circuit in the first direction X. The fourth transistor T4 and the fifth transistor T5 are arranged in the second direction Y in sequence and are located between the second transistor T2 and the eighth transistor T8 in the first direction X. The sixth transistor T6 is located between the second transistor T2 and the fifth transistor T5 in the first direction X. The second direction Y is in the same plane as the first direction X, and the first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0381] In some example embodiments, as Figure 34 As shown, in a direction perpendicular to the display substrate, the non-display area of the display substrate can include: a substrate 20, a first semiconductor layer 31, a first conductive layer 41, a second semiconductor layer 32, a second conductive layer 42, a third conductive layer 43, and a fourth conductive layer 44 arranged in sequence on the substrate 20. Among them, the first insulating layer 21 is arranged between the first semiconductor layer 31 and the first conductive layer 41, the second insulating layer 22 is arranged between the first conductive layer 41 and the second semiconductor layer 32, the third insulating layer 23 is arranged between the second semiconductor layer 32 and the second conductive layer 42, the fourth insulating layer 24 is arranged between the second conductive layer 42 and the third conductive layer 43, and the fifth insulating layer 25 is arranged between the third conductive layer 43 and the fourth conductive layer 44. In some examples, the first insulating layer 21 to the fifth insulating layer 25 can all be inorganic insulating layers. However, the present embodiment is not limited thereto.

[0382] Figure 35A For Figure 33 A top view of the drive control circuit after the first semiconductor layer is formed. As Figures 33 to 35AAs shown, the first semiconductor layer 31 of the non-display region at least includes active layers of a plurality of first semiconductor transistors of a drive control circuit. For example, the first semiconductor layer 31 at least includes an active layer 110 of a first transistor T1, an active layer 120 of a second transistor T2, an active layer 130 of a third transistor T3, an active layer 140 of a fourth transistor T4, an active layer 150 of a fifth transistor T5, an active layer 160 of a sixth transistor T6, an active layer 170 of a seventh transistor T7, an active layer 180 of an eighth transistor T8, and an active layer 190 of a ninth transistor T9.

[0383] In some example embodiments, as shown in FIG. 1A, the active layer 110 of the first transistor T1, the active layer 120 of the second transistor T2, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the active layer 150 of the fifth transistor T5, the active layer 160 of the sixth transistor T6, the active layer 170 of the seventh transistor T7, and the active layer 180 of the eighth transistor T8 all extend along the second direction Y, and the active layer 190 of the ninth transistor T9 extends along the first direction X. Figure 35A

[0384] In some example embodiments, as shown in FIG. 1A, the active layer 110 of the first transistor T1, the active layer 120 of the second transistor T2, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the active layer 150 of the fifth transistor T5, the active layer 160 of the sixth transistor T6, the active layer 170 of the seventh transistor T7, and the active layer 180 of the eighth transistor T8 all extend along the second direction Y, and the active layer 190 of the ninth transistor T9 extends along the first direction X. Figure 35A In some example embodiments, as shown in FIG. 1A, the active layer 140 of the fourth transistor T4 and the active layer 150 of the fifth transistor T5 can be an integral structure, for example, can be in a long strip shape. The active layer 130 of the third transistor T3 and the active layer 180 of the eighth transistor T8 can be an integral structure, for example, in a “N” shape. However, the present embodiments are not limited thereto.

[0385] In some example embodiments, the material of the first semiconductor layer 31 can include, for example, polysilicon. The active layer can include at least one channel region and a plurality of doped regions. The channel region can not be doped with impurities and have semiconductor properties. The plurality of doped regions can be on both sides of the channel region and doped with impurities and thus have electrical conductivity. The impurities can vary depending on the type of transistor. The doped regions of the active layer can be interpreted as the source electrode or the drain electrode of the transistor. For example, the first pole of the transistor can correspond to the periphery of the channel region of the active layer, the first doped region doped with impurities; the second pole of the transistor can correspond to the periphery of the channel region of the active layer, the second doped region doped with impurities. In addition, the part of the active layer between the transistors can be interpreted as a wiring doped with impurities and can be used to electrically connect the transistors.

[0386] Figure 35A ​​As shown, the active layer 110 of the first transistor T1 can include a channel region 110a, and a first doped region 110b and a second doped region 110c located on both sides of the channel region 110a along the second direction Y. The active layer 120 of the second transistor T2 can include a channel region 120a, and a first doped region 120b and a second doped region 120c located on both sides of the channel region 120a along the second direction Y. The active layer 130 of the third transistor T3 can include a channel region 130a, and a first doped region 130b and a second doped region 130c located on both sides of the channel region 130a along the second direction Y. The active layer 140 of the fourth transistor T4 can include a channel region 140a, and a first doped region 140b and a second doped region 140c located on both sides of the channel region 140a along the second direction Y. The active layer 150 of the fifth transistor T5 can include a channel region 150a, and a first doped region 150b and a second doped region 150c located on both sides of the channel region 150a along the second direction Y. The first doped region 150b of the fifth transistor T5 and the second doped region 140c of the fourth transistor T4 are connected. The active layer 160 of the sixth transistor T6 can include a channel region 160a, and a first doped region 160b and a second doped region 160c located on both sides of the channel region 160a along the second direction Y. The active layer 170 of the seventh transistor T7 can include a channel region 170a, and a first doped region 170b and a second doped region 170c located on both sides of the channel region 170a along the second direction Y. The active layer 180 of the eighth transistor T8 can include channel regions 180a1, 180a2 and 180a3 arranged in sequence along the second direction Y, a first doped region 180b1 and a second doped region 180c1 located on both sides of the channel region 180a1 along the second direction Y, a third doped region 180b2 and a fourth doped region 180c2 located on both sides of the channel region 180a3 along the second direction Y. The second doped region 180c1 of the eighth transistor T8 and the second doped region 130c of the third transistor T3 are connected.

[0387] Figure 35B For Figure 33 A top view of the driving control circuit after the first conductive layer is formed in the middle. As Figures 33 to 35BAs shown, the first conductive layer 41 of the non-display region at least includes: a control electrode of a first semiconductor transistor of the drive control circuit, and a first plate of a plurality of capacitors. For example, the first conductive layer 41 can include: a control electrode 111 of a first transistor T1, control electrodes 121a and 121b of a second transistor T2, a control electrode 131 of a third transistor T3, a control electrode 141 of a fourth transistor T4, a control electrode 151 of a fifth transistor T5, a control electrode 161 of a sixth transistor T6, a control electrode 171 of a seventh transistor T7, control electrodes 181a, 181b and 181c of an eighth transistor T8, a first plate C1-1 of a first capacitor C1, and a first plate C2-1 of a second capacitor C2.

[0388] In some examples, as Figure 35B shown, the control electrode 111 of the first transistor T1 and the control electrodes 121a and 121b of the second transistor T2 can be an integrated structure. The control electrode 131 of the third transistor T3, the control electrode 141 of the fourth transistor T4, and the first plate C1-1 of the first capacitor C1 can be an integrated structure. The control electrodes 181a, 181b and 181c of the eighth transistor T8 and the first plate C2-1 of the second capacitor C2 can be an integrated structure. However, the present embodiment is not limited thereto.

[0389] In the present example, the second transistor T2 can be a double-gate transistor, and the eighth transistor T8 can be a triple-gate transistor, to prevent and reduce the occurrence of leakage current. However, the present embodiment is not limited thereto.

[0390] Figure 35C For Figure 33 example, the second conductive layer 42 can include: a first plate C1-2 of the first capacitor C1, a first plate C2-2 of the second capacitor C2, a first plate C3-1 of a third capacitor C3, a first plate C4-1 of a fourth capacitor C4, a first plate C5-1 of a fifth capacitor C5, a first plate C6-1 of a sixth capacitor C6, a first plate C7-1 of a seventh capacitor C7, and a first plate C8-1 of an eighth capacitor C8. Figures 33 to 35C As shown, the second semiconductor layer 32 of the non-display region at least includes: an active layer of a second semiconductor transistor of the drive control circuit. For example, the second semiconductor layer 32 can include: an active layer 200 of a tenth transistor T10. In some examples, the material of the second semiconductor layer 32 can include IGZO. The active layer 200 of the tenth transistor T10 extends along the first direction X. The active layer 200 of the tenth transistor T10 can include: a channel region 200a, and a first region 200b and a second region 200c located on both sides of the channel region 200a along the first direction X. The first region 200b corresponds to a first electrode of the tenth transistor T10, and the second region 200c corresponds to a second electrode of the tenth transistor T10.

[0391] Figure 35D For Figure 33 example, the second conductive layer 42 can include: a first plate C1-2 of the first capacitor C1, a first plate C2-2 of the second capacitor C2, a first plate C3-1 of a third capacitor C3, a first plate C4-1 of a fourth capacitor C4, a first plate C5-1 of a fifth capacitor C5, a first plate C6-1 of a sixth capacitor C6, a first plate C7-1 of a seventh capacitor C7, and a first plate C8-1 of an eighth capacitor C8. Figures 33 to 35DAs shown, the second conductive layer 42 of the non-display region at least includes: a control electrode of a second semiconductor transistor of the drive control circuit, a second plate of a plurality of capacitors. For example, the second conductive layer 42 can include: a control electrode 201 of the tenth transistor T10, a control electrode 191 of the ninth transistor T9, a second plate C1-2 of the first capacitor C1, a second plate C2-2 of the second capacitor C2, and a first connection electrode L1. The second plate C1-2 of the first capacitor C1 is located within the first plate C1-1 in the orthographic projection of the substrate, and the second plate C2-2 of the second capacitor C2 is located within the first plate C2-1 in the orthographic projection of the substrate. The orthographic projection of the first connection electrode L1 on the substrate can not overlap with the orthographic projection of the first semiconductor layer 31, the first conductive layer 41 and the second semiconductor layer 32 on the substrate.

[0392] In some examples, as Figure 35D As shown, the control electrode 191 of the ninth transistor T9 and the control electrode 201 of the tenth transistor T10 can be an integral structure, for example, can be in a strip shape extending along the second direction Y. However, the present embodiment is not limited thereto.

[0393] Figure 35E As Figure 33 A top view of the drive control circuit after the fourth insulating layer is formed. As Figures 33 to 35E As shown, a plurality of vias are formed on the fourth insulating layer 24 of the non-display region. The plurality of vias can include: a plurality of first type vias, a plurality of second type vias, a plurality of third type vias and a plurality of fourth type vias. The fourth insulating layer 24, the third insulating layer 23, the second insulating layer 22 and the first insulating layer 21 in the first type via are removed, exposing the surface of the first semiconductor layer 31. The fourth insulating layer 24, the third insulating layer 23 and the second insulating layer 22 in the second type via are removed, exposing the surface of the first conductive layer 41. The fourth insulating layer 24 and the third insulating layer 23 in the third type via are removed, exposing the surface of the second semiconductor layer 32. The fourth insulating layer 24 in the fourth type via is removed, exposing the surface of the second conductive layer 42. For example, the first type via can include: the first via K1 to the seventeenth via K17, the second type via can include: the eighteenth via K18 to the twenty-third via K23, the third type via can include: the twenty-fourth via K24 and the twenty-fifth via K25, and the fourth type via can include: the twenty-sixth via K26 to the thirtieth via K30.

[0394] Figure 35F As Figure 33 A top view of the drive control circuit after the third conductive layer is formed. As Figures 33 to 35FAs shown, the third conductive layer 43 of the non-display region can include a plurality of connection electrodes (e.g., the second connection electrode L2 to the thirteenth connection electrode L13), the first output terminal OUT1, the signal input terminal INPUT, the first power line VGH, and the second power line VGL. The first power line VGH and the second power line VGL can each extend along the second direction Y. The signal input terminal INPUT of the current stage of the drive control circuit can be electrically connected with the first output terminal of the previous stage of the drive control circuit, for example, both can be an integral structure. However, the present embodiment is not limited thereto. In other examples, the signal input terminal of the current stage of the drive control circuit can be located on the fourth conductive layer and can be electrically connected with the first output terminal of the previous stage of the drive control circuit located on the third conductive layer through a connection electrode.

[0395] In some examples, as Figures 33 to 35FAs shown, the second connection electrode L2 can be electrically connected with the second doped region 190c of the active layer 190 of the ninth transistor T9 through the sixteenth via hole K16, and can be electrically connected with the second region 200c of the active layer 200 of the tenth transistor T10 through the twenty-fourth via hole K24. The third connection electrode L3 can be electrically connected with the first doped region 110b of the active layer 110 of the first transistor T1 through the first via hole K1. The fifth connection line L5 can be electrically connected with the first region 200b of the active layer 200 of the tenth transistor T10 through the twenty-fifth via hole K25, and can be electrically connected with the control electrode 161 of the sixth transistor T6 through two twenty-first via holes K21 arranged side by side. The third connection line L3, the fifth connection line L5 and the second power supply line VGL can be an integral structure. The fourth connection electrode L4 can be electrically connected with the first doped region 190b of the active layer 190 of the ninth transistor T9 through the seventeenth via hole K17. The sixth connection electrode L6 can be electrically connected with the second doped region 110c of the active layer 110 of the first transistor T1 through the second via hole K2, and can be electrically connected with the second doped region 170c of the active layer 170 of the seventh transistor T7 through the tenth via hole K10, and can be electrically connected with the first connection electrode L1 through the twenty-seventh via hole K27. The seventh connection electrode L7 can be electrically connected with the second doped region 120c of the active layer 120 of the second transistor T2 through the fourth via hole K4, and can be electrically connected with the control electrode 171 of the seventh transistor T7 through the twentieth via hole K20, and can be electrically connected with the first doped region 160b of the active layer 160 of the sixth transistor T6 through the seventh via hole K7, and can be electrically connected with the second doped region 150c of the active layer 150 of the fifth transistor T5 through the sixth via hole K6. The eighth connection electrode L8 can be electrically connected with the first connection electrode L1 through two twenty-eighth via holes K28 arranged in vertical rows, and can be electrically connected with the control electrode 141 of the fourth transistor T4 through the nineteenth via hole K19. The ninth connection electrode L9 can be electrically connected with the second doped region 160c of the active layer 160 of the sixth transistor T6 through the eighth via hole K8, and can be electrically connected with the control electrode 181c of the eighth transistor T8 through two twenty-third via holes K23 arranged side by side. The tenth connection electrode L10 can be electrically connected with the control electrode 151 of the fifth transistor T5 through two twenty-second via holes K22 arranged side by side, and can be electrically connected with the first doped region 180b1 of the active layer 180 of the eighth transistor T8 through three thirteenth via holes K13 arranged side by side, and can be electrically connected with the third doped region 180b2 of the active layer 180 of the eighth transistor T8 through ten fourteenth via holes K14 arranged side by side. The eleventh connection electrode L11 can be electrically connected with the first doped region 140b of the active layer 140 of the fourth transistor T4 through the fifth via hole K5, and can be electrically connected with the first doped region 130b of the active layer 130 of the third transistor T3 through a plurality (for example, six) eleventh via holes K11 arranged side by side.The eleventh connecting electrode L11 and the first power line VGH can be an integral structure. The first power line VGH can be electrically connected to the second plate C1-2 of the first capacitor C1 through two parallel twenty-ninth vias K29. The twelfth connecting electrode L12 can be electrically connected to the second doped region 130c of the active layer 130 of the third transistor T3 through multiple (e.g., six) parallel twelfth vias K12, and can also be electrically connected to the second doped region 180c1 of the active layer 180 of the eighth transistor T8 through multiple (e.g., ten) parallel twelfth vias K12, and can also be electrically connected to the fourth doped region 180c2 of the active layer 180 of the eighth transistor T8 through multiple (e.g., ten) parallel fifteenth vias K15, and can also be electrically connected to the second plate C2-2 of the second capacitor C2 through two vertically arranged thirtieth vias K30. The twelfth connecting electrode L12 and the first output terminal OUT1 can be an integral structure. The first output terminal OUT1 can be electrically connected to the control electrode 201 of the tenth transistor T10 through the twenty-sixth via K26. The thirteenth connection electrode L13 can be electrically connected to the first doped region 170b of the active layer 170 of the seventh transistor T7 through the ninth via K9, and can also be electrically connected to the control electrode 121a of the second transistor T2 through the eighteenth via K18. The signal input terminal INPUT can be electrically connected to the first doped region 120b of the active layer 120 of the second transistor T2 through the third via K3.

[0396] In the embodiments of this disclosure, "side-by-side arrangement" can mean arranged sequentially along the first direction X, and "vertical arrangement" can mean arranged sequentially along the second direction Y.

[0397] Figure 35G for Figure 33 A top view of the drive control circuit after the fifth insulating layer has been formed. (See attached image.) Figures 33 to 35G As shown, the fifth insulating layer 25 in the non-display area has multiple vias, such as multiple fifth-type vias and sixth-type vias. The fifth insulating layer 25, fourth insulating layer 24, third insulating layer 23, and second insulating layer 22 within the fifth-type vias are removed, exposing the surface of the first conductive layer 41. The fifth insulating layer 25 within the sixth-type vias is removed, exposing the surface of the third conductive layer 43. For example, the fifth-type vias may include the thirty-first via K31 and the thirty-second via K32. The sixth-type vias may include the thirty-third via K33 to the thirty-fifth via K35.

[0398] In some exemplary implementations, such as Figures 33 to 35GAs shown, the fourth conductive layer 44 in the non-display area may include: a first clock signal line CKL, a second clock signal line CBL, a second output terminal OUT2, and a fourteenth connection electrode L14. Both the first clock signal line CKL and the second clock signal line CBL extend along the second direction Y. The second output terminal OUT2 extends along the second direction Y and is located on the side of the second power line VGL near the second output circuit in the first direction X. However, this embodiment is not limited to this. In other examples, the first clock signal line and the second clock signal line may be located in the third conductive layer, and the first power line and the second power line may be located in the fourth conductive layer.

[0399] In some examples, such as Figures 33 to 35G As shown, the second output terminal OUT2 can be electrically connected to the second connecting electrode L2 through the thirty-third via K33. In this example, the first output terminal OUT1 and the second output terminal OUT2 are of different layers, with the second output terminal OUT2 located on the side of the first output terminal OUT1 away from the substrate. In the second direction Y, the first output terminal OUT1 and the second output terminal OUT2 are located on opposite sides of the drive control circuit of this stage, and the extension directions of the first output terminal OUT1 and the second output terminal OUT2 are opposite.

[0400] In some examples, such as Figures 33 to 35G As shown, the first clock signal line CKL is electrically connected to the control electrode 111 of the first transistor T1 through two vertically arranged 32 vias K32. The second clock signal line CBL is electrically connected to the control electrode 151 of the fifth transistor T5 through two vertically arranged 31 vias K31. The fourteenth connecting electrode L14 can be electrically connected to the fourth connecting electrode L4 through the 34th via K34, and can also be electrically connected to the eleventh connecting electrode L11 through the 35th via K35, thereby realizing the electrical connection between the second output circuit and the first power supply line VGH.

[0401] In this exemplary embodiment, by placing the second output circuit between the second power line and the input circuit, the layout of the drive control circuit can be optimized, thereby saving space.

[0402] Figure 36 This is another top view of the drive control circuit of at least one embodiment of the present disclosure. Figure 37 for Figure 36 A partial cross-sectional schematic diagram along the Q-Q' direction. The equivalent circuit of the drive control circuit in this exemplary embodiment can be as follows: Figure 4 As shown. In this exemplary embodiment, the example is given where the thirty-first transistor T31 to the forty-fourth transistor T44 in the drive control circuit are P-type transistors and LTPS transistors, and the forty-fifth transistor T45 is an N-type transistor and an oxide thin-film transistor. However, this embodiment is not limited in this respect.

[0403] In some exemplary implementations, such as Figure 36 As shown, in a plane parallel to the display substrate, the second output circuit is located between the input circuit and the first output circuit in the first direction X. The input circuit and the second output circuit are located between a clock signal line (e.g., including a first clock signal line CKL and a second clock signal line CBL) and a first power supply line VGH in the first direction X. The first clock signal line CKL is located on the side of the second clock signal line CBL away from the input circuit in the first direction X. In other words, the clock signal line, the input circuit, the second output circuit, and the first output circuit are arranged sequentially along the first direction X. The orthographic projection of the first second power supply line VGL1 onto the substrate overlaps with the orthographic projection of the input circuit onto the substrate. The second second power supply line VGL2 is located on the side of the first power supply line VGH away from the second output circuit in the first direction X. That is, the first power supply line VGH is located between the second output circuit and the second second power supply line VGL in the first direction X. The orthographic projection of the second second power supply line VGL2 onto the substrate overlaps with the orthographic projection of the first output circuit onto the substrate. The orthographic projection of the first power supply line VGH onto the substrate overlaps with the orthographic projection of the first output circuit onto the substrate.

[0404] In some exemplary implementations, such as Figure 36 As shown, in a plane parallel to the display substrate, the forty-fourth transistor T44 and the forty-fifth transistor T45 of the second output circuit are arranged sequentially along the second direction Y. The fortieth transistor T40 and the thirty-ninth transistor T39 of the first output circuit are arranged sequentially along the second direction Y. The third capacitor C3 is adjacent to the thirty-ninth transistor T39 in the first direction X and is located on the side of the thirty-ninth transistor T39 closer to the input circuit. The orthographic projection of the third capacitor C3 onto the substrate overlaps with the orthographic projection of the first power line VGH onto the substrate. The orthographic projection of the second power line VGL2 onto the substrate overlaps with the orthographic projections of the thirty-ninth transistor T39 and the fortieth transistor T40 onto the substrate.

[0405] In some exemplary implementations, such as Figure 36 As shown, the forty-second transistor T42, the thirty-third transistor T33, and the thirty-first transistor T31 of the input circuit are arranged sequentially along the second direction Y, and located between the second clock signal line CBL and the first second power supply line VGL1 in the first direction X. The forty-first transistor T41 and the thirty-second transistor T32 are arranged sequentially along the second direction Y. The forty-first transistor T41 is adjacent to the forty-second transistor T42 in the first direction X. The thirty-second transistor T32 is adjacent to both the thirty-first transistor T31 and the thirty-third transistor T33 in the first direction X.

[0406] In some examples, such as Figure 36 As shown, multiple start signal lines (e.g., start signal lines STV1, STV2, and STV3) and a first control signal line NXL are disposed between the first second power supply line VGL1 and the first power supply line VGH. The multiple start signal lines are arranged sequentially along a first direction X. Start signal line STV1 can provide an input signal to the first-stage drive control circuit of this example, and start signal lines STV2 and STV3 can provide input signals to the first-stage drive control circuits of the remaining gate control circuits. The first control signal line NXL is located between the start signal line STV3 and the first power supply line VGH. However, this embodiment is not limited in this respect.

[0407] In some examples, such as Figure 36 As shown, transistors T34, T35, T43, T38, T36, and T37 can be arranged sequentially along the second direction Y, and are all located between the start signal line STV3 and the first control signal line NXL. The fourth capacitor C4 is located in the second direction Y between transistor T34 and the second output terminal OUT2. The fifth capacitor C5 is located in the second direction Y between transistors T36 and T37.

[0408] In some exemplary implementations, such as Figure 37 As shown, in the direction perpendicular to the display substrate, the non-display area of ​​the display substrate may include: a substrate 20, and a first semiconductor layer 31, a first conductive layer 41, a second semiconductor layer 32, a second conductive layer 42, a third conductive layer 43, and a fourth conductive layer 44 sequentially disposed on the substrate 20. Specifically, a first insulating layer 21 is disposed between the first semiconductor layer 31 and the first conductive layer 41; a second insulating layer 22 is disposed between the first conductive layer 41 and the second semiconductor layer 32; a third insulating layer 23 is disposed between the second semiconductor layer 32 and the second conductive layer 42; a fourth insulating layer 24 is disposed between the second conductive layer 42 and the third conductive layer 43; and a fifth insulating layer 25 is disposed between the third conductive layer 43 and the fourth conductive layer 44. In some examples, the first insulating layer 21 to the fifth insulating layer 25 may all be inorganic insulating layers. However, this embodiment is not limited to this.

[0409] Figure 38A for FIG. 36 A top view of the drive control circuit after the first semiconductor layer has been formed. (See attached image.) FIGS. 36-38AAs shown, the first semiconductor layer 31 of the non-display region at least includes an active layer of a first semiconductor transistor of a drive control circuit. For example, the first semiconductor layer 31 at least includes an active layer 310 of the thirty-first transistor T31, an active layer 320 of the thirty-second transistor T32, an active layer 330 of the thirty-third transistor T33, an active layer 340 of the thirty-fourth transistor T34, an active layer 350 of the thirty-fifth transistor T35, an active layer 360 of the thirty-sixth transistor T36, an active layer 370 of the thirty-seventh transistor T37, an active layer 380 of the thirty-eighth transistor T38, an active layer 390 of the thirty-ninth transistor T39, an active layer 400 of the fortieth transistor T40, an active layer 410 of the forty-first transistor T41, an active layer 420 of the forty-second transistor T42, and an active layer 440 of the forty-fourth transistor T44.

[0410] In some examples, as shown in FIG. 1A, the active layer 310 of the thirty-first transistor T31, the active layer 320 of the thirty-second transistor T32, the active layer 330 of the thirty-third transistor T33, the active layer 350 of the thirty-fifth transistor T35, the active layer 370 of the thirty-seventh transistor T37, the active layer 380 of the thirty-eighth transistor T38, the active layer 410 of the forty-first transistor T41, and the active layer 420 of the forty-second transistor T42 can each extend along the second direction Y. The active layer 340 of the thirty-fourth transistor T34, the active layer 360 of the thirty-sixth transistor T36, the active layer 390 of the thirty-ninth transistor T39, the active layer 400 of the fortieth transistor T40, the active layer 430 of the forty-third transistor T43, and the active layer 440 of the forty-fourth transistor T44 can each extend along the first direction X. The active layer 340 of the thirty-fourth transistor T34, the active layer 350 of the thirty-fifth transistor T35, the active layer 380 of the thirty-eighth transistor T38, and the active layer 430 of the forty-third transistor T43 can be an integral structure. However, the present embodiment is not limited thereto. FIG. 38A In some examples, as shown in FIG. 1A, the active layer 310 of the thirty-first transistor T31, the active layer 320 of the thirty-second transistor T32, the active layer 330 of the thirty-third transistor T33, the active layer 350 of the thirty-fifth transistor T35, the active layer 370 of the thirty-seventh transistor T37, the active layer 380 of the thirty-eighth transistor T38, the active layer 410 of the forty-first transistor T41, and the active layer 420 of the forty-second transistor T42 can each extend along the second direction Y. The active layer 340 of the thirty-fourth transistor T34, the active layer 360 of the thirty-sixth transistor T36, the active layer 390 of the thirty-ninth transistor T39, the active layer 400 of the fortieth transistor T40, the active layer 430 of the forty-third transistor T43, and the active layer 440 of the forty-fourth transistor T44 can each extend along the first direction X. The active layer 340 of the thirty-fourth transistor T34, the active layer 350 of the thirty-fifth transistor T35, the active layer 380 of the thirty-eighth transistor T38, and the active layer 430 of the forty-third transistor T43 can be an integral structure. However, the present embodiment is not limited thereto.

[0411] FIG. 38A ​As shown, the active layer 310 of the thirty-first transistor T31 can include a channel region 310a, and a first doped region 310b and a second doped region 310c located on both sides of the channel region 310a along the second direction Y. The active layer of the thirty-second transistor T32 can include a channel region 320a, and a first doped region 320b and a second doped region 320c located on both sides of the channel region 320a along the second direction Y. The active layer 330 of the thirty-third transistor T33 can include a channel region 330a, and a first doped region 330b and a second doped region 330c located on both sides of the channel region 330a along the second direction Y. The active layer 340 of the thirty-fourth transistor T34 can include a channel region 340a, and a first doped region 340b and a second doped region 340c located on both sides of the channel region 340a along the first direction X. The active layer 350 of the thirty-fifth transistor T35 can include a channel region 350a, and a first doped region 350b and a second doped region 350c located on both sides of the channel region 350a along the second direction Y. The second doped region 350c of the active layer 350 of the thirty-fifth transistor T35 is connected with the second doped region 340c of the active layer 340 of the thirty-fourth transistor T34. The active layer 360 of the thirty-sixth transistor T36 can include a channel region 360a, and a first doped region 360b and a second doped region 360c located on both sides of the channel region 360a along the first direction X. The active layer 370 of the thirty-seventh transistor T37 can include a channel region 370a, and a first doped region 370b and a second doped region 370c located on both sides of the channel region 370a along the second direction Y. The active layer 380 of the thirty-eighth transistor T38 can include a channel region 380a, and a first doped region 380b and a second doped region 380c located on both sides of the channel region 380a along the second direction Y. The first doped region 380b of the active layer 380 of the thirty-eighth transistor T38 is connected with the first doped region 350b of the active layer 350 of the thirty-fifth transistor T35. The active layer 390 of the thirty-ninth transistor T39 can include a channel region 390a, and a first doped region 390b and a second doped region 390c located on both sides of the channel region 390a along the first direction X. The active layer 400 of the fortieth transistor T40 can include a channel region 400a, and a first doped region 400b and a second doped region 400c located on both sides of the channel region 400a along the first direction X. The active layer 410 of the forty-first transistor T41 can include a channel region 410a, and a first doped region 410b and a second doped region 410c located on both sides of the channel region 410a along the second direction Y. The active layer 420 of the forty-second transistor T42 can include a channel region 420a, and a first doped region 420b and a second doped region 420c located on both sides of the channel region 420a along the second direction Y.The active layer 430 of the forty-third transistor T43 may include a channel region 430a, and a first doped region 430b and a second doped region 430c located on both sides of the channel region 430a along the first direction X. The first doped region 430b of the active layer 430 of the forty-third transistor T43 is connected to the first doped region 350b of the active layer 350 of the thirty-fifth transistor T35. The active layer 440 of the forty-fourth transistor T44 may include a channel region 440a, and a first doped region 440b and a second doped region 440c located on both sides of the channel region 440a along the first direction X.

[0412] FIG. 38B for FIG. 36 A top view of the drive control circuit after the first conductive layer has been formed. (See attached image.) FIGS. 36-38B As shown, the first conductive layer 41 in the non-display area includes at least: the control electrode of the first semiconductor transistor of the drive control circuit, and the first electrode plates of multiple capacitors. For example, the first conductive layer 41 may include: the control electrode 311 of the thirty-first transistor T31, the control electrodes 321a and 321b of the thirty-second transistor T32, the control electrode 331 of the thirty-third transistor T33, the control electrode 341 of the thirty-fourth transistor T34, the control electrode 351 of the thirty-fifth transistor T35, the control electrode 361 of the thirty-sixth transistor T36, the control electrode 371 of the thirty-seventh transistor T37, the control electrode 381 of the thirty-eighth transistor T38, the control electrode 391 of the thirty-ninth transistor T39, the control electrode 401 of the fortieth transistor T40, the control electrode 411 of the forty-first transistor T41, the control electrode 421 of the forty-second transistor T42, the control electrode 431 of the forty-third transistor T43, the control electrode 441 of the forty-fourth transistor T44, the first electrode C3-1 of the third capacitor C3, the first electrode C4-1 of the fourth capacitor C4, and the first electrode C5-1 of the fifth capacitor C5.

[0413] In some examples, such as FIG. 38B As shown, the control electrodes 321a and 321b of the thirty-second transistor T32 can be a single integrated structure. The control electrode 341 of the thirty-fourth transistor T34, the control electrode 401 of the fortieth transistor T40, and the first plate C4-1 of the fourth capacitor C4 can be a single integrated structure. The control electrode 361 of the thirty-sixth transistor T36 and the first plate C5-1 of the fifth capacitor C5 can be a single integrated structure. The control electrode 391 of the thirty-ninth transistor T39 and the first plate C3-1 of the third capacitor C3 can be a single integrated structure. In this example, the thirty-second transistor T32 can be a dual-gate transistor to prevent and reduce leakage current. However, this embodiment is not limited to this.

[0414] FIG. 38C for FIG. 36A top view of the drive control circuit after the second semiconductor layer has been formed. (See attached image.) FIGS. 36-38C As shown, the second semiconductor layer 32 in the non-display area includes at least the active layer of a second semiconductor transistor for a driving control circuit. For example, the second semiconductor layer 32 may include the active layer 450 of the forty-fifth transistor T45. In some examples, the material of the second semiconductor layer 32 may include IGZO. The active layer 450 of the forty-fifth transistor T45 extends along a first direction X. The active layer 450 of the forty-fifth transistor T45 may include a channel region 450a, and a first region 450b and a second region 450c located on both sides of the channel region 450a along the first direction X. The first region 450b corresponds to the first electrode of the forty-fifth transistor T45, and the second region 450c corresponds to the second electrode of the forty-fifth transistor T45.

[0415] FIG. 38D for FIG. 36 A top view of the drive control circuit after the second conductive layer has been formed. (See attached image.) FIGS. 36-38D As shown, the second conductive layer 42 in the non-display area includes at least: the control electrode of the second semiconductor transistor of the drive control circuit, and the second plates of multiple capacitors. For example, the second conductive layer 42 may include: the control electrode 451 of the forty-fifth transistor T45, the second plate C3-2 of the third capacitor C3, the second plate C4-2 of the fourth capacitor C4, the second plate C5-2 of the fifth capacitor C5, the twenty-first connecting electrode L21, and the twenty-second connecting electrode L22. The orthographic projection of the second plate C3-2 of the third capacitor C3 onto the substrate is located within the orthographic projection of the first plate C3-1 onto the substrate; the orthographic projection of the second plate C4-2 of the fourth capacitor C4 onto the substrate is located within the orthographic projection of the first plate C4-1 onto the substrate; and the orthographic projection of the second plate C5-2 of the fifth capacitor C5 onto the substrate is located within the orthographic projection of the first plate C5-1 onto the substrate.

[0416] FIG. 38E for FIG. 36 A top view of the drive control circuit after the fourth insulating layer has been formed. (See attached image.) FIGS. 36-38EAs shown, multiple vias are formed on the fourth insulating layer 24 in the non-display area. These vias may include: first-type vias, multiple second-type vias, multiple third-type vias, and multiple fourth-type vias. In the first-type vias, the fourth insulating layer 24, third insulating layer 23, second insulating layer 22, and first insulating layer 21 are removed, exposing the surface of the first semiconductor layer 31. In the second-type vias, the fourth insulating layer 24, third insulating layer 23, and second insulating layer 22 are removed, exposing the surface of the first conductive layer 41. In the third-type vias, the fourth insulating layer 24 and third insulating layer 23 are removed, exposing the surface of the second semiconductor layer 32. In the fourth-type vias, the fourth insulating layer 24 is removed, exposing the surface of the second conductive layer 42. For example, the first type of via may include: the thirty-sixth via K36 to the sixtieth via K60; the second type of via may include: the sixty-first via K61 to the seventy-sixth via K76; the third type of via may include: the seventy-seventh via K77 and the seventy-eighth via K78; and the fourth type of via may include: the seventy-ninth via K79 to the eighty-sixth via K86.

[0417] FIG. 38F for FIG. 36 A top view of the drive control circuit after the third conductive layer has been formed. (See attached image.) FIGS. 36-38F As shown, the third conductive layer 43 in the non-display area may include: multiple connection electrodes (e.g., the twenty-third connection electrode L23 to the forty-second connection electrode L42), a signal input terminal INPUT, a second output terminal OUT2, a first clock signal line CKL, a second clock signal line CBL, and a first control signal line NXL. The first clock signal line CKL, the second clock signal line CBL, and the first control signal line NXL may all extend along the second direction Y. The signal input terminal INPUT of this stage of the drive control circuit may be electrically connected to the first output terminal of the previous stage of the drive control circuit; for example, the two may be an integral structure. The first output terminal of the drive control circuit may be electrically connected to the fortieth connection electrode L40; for example, they may be an integral structure. However, this embodiment is not limited to this. In other examples, the first output terminal may be located in the fourth conductive layer and electrically connected to the fortieth connection electrode.

[0418] In some examples, such as FIGS. 36-38FAs shown, the signal input terminal INPUT can be electrically connected with the first doped region 310b of the active layer 310 of the thirty-first transistor T31 through the thirty-sixth via hole K36. The twenty-third connection electrode L23 can be electrically connected with the second doped region 310c of the active layer 310 of the thirty-first transistor T31 through the thirty-seventh via hole K37, and also electrically connected with the control electrode 321b of the thirty-second transistor T32 through the sixty-fifth via hole K65. The twenty-fourth connection electrode L24 can be electrically connected with the first doped region 320b of the active layer 320 of the thirty-second transistor T32 through the forty-first via hole K41, and also electrically connected with the control electrode 311 of the thirty-first transistor T31 through the sixty-third via hole K63. The twenty-fifth connection electrode L25 can be electrically connected with the first doped region 330b of the active layer 330 of the thirty-third transistor T33 through the thirty-eighth via hole K38. The twenty-sixth connection electrode L26 can be electrically connected with the second doped region 330c of the active layer 330 of the thirty-third transistor T33 through the thirty-ninth via hole K39, and also electrically connected with the second doped region 320c of the active layer 320 of the thirty-second transistor T32 through the fortieth via hole K40, and also electrically connected with the first doped region 410b of the active layer 410 of the forty-first transistor T41 through the fifty-sixth via hole K56, and also electrically connected with the control electrode 351 of the thirty-fifth transistor T35 through the sixty-sixth via hole K66. The twenty-seventh connection electrode L27 can be electrically connected with the first doped region 420b of the active layer 420 of the forty-second transistor T42 through the fifty-eighth via hole K58, and also electrically connected with the control electrode 321a of the thirty-second transistor T32 through the sixty-fourth via hole K64. The twenty-eighth connection electrode L28 can be electrically connected with the second doped region 420c of the active layer 420 of the forty-second transistor T42 through the fifty-seventh via hole K57, and also electrically connected with the first plate C4-1 of the fourth capacitor C4 through the seventy-sixth via hole K76. The twenty-ninth connection electrode L29 can be electrically connected with the second doped region 410c of the active layer 410 of the forty-first transistor T41 through the fifty-fifth via hole K55, and also electrically connected with the control electrode 361 of the thirty-sixth transistor T36 through the sixty-eighth via hole K68. The thirtieth connection electrode L30 can be electrically connected with the second doped region 360c of the active layer 360 of the thirty-sixth transistor T36 through the forty-second via hole K42, and also electrically connected with the second plate C5-2 of the fifth capacitor C5 through the eighty-sixth via hole K86, and also electrically connected with the first doped region 370b of the active layer 370 of the thirty-seventh transistor T37 through the forty-fifth via hole K45.The thirty-first connection electrode L31 can be electrically connected with the first doped region 340b of the active layer 340 of the thirty-fourth transistor T34 through the forty-sixth via hole K46, electrically connected with the second doped region 360c of the active layer 360 of the thirty-sixth transistor T36 through the forty-third via hole K43, and electrically connected with the control electrode 371 of the thirty-seventh transistor T37 through the seventy-fifth via hole K75. The second clock signal line CBL can be electrically connected with the control electrode 371 of the thirty-seventh transistor T37 through the seventy-fourth via hole K74. The thirty-second connection electrode L32 can be electrically connected with the second doped region 430c of the active layer 430 of the forty-third transistor T43 through the forty-eighth via hole K48, electrically connected with the control electrode 321a of the thirty-second transistor T32 through the sixty-seventh via hole K67, and electrically connected with the control electrode 381 of the thirty-eighth transistor T38 through the seventieth via hole K70. The thirty-third connection electrode L33 can be electrically connected with the second doped region 380c of the active layer 380 of the thirty-eighth transistor T38 through the fifty-second via hole K52, electrically connected with the control electrode 391 of the thirty-ninth transistor T39 through the seventy-third via hole K73, and electrically connected with the second doped region 370c of the active layer 370 of the thirty-seventh transistor T37 through the forty-fourth via hole K44. The thirty-fourth connection electrode L34 can be electrically connected with the twenty-first connection electrode L21 through the eighty-first via hole K81, electrically connected with the second doped region 440c of the active layer 440 of the forty-fourth transistor T44 through the fifty-ninth via hole K59, and electrically connected with the second region 450c of the active layer 450 of the forty-fifth transistor T45 through the seventy-seventh via hole K77. The second output terminal OUT2 can be electrically connected with the twenty-first connection electrode L21 through the eighty-first via hole K81. The thirty-fifth connection electrode L35 can be electrically connected with the control electrode 441 of the forty-fourth transistor T44 through the seventy-second via hole K72, and electrically connected with the twenty-second connection electrode L22 through the eighty-third via hole K83. The thirty-sixth connection electrode L36 can be electrically connected with the first doped region 440b of the active layer 440 of the forty-fourth transistor T44 through the sixtieth via hole K60. The thirty-seventh connection electrode L37 can be electrically connected with the control electrode 441 of the forty-fourth transistor T44 through the seventy-first via hole K71, and electrically connected with the control electrode 451 of the forty-fifth transistor T45 through the seventy-ninth via hole K79. The thirty-eighth connection electrode L38 can be electrically connected with the first region 450b of the active layer 450 of the forty-fifth transistor T45 through the seventy-eighth via hole K78. The thirty-ninth connection electrode L39 can be electrically connected with the first doped region 400b of the active layer 400 of the fourth transistor T40 through the fiftieth via hole K50.The fortieth connecting electrode L40 can be electrically connected to the twenty-second connecting electrode L22 through the eighty-fourth via K84, and can also be electrically connected to the second doped region 400c of the active layer 400 of the fortieth transistor T40 through the fifty-first via K51, and can also be electrically connected to the second doped region 390c of the active layer 390 of the thirty-ninth transistor T39 through the fifty-fourth via K54. The forty-first connecting electrode L41 can be electrically connected to the first doped region 350b of the active layer 350 of the thirty-fifth transistor T35 through the forty-ninth via K49, and can also be electrically connected to the second plate C3-2 of the third capacitor C3 through the eighty-fifth via K85, and can also be electrically connected to the first doped region 390b of the active layer 390 of the thirty-ninth transistor T39 through the fifty-third via K53. The forty-second connecting electrode L42 can be electrically connected to the second doped region 340c of the active layer 340 of the thirty-fourth transistor T34 through the forty-seventh via K47, and can also be electrically connected to the second electrode C4-2 of the fourth capacitor C4 through the eightieth via K80. The first control signal line NXL can be electrically connected to the control electrode 431 of the forty-third transistor T43 through the sixty-ninth via K69. The first clock signal line CKL can be electrically connected to the control electrode 331 of the thirty-third transistor T33 through the sixty-first via K61, and can also be electrically connected to the control electrode 311 of the thirty-first transistor T31 through the sixty-second via K62.

[0419] FIG. 38G for FIG. 36 A top view of the drive control circuit after the fifth insulating layer has been formed. (See attached image.) FIGS. 36-38G As shown, the fifth insulating layer 25 in the non-display area has multiple vias, such as multiple fifth-type vias and sixth-type vias. The fifth insulating layer 25, fourth insulating layer 24, third insulating layer 23, and second insulating layer 22 within the fifth-type vias are removed, exposing the surface of the first conductive layer 41. The fifth insulating layer 25 within the sixth-type vias is removed, exposing the surface of the third conductive layer 43. For example, the fifth-type vias may include an eighty-seventh via K87. The sixth-type vias may include eighty-eighth vias K88 to ninety-second vias K92.

[0420] In some exemplary implementations, such as FIGS. 36-38GAs shown, the fourth conductive layer 44 of the non-display region can include a plurality of start signal lines (e.g., start signal lines STV1 to STV3), a first power line VGH, and two second power lines VGL1 and VGL2. The start signal lines, the first power line VGH, and the two second power lines VGL1 and VGL2 all extend along the second direction Y. In the first direction X, the first second power line VGL1, the plurality of start signal lines, the first power line VGH, and the second second power line VGL2 can be arranged in sequence. The first second power line VGL1 is electrically connected to the input circuit, and the second second power line VGL2 is electrically connected to the first output circuit and the second output circuit. The first second power line VGL1 can be electrically connected to the control electrode 411 of the forty-first transistor T41 through the eighty-seventh via hole K87, and can also be electrically connected to the twenty-fifth connection electrode L25 through the eighty-eighth via hole K88. The second second power line VGL2 can be electrically connected to the thirty-eighth connection electrode L38 through the ninetieth via hole K90, and can also be electrically connected to the thirty-ninth connection electrode L39 through the ninety-first via hole K91. The first power line VGH can be electrically connected to the thirty-sixth connection electrode L36 through the eighty-ninth via hole K89, and can also be electrically connected to the forty-first connection electrode L41 through the ninety-second via hole K92. However, the present embodiment is not limited thereto. In other examples, the first power line and the second power line can be located in the third conductive layer, and the clock signal line can be located in the fourth conductive layer.

[0421] In the present example embodiment, by arranging the second output circuit between the input circuit and the first output circuit, the arrangement of the drive control circuit can be optimized, thereby saving space.

[0422] FIG. 39 Another top view of the drive control circuit of at least one embodiment of the present disclosure. FIG. 40 For FIG. 39 A partial cross-sectional view along the direction of R-R'. The equivalent circuit of the drive control circuit of the present example embodiment can be as shown. FIG. 25 In the present example embodiment, the twenty-second transistor T22 to the twenty-eighth transistor T28 in the drive control circuit are taken as P-type transistors and LTPS transistors, and the twenty-first transistor T21 is taken as an N-type transistor and an oxide thin film transistor. However, the present embodiment is not limited thereto.

[0423] In some example embodiments, as FIG. 39As shown, in the plane parallel to the display substrate, the second output circuit is located between the input circuit and the second power supply line VGL in the first direction X, the first output circuit is located between the input circuit and the second power supply line VGL away from the second output circuit, and the clock signal line (for example, including the first clock signal line CKL and the second clock signal line CBL) is located on the side of the second power supply line VGL away from the second output circuit. In other words, the clock signal line, the second power supply line VGL, the second output circuit, the input circuit and the first output circuit are sequentially arranged along the first direction X. The first power supply line VGH is located on the side of the input circuit away from the second output circuit, and the first power supply line VGH can overlap with the first output circuit in the orthographic projection of the substrate substrate. The second output circuit is located between the first power supply line VGL and the input sub-circuit in the first direction X, and the control sub-circuit is located between the input sub-circuit and the first output circuit in the first direction X. In some examples, the second clock signal line CBL can be located on the side of the first clock signal line CKL away from the second power supply line VGL. However, the present embodiment is not limited thereto.

[0424] In some examples, as shown, FIG. 39 The twenty-first transistor T21 and the twenty-seventh transistor T27 can be sequentially arranged along the first direction X, and the twenty-first transistor T21 is located between the second power supply line VGL and the twenty-seventh transistor T27 in the first direction X. The twenty-second transistor T22 is located between the twenty-seventh transistor T27 and the twenty-fourth transistor T24 in the first direction X. The twenty-fourth transistor T24 and the twenty-fifth transistor T25 are sequentially arranged along the second direction Y. The twenty-third transistor T23 and the twenty-eighth transistor T28 are sequentially arranged along the second direction Y. The twenty-sixth transistor T26 is located between the twenty-second transistor T22 and the twenty-fifth transistor T25 in the first direction X. The twenty-fifth transistor T25 is adjacent to the twenty-eighth transistor T28 in the first direction X.

[0425] In some example embodiments, as shown, FIG. 40As shown, in the direction perpendicular to the display substrate, the non-display area of the display substrate can include: the substrate 20, the first semiconductor layer 31, the first conductive layer 41, the second semiconductor layer 32, the second conductive layer 42, the third conductive layer 43 and the fourth conductive layer 44 which are sequentially arranged on the substrate 20. Among them, the first insulating layer 21 is arranged between the first semiconductor layer 31 and the first conductive layer 41, the second insulating layer 22 is arranged between the first conductive layer 41 and the second semiconductor layer 32, the third insulating layer 23 is arranged between the second semiconductor layer 32 and the second conductive layer 42, the fourth insulating layer 24 is arranged between the second conductive layer 42 and the third conductive layer 43, and the fifth insulating layer 25 is arranged between the third conductive layer 43 and the fourth conductive layer 44. In some examples, the first insulating layer 21 to the fifth insulating layer 25 can all be inorganic insulating layers. However, the present embodiment is not limited thereto.

[0426] FIG. 41A For FIG. 39 the first semiconductor layer, a top view of the drive control circuit is shown. As FIGS. 39-41A shown, the first semiconductor layer 31 of the non-display area at least includes: the active layer of the first semiconductor transistor of the drive control circuit. For example, the first semiconductor layer 31 at least includes: the active layer 220A of the twenty-second transistor T22 to the active layer 280A of the twenty-eighth transistor T28.

[0427] In some examples, as FIG. 41A shown, the active layer 240A of the twenty-fourth transistor T24 and the active layer 250A of the twenty-fifth transistor T25 can be a one-piece structure, for example, a strip structure extending along the second direction Y. The active layer 230A of the twenty-third transistor T23 and the active layer 280A of the twenty-eighth transistor T28 can be a one-piece structure. However, the present embodiment is not limited thereto.

[0428] In some examples, as shown in Figure 41, the active layer 220A of the twenty-second transistor T22 may include: a channel region 220Aa, and a first doped region 220Ab and a second doped region 220Ac located on both sides of the channel region 220Aa along the second direction Y. The active layer 230A of the twenty-third transistor T23 may include: a channel region 230Aa, and a first doped region 230Ab and a second doped region 230Ac located on both sides of the channel region 230Aa along the second direction Y. The active layer 240A of the twenty-fourth transistor T24 may include: a channel region 240Aa, and a first doped region 240Ab and a second doped region 240Ac located on both sides of the channel region 240Aa along the second direction Y. The active layer 250A of the twenty-fifth transistor T25 may include: a channel region 250Aa, and a first doped region 250Ab and a second doped region 250Ac located on both sides of the channel region 250Aa along the second direction Y. The first doped region 250Ab of the twenty-fifth transistor T25 is connected to the second doped region 240Ac of the twenty-fourth transistor T24. The active layer 260A of the twenty-sixth transistor T26 may include a channel region 260Aa, and a first doped region 260Ab and a second doped region 260Ac located on both sides of the channel region 260Aa along the second direction Y. The active layer 270A of the twenty-seventh transistor T27 may include a channel region 270Aa, and a first doped region 270Ab and a second doped region 270Ac located on both sides of the channel region 270Aa along the second direction Y. The active layer 280A of the 28th transistor T28 may include: channel regions 280Aa1, 280Aa2 and 280Aa3 arranged sequentially along the second direction Y; a first doped region 280Ab1 and a second doped region 280Ac1 located on both sides of the channel region 280Aa1 along the second direction Y; and a third doped region 280Ab2 and a fourth doped region 280Ac2 located on both sides of the channel region 280Aa3 along the second direction Y.

[0429] FIG. 41B for FIG. 39 A top view of the drive control circuit after the first conductive layer has been formed. (See attached image.) FIGS. 39-41B As shown, the first conductive layer 41 in the non-display area includes at least: the control electrode of the first semiconductor transistor of the drive control circuit, and the first plates of multiple capacitors. For example, the first conductive layer 41 may include: the control electrodes 221Aa and 221Ab of the twenty-second transistor T22, the control electrode 231A of the twenty-third transistor T23, the control elect...

Claims

1. A drive control circuit, comprising: Input circuit, first output circuit, and second output circuit; The first output circuit is electrically connected to the input circuit and the first output terminal, and is configured to output a first output signal from the first output terminal under the control of the input circuit; The second output circuit is electrically connected to the input circuit and the second output terminal, or electrically connected to the first output terminal and the second output terminal, and is configured to output a second output signal from the second output terminal under the control of the input circuit or the first output terminal; The first output signal and the second output signal differ from at least one of the following: the absolute value of the voltage of the effective level, the polarity of the effective level, the duration of the effective level within one frame, and the continuous voltage fluctuation phase after the effective level; The first output signal and the second output signal are out of phase; The second output circuit includes at least one inverting sub-circuit, which is electrically connected to the first output terminal, the second output terminal, the first power line, and the second power line, and is configured to control the second output terminal to output a first power signal provided by the first power line or a second power signal provided by the second power line under the control of the first output terminal; the effective levels of the first power signal and the second power signal have different polarities.

2. The drive control circuit according to claim 1, wherein, The effective level duration of the first output signal within one frame is less than or equal to the effective level duration of the second output signal within one frame.

3. The drive control circuit according to claim 1, wherein, The effective level of the first output signal and the effective level of the second output signal have opposite polarities.

4. The drive control circuit according to claim 3, wherein, The effective level of the first output signal is configured to enable the P-type transistor, and the effective level of the second output signal is configured to enable the N-type transistor.

5. The drive control circuit according to claim 1, wherein, The first output signal has a continuous voltage fluctuation phase after the effective level, and the duration of the voltage fluctuation is less than the duration of the effective level; the second output signal does not have a continuous voltage fluctuation phase after the effective level.

6. The drive control circuit according to claim 1, wherein, The effective level duration of the first output signal within one frame is greater than the effective level duration of the second output signal within one frame, and the effective level of the first output signal and the effective level of the second output signal have the same polarity.

7. The drive control circuit according to claim 1, wherein, The first output circuit includes at least one inverting sub-circuit, which is electrically connected to the input circuit and the first output terminal.

8. The drive control circuit according to any one of claims 1 to 5, wherein, The input circuit is electrically connected to at least one output control node and configured to control the potential of the output control node; The first output circuit is electrically connected to the at least one output control node and the first output terminal, and is configured to control the first output terminal to output the first output signal under the control of the at least one output control node; The second output circuit is electrically connected to one of the output control nodes and the second output terminal, and is configured to control the second output terminal to output the second output signal under the control of the output control node.

9. The drive control circuit according to claim 8, wherein, The second output circuit includes: a first output transistor and a second output transistor; the first output transistor and the second output transistor are of different transistor types; The control electrode of the first output transistor is electrically connected to the output control node, the first electrode of the first output transistor is electrically connected to the second power line, and the second electrode of the first output transistor is electrically connected to the second output terminal. The control electrode of the second output transistor is electrically connected to the output control node, the first electrode of the second output transistor is electrically connected to the first power line or the third power line, and the second electrode of the second output transistor is electrically connected to the second output terminal. The effective level of the second power signal provided by the second power line has the same polarity as the effective level of the first output transistor. The effective level of the first power signal provided by the first power line or the third power signal provided by the third power line has the same polarity as the effective level of the second output transistor. The absolute voltage value of the effective level of the first power signal is different from the absolute voltage value of the effective level of the third power signal.

10. The drive control circuit according to claim 8, wherein, The second output circuit includes an inverting sub-circuit, which is electrically connected to the output control node, the second output terminal, the first power line, and the second power line. The inverting sub-circuit is configured, under the control of the output control node, to control the second output terminal to output a first power signal provided by the first power line or a second power signal provided by the second power line. The effective levels of the first power signal and the second power signal have different polarities, and the absolute voltage value of the effective level of the first power signal is greater than or equal to the absolute voltage value of the effective level of the second power signal.

11. The drive control circuit according to any one of claims 1 to 5, wherein, The input circuit includes: an input sub-circuit and a control sub-circuit; The input sub-circuit is electrically connected to the signal input terminal, the first clock terminal, and the first control node, and is configured to control the potential of the first control node under the control of the signal input terminal and the first clock terminal; The control sub-circuit is electrically connected to at least the first control node, the first power line, the second power line, the first output control node, and the second output control node, and is configured to control the potential of the first output control node and the second output control node under the control of the first control node. The first output circuit is electrically connected to the first output control node, the second output control node and the first output terminal, and is configured to control the first output terminal to output the first output signal under the control of the first output control node and the second output control node; The second output circuit is electrically connected to the first control node and is configured to control the second output terminal to output the second output signal under the control of the first control node.

12. The drive control circuit according to claim 11, wherein, The second output terminal is directly electrically connected to the first output control node.

13. The drive control circuit according to claim 11, wherein, The second output circuit includes an inverting sub-circuit, which is electrically connected to the first control node, the second output terminal, the first power line, and the second power line. The inverting sub-circuit is configured, under the control of the first control node, to control the second output terminal to output a first power signal provided by the first power line or a second power signal provided by the second power line. The effective levels of the first power signal and the second power signal have different polarities, and the absolute voltage value of the effective level of the first power signal is greater than or equal to the absolute voltage value of the effective level of the second power signal.

14. The drive control circuit according to claim 11, further comprising: A third output circuit is electrically connected to the first control node and the third output terminal, or electrically connected to the first output control node and the third output terminal, or electrically connected to the first output terminal and the third output terminal. The third output circuit is configured to control the third output terminal to output a third output signal under the control of the first control node, the first output control node, or the first output terminal. The third output signal is different from both the first output signal and the second output signal.

15. The drive control circuit according to claim 14, wherein, The third output terminal is directly electrically connected to the first output control node.

16. The drive control circuit according to claim 1, wherein, The inverting sub-circuit includes: a first semiconductor transistor and a second semiconductor transistor, wherein the first semiconductor transistor and the second semiconductor transistor are of different transistor types; The first terminal of the first semiconductor transistor is electrically connected to the first power line, and the first terminal of the second semiconductor transistor is electrically connected to the second power line; The effective level of the first power signal provided by the first power line is opposite in polarity to the effective level of the first semiconductor transistor, and the effective level of the second power signal provided by the second power line is opposite in polarity to the effective level of the second semiconductor transistor.

17. The drive control circuit according to claim 8, wherein, The first output circuit includes at least a third output transistor and a fourth output transistor; the third output transistor and the fourth output transistor are of the same transistor type. The control electrode of the third output transistor is electrically connected to the first output control node, the first electrode of the third output transistor is electrically connected to the first power line, and the second electrode of the third output transistor is electrically connected to the first output terminal. The control electrode of the fourth output transistor is electrically connected to the second output control node, the first electrode of the fourth output transistor is electrically connected to the second power line or the second clock terminal, and the second electrode of the fourth output transistor is electrically connected to the first output terminal.

18. A gate drive circuit, comprising a plurality of cascaded drive control circuits as described in any one of claims 1 to 17; in, The signal input terminal of the first-stage drive control circuit is electrically connected to the starting signal line, and the signal input terminal of the (i+1)th-stage drive control circuit is electrically connected to the first output terminal of the i-th-stage drive control circuit, where i is an integer greater than 0.

19. A display substrate, comprising: A display area and a non-display area surrounding the display area. The non-display area is provided with a gate driving circuit. The gate driving circuit includes multiple cascaded driving control circuits. The driving control circuit includes an input circuit, a first output circuit, and a second output circuit. The first output circuit is electrically connected to the input circuit, and the second output circuit is electrically connected to either the input circuit or the first output circuit. In a first direction, the input circuit is located between the first output circuit and the second output circuit, or the second output circuit is located between the input circuit and the first output circuit; The drive control circuit is electrically connected to the clock signal line, the second power line and the first power line; In the first direction, the clock signal line, the second power line, the second output circuit, the input circuit, and the first output circuit are arranged in sequence; the orthographic projection of the first power line on the substrate overlaps with the orthographic projection of the first output circuit on the substrate.

20. The display substrate according to claim 19, wherein, The second output circuit includes at least one first semiconductor transistor and at least one second semiconductor transistor, wherein the first semiconductor transistor and the second semiconductor transistor are of opposite transistor types.

21. The display substrate according to claim 20, wherein, The control electrode of the first semiconductor transistor and the second semiconductor transistor is an integrated structure.

22. The display substrate according to claim 20, wherein, The first semiconductor transistor and the second semiconductor transistor are arranged sequentially along the first direction or along the second direction, wherein the first direction and the second direction intersect.

23. The display substrate according to claim 22, wherein, The first semiconductor transistor and the second semiconductor transistor are arranged sequentially along the first direction, and the active layers of both the first semiconductor transistor and the second semiconductor transistor extend along the second direction.

24. The display substrate according to claim 22, wherein, The first semiconductor transistor and the second semiconductor transistor are arranged sequentially along the second direction, and the active layers of the first semiconductor transistor and the second semiconductor transistor both extend along the first direction.

25. The display substrate according to any one of claims 20 to 24, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a substrate and a first semiconductor layer and a second semiconductor layer disposed on the substrate, wherein the second semiconductor layer is located on the side of the first semiconductor layer away from the substrate. The first semiconductor layer includes: the active layer of the first semiconductor transistor; The second semiconductor layer includes: the active layer of the second semiconductor transistor; The first output circuit is electrically connected to the first output terminal, and the second output circuit is electrically connected to the second output terminal. The first output terminal and the second output terminal are located on the side of the second semiconductor layer away from the substrate.

26. The display substrate according to claim 25, wherein, The first output terminal and the second output terminal are in the same layer, or the second output terminal is located on the side of the first output terminal away from the substrate.

27. The display substrate according to claim 19, wherein, The first clock terminal of the k-th stage drive control circuit is electrically connected to the first clock signal line, and the second clock terminal of the k-th stage drive control circuit is electrically connected to the second clock signal line. The first clock terminal of the (k+1)th stage drive control circuit is electrically connected to the second clock signal line, and the second clock terminal of the (k+1)th stage drive control circuit is electrically connected to the first clock signal line. The (k+1)th stage drive control circuit is electrically connected to the second clock signal line through the k-th stage drive control circuit, and the (k+2)th stage drive control circuit is electrically connected to the first clock signal line through the (k+1)th stage drive control circuit, where k takes the value of 2n or 2n-1, and n is an integer greater than 0.

28. The display substrate according to claim 27, wherein, The control electrode of the transistor electrically connected to the second clock signal line in the (k+1)th stage drive control circuit and the (k)th stage drive control circuit is an integrated structure, and the control electrode of the transistor electrically connected to the first clock signal line in the (k+2)th stage drive control circuit and the (k+1)th stage drive control circuit is an integrated structure.

29. The display substrate according to claim 19, wherein, The gate driving circuit includes multiple driving control circuit groups, and at least one driving control circuit group includes: a k-th stage driving control circuit and a k+1-th stage driving control circuit, wherein the value of k is 2n or 2n-1, and n is an integer greater than 0; The k-th level drive control circuit and the (k+1)-th level drive control circuit are approximately symmetrical about the centerline of the drive control circuit group in the second direction, and the second direction intersects the first direction.

30. The display substrate according to claim 29, wherein, The second output terminal of the k-th stage drive control circuit and the second output terminal of the (k+1)-th stage drive control circuit are adjacent in the second direction; The second output terminal of the k-th stage drive control circuit is electrically connected to the first lead-out line, and the second output terminal of the k-th stage drive control circuit is located on the side of the first output terminal away from the substrate. The second output terminal of the (k+1)th stage drive control circuit is electrically connected to the second lead, which is located on the side of the second output terminal closer to the substrate.

31. The display substrate according to claim 29, wherein, The signal input terminal of the (k+1)th stage drive control circuit is electrically connected to the first output terminal of the kth stage drive control circuit, and the signal input terminal is located on the side of the first output terminal away from the substrate.

32. The display substrate according to claim 29, wherein, The signal input terminal of the (k+2)th stage drive control circuit is electrically connected to the first output terminal of the (k+1)th stage drive control circuit, and the first output terminal is located on the side of the signal input terminal away from the substrate.

33. The display substrate according to claim 29, wherein, The second output circuit of the (k+2)th stage drive control circuit is electrically connected to the first power supply line through the second output circuit of the (k+1)th stage drive control circuit.

34. The display substrate according to claim 19, wherein, The drive control circuit is electrically connected to the clock signal line, the second power line and the first power line; The clock signal line is located on the side of the input power supply away from the first output circuit in the first direction; The projection of the second power line onto the substrate overlaps with the projection of the input circuit onto the substrate, and the projection of the first power line onto the substrate overlaps with the projection of the second output circuit onto the substrate.

35. The display substrate according to claim 19, wherein, The drive control circuit is electrically connected to the clock signal line, the first power line, and two second power lines. In the first direction, the clock signal line, the input circuit, the second output circuit, and the first output circuit are arranged in sequence; the orthographic projection of the first second power line on the substrate overlaps with the orthographic projection of the input circuit on the substrate, and the orthographic projection of the second second power line on the substrate overlaps with the orthographic projection of the first output circuit on the substrate. The first power line is located between the second output circuit and the second second power line in the first direction.

36. The display substrate according to claim 19, wherein, The first power line and the second power line are in the same layer, and the clock signal line is located on the side of the first power line away from the substrate.

37. The display substrate according to claim 19, wherein, The first power line and the second power line are on the same layer, and the clock signal line is located on the side of the first power line closer to the substrate.

38. A display device comprising a display substrate as claimed in any one of claims 19 to 37.

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