Wide input voltage stabilizing circuit

Abstract

The application discloses a wide input voltage stabilizing circuit, and belongs to the technical field of integrated circuits. The circuit comprises a reference circuit, a mode selection circuit, an internal power supply circuit, a charge pump control circuit, a substrate control circuit, an oscillator, an operational amplifier, a voltage comparator, a resistor, a capacitor and a PMOS transistor. When the power supply voltage VDD is less than a set voltage, the overall circuit works in working mode 1, switch S0 is disconnected, S1 is connected, the charge pump control circuit controls the charging and discharging of the capacitor, and the VO voltage finally reaches or approaches the required output voltage. When the power supply voltage VDD is greater than the set voltage, the overall circuit works in working mode 2, switch S0 is connected, S1 is disconnected, the charge pump control circuit provides a low level for the gate end of the PMOS transistor P1, P1 is turned on, and the overall circuit realizes the voltage stabilizing function through a feedback loop, so that the VO voltage is stabilized at the required output voltage, and the output voltage stabilizing under the working condition of a low power supply voltage is realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular to a wide-input voltage stabilization circuit. Background Art

[0002] Voltage stabilizing circuit technology has a wide range of applications, especially in various power supply products, such circuits have become an indispensable part.

[0003] A traditional voltage stabilization circuit such as Figure 1 As shown, it includes a reference circuit, an operational amplifier, a PMOS transistor PM, and resistors R0 and R1. Its voltage regulation function is mainly achieved by the feedback loop, which controls the gate-source voltage difference of the PMOS transistor to adjust the circuit current and thus maintain a stable output voltage. The input and output relationship of the circuit is shown as follows Figure 2 As shown in the figure, when the power supply voltage is greater than the set voltage, the circuit output voltage is relatively stable. However, when the power supply voltage is less than the set voltage, the circuit output voltage will change with the power supply voltage. Therefore, this structure has difficulty achieving voltage regulation under certain low input voltage conditions. In particular, in power management and motor drive applications, power MOSFETs and IGBTs require higher voltage drive, and low input power can easily cause undervoltage problems.

[0004] To address the narrow input operating voltage range of voltage regulator circuits, a search of existing patents revealed a Chinese invention patent, "A Voltage Regulator Circuit with Wide Power Input" (patent number CN105915053A), that implements a voltage regulator circuit with a wide input voltage range. This circuit changes the traditional PWM controller circuit. The PWM controller and MOSFET determine which circuit performs voltage regulation. The regulated voltage is then passed to a DC-DC converter circuit for step-down regulation to achieve the desired voltage. However, this implementation is relatively complex, requiring numerous peripheral components and resulting in high implementation costs. Summary of the Invention

[0005] The present invention provides a wide-input voltage stabilization circuit that solves the problem that conventional voltage stabilization circuits have difficulty achieving voltage stabilization when the power supply voltage is low, while also avoiding the problem of overly complex peripheral circuits. The technical solution is as follows:

[0006] A wide input voltage regulator circuit, characterized in that the wide input voltage regulator circuit includes: a reference circuit, a mode selection circuit, an internal power supply circuit, a charge pump control circuit, a substrate control circuit, an oscillator, an operational amplifier, a voltage comparator, resistors R0 and R1, a capacitor C0, and PMOS tubes P0 and P1.

[0007] The output end of the oscillator is connected to the clock input port of the charge pump control circuit, and the power supply is connected to VDD;

[0008] The operational amplifier has a non-inverting input connected to a common port of resistors R0 and R1 connected in series, an inverting input connected to the output of the reference circuit, an output connected to the switch S0 and the gate of the PMOS transistor P0, and a power supply connected to VDD;

[0009] The non-inverting input terminal of the voltage comparator is connected to the output terminal of the reference circuit, the inverting input terminal is connected to the common port of the resistor R0 and the resistor R1 connected in series, the output terminal is connected to the feedback input port of the charge pump control circuit, and the power supply is connected to VDD;

[0010] The power detection port of the mode selection circuit is connected to VDD, the output detection port is connected to the drain end of the PMOS tube P1 and the other end of the resistor R0, and serves as the output port VO of the wide input voltage regulator circuit, the reference input port of the mode selection circuit is connected to the output end of the reference circuit, and the pass-through control port and the enable output port are respectively connected to the pass-through control port and the enable input port of the charge pump control circuit;

[0011] The high-side input port of the internal power supply circuit is connected to VDD, and the low-side input port is connected to the output port VO of the wide input voltage stabilizing circuit;

[0012] The input port of the substrate control circuit is connected to the enable output port of the mode selection circuit, the source output port is connected to VDD and the source end of the PMOS transistor P0, the substrate output port is connected to the substrate of the PMOS transistor P0, and the drain output port is connected to the drain end of the PMOS transistor P0, the source end of P1 and one end of the capacitor C0;

[0013] The high-side output port of the charge pump control circuit is connected to the switch S1 and the gate end of the PMOS transistor P0, the low-side output port is connected to the gate end of the PMOS transistor P1, and the capacitor control port is connected to the other end of the capacitor C0;

[0014] The substrate of the PMOS tube P1 is connected to the drain end of P1; the other end of the resistor R1 is connected to the ground.

[0015] As an embodiment, the mode selection circuit includes: a voltage shift circuit, comparators A and B, and resistors R2 and R3. The power detection port of the mode selection circuit is internally connected to one end of resistor R2 and the input end of the voltage shift circuit, the output detection port of the mode selection circuit is internally connected to the inverting input end of comparator B, the reference input port is internally connected to the non-inverting input end of comparator A, the enable output end is internally connected to the output end of comparator A, and the pass-through control end is internally connected to the output end of comparator B; the other end of resistor R2 is connected to the inverting input end of comparator A and one end of resistor R3; and the other end of resistor R3 is connected to ground.

[0016] As an implementation, the internal power supply circuit includes a comparator C, an inverter INV0, PMOS tubes P2 and P3. The high-side input of the internal power supply circuit is internally connected to the inverting input of the comparator C, the low-side input is internally connected to the non-inverting input of the comparator C, and the output is connected to the drain of PMOS tubes P2 and P3; the input of the inverter INV0 is connected to the output of the comparator C and the gate of the PMOS tube P2, and the output of the inverter INV0 is connected to the gate of the PMOS tube P3; the source of the PMOS tube P2 is connected to VDD, the substrate is connected to the drain of P2, the source of the PMOS tube P3 is connected to the output VO of the wide input voltage stabilizing circuit, and the substrate is connected to the drain of P3.

[0017] As an implementation, the charge pump control circuit includes an AND gate AND0, NAND gates NAND0, NAND1 and NAND2, NOR gates NOR0 and NOR1, an OR gate OR0, buffers BUF0, BUF1 and BUF2, delay circuits 1 and 2, and level shift circuits 1 and 2. The enable input port, clock input port and feedback input port of the charge pump control circuit are respectively connected to the three input ports of the AND gate AND0, the pass-through control port of the charge pump control circuit is internally connected to one input port of the NOR gate NOR0, the high-side output port is internally connected to the output port of the buffer BUF0, the capacitor control port is internally connected to the output port of the buffer BUF1, and the low-side output port is internally connected to the output port of the buffer BUF2; the input port of the delay circuit 1 is connected to the output port of the AND gate AND0, one input port of the NOR gate OR0 and one input port of the NAND gate NAND0, and the output port is connected to the input port of the buffer BUF1 and the input port of the delay circuit 2; the other input port of the NOR gate OR0 is connected to the output port of the delay circuit 2 and the other input port of the NAND gate NAND0, and the output port is connected to one input port of the NAND gate NAND2; one input port of the NAND gate NAND1 is connected to the output port of the NAND gate NAND0, the other input port is connected to the voltage comparator output signal, and the output port is connected to one input port of the NOR gate NOR1; the other input port of the NOR gate NOR1 is connected to the pass-through control signal, and the output port is connected to the input port of the level shift circuit 2; the other input port of the NOR gate NOR0 is connected to the output port of the NAND gate NAND2, and the output port is connected to the input port of the level shift circuit 1; the input port of the buffer BUF2 is connected to the output port of the level shift circuit 2, the input port of the buffer BUF0 is connected to the output port of the level shift circuit 1, and the other input port of the NAND gate NAND2 is connected to the voltage comparator output signal.

[0018] In one embodiment, the substrate control circuit includes: a level shift circuit 0, an inverter INV1, and PMOS transistors P4 and P5. The input port of the substrate control circuit is internally connected to the input of the level shift circuit 0, the source output is internally connected to the source of the PMOS transistor P4, the substrate output is internally connected to the drain of the PMOS transistor P4 and the source of P5, and the drain output is internally connected to the drain of the PMOS transistor P5. The input of the inverter IN1 is connected to the output of the level shift circuit and the gate of the PMOS transistor P4, and the output is connected to the gate of the PMOS transistor P5. The substrate of the PMOS transistor P4 is connected to the source and substrate of the PMOS transistor P5.

[0019] As an embodiment, the level shift circuit includes: PMOS transistors P7 and P8, NMOS transistors N0 and N1, and an inverter INV2. The input end of the level shift circuit is internally connected to the input end of inverter INV2 and the gate end of NMOS transistor N1, and the output end is internally connected to the drain end of PMOS transistor P7, the gate end of P8, and the drain end of NMOS transistor N0. The output end of the inverter is connected to the gate end of NMOS transistor N0 and the power supply is connected to VDD. The drain end of NMOS transistor N1 is connected to the drain end of PMOS transistor P8 and the gate end of P7, and the source end is connected to ground. The source end of PMOS transistor P7 is connected to the source end of PMOS transistor P8 and VDDA, and the source end of NMOS transistor N0 is connected to ground.

[0020] The beneficial effects of the technical solutions provided by the embodiments of the present application include at least:

[0021] This circuit structure solves the problem that traditional voltage stabilization circuits are difficult to achieve voltage stabilization when the power supply voltage is low, and avoids the problem of overly complex peripheral circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 Schematic diagram of a traditional voltage stabilizing circuit;

[0024] Figure 2 for Figure 1 Schematic diagram of the input and output relationship in the circuit;

[0025] Figure 3 A wide input voltage stabilization circuit proposed in this application;

[0026] Figure 4 for Figure 3An implementation of a mode selection circuit in a circuit;

[0027] Figure 5 for Figure 3 An implementation method of an internal power supply circuit in a circuit;

[0028] Figure 6 for Figure 3 An implementation of a substrate control circuit in a circuit;

[0029] Figure 7 for Figure 3 An implementation of a charge pump control circuit in a circuit;

[0030] Figure 8 for Figure 3 A working waveform diagram of the charge pump control circuit in the circuit;

[0031] Figure 9 for Figure 3 An implementation of a voltage shift circuit in a circuit;

[0032] Figure 10 for Figure 3 An implementation of a level shift circuit in a circuit;

[0033] Figure 11 This is a schematic diagram of the input-output relationship of the wide-input voltage stabilization circuit proposed in this application;

[0034] Figure 12 This is a comparison chart of the operating range of the wide input voltage stabilization circuit proposed in this application and the traditional voltage stabilization circuit. Implementation Method

[0035] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0036] The specific implementation of the wide input voltage stabilizing circuit of the present invention is as follows Figure 3As shown, including mode selection circuit, internal power supply circuit, substrate control circuit, charge pump control circuit, resistance, capacitance, oscillator, operational amplifier and voltage comparator. The power detection port of the mode selection circuit is connected to VDD, the output detection port is connected to the drain of PMOS P1 and one port of resistor R0, and serves as the output port VO of the wide input voltage regulator circuit, the reference input port of the mode selection circuit is connected to the output of the reference circuit, the pass-through control port and the enable output port are respectively connected to the pass-through control port and the enable input port of the charge pump control circuit; the high-side input port of the internal power supply circuit is connected to VDD, the low-side input port is connected to the output VO of the wide input voltage regulator circuit, and the voltage of the internal power supply circuit output port serves as the power voltage of part of the logic circuit; the input port of the substrate control circuit is connected to the enable output port of the mode selection circuit, the source output port is connected to VDD and the source of PMOS P0, and the substrate output port is connected to the substrate of PMOS P0; the drain output port is connected to the drain of PMOS P0, the source of P1 and one end of capacitor C0; the clock input port of the charge pump control circuit is connected to the output of the oscillator, the high-side output port is connected to the gate of PMOS P0 through switch S1, the low-side output port is connected to the gate of PMOS P1, and the capacitor control port is connected to the other end of capacitor C0; the non-inverting input of the operational amplifier is connected to the common port of resistor R0 and resistor R1 in series, the inverting input is connected to the output of the reference circuit, the output is connected to the gate of PMOS P0 through switch S0, and the power supply is connected to VDD; the non-inverting input of the voltage comparator is connected to the output of the reference circuit, the inverting input is connected to the common port of resistor R0 and resistor R1 in series, the output is connected to the feedback input port of the charge pump control circuit, and the power supply is connected to VDD; the substrate of PMOS P1 is connected to the drain of P1; the other port of resistor R1 is connected to ground.

[0037] Figure 3 The mode selection circuit in the above embodiment is shown in Figure 4 An embodiment, which contains comparator A, comparator B, resistors 2 and 3, voltage displacement circuit. One end of resistor R2 is connected to power supply voltage VDD, the other end is connected to one input port of comparator A and one port of R3; the other port of resistor R3 is connected to ground, the other input of comparator A is connected to reference voltage VREF, and the output is connected to the enable output port; one input of comparator B is connected to the output of voltage displacement circuit, the other input is connected to the output signal of wide input voltage regulator circuit, and the output is connected to the direct control port.

[0038] Figure 4The working principle of the mode selection circuit shown is as follows: when the power supply voltage VDD is less than the set voltage VSET, comparator A outputs a high level, comparator B outputs a low level, and the entire circuit enters working mode 1; when the power supply voltage is greater than the set voltage VSET, comparator A outputs a low level, comparator B outputs a low level, and the entire circuit enters working mode 2.

[0039] Figure 3 The internal power supply circuit in Figure 5 An embodiment shown includes a comparator C, an inverter INV0, and PMOS transistors P2 and P3. One input terminal of the comparator C is connected to the power supply voltage VDD, the other input terminal is connected to VO, and the output terminal is connected to the input terminal of the inverter and the gate terminal of the PMOS transistor P2.

[0040] Figure 5 The working principle of the internal power supply circuit shown is as follows: when the power supply voltage VDD is lower than the output voltage VO, the comparator C outputs a high level, the PMOS transistor P2 is turned off, P3 is turned on, and the output terminal VDDA of the internal power supply circuit outputs the drain voltage of the PMOS transistor P3; when the power supply voltage VDD is higher than the output voltage VO, the comparator C outputs a low level, the PMOS transistor P2 is turned on, P3 is turned off, and the output terminal VDDA of the internal power supply circuit outputs the drain voltage of the PMOS transistor P2.

[0041] Figure 3 The substrate control circuit in Figure 6 One embodiment shown includes a level shift circuit, an inverter INV1, and PMOS transistors P4 and P5. The input of the level shift circuit is connected to the enable output signal of the mode selection circuit, and the output is connected to the gate of PMOS transistor P4 and the input of inverter INV1. The source of PMOS transistor P4 is connected to the power supply voltage VDD, and the drain is connected to the source of PMOS transistor P5 and the substrate of P0. The gate of PMOS transistor P5 is connected to the output of inverter INV1, and the drain is connected to the drain of P0.

[0042] Figure 6 The working principle of the substrate control circuit shown is as follows: when the entire circuit operates in working mode 2, PMOS transistor P4 is turned on and P5 is turned off. At this time, the substrate of PMOS transistor P0 can be regarded as short-circuited to the source terminal; when the entire circuit operates in working mode 1, PMOS transistor P4 is turned off and P5 is turned on. At this time, the substrate of PMOS transistor P0 can be regarded as short-circuited to the drain terminal.

[0043] Figure 3 The charge pump control circuit in Figure 7An embodiment shown includes an AND gate, several NAND gates, several NOT gates, several NOR gates, a delay circuit, a level shift circuit, and several buffers. The three inputs of AND gate AND0 are respectively connected to an enable input signal, a clock input signal, and a voltage comparator output signal, while the output is connected to an input of delay circuit 1, an input segment of NAND gate NAND0, and an input of NOT gate OR0. Another input of NAND gate NAND0 is connected to the output of delay circuit 2 and another input of NOT gate OR0, and the output is connected to an input of NAND gate NAND1. Another input of NAND gate NAND1 is connected to the voltage comparator output signal, and the output is connected to an input signal of NOR gate NOR1. Another input signal of NOR gate NOR1 is connected to a direct control signal, and the output is connected to the input port of level shift circuit 2. The output port of level shift circuit 2 is connected to buffer BUF. 2, the output end of the buffer BUF2 is connected to the low-side output port of the charge pump control circuit; the input end of the delay circuit 2 is connected to the output end of the delay circuit 1 and the input end of the buffer BUF1, and the output end of the buffer BUF1 is connected to the capacitor control port of the charge pump control circuit; the output end of the NOT gate OR0 is connected to one input end of the NAND gate NAND2, the other input end is connected to the voltage comparator output signal, and the output end is connected to one input end of the NOR gate NOR0; the other input end of the NOR gate NOR0 is connected to the direct control signal, the output end is connected to the input end of the level shift circuit 1, the output end of the level shift circuit 1 is connected to the input end of the buffer BUF0, and the output end of the buffer BUF0 is connected to the high-side output port of the charge pump control circuit.

[0044] Figure 7 The charge pump control circuit operates as follows: When the circuit operates in operating mode 1, the operating waveforms are shown in the figure, where A, B, and C represent the voltages at the high-side output port, capacitor control port, and low-side output port, respectively. When the high-side output port is low, the low-side output port is high. PMOS transistor P0 is on, P1 is off, and capacitor C0 is charged. When the low-side output port is low, the high-side output port is high. PMOS transistor P0 is off, P1 is on, and capacitor C0 is discharged. When the capacitor control port voltage changes, both the high-side and low-side output ports are high, and both PMOS transistors P0 and P1 are off. When the circuit operates in operating mode 2, the charge pump control circuit's enable input signal and direct control signal are low. The low-side output signal remains low, and PMOS transistor P1 remains on.

[0045] Figure 4 The voltage shift circuit in Figure 9An embodiment shown includes a PMOS transistor P6 and a current source I0. The source end of the PMOS transistor P6 is connected to the power supply voltage VDD, the gate and drain ends are short-circuited and connected to the current source I0, and the output end is connected to an input end of the comparator B in the mode selection circuit. The other end of the current source is grounded.

[0046] Figure 9 The working principle of the voltage shift circuit shown is as follows: the current flowing through the PMOS transistor P6 is controlled by the current source I0. As long as the current output by the current source I0 is controlled, the voltage difference between the drain terminal and the source terminal of P6 is constant. At this time, the voltage difference between the output terminal voltage of the voltage shift circuit and the VDD voltage is constant, realizing the voltage shift function.

[0047] Figure 6 and Figure 7 The level shift circuit in Figure 10 One embodiment shown includes PMOS transistors P7 and P8, NMOS transistors N0 and N1, and an inverter INV2. The gate of NMOS transistor N0 is connected to the output of inverter INV2, its source is grounded, and its drain is connected to the drain of PMOS transistor P7 and the gate of P8, serving as the output of a level shift circuit. The gate of NMOS transistor N1 is connected to the input of the inverter and serves as the input of the level shift circuit. Its source is grounded, and its drain is connected to the drain of PMOS transistor P8 and the gate of P7. The sources of PMOS transistors P7 and P8 are connected to the output signal of an internal power supply circuit. The power supply of inverter INV2 is connected to power supply voltage VDD.

[0048] Figure 10 The level shift circuit shown in the figure operates as follows: When the input signal to the level shift circuit is high, NMOS transistor N0 is turned off and N1 is turned on, pulling down the voltage at N1's drain. This in turn turns on PMOS transistor P7, causing the voltage at P7's drain to rise. At this point, P8 is turned off, and the output signal is high. When the input signal to the level shift circuit is low, NMOS transistor N0 is turned on and N1 is turned off, pulling down the voltage at N0's drain. This in turn turns on PMOS transistor P8, causing the voltage at P8's drain to rise. At this point, P7 is turned off, and the output signal is low. This changes the voltage domain of the transmitted signal, allowing the subsequent circuits to function normally.

[0049] The working principle of the voltage stabilizing circuit of the present invention is: when it is detected that the power supply voltage VDD is less than the set voltage, the circuit works in working mode 1, and when the power supply voltage VDD is greater than the set voltage, the circuit works in working mode 2. The specific input and output correspondence is as follows: Figure 11 In operating mode 1, the charge pump control circuit plays a major role, controlling the charging and discharging of the capacitor to achieve voltage regulation. In operating mode 2, the operating circuit is similar to a traditional voltage regulator circuit, stabilizing the voltage output through a feedback loop.

[0050] The specific working principle of working mode 1 is as follows: when the power supply voltage VDD is less than the set voltage VSET and greater than the minimum operating voltage, the mode selection circuit enables the output signal to be high, switch S0 is disconnected, and S1 is closed. At this time, the charge pump control circuit plays an important role in the overall circuit: when the clock signal and delay signal D2 output by the oscillator are both low, P0 is turned on, P1 is cut off, the capacitor control end outputs a low level, and the capacitor C0 is in a charging state; when the clock signal and delay signal D2 output by the oscillator are both high, P1 is turned on, P0 is cut off, the capacitor control end outputs a high level, the capacitor C0 is in a discharging state, and the VO voltage also increases accordingly; this process is repeated continuously, and the VO voltage eventually tends to a stable value.

[0051] The specific operating principle of operating mode 2 is as follows: When the power supply voltage VDD is greater than the set voltage VSET, the mode select circuit enables the output signal to a low level, closing switch S0 and opening switch S1. The low-side output of the charge pump control circuit is low, and P1 is turned on. At this point, the operating circuit is similar to a traditional voltage regulator circuit, relying on a feedback loop to stabilize the output voltage. The specific operating principle is as follows: If the circuit operates in operating mode 2 and the voltage on VO drops for some reason, the voltage across resistors R0 and R1 will also drop, causing the voltage on the non-inverting input of the operational amplifier to drop, and the gate voltage of the PMOS transistor P0 connected to the output of the operational amplifier to drop as well. At this time, because the source of P0 is connected to the power supply voltage VDD, the gate-source voltage difference increases due to the drop in gate voltage, increasing the current flowing through P0 and causing the voltage on VO to rise. This completes a feedback control, keeping the voltage on VO essentially constant. Similarly, when the voltage on VO rises, the voltage on the gate of the PMOS transistor P0 also rises, causing the circuit current to drop. At this point, the voltage on VO drops to its normal value and remains constant.

[0052] Figure 12 This paper compares the input operating ranges of the present invention and conventional voltage regulator circuits. It's clear that conventional voltage regulators struggle to achieve voltage regulation when the power supply voltage is low, while the wide-input voltage regulator circuit of the present invention can. This is because the present invention modifies the conventional voltage regulator circuit, using a mode selection circuit to determine how to regulate voltage. When the VDD voltage is below a set voltage, the charge pump control circuit controls the charging and discharging of the capacitor for voltage regulation; when the voltage is above the set voltage, the conventional voltage regulator circuit performs voltage regulation. Therefore, the wide-input voltage regulator circuit of the present invention has lower application requirements and broader application prospects.

[0053] Those skilled in the art will understand that all or part of the steps of implementing the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0054] The above description is not intended to limit the embodiments of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the embodiments of the present application.

Claims

1. A wide input voltage stabilizing circuit, characterized in that: The wide input voltage stabilization circuit includes: a reference circuit, a mode selection circuit, an internal power supply circuit, a charge pump control circuit, a substrate control circuit, an oscillator, an operational amplifier, a voltage comparator, a resistor R0, a resistor R1, a capacitor C0, a PMOS transistor P0 and a PMOS transistor P1; The output end of the oscillator is connected to the clock input port of the charge pump control circuit, and the power supply is connected to VDD; The non-inverting input terminal of the operational amplifier is connected to the common port of the resistor R0 and the resistor R1 connected in series, the inverting input terminal of the operational amplifier is connected to the output terminal of the reference circuit, the output terminal of the operational amplifier is connected to the switch S0 and the gate terminal of the PMOS transistor P0, and the power supply is connected to VDD; The non-inverting input terminal of the voltage comparator is connected to the output terminal of the reference circuit, the inverting input terminal of the voltage comparator is connected to the common port of the resistor R0 and the resistor R1 connected in series, the output terminal of the voltage comparator is connected to the feedback input port of the charge pump control circuit, and the power supply is connected to VDD; The power detection port of the mode selection circuit is connected to the VDD, the output detection port of the mode selection circuit is connected to the drain end of the PMOS tube P1 and the other end of the resistor R0, the reference input port of the mode selection circuit is connected to the output end of the reference circuit, and the through control port PON and the enable output port CPEN of the mode selection circuit are respectively connected to the through control port and the enable input port of the charge pump control circuit; The high-side input port of the internal power supply circuit is connected to the VDD, the low-side input port of the internal power supply circuit is connected to the output port VO of the wide-input voltage stabilizing circuit, and the output end of the internal power supply circuit outputs the power supply voltage VDDA; The input port of the substrate control circuit is connected to the enable output port of the mode selection circuit, the source output port of the substrate control circuit is connected to VDD and the source end of the PMOS transistor P0, the substrate output port of the substrate control circuit is connected to the substrate of the PMOS transistor P0, and the drain output port of the substrate control circuit is connected to the drain end of the PMOS transistor P0, the source end of the PMOS transistor P1, and one end of the capacitor C0; The high-side output port of the charge pump control circuit is connected to the switch S1 and the gate end of the PMOS transistor P0, the low-side output port of the charge pump control circuit is connected to the gate end of the PMOS transistor P1, and the capacitor control port is connected to the other end of the capacitor C0; The substrate of the PMOS transistor P1 is connected to the drain end of the PMOS transistor P1 ; the other end of the resistor R1 is connected to the ground.

2. The circuit according to claim 1, wherein: The mode selection circuit includes a voltage shift circuit, a comparator A, a comparator B, a resistor R2 and a resistor R3; The power detection port of the mode selection circuit is internally connected to one end of the resistor R2 and the input end of the voltage shift circuit, the output detection port of the mode selection circuit is internally connected to the inverting input end of the comparator B, the reference input port is internally connected to the non-inverting input end of the comparator A, the enable output end is internally connected to the output end of the comparator A, and the pass-through control end is internally connected to the output end of the comparator B; The other end of the resistor R2 is connected to the inverting input end of the comparator A and one end of the resistor R3; the other end of the resistor R3 is connected to the ground.

3. The circuit according to claim 1, wherein: The internal power supply circuit includes a comparator C, an inverter INV0, a ​​PMOS tube P2 and a PMOS tube P3; The high-side input end of the internal power supply circuit is internally connected to the inverting input end of the comparator C, the low-side input end is internally connected to the non-inverting input end of the comparator C, and the output end is connected to the drain ends of the PMOS tube P2 and the PMOS tube P3; The input end of the inverter INV0 is connected to the output end of the comparator C and the gate of the PMOS transistor P2, and the output end of the inverter INV0 is connected to the gate of the PMOS transistor P3; The source end of the PMOS transistor P2 is connected to VDD, the substrate is connected to the drain end of P2, the source end of the PMOS transistor P3 is connected to the output VO of the wide input voltage regulator circuit, and the substrate is connected to the drain end of the PMOS transistor P3.

4. The circuit according to claim 1, wherein: The charge pump control circuit includes an AND gate AND0, a NAND gate NAND0, a NAND gate NAND1, a NAND gate NAND2, a NOR gate NOR0, a NOR gate NOR1, an OR gate OR0, a buffer BUF0, a buffer BUF1, a buffer BUF2, a delay circuit 1, a delay circuit 2, a level shift circuit 1 and a level shift circuit 2; The enable input port, the clock input port and the feedback input port of the charge pump control circuit are respectively connected to the three input ports of the AND gate AND0, the through control port of the charge pump control circuit is internally connected to an input port of the NOR gate NOR0, the high-side output port is internally connected to the output port of the buffer BUF0, the capacitor control port is internally connected to the output port of the buffer BUF1, and the low-side output port is internally connected to the output port of the buffer BUF2; The input port of the delay circuit 1 is connected to the output port of the AND gate AND0, an input port of the OR gate OR0 and an input port of the NAND gate NAND0, and the output port is connected to the input port of the buffer BUF1 and the input port of the delay circuit 2; Another input port of the OR gate OR0 is connected to the output port of the delay circuit 2 and another input port of the NAND gate NAND0, and the output port is connected to an input port of the NAND gate NAND2; one input port of the NAND gate NAND1 is connected to the output port of the NAND gate NAND0, another input port is connected to the voltage comparator output signal, and the output port is connected to an input port of the NOR gate NOR1; another input port of the NOR gate NOR1 is connected to the through control signal, and the output port is connected to the input port of the level shift circuit 2; Another input port of the NOR gate NOR0 is connected to the output port of the NAND gate NAND2, and the output port is connected to the input port of the level shift circuit 1; The input port of the buffer BUF2 is connected to the output port of the level shift circuit 2, the input port of the buffer BUF0 is connected to the output port of the level shift circuit 1, and the other input port of the NAND gate NAND2 is connected to the output signal of the voltage comparator; In the charge pump control circuit, the power supply voltage of the buffer BUF0 and the buffer BUF2 is VDDA.

5. The circuit according to claim 1, wherein: The substrate control circuit includes: a level shift circuit 0, an inverter INV1, a PMOS transistor P4 and a PMOS transistor P5; The input port of the substrate control circuit is internally connected to the input end of the level shift circuit 0, the source output end is internally connected to the source end of the PMOS transistor P4, the substrate output end is internally connected to the drain end of the PMOS transistor P4 and the source end of the PMOS transistor P5, and the drain output end is internally connected to the drain end of the PMOS transistor P5; the input end of the inverter INV1 is connected to the output end of the level shift circuit and the gate end of the PMOS transistor P4, and the output end is connected to the gate end of the PMOS transistor P5; the substrate of the PMOS transistor P4 is connected to the source end and the substrate of the PMOS transistor P5; The power supply voltage of the inverter INV1 is VDDA.

6. The circuit according to claim 4 or 5, characterized in that The level shift circuit includes: a PMOS transistor P7, a PMOS transistor P8, an NMOS transistor N0, an NMOS transistor N1 and an inverter INV2; The input end of the level shift circuit is internally connected to the input end of the inverter INV2 and the gate end of the NMOS transistor N1, and the output end is internally connected to the drain end of the PMOS transistor P7, the gate end of the PMOS transistor P8, and the drain end of the NMOS transistor N0; the output end of the inverter is connected to the gate end of the NMOS transistor N0, and the power supply is connected to VDD; the drain end of the NMOS transistor N1 is connected to the drain end of the PMOS transistor P8 and the gate end of the PMOS transistor P7, and the source end is connected to ground; the source end of the PMOS transistor P7 is connected to the source end of the PMOS transistor P8 and the power supply voltage VDDA, and the source end of the NMOS transistor N0 is connected to ground.

7. The circuit according to claim 1, wherein: The voltages of the pass-through control port and the enable output port of the mode selection circuit depend on the voltages of the remaining ports; when VDD is less than the set voltage VSET, comparator A outputs a high level, the enable output port outputs a high level, and the overall circuit operates in operating mode 1; when VDD is greater than VSET, comparator A outputs a low level, the enable output port outputs a low level, and the overall circuit operates in operating mode 2.

8. The circuit according to claim 2, characterized in that The voltage shift circuit reduces the input signal voltage by a fixed value for output.

9. The circuit according to claim 2, characterized in that The charge pump control circuit, driven by the clock signal generated by the oscillator, adjusts the voltages of the high-side and low-side output ports and the capacitor control port in combination with the voltages of the through control port, the enable input port and the feedback input port; When the pass-through control port input is low, and the enable input port and feedback input port are high, the voltages of the high-side and low-side output ports and the capacitor control port are affected by the clock input signal: When the clock input signal and the delay signal D2 are both low, the high-side output port is low and P0 is turned on. Conversely, when the clock signal or the delay signal D2 is high, P0 is turned off. When the clock input signal and the delay signal D2 are both high, the low-side output port is low and P1 is turned on. When the clock signal or the delay signal D2 is low, P1 is turned off. When the delay signal D1 is high, the capacitor control port output is high, otherwise, it outputs low. When the through control port, the enable input port, and the feedback input port are at a low level, the voltages of the high-side and low-side output ports and the capacitor control port are all at a low level, and the PMOS tube P1 is turned on.

10. The circuit according to claim 1, wherein: The substrate control circuit is controlled by the voltage of the mode selection circuit enabling output port. When the mode selection circuit enabling output port outputs a low level, the substrate of the PMOS tube P0 is connected to VDD; when the mode selection circuit enabling output port outputs a high level, the substrate of the PMOS tube P0 is connected to the drain end of P0.

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