A circuit and method for LDO with constant power consumption without internal compensation capacitors

Abstract

This application discloses an LDO circuit and method with constant power consumption without internal compensation capacitors. The circuit includes: a power supply module that supplies power to the LDO circuit based on a power supply and a current mirror; a bias module that implements current bias based on a bias current and a current mirror; an output voltage divider feedback module that feeds back the output voltage to an operational amplifier module based on a voltage divider resistor; an input voltage divider feedback module that feeds back the input voltage to the operational amplifier module based on a voltage divider resistor; and an operational amplifier module that, based on the input and output voltage divider feedbacks, sets the value of an offset resistor to ensure that the output transistor is always in the saturation region, thereby maintaining constant power consumption. This application proposes an LDO circuit and method with constant power consumption without internal compensation capacitors, achieving constant power consumption of the LDO circuit by eliminating the internal compensation capacitors and introducing input feedback.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to an LDO circuit and method with constant power consumption without internal compensation capacitor. Background Technology

[0002] LDO, or low dropout regulator, is a type of low-dropout linear voltage regulator. Traditional linear regulators, such as the 78XX series chips, require the input voltage to be at least 2V to 3V higher than the output voltage; otherwise, they will not function properly. However, in some cases, this condition is clearly too stringent. For example, in a 5V to 3.3V conversion, the voltage difference between the input and output is only 1.7V, which obviously does not meet the operating conditions of traditional linear regulators. To address this, LDO-type voltage conversion chips were developed. LDO linear regulators have the advantages of low cost, low noise, and low quiescent current.

[0003] In power management chips, LDO circuits are required to power internal circuits. Traditional LDO circuits require large internal compensation capacitors, resulting in a large chip area. Furthermore, existing capacitorless LDOs suffer from increased power consumption when the input voltage drops below a preset output value, leading to higher chip power consumption in this situation. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this application provides an LDO circuit and method with constant power consumption and no internal compensation capacitor.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] An LDO circuit with constant power consumption and no internal compensation capacitor includes a power supply module, a bias module, an operational amplifier module, an input voltage divider feedback module, and an output voltage divider feedback module.

[0007] The power supply module is connected to the bias module and the operational amplifier module respectively, and is used to supply power to the LDO circuit based on the power supply VINT and the current mirror formed by MOS transistors MC3 and MC4.

[0008] The bias module is used to achieve current bias based on the bias current ibn and the current mirror formed by MOS transistors MC1 and MC2.

[0009] The output voltage divider feedback module is connected to the output voltage REGN and is used to feed the output voltage divider back to the operational amplifier module based on the voltage divider resistors R1 and R2.

[0010] The input voltage divider feedback module is connected to the input voltage HV and is used to feed the input voltage divider back to the operational amplifier module based on the voltage divider resistors R3 and R4.

[0011] The operational amplifier module receives output voltage divider feedback and input voltage divider feedback through input transistors MP1 and MP3, respectively. Based on the input voltage divider feedback and output voltage divider feedback, the output transistor MH3 is kept in the saturation region by setting the value of the offset resistor, thereby achieving the purpose of maintaining constant circuit power consumption.

[0012] The present invention further includes the following preferred embodiments:

[0013] Preferably, the power supply module includes the power supply VINT of the LDO circuit error amplifier module and a current mirror composed of MOS transistors MC3 and MC4;

[0014] Both MOS transistors MC3 and MC4 are PMOS transistors. The sources of MC3 and MC4 are connected to the power supply VINT, the gates of MC3 and MC4 are connected to the bias module, and the drains of MC3 and MC4 are connected to the bias module and the operational amplifier module, respectively.

[0015] Preferably, the bias module includes a bias current ibn and a current mirror composed of MOS transistors MC1 and MC2;

[0016] Both MOS transistors MC1 and MC2 are NMOS transistors. The sources of both MC1 and MC2 are connected to ground potential GND, the gates of both MC1 and MC2 are connected to bias current ibn, and the drains of both MC1 and MC2 are connected to bias current ibn and power supply module, respectively.

[0017] Preferably, the output voltage divider feedback module includes voltage divider resistors R1 and R2;

[0018] One end of resistor R1 is connected to the output voltage REGN of the LDO circuit, and the other end is connected to one end of resistor R2 and the input transistor MP1.

[0019] The other end of the resistor R2 is connected to ground potential GND;

[0020] The voltage divider resistors R1 and R2 divide the output voltage REGN according to the voltage division coefficient k to obtain the output voltage divider feedback voltage vfb, and feed it back to the input pair MP1 of the operational amplifier module.

[0021] Preferably, the input voltage divider feedback module includes voltage divider resistors R3 and R4;

[0022] One end of resistor R3 is connected to the input voltage HV of LDO, and the other end is connected to one end of resistor R4 and the input transistor MP3.

[0023] The other end of the resistor R4 is connected to ground potential GND;

[0024] The voltage divider resistors R3 and R4 divide the input voltage HV according to the voltage division coefficient k to obtain the input voltage divider feedback voltage hv_fb, and feed it back to the input transistor MP3 of the operational amplifier module.

[0025] Preferably, the operational amplifier module includes input transistors MP1, MP2 and MP3, offset resistors R0 and R0, a current mirror load composed of MOSFETs MN1 and MN2, and high-voltage transistors MH1, MH2 and MH3.

[0026] The input transistors MP1, MP2 and MP3 are all PMOS transistors;

[0027] The MOS transistors MN1 and MN2 and the high-voltage transistor MH1 are all NMOS transistors, while MH2 and MH3 are both PMOS transistors.

[0028] The gate of the input pair transistor MP1 is the output voltage divider feedback input terminal, the source is connected to the power supply module through the offset resistor R0, and the drain is connected to the gate of MH1 and the drain of MN2.

[0029] The source of MH1 is connected to ground potential GND, and the drain is connected to the gates of MH2 and MH3 as well as the drain of MH2.

[0030] The sources of MH2 and MH3 are both connected to the input voltage HV. MH3 is the output transistor, and its drain is connected to the output voltage REGN.

[0031] The source of MN2 is connected to ground potential GND, and the gates of MN1 and MN2 are both connected to the drain of MP2 and the drain of MP3.

[0032] The source of MN1 is connected to ground potential GND, and the drain is connected to the drain of MP3;

[0033] The MP3's gate is the input voltage divider feedback input terminal, and the source is connected to the power supply module;

[0034] The gate of MP2 is connected to the reference voltage vbg, and the source is connected to one end of the offset resistor R0. The other end is connected to the connection point between R0 and the power supply module.

[0035] Preferably, the resistors R1:R2 = R3:R4, and R0 = R0.

[0036] A method for maintaining constant power consumption without internal compensation capacitors, the method comprising the following steps:

[0037] Step 1: Set the voltage divider coefficient k from REGN to vfb, R1:R2=R3:R4, then vfb=kREGN, hv_fb=kHV;

[0038] Step 2: Ignore the area where MP3 and MP2 work together, and analyze the output voltage REGN when MP2 and MP3 work alone;

[0039] Step 3: Based on the output voltage REGN, analyze the VDS of output transistor MH3;

[0040] Step 4: Based on the VDS value of the output transistor MH3 obtained from the analysis, set the values ​​of R0 and R2 to keep the output transistor MH3 in the saturation region, thereby achieving the purpose of keeping the circuit power consumption constant.

[0041] Preferably, in step 2, when only MP2 is working, the output voltage REGN = vbg / k;

[0042] When only MP3 is working, hv_fb = vfb + ΔV;

[0043] Where ΔV is the voltage drop across R0, the output voltage REGN = HV - (ΔV / k).

[0044] Preferably, in step 3, when HV>(vbg+ΔV) / k, hv_fb>vbg, only MP2 works, and at this time the VDS of the output tube MH3 is HV-REGN=HV-(vbg / k)>ΔV / k;

[0045] When HV < (vbg + ΔV) / k, only MP3 works. At this time, the VDS of the output tube MH3 is HV - REGN = ΔV / k.

[0046] Therefore, the VDS value of the output tube MH3 is greater than or equal to ΔV / k.

[0047] The beneficial effects achieved by this application are:

[0048] This application proposes an LDO circuit and method with constant power consumption without internal compensation capacitor. By eliminating the internal compensation capacitor and introducing input voltage divider feedback and output voltage divider feedback, the power consumption of the LDO circuit can be kept constant. Attached Figure Description

[0049] Figure 1 This is a circuit diagram of an LDO circuit with constant power consumption without internal compensation capacitor, provided in Embodiment 1 of this application. Detailed Implementation

[0050] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0051] like Figure 1As shown, Embodiment 1 of this application provides an LDO circuit with constant power consumption without internal compensation capacitor, including a power supply module, a bias module, an operational amplifier module, an input voltage divider feedback module, and an output voltage divider feedback module. In a preferred but non-limiting embodiment of the present invention, the power supply module is connected to the bias module and the operational amplifier module respectively, and is used to power the LDO circuit based on the power supply VINT and the current mirror formed by MOS transistors MC3 and MC4.

[0052] More preferably, the power supply module includes the power supply VINT for the LDO error amplifier section and a current mirror composed of MOSFETs MC3 and MC4;

[0053] Both MOS transistors MC3 and MC4 are PMOS transistors. The sources of MC3 and MC4 are connected to the power supply VINT, the gates of MC3 and MC4 are connected to the bias module, and the drains of MC3 and MC4 are connected to the bias module and the operational amplifier module, respectively.

[0054] The bias module is used to achieve current bias based on the bias current ibn and the current mirror formed by MOS transistors MC1 and MC2.

[0055] More preferably, the bias module includes a bias current ibn and a current mirror formed by MOS transistors MC1 and MC2;

[0056] Both MOS transistors MC1 and MC2 are NMOS transistors. The sources of both MC1 and MC2 are connected to ground potential GND, the gates of both MC1 and MC2 are connected to bias current ibn, and the drains of both MC1 and MC2 are connected to bias current ibn and power supply module, respectively.

[0057] The output voltage divider feedback module is connected to the output voltage REGN and is used to feed the output voltage divider back to the operational amplifier module based on the voltage divider resistors R1 and R2.

[0058] More preferably, the output voltage divider feedback module includes voltage divider resistors R1 and R2;

[0059] One end of resistor R1 is connected to the output voltage REGN of the LDO circuit, and the other end is connected to one end of resistor R2 and the input transistor MP1.

[0060] The other end of the resistor R2 is connected to ground potential GND;

[0061] The voltage divider resistors R1 and R2 divide the output voltage REGN according to the voltage division coefficient k to obtain the output voltage divider feedback voltage vfb, and feed it back to the input pair MP1 of the operational amplifier module.

[0062] The input voltage divider feedback module is connected to the input voltage HV and is used to feed the input voltage divider back to the operational amplifier module based on the voltage divider resistors R3 and R4.

[0063] More preferably, the input voltage divider feedback module includes voltage divider resistors R3 and R4;

[0064] One end of resistor R3 is connected to the input voltage HV of LDO, and the other end is connected to one end of resistor R4 and the input transistor MP3.

[0065] The other end of the resistor R4 is connected to ground potential GND;

[0066] The voltage divider resistors R3 and R4 divide the input voltage HV according to the voltage division coefficient k to obtain the input voltage divider feedback voltage hv_fb, and feed it back to the input transistor MP3 of the operational amplifier module.

[0067] The operational amplifier module receives output voltage divider feedback and input voltage divider feedback through input transistors MP1 and MP3, respectively. Based on the input voltage divider feedback and output voltage divider feedback, the output transistor MH3 is kept in the saturation region by setting the value of the offset resistor R0, thereby achieving the purpose of maintaining constant circuit power consumption.

[0068] More preferably, the operational amplifier module includes input transistors MP1, MP2 and MP3, offset resistors R0 and R0, a current mirror load composed of MOSFETs MN1 and MN2, and high-voltage transistors MH1, MH2 and MH3.

[0069] The input transistors MP1, MP2 and MP3 are all PMOS transistors;

[0070] The MOS transistors MN1 and MN2 and the high-voltage transistor MH1 are all NMOS transistors, while MH2 and MH3 are both PMOS transistors.

[0071] The gate of the input pair transistor MP1 is the output voltage divider feedback input terminal, the source is connected to the power supply module through the offset resistor R0, and the drain is connected to the gate of MH1 and the drain of MN2.

[0072] The source of MH1 is connected to ground potential GND, and the drain is connected to the gates of MH2 and MH3 as well as the drain of MH2.

[0073] The sources of MH2 and MH3 are both connected to the input voltage HV. MH3 is the output transistor, and its drain is connected to the output voltage REGN.

[0074] The source of MN2 is connected to ground potential GND, and the gates of MN1 and MN2 are both connected to the drain of MP2 and the drain of MP3.

[0075] The source of MN1 is connected to ground potential GND, and the drain is connected to the drain of MP3;

[0076] The MP3's gate is the input voltage divider feedback input terminal, and the source is connected to the power supply module;

[0077] The gate of MP2 is connected to the reference voltage vbg, and the source is connected to one end of the offset resistor R0. The other end is connected to R0 and the power supply module.

[0078] More preferably, the resistors R1:R2 = R3:R4, and R0 = R0.

[0079] The present invention also provides a method for maintaining constant power consumption without internal compensation capacitor based on the above-mentioned LDO circuit with constant power consumption without internal compensation capacitor, the method comprising the following steps:

[0080] Step 1: Set the voltage divider coefficient k from REGN to vfb, R1:R2=R3:R4, then vfb=kREGN, hv_fb=kHV;

[0081] Step 2: Ignoring the region where MP3 and MP2 work together, analyze the output voltage REGN when MP2 and MP3 work alone:

[0082] When only MP2 is working, the output voltage REGN = vbg / k;

[0083] When only MP3 is working, hv_fb = vfb + ΔV;

[0084] Where ΔV is the voltage drop across R0 (ignoring substrate bias effect), the output voltage REGN = HV - (ΔV / k).

[0085] Step 3: Based on the output voltage REGN, analyze the VDS of output transistor MH3;

[0086] When HV>(vbg+ΔV) / k, hv_fb>vbg, only MP2 works, and at this time the VDS of the output tube MH3 is =HV-REGN=HV-(vbg / k)>ΔV / k;

[0087] When HV < (vbg + ΔV) / k, only MP3 works. At this time, the VDS of the output tube MH3 is HV - REGN = ΔV / k.

[0088] Therefore, the VDS value of the output tube MH3 is greater than or equal to ΔV / k.

[0089] Step 4: Based on the VDS value of the output transistor MH3 obtained from the analysis, set the value of R0 and R0 to ΔV divided by the current flowing through R0, so that the output transistor MH3 is always in the saturation region, thereby achieving the purpose of keeping the circuit power consumption constant.

[0090] This application proposes an LDO circuit and method with constant power consumption without internal compensation capacitor. By eliminating the internal compensation capacitor and introducing input feedback, the power consumption of the LDO circuit can be kept constant.

[0091] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. An LDO circuit with constant power consumption and no internal compensation capacitor, comprising a power supply module, a bias module, an operational amplifier module, an input voltage divider feedback module, and an output voltage divider feedback module, characterized in that: The power supply module is connected to the bias module and the operational amplifier module respectively, and is used to supply power to the LDO circuit based on the power supply VINT and the current mirror formed by MOS transistors MC3 and MC4. The bias module is used to achieve current bias based on the bias current ibn and the current mirror formed by MOS transistors MC1 and MC2. The output voltage divider feedback module is connected to the output voltage REGN and is used to feed the output voltage divider back to the operational amplifier module based on the voltage divider resistors R1 and R2. The input voltage divider feedback module is connected to the input voltage HV and is used to feed the input voltage divider back to the operational amplifier module based on the voltage divider resistors R3 and R4. The operational amplifier module receives output voltage divider feedback and input voltage divider feedback through input transistors MP1 and MP3, respectively. Based on the input voltage divider feedback and output voltage divider feedback, the output transistor MH3 is kept in the saturation region by setting the value of the offset resistor, thereby achieving the purpose of maintaining constant circuit power consumption.

2. The LDO circuit with constant power consumption without internal compensation capacitor according to claim 1, characterized in that: The power supply module includes the power supply VINT of the LDO circuit error amplifier module and a current mirror composed of MOS transistors MC3 and MC4. Both MOS transistors MC3 and MC4 are PMOS transistors. The sources of MC3 and MC4 are connected to the power supply VINT, the gates of MC3 and MC4 are connected to the bias module, and the drains of MC3 and MC4 are connected to the bias module and the operational amplifier module, respectively.

3. The LDO circuit with constant power consumption without internal compensation capacitor according to claim 2, characterized in that: The bias module includes a bias current ibn and a current mirror composed of MOS transistors MC1 and MC2; Both MOS transistors MC1 and MC2 are NMOS transistors. The sources of both MC1 and MC2 are connected to ground potential GND, the gates of both MC1 and MC2 are connected to bias current ibn, and the drains of both MC1 and MC2 are connected to bias current ibn and power supply module, respectively.

4. The LDO circuit with constant power consumption without internal compensation capacitor according to claim 3, characterized in that: The output voltage divider feedback module includes voltage divider resistors R1 and R2; One end of resistor R1 is connected to the output voltage REGN of the LDO circuit, and the other end is connected to one end of resistor R2 and the input transistor MP1. The other end of the resistor R2 is connected to ground potential GND; The voltage divider resistors R1 and R2 divide the output voltage REGN according to the voltage division coefficient k to obtain the output voltage divider feedback voltage vfb, and feed it back to the input pair MP1 of the operational amplifier module.

5. The LDO circuit with constant power consumption without internal compensation capacitor according to claim 4, characterized in that: The input voltage divider feedback module includes voltage divider resistors R3 and R4; One end of resistor R3 is connected to the input voltage HV of the LDO circuit, and the other end is connected to one end of resistor R4 and the input transistor MP3. The other end of the resistor R4 is connected to ground potential GND; The voltage divider resistors R3 and R4 divide the input voltage HV according to the voltage division coefficient k to obtain the input voltage divider feedback voltage hv_fb, and feed it back to the input transistor MP3 of the operational amplifier module.

6. The LDO circuit with constant power consumption without internal compensation capacitor according to claim 5, characterized in that: The operational amplifier module includes input transistors MP1, MP2 and MP3, offset resistors R0 and R0, a current mirror load composed of MOSFETs MN1 and MN2, and high-voltage transistors MH1, MH2 and MH3. The input transistors MP1, MP2 and MP3 are all PMOS transistors; The MOS transistors MN1 and MN2 and the high-voltage transistor MH1 are all NMOS transistors, while MH2 and MH3 are both PMOS transistors. The gate of the input pair transistor MP1 is the output voltage divider feedback input terminal, the source is connected to the power supply module through the offset resistor R0, and the drain is connected to the gate of MH1 and the drain of MN2. The source of MH1 is connected to ground potential GND, and the drain is connected to the gates of MH2 and MH3 as well as the drain of MH2. The sources of MH2 and MH3 are both connected to the input voltage HV. MH3 is the output transistor, and its drain is connected to the output voltage REGN. The source of MN2 is connected to ground potential GND, and the gates of MN1 and MN2 are both connected to the drain of MP2 and the drain of MP3. The source of MN1 is connected to ground potential GND, and the drain is connected to the drain of MP3; The MP3's gate is the input voltage divider feedback input terminal, and the source is connected to the power supply module; The gate of MP2 is connected to the reference voltage vbg, and the source is connected to one end of the offset resistor R0. The other end is connected to the connection point between R0 and the power supply module.

7. The LDO circuit with constant power consumption without internal compensation capacitor according to claim 6, characterized in that: Resistors R1:R2 = R3:R4, R0 = R0.

8. A method for maintaining constant power consumption without internal compensation capacitor based on the LDO circuit with constant power consumption without internal compensation capacitor as described in claim 6, characterized in that: The method includes the following steps: Step 1: Set the voltage divider coefficient k from REGN to vfb, set R1:R2=R3:R4, then vfb=kREGN, hv_fb=kHV; Step 2: Ignore the area where MP3 and MP2 work together, and analyze the output voltage REGN when MP2 and MP3 work alone; Step 3: Based on the output voltage REGN, analyze the drain-source voltage VDS of the output transistor MH3; Step 4: Based on the VDS value of the output transistor MH3 obtained from the analysis, set the values ​​of R0 and R2 to keep the output transistor MH3 in the saturation region, thereby achieving the purpose of keeping the circuit power consumption constant.

9. The method for maintaining constant power consumption without internal compensation capacitor according to claim 8, characterized in that: In step 2, when only MP2 is working, the output voltage REGN = vbg / k; When only MP3 is working, hv_fb = vfb + ΔV; Where ΔV is the voltage drop across R0, the output voltage REGN = HV - (ΔV / k).

10. A method for maintaining constant power consumption without internal compensation capacitor according to claim 9, characterized in that: In step 3, when HV>(vbg+ΔV) / k, hv_fb>vbg, only MP2 works, and at this time the VDS of output tube MH3 is HV-REGN=HV-(vbg / k)>ΔV / k; When HV < (vbg + ΔV) / k, only MP3 works. At this time, the VDS of the output tube MH3 is HV - REGN = ΔV / k. Therefore, the VDS value of the output tube MH3 is greater than or equal to ΔV / k.

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