Processing systems, related integrated circuits, devices, and methods

Abstract

The present disclosure relates to processing systems, related integrated circuits, devices and methods. In one embodiment, a processing system comprises a subcircuit comprising a tri-state driver circuit, wherein the tri-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal and to selectively activate one of the following switch states depending on the logic levels of the first signal and the second signal: in a first switch state, connecting the transmission terminal to the positive power supply terminal by closing a first electronic switch, in a second switch state, connecting the transmission terminal to the negative power supply terminal by closing a second electronic switch, and in a third switch state, placing the transmission terminal in a high impedance state by opening the first electronic switch and the second electronic switch.

Description

[0001] Cross-references to related applications

[0002] This application claims the right to Italian application No. 102022000005354, filed on March 18, 2022, which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a processing system, such as a microcontroller, configured to exchange data via a CAN FD optical bus. Background Technology

[0004] Figure 1 A typical electronic system, such as the electronic system of a vehicle, is shown, including multiple processing systems 10, such as embedded systems or integrated circuits, such as field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or microcontrollers (e.g., dedicated to the automotive market).

[0005] For example, in Figure 1 The diagram illustrates three processing systems 101, 102, and 103 connected via a suitable communication system 20. For example, the communication system may include a vehicle control bus, such as a Controller Area Network (CAN) bus, connected via a gateway to a vehicle control bus, and possibly a multimedia bus, such as a Media-Oriented System Transport (MOST) bus. Typically, the processing systems 10 are located in different locations within the vehicle and may include, for example, an engine control unit, a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM), and / or a navigation and / or multimedia audio system. Therefore, one or more processing systems 10 may also implement real-time control and adjustment functions. These processing systems are typically identified as electronic control units (ECUs).

[0006] Figure 2 The display can be used as Figure 1 A block diagram of an exemplary digital processing system 10 (e.g., a microcontroller) of any of the processing systems 10.

[0007] In the considered example, processing system 10 includes digital processing circuitry 102. For example, digital processing circuitry 102 may include one or more dedicated combinational and / or sequential logic circuits and / or a microprocessor and / or programmable logic circuitry, such as an FPGA, programmed via software instructions. Typically, the program data of the software and / or programmable logic circuitry executed by microprocessor 102 is stored in non-volatile program memory 104, such as flash memory or EEPROM. Therefore, memory 104 is configured to store firmware of processing unit 102, wherein the firmware includes software instructions and / or program data of programmable logic circuitry to be executed by microprocessor 102. Typically, non-volatile memory 104 may also be used to store other data, such as configuration data, such as calibration data.

[0008] The digital processing circuitry 102 is also typically associated with volatile memory 104b, such as random access memory (RAM). For example, memory 104b can be used to store temporary data.

[0009] like Figure 2 As shown, communication with the memories 104 and / or 104b is typically performed via one or more memory controllers 100. The memory controllers 100 may be integrated into the digital processing circuitry 102 or connected to the digital processing circuitry 102 via a communication channel (e.g., the system bus of the processing system 10). For example, the system bus may include one or more bus systems, such as those based on an Advanced Scalable Interface (AXI) bus architecture and / or a Network on Chip (NoC).

[0010] Similarly, memory 104 and / or 104b may be integrated with digital processing circuitry 102 in a single integrated circuit, or memory 104 and / or 104b may be in the form of a separate integrated circuit and connected to digital processing circuitry 102, for example, via traces on a printed circuit board.

[0011] In the example under consideration, the digital processing circuit 102 may have one or more associated (hardware) resources / peripherals 106 selected from the following group:

[0012] - One or more communication interfaces IF, such as those used for exchanging data via communication system 20, such as Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface Bus (SPI), Inter-Integrated Circuit (I2C), Controller Area Network (CAN) bus, and / or Ethernet interface, and / or debug interface; and / or

[0013] - One or more analog-to-digital converters (AD) and / or digital-to-analog converters (DA); and / or one or more dedicated digital components (DC), such as hardware timers and / or counters, or cryptographic coprocessors; and / or

[0014] - One or more analog components AC, such as comparators, sensors, such as temperature sensors, etc.; and / or

[0015] One or more mixed-signal component MSCs, such as PWM (Pulse Width Modulation) drivers.

[0016] For example, for this purpose, the system bus may actually include the Advanced Microcontroller Bus Architecture (AMBA) High Performance Bus (AHB) and the Advanced Peripheral Bus (APB) for connecting the resource / peripheral device 106 to the AMBAAHB bus.

[0017] Therefore, the digital processing system 10 can support different functions. For example, the behavior of the digital processing circuit 102 is determined by firmware stored in the memory 104, such as software instructions executed by the microprocessor 102 of the microcontroller 10. Thus, by installing different firmware, the same hardware (microcontroller) can be used for different applications.

[0018] As described above, in many applications, data must be exchanged between several processing systems 10 via communication channel 20. For example, in the automotive industry and many other fields, one or more CAN buses are often used to exchange data between processing systems 10. More specifically, in many applications, processing system 10 should be connected to a CAN FD Light bus. For example, the CAN FD Light protocol is described in the documents “CAN FD Light specification and test plan,” CAN in Automation (CiA) 604-1, version 1.0.0, or “CAN FD Light network protocol and implementation,” EuES003-06, version 1.3, which are incorporated herein by reference.

[0019] For example, Figure 3 A typical case is shown, in which the first processing system 101 and the second processing system 102 are connected to the CANFD optical bus 20.

[0020] For example, each of processing systems 101 and 102 may include:

[0021] - CAN FD bus transceiver 320, which is configured to connect to CAN bus 20;

[0022] - Processing unit 102; and

[0023] - Communication interface IF, which is configured to connect processing unit 102 to CAN bus transceiver 320;

[0024] For example, such an additional CAN bus transceiver 320 is often required because the CAN bus 20 uses a different signal level than the processing unit 102 and / or for current isolation. For example, in the case of the CAN FDLight protocol, transceiver 320 is a Controller Area Network Flexible Data Rate (CAN FD) transceiver.

[0025] For example, a conventional CAN FD bus transceiver 320 includes two interfaces. The first interface is configured to exchange data via the CAN bus 20 by transmitting and receiving differential non-return-to-zero (NRZ) encoded signals. Conversely, the second interface is configured to receive a transmit signal TXD and provide a receive signal RXD, where the transmit signal TXD and the receive signal RXD are NRZ signals, preferably single-pole non-return-to-zero (NRZ-L) encoded signals, such as binary encoded signals set high (typically the power supply voltage of the processing unit 102) for transmitting logic "1" or low (typically ground) for transmitting logic "0".

[0026] Typically, transceiver 320 may be provided as a separate integrated circuit 32 connected to integrated circuit 30, which includes digital processing circuitry 102 and hardware interface IF (see, for example, processing system 101), or transceiver 320 may be integrated into integrated circuit 30, which includes digital processing circuitry 102 and hardware interface IF (see, for example, processing system 102). Typically, hardware interface IF may also be integrated into integrated circuit 32 of transceiver 320.

[0027] For example, Figure 4 A possible example of a CAN bus 20 is shown, specifically the physical layer as specified in ISO 11898-2.

[0028] Specifically, in the example under consideration, the CAN bus is implemented via two lines CANH and CANL, which are terminated at both ends by their respective terminating resistors RT, which are typically 120Ω in the case of the CAN bus.

[0029] Figure 5 An example of the CAN FD transceiver 320 is shown in this regard.

[0030] Specifically, transceiver 320 includes terminals RX and TX, such as pins / pads of integrated circuit 32, for providing a receive signal RXD and a receive transmit signal TXD. Furthermore, transceiver 320 includes terminals, such as pins / pads, for connecting transceiver 320 to lines CANH and CANL.

[0031] According to the CAN FD standard, transceiver 320 is configured to receive NRZ (e.g., NRZ-L) encoded transmission signals TXD, such as binary bit sequences. In the considered example, transceiver 320 therefore includes a CAN FD transmitter circuit 322, which is configured to selectively apply differential voltages to the CANH and CANL lines, for example, by selectively connecting the following:

[0032] - Terminal / wire CANH via first electronic switch SW H To the first power supply voltage V P And - terminal / line CANL via second electronic switch SW L To the second power supply voltage V N The second power supply voltage V N Less than the first power supply voltage V P .

[0033] Logic signals ('0' and '1') are transmitted via CAN bus 20 in "dominant" and "recessive" levels. For example, this can be achieved by closing switch SW via driver 322. H and SW L To emit a dominant level. In this state, current flows from voltage V. P / Switch SW H The current flows through the CANH line, via the CANL line, through the terminal resistor RT, to the switch SW. L / Voltage V N This current results in a first differential voltage between wires CANH and CANL. To transmit a recessive signal, driver 322 can disconnect switch SW. H and SW L Therefore, when all processing systems emit a recessive level, no current flows through the terminal resistor RT, resulting in a second differential voltage between lines CANH and CANL that is less than the first differential voltage and is, for example, zero or smaller in any case. As a result of this implementation, the dominant level always overrides the recessive level; that is, at least one driver 320 emitting a dominant level will enforce a dominant level across the entire bus 20. For example, according to ISO 11898-2, a dominant level is interpreted as logic "0" and a recessive signal is interpreted as logic "1".

[0034] Transceiver 320 therefore also includes a CAN FD receiver circuit 324, which is configured to generate a receive signal RXD by analyzing the differential voltage between the terminals / wires CANH and CANL. Specifically, according to the CAN FD standard, the signal RXD is also an NRZ-encoded signal, such as a binary-encoded signal, used to indicate the logic level of the CAN bus 20, i.e., a dominant level ('0') or a recessive level ('1').

[0035] Typically, each processing system 10 implementing the CAN FDLight protocol controller should be able to manage the transmission and reception of CAN FDLight frames. In practice, the processing system 10 / CAN FDLight controller can be a CAN FDLight master circuit (commander) or a CAN FDLight slave circuit (responder). Specifically, in the case of a CAN FDLight commander, the processing system 10 first transmits a CAN FDLight frame, and if the CAN FDLight frame includes a request for a desired response, the processing system 10 will then receive a response CAN FDLight frame. Conversely, in the case of a CAN FDLight responder, the processing system 10 first receives a CAN FDLight frame, and if the received CAN FDLight frame corresponds to a request for a response from the CAN FDLight responder, the processing system 10 will then transmit a response CAN FDLight frame.

[0036] Therefore, the CAN transceiver 320 essentially converts the voltage level of the signal, while CAN FD Light protocol management and corresponding signal timing are implemented in the CAN FD Light controller implemented in the processing system 10. Typically, the communication interface IF implements at least the data link layer. Conversely, higher protocol layers (e.g., for implementing the CAN FD Light protocol controller) can be implemented within the communication interface IF and / or processing circuitry 102 in any suitable manner. For example, Italian patent applications 102021000022037 and 102021000022124 disclose possible solutions for implementing such a CAN FD Light controller and communication interface IF in the microcontroller 10, which are incorporated herein by reference.

[0037] Therefore, according to the CAN FD optical standard, each processing system 10 connected to the CAN FD optical bus 20 requires a corresponding CAN FD transceiver 320.

[0038] The inventors have observed that the processing system 10 (e.g., a vehicle's ECU) may also include multiple processing units 102, which may be integrated into the same integrated circuit or provided as separate integrated circuits and connected together on a common printed circuit board. Thus, one or more such processing units can be configured to exchange data on the CAN FD optical bus 20, for example, to communicate with other processing units 102 within the same processing system 10 or with other processing systems 10. Therefore, in this case, providing a CAN FD transceiver 320 for each of these processing units could involve significant costs. Summary of the Invention

[0039] The embodiments provide a solution for managing communication on a CAN FD optical bus that does not require a CAN FD transceiver for each processing unit.

[0040] As described above, various embodiments of this disclosure relate to a processing system including a sub-circuit, which includes a CANFD Light controller. Specifically, in various embodiments, the processing system includes a positive power supply terminal and a negative power supply terminal configured to be connected to a power supply voltage. Furthermore, in various embodiments, the sub-circuit includes a transmission terminal and a three-state driver circuit. For example, the three-state driver circuit may include a first electronic switch connected between the transmission terminal and the positive power supply terminal and a second electronic switch connected between the transmission terminal and the negative power supply terminal. The three-state driver circuit also includes combinational logic circuitry configured to monitor the logic levels of a first signal and a second signal, and selectively activate one of a plurality of switch states based on the logic levels of the first signal and the second signal. Specifically, in a first switch state, the three-state driver circuit connects the transmission terminal to the positive power supply terminal by closing the first electronic switch. In a second switch state, the three-state driver circuit connects the transmission terminal to the negative power supply terminal by closing the second electronic switch. Finally, in a third switch state, the three-state driver circuit places the transmission terminal in a high-impedance state by opening the first and second electronic switches.

[0041] For example, for this purpose, the combinational logic circuit of a three-state driver circuit can be configured to activate a second switch state when the first signal is deasserted, activate a first switch state when both the first and second signals are asserted, and activate a third switch state when both the first and second signals are deasserted. Alternatively, the combinational logic circuit of a three-state driver circuit can be configured to activate a second switch state when both the first and second signals are asserted, activate a first switch state when both the first and second signals are asserted, and activate a third switch state when the second signal is deasserted.

[0042] In various embodiments, the CAN FD Light controller is configured to transmit the bits of the CAN FD Light frame sequentially. Typically, a CAN FD Light frame includes a start-of-frame bit, followed by a sequence of bits in sequence including a cyclic redundancy check (CRC) delimiter bit, an acknowledgment bit, an acknowledgment delimiter bit, and a 7-bit end-of-frame field, as well as multiple intermediate bits between the start-of-frame bit and the CRC delimiter bit.

[0043] Specifically, in various embodiments, the CAN FD Light controller supports one or more operating modes to sequentially transmit bits of the CAN FD Light frame by generating a first signal and a second signal in response to a transmission clock signal.

[0044] Specifically, in the first operating mode, the CAN FD Light controller is configured to transmit a start-of-frame bit by activating a second switch state for one clock cycle, sequentially transmit intermediate bits by sequentially selecting one bit from the intermediate bits and activating either the first or second switch state according to the logic level of the selected bit, and activate a third switch state once the intermediate bit has been transmitted. Therefore, in this case, the CAN FD Light controller activates a high-impedance state once the intermediate bit has been transmitted. Preferably, the CAN FD Light controller activates the third switch state at the end of the last bit of the intermediate bits or during the CRC delimiter bit. For example, by holding the third switch state for ten clock cycles, the CRC delimiter bit, acknowledgment bit, acknowledgment delimiter bit, and end-of-frame field can be transmitted. However, the CAN FD Light controller may also simply activate the high-impedance state without explicitly waiting for ten clock cycles.

[0045] Therefore, in the first operating mode, the CAN FD Light controller is configured to transmit the frame start bit and middle bit using a push-pull configuration of a tri-state driver, and then activate a high-impedance state once the middle bit has been transmitted, for example, at the end of the last bit of the middle bit or during the CRC delimiting bit. For example, in the case of the previously mentioned embodiment of the tri-state driver circuit, the CAN FD Light controller can be configured to generate a transmission signal corresponding to the first signal by sequentially providing the bits of the CAN FD Light frame in response to a transmission clock signal, assert a second signal when the frame start bit and middle bit are provided, and deassert the second signal, for example, at the end of the last bit of the middle bit or during the CRC delimiting bit.

[0046] For example, to generate the transmission signal, the CAN FD Light controller may include digital processing circuitry and a serial communication interface. The digital processing circuitry is configured to generate frames that include at least the middle bits of the CAN FD Light frame. For example, the serial communication interface may include: a control register configured to store data identifying the requested number of bits; clock management circuitry configured to receive a system clock signal and generate a scaled-down clock signal corresponding to the transmission clock signal; and a transmission shift register configured to generate the transmission signal by sequentially providing the contents of the transmission shift register in response to the transmission clock signal when an assertion transmission enable signal is given. Therefore, in this case, the processing system can be configured to selectively transfer frames from the digital processing circuitry to the transmission shift register, and the transmission control circuitry can be configured to receive a transmission start signal requesting data transmission and then assert the transmission enable signal. Furthermore, when the transmission enable signal is asserted, the transmission control circuitry increments the transmission count value in response to the transmission clock signal and determines whether the transmission count value has reached the requested number of bits. Therefore, in response to determining that the transmission count value has reached the requested number of bits, the transmission control circuitry can cancel the assertion of the transmission enable signal. For example, in this case, the transmission control circuit can be configured to assert the second signal in response to the start of the transmission signal, determine whether the serial communication interface provides the last bit of the intermediate bit, and then deassert the second signal again.

[0047] In different embodiments, the processing system further includes a receive terminal and the CAN FD Light controller is configured to sequentially receive bits of another CAN FD Light frame via the receive terminal. This processing system can be used in various applications. For example, in a first case, the processing system further includes a CAN FD transceiver comprising a transmit terminal and a receive terminal, wherein the transmit terminal of the CAN FD transceiver is connected to the transmit terminal of the sub-circuit and the receive terminal of the CAN FD transceiver is connected to the receive terminal of the sub-circuit; that is, the sub-circuit including the CAN FD Light controller is connected to the CAN FD transceiver. However, when using this first operating mode, the processing system may also include additional sub-circuit components, wherein these additional sub-circuit components further include additional transmit terminals, additional receive terminals, additional tri-state driver circuitry, and additional CAN FD Light controllers, wherein the additional transmit terminal of the additional sub-circuit is connected to the transmit terminal of the sub-circuit, and the receive terminal of the additional sub-circuit is connected to the receive terminal of the sub-circuit. Specifically, as will be described in more detail below, in this case, by connecting a pull-up resistor between the transmission terminal and the positive power supply terminal of the sub-circuit, the two sub-circuits can exchange data by transmitting at least the middle bit of the CANFD Light frame in a push-pull configuration, thereby allowing a higher transmission speed than the conventional configuration of a CAN controller using a shared pull-up resistor.

[0048] Alternatively, the CAN FD transceiver can be omitted, and additional transmit terminals of another sub-circuit can be connected to the transmit terminals of the other sub-circuit, and receive terminals of another sub-circuit can be connected to the transmit terminals of the other sub-circuit, and receive terminals of the other sub-circuit can be connected to the transmit terminals of the other sub-circuit. Therefore, in the same case, the two sub-circuits can exchange data by transmitting at least the middle bits of a CAN FD Light frame with a push-pull configuration.

[0049] In different embodiments, the processing system may also support a second operating mode, which can be used when the additional sub-circuit is omitted and the transmit terminal of the CAN FD transceiver is connected to the transmit terminal of the sub-circuit, and the receive terminal of the CAN FD transceiver is connected to the receive terminal of the sub-circuit. Specifically, in this case, the CAN FD Light controller can always use a push-pull configuration, that is, transmitting the start-of-frame bit by activating the second switch state within one clock cycle, transmitting the intermediate bit sequentially by selecting one bit of the intermediate bit and activating the first or second switch state according to the logic level of the selected bit, and activating the first switch state once the intermediate bit has been transmitted. For example, in this case, the transmission control circuit may not interrupt the second signal. Attached Figure Description

[0050] Embodiments of this disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0051] Figure 1 An example of an electronic system including multiple processing systems is shown;

[0052] Figure 2 An example of a processing system is shown;

[0053] Figure 3 An example of a CAN FD Light communication system is shown;

[0054] Figure 4 An example of a CAN bus is shown;

[0055] Figure 5 An example of a CAN FD transceiver is shown;

[0056] Figure 6 An embodiment of two CAN FD Light controllers connected to a shared CAN FD transceiver is shown;

[0057] Figure 7 It shows the use of Figure 6 An example of an open-drain driver circuit for a CAN FD Light controller;

[0058] Figure 8 An embodiment of two CAN FD Light controllers connected to a common line without CAN FD Light transceivers is shown;

[0059] Figure 9 and 10 An embodiment of a configurable CAN FD Light controller is shown;

[0060] Figure 11 and Figure 12 It shows according to Figures 6 to 10 Two embodiments of the output driver circuit of the CAN FD Light controller;

[0061] Figure 13A and 13B An example of a CAN FD Light frame is shown;

[0062] Figure 14A and 14B It shows the result of Figure 11 and 12 An embodiment of the control signals used in the output driver circuit; and

[0063] Figure 15 and 16 It shows according to Figures 6 to 10 An example of a serial communication interface for a CAN FD Light controller. Detailed Implementation

[0064] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0065] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0066] The titles provided in this document are for convenience only and do not explain the scope or meaning of the embodiments.

[0067] In the following Figures 6 to 16 In China, it has already been referred to Figures 1 to 5 The parts, elements, or components described are indicated by the same reference numerals previously used in this figure; in order not to overburden the detailed description of the invention, the description of these previously described elements will not be repeated below.

[0068] As mentioned above Figures 1 to 5 As described, in many applications, multiple CAN FD Light controllers can connect to a CAN FD optical bus 20. For example... Figure 3As shown, in this case, each CAN FD Light controller is connected to the CAN FD optical bus 20 via a corresponding transceiver 320.

[0069] Specifically, as mentioned above, each CAN FD Light controller provides an NRZ-encoded transmission signal TXD. Specifically, in different embodiments, the NRZ-encoded signals TXD and RXD are non-return-to-zero (NRZ-L) level encoded signals, where a first voltage (typically the power supply voltage of the CAN FD Light protocol controller, particularly the communication interface IF) indicates a first logic level (typically '1'), and a second voltage (typically the ground level of the CAN FD Light protocol controller, particularly the communication interface IF) indicates a second logic level (typically '0').

[0070] The inventors have observed that the above-described behavior can be used to exchange data between two CAN FD Light controllers without using the CAN bus transceiver 320, or by sharing a common CAN bus transceiver 320. In fact, for short distances, such as within the same processing system, like on the same printed circuit board, embedded system, or integrated circuit, bits according to the CAN FD light standard can still be reliably transmitted via NRZ-encoded signals TXD and RXD without using the CAN bus transceiver 320, which is required for data transmission over longer distances. A similar solution is disclosed in the context of the CANXL bus in Italian patent application 102020000030434, which is incorporated herein by reference.

[0071] Specifically, Figure 6 An embodiment of a processing system 10a comprising multiple integrated circuits 50 (e.g., integrated circuits 501 and 502) is shown, wherein each integrated circuit 50 includes a corresponding CAN FD Light controller 500. As described above, such a CAN FD Light controller 500 can be implemented using a communication interface IF and a CAN FD Light protocol controller, for example, using a microprocessor 102; that is, the integrated circuit 50 can be a microcontroller. Typically, the CAN FD Light controller 500 can also be provided as a sub-circuit 50 of the same integrated circuit. For example, the CAN FD Light protocol controller of circuit 501 can be a command unit, while the CAN FD Light protocol controller of circuit 502 can be a transponder.

[0072] In the considered embodiments, each circuit 50 includes a transmitter (TX) and a receiver (RX). Specifically, in the considered embodiments, the transmit terminals (TX) of the various circuits 50 are connected (e.g., directly) to a (common) transmission node or line (TXL). Furthermore, the transmission node or line (TXL) is connected to the power supply voltage (VDD) via pull-up resistors (R). For example, the power supply voltage (VDD) may correspond to the power supply voltage of the circuit 50, as schematically shown via terminals VDD and GND of circuit 501. Typically, the pull-up resistors (R) may also be integrated within a single circuit 50, or implemented using pull-up resistors within each (or at least a subset of) circuits 50.

[0073] As previously described, each CAN FD Light controller 500 can generate a binary transmit signal TXD and receive a binary receive signal RXD. However, in the considered embodiment, in order not to transmit data or to transmit a recessive level, circuit 50 should apply a high-impedance state to each terminal TX. Conversely, in order to transmit a main level, circuit 50 should pull the corresponding terminal TX to ground.

[0074] Therefore, in various embodiments, each circuit 50 includes a driver circuit 502 configured to drive a corresponding terminal TX according to a corresponding transmission signal TXD.

[0075] like Figure 7 As shown, such a driver circuit 502 is configured to receive the corresponding transmission signal TXD at the input terminal and set the corresponding transmission terminal TX to floating (high impedance state) or ground GND.

[0076] For example, such as Figure 7 As shown, for this reason, terminal TX can be connected (e.g., directly) to ground GND via an electronic switch 5022, such as a field-effect transistor (FET). Furthermore, a control terminal (e.g., the gate terminal of the FET) can be driven based on a signal TXD applied to terminal TX. For example, in the considered embodiment, electronic switch 5022 is driven via an inverted version of signal TXD, as schematically shown via inverter 5020. Thus, when signal TXD is low, electronic switch 5022 is closed and terminal TX is shorted to ground. Conversely, when signal TXD is high, electronic switch 5022 is open and terminal TX is floating. For example, when the electronic switch is a FET, driver circuit 502 is typically referred to as an open-drain driver circuit because the drain terminal can remain open. Thus, open-drain driver 502 and pull-up resistor R implement a logic AND operation, where the line / node TXL is set to "0" when at least one signal TXD is set to "0".

[0077] Therefore, the CAN FD transceiver 320 can drive lines CANH and CANL according to the voltage at the corresponding terminal TX connected to the transmission node / line TXL. That is, when the voltage at the transmission node / line TXL is less than a given threshold (less than the power supply voltage VDD), a dominant level is applied to lines CANH and CANL, thereby transmitting the logic level of the signal TXD to possible other circuits connected to the CAN bus 20.

[0078] Conversely, in order to receive CAN FD Light frames, the CAN FD transceiver 320, particularly the receiver circuit 324, sets the corresponding terminal RX high or low based on the differential voltage between the terminals / lines CANH and CANL. Therefore, in the considered embodiment, the receiver terminals RX of the various circuits 50 and the transceiver 320 are connected (e.g., directly) to the (common) receiver node or line RXL.

[0079] Therefore, the shared transmission line TXL with pull-up resistor R, the open-drain driver circuit 502, and the shared receiver line RXL are essentially implemented as a bus. Thus, multiple circuits 50 can drive the transmission line / node TXL to transmit data and monitor the logic level of the receiver line / node RXL to receive data. Therefore, in various embodiments, each circuit 50 may include an optional input circuit 504, implemented, for example, with one or more inverters and / or Schmitt triggers, to generate a receive signal RXD for circuit 50 based on the voltage at the corresponding terminal RX. Generally, the input circuit 504 is purely optional, and the signal RXD may also directly correspond to the voltage at the corresponding terminal RX, for example, when circuits 500 and 324 use the same supply voltage and are integrated in the same integrated circuit.

[0080] Figure 6 The processing system 10a shown can also be used to transmit a CAN FD Light frame from circuit 501 to circuit 502 (and vice versa). In practice, once circuit 501 sequentially applies the bits of the CAN FD Light frame to the transmission line / node TXL, the transmitter circuit 322 of the CAN FD transceiver applies the corresponding dominant or recessive level to the CAN bus 20. However, the receiver circuit 324 samples the level of the CAN bus 20 and drives the receive line / node RXL, thereby providing feedback to circuit 502.

[0081] like Figure 8As shown, in various embodiments, the CAN FD transceiver 320 may also be omitted, for example, when data must be exchanged only between circuits 50 connected to the transmitting and receiving nodes / lines TXL and RXL. However, in this case, due to the lack of feedback via the CAN FD transceiver 320, the receiving node / line RXL is connected (e.g., directly) to the transmitting node / line TXL. For example, the connection between the transmitting and receiving nodes / lines TXL and RXL can be achieved by connecting the RX terminal of at least one circuit 50 to the corresponding TX terminal.

[0082] For example, Figure 9 An embodiment of circuit 50, such as a microcontroller, is shown.

[0083] Specifically, circuit 50 again includes at least one CAN FD Light controller 500, which may include a serial communication interface 5000 and digital processing circuitry 102 that implements the CAN FD Light protocol controller.

[0084] However, in the considered embodiments, the driver circuit 502 and / or receiver circuit 504 are implemented via circuit 506 comprising one or more programmable / configurable input / output terminal I / Os (e.g., input / output pads of integrated circuit 50) or pins of integrated circuit 50 (e.g., general purpose input / output terminals).

[0085] For example, Figure 10 An embodiment of the input / output circuit 506 is shown.

[0086] Specifically, in the considered embodiment, circuit 506 includes a tri-state driver circuit 5060.

[0087] For example, Figure 11 A first embodiment of the three-state driver circuit 5060 is shown.

[0088] Specifically, in the considered embodiment, the tri-state driver circuit 5060 includes two electronic switches SW1 and SW2 connected in series (e.g., directly) between the power supply voltage VDD and ground GND, wherein an intermediate node between the two electronic switches SW1 and SW2 is connected (e.g., directly) to terminal I / O. For example, switch SW1 may be a p-channel FET, such as a PMOS, while switch SW2 may be an n-channel FET, such as an NMOS. In various embodiments, optional clamping diodes D1 and D2 may be connected between terminal I / O and the power supply voltage VDD, and between terminal I / O and ground GND, respectively.

[0089] In the considered embodiment, the control (e.g., gate) terminals of electronic switches SW1 and SW2 are driven via combinational logic circuitry as a function of signal OUT and control signal CTRL1. For example, in the considered embodiment, the combinational logic circuitry is configured as follows:

[0090] - When the control signal CTRL1 has a first logic level (e.g., high), a so-called push-pull configuration is achieved, for example, by connecting the terminal I / O to the power supply voltage VDD or ground GND respectively via electronic switches SW1 and SW2, and setting the terminal I / O high or low according to the signal OUT; and

[0091] - When the control signal CTRL1 has a second logic level (e.g., low), the terminal I / O is set to a high-impedance state or low according to the signal OUT, thereby realizing an open-drain driver configuration (see also...). Figure 7 (Description).

[0092] For example, in the considered embodiment, switch SW2 is closed when signal OUT is low, as schematically shown via inverter INV1. Conversely, to selectively use a push-pull or open-drain driver configuration when signal OUT is high, switch SW1 is closed only when signal OUT is high and control signal CTRL1 has a given logic level (e.g., high). For example, in the considered embodiment, the gate terminal of p-channel FET SW1 is driven via OR gate OR1, which receives at its input an inverted version of signal OUT and an inverted version of signal CTRL1, for example, generated via another inverter INV2.

[0093] Therefore, in the considered embodiment, the control signal CTRL1 represents a mode selection signal that allows selection of the push-pull or open-drain driver operation mode of the driver circuit 5060.

[0094] In contrast, Figure 12 A second embodiment of the driver circuit 5060 is shown. (Compared to...) Figure 11 In contrast, the combinational logic circuit is configured as follows in this case:

[0095] - When the control signal CTRL1 has a first logic level (e.g., high), a push-pull configuration is achieved, for example, by connecting the terminal I / O to the power supply voltage VDD or ground GND respectively via electronic switches SW1 and SW2, and setting the terminal I / O high or low according to the signal OUT; and

[0096] - When the control signal CTRL1 has a second logic level (e.g., low), the terminal I / O is placed in a high impedance state, for example by keeping switches SW1 and SW2 open.

[0097] For example, for this purpose, the gate terminal of the n-channel FET SW2 can be driven by an AND gate AND1 that receives the inverted version of the signal OUT and the signal CTRL1 at its input. For the remainder, the combinational logic circuitry for driving the switch SW1 can correspond to... Figure 11 Combinatorial circuits.

[0098] Therefore, in the considered embodiment, the control signal CTRL1 represents an enable signal that allows the selection of the push-pull operation mode of the driver circuit 5060 or disables the enable signal of the driver circuit 5060, thereby placing the terminal I / O in a high-impedance state.

[0099] Therefore, in both cases, the signals OUT and CTRL1 can be used to switch between three states "0", "1", and "Z" (high impedance state), thereby enabling push-pull or open-drain drive. For example, as described above, the first (push-pull) configuration can be used when the CAN FDLight protocol controller 500 is connected to a separate CAN FD transceiver 320, and the second configuration (open-drain) can be used when using a shared transmission node / line TXL.

[0100] like Figure 10 As shown, in various embodiments, circuit 506 further includes input circuitry 5062, configured to drive a logic level of signal IN as a function of the voltage at terminal I / O. For example, signal IN is set to a first logic level (e.g., high) when the voltage at terminal I / O is greater than an upper threshold, and signal IN is set to a second logic level (e.g., low) when the voltage at terminal I / O is less than a lower threshold, wherein the lower threshold is less than or corresponds to the upper threshold. For example, input circuitry 5062 may include a comparator, a Schmitt trigger, and / or one or more inverter stages.

[0101] In various embodiments, circuit 506 further includes a pull-up resistor 5066, which is preferably selectively enabled, for example, by connecting resistor 5066 between the power supply voltage VDD and the terminal I / O according to control signal CTRL2, as schematically shown via electronic switch 5064.

[0102] Therefore, the tri-state driver circuit 5060 of the terminal I / O can be used, for example, to implement circuit 502 by providing the signal TXD as the signal OUT to the circuit 506 associated with the transmission terminal TX.

[0103] also, Figure 6 The configuration can be achieved by using the input circuit 5062 of the circuit 506 associated with another / receive terminal RX, for example by providing the signal IN of the circuit 506 associated with the receive terminal RX as the signal RXD to the CAN FDLight protocol controller 500.

[0104] In contrast, Figure 8 The configuration can be achieved by directly using the input circuit 5062 of the circuit 506 associated with the transmission terminal TX, for example, by providing the signal IN of the circuit 506 associated with the transmission terminal TX as the signal RXD to the CANFDLight protocol controller 500. Alternatively, Figure 8 The configuration can be achieved by using the input circuit 5062 of the circuit 506 associated with another / receive terminal RX, for example by providing the signal IN of the circuit 506 associated with the receive terminal RX as the signal RXD to the CAN FDLight protocol controller 500, and connecting the terminal RX to the terminal TX (e.g., externally).

[0105] like Figure 9 As shown, in various embodiments, circuit 50 may therefore include a switching circuit 508 configured to support two operating modes, as schematically illustrated via multiplexer 5080, which is configured to provide signal RXD by selecting either signal IN of circuit 506 associated with terminal TX or signal IN of circuit 506 associated with another terminal RX. In various embodiments, switching circuit 508 may also be more complex and may allow selective connection of signals TXD and RXD to different terminals / pings / pads of circuit 50.

[0106] Therefore, by configuring the switching circuit 508 and setting the control signal CTRL1 and optionally the control signal CTRL2, for example via software instructions executed by the microprocessor 102 of the circuit 50, the circuit 50 can be configured according to any previously described operating mode (separate transceiver, shared transmission line with pull-up resistors enabled or disabled, separate receive line, etc.).

[0107] However, the inventors have observed that one of the main problems with several CAN controllers 500 sharing a common transmission node / line TXL is that the transmission node / line TXL, and therefore also the transceiver 320's terminal TX (when in use), is only passively pulled high (corresponding to a recessive level / logic '1'). This means that the rise time of the rising edge is determined by the capacitive load and the value of the pull-up resistor R (see also...). Figure 10 (Description of resistor 5066). Reducing the resistance value R to accelerate the rising edge means a stronger pull-down transistor is needed, such as... Figure 11 and 12The transistor SW2 shown is used to pull the voltage at the transmission line / node TXL to ground GND. Larger transistors have higher capacitance, which increases the capacitive load on the transmission line / node TXL. This can limit the number of CAN controllers 500 that can share the same transmission line / node TXL and the achievable data rate. Slower scalars are also generally more sensitive to distortion caused by electromagnetic interference or power supply distortion (i.e., "ISO pulses").

[0108] However, when sharing a transmission line / node TXL among multiple CAN, CAN FD, or CAN XL controllers, such a pull-up resistor R is required. Specifically, as... Figure 13A and 13B As shown, a typical CAN frame includes the following in sequence:

[0109] - Set the Start of Frame (SOF) bit to a dominant level;

[0110] - The 11-bit CAN standard identifier SID<10:0> is also commonly identified as the "basic identifier" or "basic ID" in ISO 11898-1;

[0111] - Remote Request Substitute Bit RRS;

[0112] - Identifier extension bit IDE;

[0113] - Flexible data format bit FDS;

[0114] - The reserved bit res is usually set to a dominant level;

[0115] - Bit rate switching bit BRS;

[0116] - Error status indicator bit ESI;

[0117] - The 4-bit Data Length Code field DLC<3:0> allows you to specify the amount of data to be transmitted (values ​​0x0000 to 0x1000 correspond to 0-8 data bytes respectively, and values ​​0x1001 to 0x1111 correspond to 12, 16, 20, 24, 32, 48 and 64 data bytes respectively).

[0118] - Payload DATA, which can correspond to 0-8, 12, 16, 20, 24, 32, 48 and 64 data bytes (see field DLC);

[0119] - 3-bit padding counter field SBC<2:0>;

[0120] - Even parity check bit P;

[0121] - Cyclic Redundancy Check (CRC) field, which has 17 bits (for up to 16 data bytes) or 21 bits (for 20 to 64 data bytes);

[0122] - The CRC delimiter bit CD is usually set to a recessive level;

[0123] - Confirmation bit AS;

[0124] - Typically set as the recessive level confirmation threshold AD; and

[0125] - Set the 7-bit end-of-frame field EOF<6:0> to recessive level.

[0126] When a transmitter wants to transmit a CAN, CAN FD, or CAN XL frame, it transmits the master bit, i.e., the start of frame (SOF) bit, to bus 20, for example, by setting the corresponding signal TXD low. Therefore, when at least one transmitter transmits the master bit, all nodes detect the master status of the bus via the CAN bus or via the shared receive line / node RXL.

[0127] In this regard, CAN, CAN FD, and CANXL determine access rights to the CAN bus 20 through arbitration. Specifically, the CAN controller transmits a bit stream of its frame identifier SID via the TXD signal and monitors the value of the RXD signal. If a logic '1' ("recessive") is transmitted via the TXD signal but a logic '0' ("dominant") is received via the RXD signal, the transmitter stops transmitting its data and becomes a receiver / slave node because the identifier SID with the higher bus access priority is attempting to access the bus.

[0128] Furthermore, after successfully receiving a CAN, CAN FD, or CAN XL frame, each receiving node transmits a master bit (acknowledgment bit AS) in the acknowledgment slot. This means that if at least one receiver has successfully received the frame, the transmitter detects the master bit. Thus, the transmitter knows that at least one other node has received the frame.

[0129] Therefore, when sharing the transmission line / node TXL of multiple CAN, CAN FD, or CANXL controllers, the high level can only be passively defined via pull-up resistor R due to arbitration and ACK bits to avoid potentially disruptive bus contention.

[0130] However, the inventors have observed that the operation of CAN FD Light is slightly different. In fact, CAN FD Light is a command / responder protocol where only one controller 500 initiates data transmission at a given time. Therefore, only one controller 500 transmits the SOF bit, and the arbitration phase can be omitted. In this respect, acknowledgment in the acknowledgment slot can also be omitted in the CAN FD Light protocol, since the transmitter can always identify whether a frame was not successfully transmitted due to the command / responder structure. Therefore, the CAN FD Light responder can not acknowledge the reception, i.e., it can not set the ACK bit to a dominant level, and the CAN FD Light command can consider a recessive ACK bit as a successful transmission. Transmission failure can then be detected by a lost response from the addressed responder.

[0131] However, in principle, the CAN FD Light protocol can also be used to exchange data with CAN or CAN FD controllers that only implement receiver / slave circuitry. However, such controllers are typically configured to respond with a dominant level during the acknowledgment slot. Similarly, for compatibility with CAN and CAN FD controllers, the CAN FD Light controller can be configured to respond, if not mandatory, to ensure compatibility with CAN and CAN FD controllers. Therefore, in principle, during the acknowledgment slot, one or more controllers receiving data can transmit a dominant level, while the transmitting CAN FD Light controller 500 (and possibly other CAN FD Light controllers) transmits a recessive level.

[0132] However, the inventors have observed that the rise slope between the CRC separator and the ACK slot is less critical because, due to the command / responder architecture, CAN FD Light does not require implicit ACK signaling. The transmitter can always identify whether a frame has not been successfully transmitted. Similarly, since the allowed ACK bit extends into the ACK separator bit, the rise time between the ACK bit and the ACK separator is also not critical. According to the CAN / CAN FD standard, the major value in this bit should be ignored.

[0133] Therefore, the inventors have observed that since only one CAN FD Light controller 500 will transmit data on the CAN bus and / or on the transmission line TXL (in addition to the ACK signal), the recessive level can be actively driven; that is, the CAN FD Light controller 500 can set the voltage at the transmission terminal TX via a push-pull configuration. This reduces the rise time on the transmission line TXL, improves robustness against distortion, and increases the time during the received bit period, in which the bit value is stable, thus increasing the margin of the points the receiver must sample the bit value.

[0134] Therefore, in a CAN FD Light system, apart from the acknowledgment slot, the transmission line / node TXL can be configured by several CAN controllers using push-pull output drivers for the transmit bits (see [link]). Figure 6 and 8 Shared. In this slot, a passive pull-up resistor R is preferred to also support the CAN controller responding with a dominant level in this slot. In practice, as mentioned above, the CAN FD Light controller can implement the ACK bit for compatibility with existing CAN FD protocol controllers embedded in the command unit. It can be optionally implicitly emitted if future CAN FD protocol controllers can be configured to ignore this bit. In contrast, the CAN FDLight protocol does not require an ACK bit. In any case, since the CAN FD specification allows the acknowledgment bit to be extended into the acknowledgment delimiter slot, which gives a two-bit time, the ACK bit is much less critical than other bits.

[0135] In various embodiments, pull-up resistors R are also used to passively transmit recessive bits for End of Frame (EOF) and / or Bus Idle (recessive level). Therefore, in various embodiments, the active transmission of the recessive bit (logic 1 bit) can begin, occur during, or immediately after the CRC delimiter bit CD.

[0136] This is also Figure 14A and 14B The diagram illustrates that the CAN FD Light controller 500 re-transmits the bits of the CAN FD Light frame sequentially via the signal TXD, specifically the Start of Frame (SOF) bit (with a dominant level), and subsequent bits including the Cyclic Redundancy Check (CRC) field. Specifically, in various embodiments, these bits are transmitted using a push-pull configuration. For example, for this purpose, the CAN FD Light controller 500 can set the control signal CTRL1 to a logic level (e.g., high) to enable the push-pull configuration (see also...). Figure 11 and 12 (Description).

[0137] Conversely, once the Cyclic Redundancy Check (CRC) field has been transmitted, the CAN FD Light controller 500 places terminal TX in a high-impedance state. For example, when using... Figure 12 When using the driver circuit 5060 shown, it is sufficient for the CAN FD Light controller 500 to change the logic level of the control signal CTRL1 to keep switches SW1 and SW2 open. Conversely, when using... Figure 12When the driver circuit 5060 is shown, the CAN FD Light controller 500 must also set the signal TXD high. However, in the case of a CAN FD Light frame, bits CD, AS, AD, and EOF are already set high.

[0138] As mentioned above, the precise position of the slope of the control signal CTRL1 is not critical. For example, the CAN FD Light controller 500 can change the logic level of the control signal CTRL1, such as setting it high, even before the start of the frame (SOF) bit, for example, one or more cycles of the CAN FD Light bit, because the CAN FD Light controller 500 knows it should transmit a frame and does not expect other transmitters to do so. Therefore, during the inter-frame interval, no other CAN FD Light controller 500 will transmit a frame. This additional delay between the activation of the push-pull configuration and the end of the SOF bit adds at most the delay between the response of the command request and the corresponding response of the responder. Therefore, generally, enabling the push-pull configuration at the end of the SOF bit is sufficient.

[0139] As previously mentioned, the critical and preferably actively pulled-high final dominant-to-recessive edge lies between the last bit of the CRC field and the CRC delimiter CD, which is always emitted recessively. Therefore, after this slope, terminal TX can be set to a high-impedance state, for example, by setting signal CTRL1 low. Thus, terminal TX can be set to a high-impedance state at any time between the start and end of the CRC delimiter CD, preferably after a given (e.g., constant) delay relative to the start of the CRC delimiter CD.

[0140] Furthermore, in systems that only include a CAN FD Light controller, it is not expected that the CAN FD Light responder will emit a major ACK bit. Therefore, in this case, the TX terminal can also be set to a high-impedance state during the ACK bit AS.

[0141] Therefore, even under the tightest timing conditions, the switching between push-pull configuration and high-impedance state can be accomplished using at least one bit of time for the transition (relative to the start of the SOF bit and relative to the end of the CRC delimiter bit CD).

[0142] The following describes a possible hardware implementation of the CAN FD Light controller 500. As described above, the CAN FD Light command controls the entire communication and initiates each communication cycle by transmitting frames without expecting responses from other network participants (“responders”) (e.g., broadcast frames), or by transmitting frames to a dedicated addressed responder and expecting a response from that responder. That is, a request and response scheme in unicast frames. Request frames can also be used to transmit data to an addressed responder. Only the addressed responder that has been requested to respond is expected to transmit a frame back; that is, no other device on the bus is expected to transmit data simultaneously. Therefore, the frame sequence on bus 20 is precisely defined, and arbitration is not required. For example, with this scheme, erroneous frames are not needed because the communication direction and response are clearly identified. Similarly, no acknowledgment from the command or responder is required. Erroneous frames may be discarded and are considered unreceived in the CAN FD Light scheme.

[0143] Therefore, in a CAN FD Light system, the CAN FD Light controller 500 can prepare a complete frame before transmission and then transmit the bit sequence of that frame without running arbitration. For example, as described in previously cited Italian patent applications 102021000022037 and 102021000022124, this means that the CAN FD Light controller 500 may include digital processing circuitry 102, such as sequential logic circuitry implementing a finite state machine and / or a microprocessor, configured to prepare a complete CAN FD Light frame, and a hardware serial communication interface 5000 configured to sequentially transmit the bits of the CAN FD Light frame.

[0144] For example, Figure 15 Possible embodiments of such a communication interface 5000, based on the disclosures in documents 102021000022037 and 102021000022124, are shown.

[0145] Specifically, in the considered embodiment, the hardware communication interface 5000 includes two shift registers 5040 and 5042. Specifically, in the considered embodiment, shift register 5040 is used to store data to be transmitted. Typically, the two shift registers 5040 and 5042 can also be implemented using the same shift register.

[0146] Therefore, once the digital processing circuit 102 has generated the data for the transmission frame, it can also determine the number of bits to be transmitted. Specifically, in various embodiments, the digital processing circuit 102 is configured to write data to the control register CTRL of the communication interface 5000, which indicates the number of bits to be transmitted.

[0147] Therefore, once a data transfer is requested, the hardware communication interface 500 receives the data DATATX to be transferred (e.g., directly from the digital processing circuit 102 or via DMA data transfer). Specifically, the transferred data DATATX may correspond to the data of a complete frame or only a portion thereof. For example, in the considered embodiment, the transferred data DATATX is transferred to the shift register 5040, for example, by using the parallel data input PDI of the shift register 5040. Typically, the transfer frame provided via the data DATATX may also not include the start-of-frame (SOF) bit. For example, in this case, the first bit of the shift register 5040 may be set to "0", while the other bits of the shift register 5040 are mapped to the corresponding bits of the transferred data register DATATX.

[0148] In various embodiments, shift register 5040 is configured to sequentially transfer stored bits to shift register 5040 based on clock signal CLK2 and transfer enable signal TX_EN.

[0149] Specifically, in the considered embodiment, the hardware communication interface 5000 further includes a clock management circuit 5044, which is configured to generate a clock signal CLK2 for the hardware communication interface 5000 in response to the system clock signal CLK of the processing system 10a.

[0150] For example, such as Figure 16 As shown, in various embodiments, the clock management circuit may include a clock prescaler circuit 5058 configured to generate a prescaled clock signal CLK. PRE The prescaled clock signal CLK PRE The scaling factor has a decreasing frequency relative to the clock signal CLK, and can be programmed as a function of configuration data stored in the control register CTRL. For example, a pre-scaling circuit 5058 can be implemented using a counter configured to increment a count value in response to the clock signal CLK, wherein the counter changes the clock signal CLK when the count value reaches a threshold. PRE The logic level, where the threshold is determined based on configuration data provided by the control register CTRL.

[0151] In the considered embodiment, the prescaled clock signal CLK is then... PRE Provided to another scaling circuit 5060, which is configured to generate a value relative to the clock signal CLK PRE The frequency of the clock signal CLK2 is reduced to a lower frequency, where the scaling factor can be fixed or programmable, and is a function of the configuration data stored in the control register CTRL. For example, a scaling factor configured to respond to the clock signal CLK2 can be used. PREThe counter that increments the count value implements the reduction circuit 5060, where the counter changes the clock signal CLK when the count value reaches a threshold. PRE The logic level, where the threshold is determined as appropriate based on the configuration data provided by the configuration register CTRL.

[0152] like Figure 15 As shown, in various embodiments, the operation of the scaling circuit 5060 is altered in response to the SYNC synchronization signal; however, the SYNC synchronization signal is only used when receiving data, and will be described later.

[0153] Therefore, when transmitting data, the clock signal CLK2 corresponds to a reduced version of the clock signal CLK (as a function of the configuration data stored in the control register CTRL), and can have, for example, 1MHz or another frequency supported by the CAN FD Light.

[0154] As previously described, shift register 5040 also receives an enable signal TX_EN, which enables data transmission operations. Specifically, in the considered embodiment, shift register 5040 is configured to sequentially provide its contents at the serial data output SDO when the enable signal TX_EN is asserted and in response to clock signal CLK2. Therefore, when the enable signal TX_EN is asserted, shift register 5040 sequentially provides bits of stored data to shift register 5040 (starting from the start of frame bit SOF).

[0155] In the considered embodiment, the enable signal TX_EN is generated by transmission control circuitry 5046, which is configured to determine whether a given number of request bits have been transmitted. Therefore, in various embodiments, transmission control circuitry 5046 is configured to determine the number of request bits to be transmitted based on configuration data stored in control register CTRL. For example, the configuration data stored in control register CTRL may correspond to the total number of bits to be transmitted (with or without the start of frame (SOF) bit.

[0156] For example, in various embodiments, the transmission control circuit 5046 may include a counter that increments in response to a clock signal CLK2 to indicate the number of bits to be transmitted. Thus, when a new data transmission operation begins, the counter can be reset to assert the enable signal TX_EN, and when the requested number of bits has been transmitted, the transmission control circuit 5046 de-asserts the enable signal TX_EN. For example, in this case, when the transmission control circuit 5046 de-asserts the enable signal TX_EN, the transmission control circuit can assert the control signal TX_OK.

[0157] In various embodiments, the hardware communication interface 5000 includes combinational logic 5050 configured to set the signal TXD to a recessive level, such as high, when the enable signal TX_EN is deasserted. For example, if the enable signal TX_EN is set low when it is deasserted, the combinational logic 5050 can be implemented using an OR gate that receives the serial data output signal SDO from the shift register 5056 and an inverted version of the enable signal TX_EN at its inputs, and provides the signal TXD at its output. The combinational logic 5050 is purely optional, as the serial data output signal SDO can also be set to a recessive level when the enable signal TX_EN is deasserted (e.g., because the end-of-frame bit EOF has been set to a recessive level).

[0158] Therefore, in various embodiments, the transmission control circuit 5046 can also generate a control signal CTRL1 for selectively enabling a push-pull configuration or a high-impedance state. For example, as described above, the transmission control circuit 5046 can change the logic level of the signal CTRL1 together with (or before) the start-of-frame bit SOF, and can change the logic level of the signal CTRL1 again using CRC delimiting CD. However, given the length of the CAN FD Light frame to be transmitted, the transmission control circuit 5046 can determine the location of the CRC delimiting CD, for example, by subtracting 9 from the total length of the CAN FD Light frame. Alternatively, the data provided by the processing circuit 102 can also simply indicate the length up to the CRC delimiting CD (with or without a delimiting CD), and the transmission control circuit 5046 can automatically transmit an additional 9 (if the bit CD is already included) or 10 (if the bit CD must be added) recessive bits, for example, by setting the signal TX_EN (and the signal CTRL1) low and asserting the signal TX_OK only after 9 or 10 additional cycles of the signal CLK2. Generally, the transmission control circuit 5046 can assert the signal TX_OK at any time after the CRC bit has been transmitted, because it is sufficient to set the signal TXD high (e.g., via a signal provided by the shift register 5040 and / or by setting the signal TX_EN low) and deassert the control signal CTRL1, thereby implicitly setting all subsequent bits to a recessive level.

[0159] Conversely, shift register 5042 is configured to store bits received via signal RXD. Specifically, when no data transmission occurs, the receive signal RXD has a recessive level, such as high. Once transmission begins by another device, the start of frame bit SOF is transmitted, thereby giving the receive signal RXD a dominant level, such as low. Therefore, in various embodiments, hardware communication interface 5000 includes receive control circuitry 5048. Specifically, receive control circuitry 5048 is configured to assert a receive enable signal RX_EN in response to a change in signal RXD from a recessive level to a dominant level, such as in response to a falling edge of signal RXD.

[0160] Typically, as mentioned earlier, the start of frame (SOF) bit can be followed by a variable number of bits (usually up to 675 bits). However, the end-of-frame condition can be precisely determined by setting a sequence of 7 bits (end of frame (EOF)) or even 8 bits (when the AD bit is also considered) to a recessive level. In fact, the bit stuffing of the CAN FDLight protocol guarantees that after a 5-bit sequence with the same logic level, the logic level of other data changes at most.

[0161] Therefore, in various embodiments, the receive control circuit 5048 is configured to de-assert the receive enable signal RX_EN in response to determining that seven or eight consecutive bits have been set to a recessive level. For example, for this purpose, the receive control circuit 5048 may include a counter configured to increment a count value in response to a clock signal CLK2, wherein the counter is reset when the signal RXD is set to a dominant level. Thus, in this case, when the counter reaches 7 or 8, the receive control circuit 5048 can de-assert the receive enable signal RX_EN.

[0162] Typically, in addition to monitoring the EOF bit, or as an alternative to monitoring the EOF bit, the receive control circuit 5048 can also directly process the received data, particularly the DLC field, to determine the expected number of transmit bits. Therefore, in this case, data reception can be stopped once the expected number of bits has been received. Thus, the expected number of bits may include only the bits up to the last CRC bit, or may also include one or more of the following bits: CD, AS, AD, and EOF.

[0163] Therefore, in various embodiments, shift register 5042 is configured to sequentially add the logic level of the serial data input SDI applied to shift register 5042 to the data stored in shift register 5042 when the enable signal RX_EN is asserted and in response to clock signal CLK2, wherein the serial data input SDI is connected to the receive signal RXD. Typically, receive control circuitry 5048 can assert a receive enable signal RX_EN with a start-of-frame bit SOF or only for the next bit, thereby storing or not storing the start-of-frame bit SOF in shift register 5042.

[0164] Therefore, once seven or eight consecutive recessive bits are received and / or once the expected number of bits are received, the receive control circuit 5048 de-asserts the receive enable signal RX_EN. In this case, the receive control circuit 5048 can also assert the control signal RX_OK. Furthermore, once seven or eight consecutive recessive bits are received and / or once the expected number of bits are received, for example in response to the signal RX_OK, the hardware communication interface 5000 transmits the contents of the shift register 5042, for example, by providing the received data DATARX, for example, by using the parallel data output PDO of the shift register 5042. Typically, the received data DATARX can also be provided sequentially during the data reception portion of the received CAN FD Light frame.

[0165] Therefore, in the considered embodiments, data transmission occurs in response to clock signal CLK2, and the data shifts out synchronously with clock CLK2. Conversely, data received via receive signal RXD may have a phase and / or frequency offset from clock CLK2. Essentially, the frequency offset results in an accumulated phase shift; that is, the frequency offset can be considered a phase shift sequence. In various embodiments, to compensate for the phase shift, receive control circuitry 5048 may be configured to adjust the sampling point of the received data based on detected bit transitions. Specifically, in various embodiments, a synchronization signal SYNC is used for this purpose. Specifically, in various embodiments, receive control circuitry 5048 is configured to assert the synchronization signal SYNC in response to a detected change in the logic level of receive signal RXD, i.e., in response to a falling edge from recessive to dominant, and / or in response to a rising edge from dominant to recessive. For example, for this purpose, receive control circuitry 5048 may respond to clock signal CLK2. PRE The received signal RXD is sampled, and the synchronization signal SYNC is asserted when the current sample is set to dominant level and the previous sample is set to recessive level and / or when the current sample is set to recessive level and the previous sample is set to dominant level.

[0166] For reference Figure 16The reduction circuit 5060 can be synchronized with the synchronization signal SYNC to generate an edge for sampling the received signal RXD. For example, in various embodiments, the proportional reduction circuit 5060 is implemented with a counter configured to increment a count value CNT and reset the count value CNT when a maximum count value is reached. Furthermore, to synchronize the count value CNT with the synchronization signal SYNC, the counter CNT can be reset in response to determining that the synchronization signal SYNC has been asserted.

[0167] Therefore, in various embodiments, the tri-state configuration of the transmission terminal TX can also be directly controlled by the transmission control circuit 5046 of the hardware serial communication interface 5000.

[0168] In various embodiments, the generation of signal CTRL1 can be selectively enabled via one or more corresponding bits in the control register CTRL, which allows specifying, for example, whether:

[0169] - Enable push-pull configuration only for the bits between the start-of-frame (bis) SOF and the CRC delimiter (CD);

[0170] - Always use a push-pull configuration, for example, when using a separate transceiver 320 and omitting the external pull-up resistor R;

[0171] - Optionally, always use the open-drain driver configuration.

[0172] in this regard, Figure 11 The embodiment shown may be preferred, especially when the terminal TX is set to ground GND to respond with an acknowledgment in the acknowledgment time slot AS, because in this case it is sufficient to simply set the signal TXD low without changing the logic level of the signal CTRL1.

[0173] In various embodiments, the control register CTRL can also be used to generate a signal CTRL2 for enabling the optional internal pull-up resistor 5066.

[0174] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art based on the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A processing system, comprising: Positive power supply terminal and negative power supply terminal; as well as Sub-circuit, including: Transmission terminals; The three-state driver circuit includes: A first electronic switch is connected between the transmission terminal and the positive power supply terminal; and A second electronic switch is connected between the transmission terminal and the negative power supply terminal. The tri-state driver circuit includes combinational logic circuitry configured to monitor the logic levels of a first signal and a second signal, and selectively activate one of the following switching states based on the logic levels of the first signal and the second signal: In the first switching state, the transmission terminal is connected to the positive power supply terminal by closing the first electronic switch. In the second switching state, the transmission terminal is connected to the negative power supply terminal by closing the second electronic switch, and In the third switching state, the transmission terminal is placed in a high-impedance state by disconnecting the first electronic switch and the second electronic switch; A CAN FD Light controller is configured to sequentially transmit bits of a CAN FD Light frame, wherein the CAN FD Light frame includes: Start of frame bit A bit sequence, comprising, in sequence, a Cyclic Redundancy Check (CRC) delimiter bit, an acknowledgment bit, an acknowledgment delimiter bit, and a 7-bit end-of-frame field, and Multiple intermediate bits, between the start of the frame bit and the CRC delimiter bit, and The CAN FD Light controller is configured to sequentially transmit the bits of the CAN FD Light frame in a first operating mode by generating the first signal and the second signal in response to a transmission clock signal, so as to: The start-of-frame bit is transmitted by activating the second switch state for one clock cycle. The intermediate bits are transmitted sequentially by selecting one bit of the intermediate bit in sequence and activating either the first switch state or the second switch state according to the logic level of the selected bit. And once the intermediate bit has been transmitted, the third switch state is activated.

2. The processing system according to claim 1, wherein, The CAN FD Light controller is configured to transmit the bit sequence by activating the third switch state for 10 clock cycles.

3. The processing system according to claim 1, wherein the combinational logic circuit of the tri-state driver circuit is configured as follows: In response to determining that the first signal has been de-asserted, the second switch state is activated. In response to determining that the first signal is asserted and the second signal is asserted, the first switch state is activated, and In response to determining that the first signal is asserted and the second signal is deasserted, the third switch state is activated.

4. The processing system according to claim 1, wherein the combinational logic circuit of the tri-state driver circuit is configured as follows: In response to determining that the first signal has been deasserted and the second signal has been asserted, the second switch state is activated. In response to determining that the first signal is asserted and the second signal is asserted, the first switch state is activated, and In response to determining that the second signal has been de-asserted, the third switch state is activated.

5. The processing system according to claim 3, wherein the CAN FD Light controller is configured to: In response to the transmission clock signal, which is the first signal, a transmission signal is generated by sequentially providing the bits of the CAN FD Light frame; Assert the second signal when the frame start bit and the middle bit are provided; and When the bit sequence is provided, the assertion of the second signal is de-asserted.

6. The processing system according to claim 5, wherein the CAN FD Light controller comprises: A digital processing circuit is configured to generate a frame that includes at least the middle bits of the CAN FD Light frame; as well as A serial communication interface includes a control register configured to store data identifying the requested number of bits; A clock management circuit is configured to receive a system clock signal and generate a reduced clock signal, wherein the transmitted clock signal corresponds to the reduced clock signal; A transfer shift register is configured to generate the transfer signal by sequentially providing the contents of the transfer shift register in response to the transfer clock signal when a transfer enable signal is asserted, wherein the processing system is configured to selectively transfer the frame from the digital processing circuit to the transfer shift register; The transmission control circuit is configured as follows: Receive the transmission start signal requesting data transmission. In response to the transmission start signal, assert the transmission enable signal. When the transmission enable signal is asserted, the transmission count value is incremented in response to the transmission clock signal. Determine whether the transmission count value has reached the requested number of bits, and In response to determining that the transmission count value has reached the requested number of bits, the assertion of the transmission enable signal is de-asserted.

7. The processing system according to claim 6, wherein the transmission control circuit is configured to: In response to the start of the transmitted signal, assert the second signal. Determine whether the serial communication interface provides the last bit of the intermediate bit, and In response to determining that the transfer shift register provides the last bit of the intermediate bit, the assertion of the second signal is released.

8. The processing system of claim 1, further comprising a receiving terminal, wherein the CAN FD Light controller is configured to sequentially receive the bits of another CAN FD Light frame via the receiving terminal.

9. The processing system of claim 8, further comprising a CAN FD transceiver, the CAN FD transceiver including a transmit terminal and a receive terminal, wherein the transmit terminal of the CAN FD transceiver is connected to the transmit terminal of the sub-circuit, and wherein the receive terminal of the CAN FD transceiver is connected to the receive terminal of the sub-circuit.

10. The processing system of claim 9, further comprising another sub-circuit, the other sub-circuit including another transmission terminal, another receiving terminal, another tri-state driver circuit and another CAN FD Light controller, wherein the other transmission terminal of the other sub-circuit is connected to the transmission terminal of the sub-circuit and the receiving terminal of the other sub-circuit is connected to the receiving terminal of the sub-circuit.

11. The processing system of claim 10 further includes a pull-up resistor connected between the transmission terminal of the sub-circuit and the positive power supply terminal.

12. The processing system of claim 8, further comprising another sub-circuit, the other sub-circuit including another transmission terminal, another receiving terminal, another tri-state driver circuit and another CAN FD Light controller, wherein the other transmission terminal of the other sub-circuit is connected to the transmission terminal of the sub-circuit, wherein the receiving terminal of the other sub-circuit is connected to the transmission terminal of the other sub-circuit, and wherein the receiving terminal of the sub-circuit is connected to the transmission terminal of the sub-circuit.

13. The processing system according to claim 1, further comprising: CAN FD transceiver, including transmit and receive terminals. The transmit terminal of the CAN FD transceiver is connected to the transmit terminal of the sub-circuit, and the receive terminal of the CAN FD transceiver is connected to the receive terminal of the sub-circuit. In the second operating mode, the CAN FD Light controller is configured to sequentially transmit bits of the CAN FD Light frame by generating the first signal and the second signal in response to a transmission clock signal, so as to: The start-of-frame bit is transmitted by activating the second switch state for one clock cycle. The intermediate bits are transmitted sequentially by selecting one bit of the intermediate bit and activating either the first or second switch state according to the logic level of the selected bit. Once the intermediate bit has been transmitted, the first switch state is activated.

14. A method for operating a processing system according to any one of claims 1-13, comprising: Multiple bits of the CAN FD Light frame are transmitted sequentially, wherein the CAN FD Light frame includes: The start bit of the frame The bit sequence, in sequence, includes the Cyclic Redundancy Check (CRC) delimiter bit, the acknowledgment bit, the acknowledgment delimiter bit, and the 7-bit end-of-frame field, and The plurality of intermediate bits, between the frame start bit and the CRC delimiter bit, wherein the bits transmitting the CAN FD Light frame include the first signal and the second signal of the processing system generated in response to the transmission clock signal, so as to: The start-of-frame bit is transmitted by activating the second switch state for one clock cycle. The intermediate bits are transmitted sequentially by selecting one bit of the intermediate bit and activating either the first or second switch state according to the logic level of the selected bit. Once the intermediate bit has been transmitted, the third switch state is activated.

15. A vehicle comprising: Multiple processing systems, each of which is the processing system according to claim 10, wherein the CAN FD transceiver of the processing system is connected to the CAN bus.

16. The vehicle of claim 15, further comprising a pull-up resistor connected between the transmission terminal and the positive power supply terminal of the sub-circuit.

17. An integrated circuit, comprising: The processing system according to claim 1.

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