Semiconductor memory device and method of operating the same

Abstract

This application relates to semiconductor memory devices and methods of operating the same. A method of operating a semiconductor memory device includes, in response to a program command, initiating a program operation on selected memory cells using a main verify voltage and a subsidiary verify voltage, receiving a program suspend command during the program operation, and in response to the program suspend command, changing at least one subsidiary voltage verify result information among threshold voltage states that have not been programmed through to at least one data pattern among threshold voltage states that have been programmed through.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device configured to retain verification data during a programming suspension, and a method of operating the semiconductor memory device. Background Technology

[0002] Memory devices can be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are stacked vertically on a semiconductor substrate. Three-dimensional memory devices are designed to address the integration limitations of two-dimensional memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0003] According to an embodiment of the present disclosure, a method of operating a semiconductor memory device includes: in response to a programming command, initiating a programming operation on a selected memory cell using a primary verification voltage and a secondary verification voltage; receiving a programming suspension command during the programming operation; and in response to the programming suspension command, changing at least one secondary voltage verification result information of a threshold voltage state that has not been programmed to at least one data mode of a threshold voltage state that has been programmed.

[0004] According to another embodiment of this disclosure, a method for operating a semiconductor memory device including memory cells for each storing N bits includes: receiving a programming recovery command; determining a first programming state up to the (2)th programming state. N -1) Whether the k-th programming state in the programming state has been verified; and identify the page buffer corresponding to the memory cell in the memory cell to be programmed into the x-th programming state, whose threshold voltage is between the x-th auxiliary verification voltage and the x-th main verification voltage, and store the auxiliary verification data pattern corresponding to the k-th programming state in the identified page buffer. Here, N is an integer greater than 1, and k is greater than 1 and less than or equal to 2. N The integer is -2, and x is greater than k and less than or equal to 2. N An integer of -1.

[0005] According to another embodiment of this disclosure, a semiconductor memory device includes a memory cell array, peripheral circuitry, and control logic. The memory cell array includes multiple memory cells, each storing N bits. The peripheral circuitry performs programming operations on the memory cell array. The control logic controls the programming operations of the peripheral circuitry. When a programming suspension command is received during programming operations on a selected memory cell among the multiple memory cells, the control logic controls the peripheral circuitry to suspend the programming operation corresponding to the first programming state up to the (2)th programming state. N-1) The auxiliary voltage verification result information of the xth threshold voltage state that has not been programmed in the programming state is changed to correspond to the first programming state to the (2)th threshold voltage state. N -1) The k-th data pattern of the k-th programming state in the programming state. Here, N is an integer greater than 1, and k is greater than 1 and less than or equal to 2. N The integer is -2, and x is greater than k and less than or equal to 2. N An integer of -1. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating a storage device and a host device according to embodiments of the present disclosure.

[0007] Figure 2 This is an example based on Figure 1 A block diagram of a semiconductor memory device.

[0008] Figure 3 This is an example Figure 2 A diagram illustrating an implementation of a memory cell array.

[0009] Figure 4 This is an example Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0010] Figure 5 This is an example Figure 2 A circuit diagram illustrating an implementation of any one of the multiple memory blocks BLK1 to BLKz included in the memory cell array, namely BLKb.

[0011] Figure 6 This is a diagram illustrating the threshold voltage distribution of a multi-level cell (MLC) and the primary and secondary verification voltages used to form the threshold voltage distribution.

[0012] Figure 7 This is a schematic illustration of a page buffer according to an embodiment of the present disclosure.

[0013] Figure 8A and Figure 8B This is a diagram illustrating the threshold voltage and latch data of the memory cell corresponding to the erase state.

[0014] Figure 9A and Figure 9B This is a diagram illustrating the threshold voltage of the memory cell and the latch data corresponding to the first programming state.

[0015] Figure 10A and Figure 10B This is a diagram illustrating the threshold voltage of the memory cell and the latch data corresponding to the second programming state.

[0016] Figure 11A and Figure 11B This is a diagram illustrating the threshold voltage and latch data of the memory cell corresponding to the third programming state.

[0017] Figure 12A and Figure 12B This is a graph illustrating the changes in data in the page buffer when a programming suspend command is received during a programming operation.

[0018] Figure 13 This is a flowchart illustrating a method for operating a semiconductor memory device according to an embodiment of the present disclosure when a programming suspension command is received.

[0019] Figure 14A and Figure 14B It provides a more detailed example based on Figure 13 A diagram illustrating the method.

[0020] Figure 15 This is a flowchart illustrating a method for operating a semiconductor memory device according to an embodiment of the present disclosure when a programming recovery command is received.

[0021] Figure 16 It provides a more detailed example based on Figure 15 A diagram illustrating the method.

[0022] Figure 17A This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming suspension command is received.

[0023] Figure 17B It provides a more detailed example based on... Figure 17A A diagram illustrating the method.

[0024] Figure 18A This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming recovery command is received.

[0025] Figure 18B It provides a more detailed example based on... Figure 18A A diagram illustrating the method.

[0026] Figure 19 This is a diagram illustrating the threshold voltage distribution of a three-level cell (TLC) and the primary and secondary verification voltages used to form the threshold voltage distribution.

[0027] Figure 20 This is a schematic illustration of a page buffer according to another embodiment of the present disclosure.

[0028] Figure 21AThis is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming suspension command is received.

[0029] Figure 21B This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming recovery command is received.

[0030] Figure 22 This is an example Figure 1 A block diagram illustrating an application example of a storage device.

[0031] Figure 23 This illustrates the example including references. Figure 22 A block diagram of a computing system describing a storage device. Detailed Implementation

[0032] The specific structural or functional descriptions illustrating embodiments of the concepts disclosed in this specification or application are merely for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0033] Embodiments of this disclosure provide a semiconductor memory device capable of holding auxiliary verification data using a minimal latch during programming suspension, and a method for operating the semiconductor memory device.

[0034] In implementation, this technology can provide a semiconductor memory device capable of retaining auxiliary verification data during programming suspension using minimal latches, and a method for operating the semiconductor memory device.

[0035] Figure 1 This is a block diagram illustrating a storage device 1000 and a host device 300 according to an embodiment of the present disclosure.

[0036] Reference Figure 1 The storage device 1000 includes a semiconductor memory device 100 and a controller 200. Furthermore, the storage device 1000 communicates with a host device 300. The controller 200 controls the overall operation of the semiconductor memory device 100. Additionally, the controller 200 controls the operation of the semiconductor memory device 100 based on operation requests received from the host device 300.

[0037] The semiconductor memory device 100 operates in response to control by the controller 200. The semiconductor memory device 100 includes an array of memory cells having multiple memory blocks. As an embodiment, the semiconductor memory device 100 may be a flash memory device.

[0038] The controller 200 can exchange data DATA based on a request RQ from the host device 300. Specifically, the controller 200 can receive write requests, read requests, or trim requests from the host device 300, and control the semiconductor memory device 100 based on the received requests. More specifically, the controller 200 can generate a command CMD for controlling the operation of the semiconductor memory device 100 and send the command CMD to the semiconductor memory device 100. Furthermore, the controller 200 can exchange data DATA with the semiconductor memory device 100.

[0039] Semiconductor memory device 100 is configured to receive commands and addresses from controller 200 and access regions in the memory cell array selected by the addresses. That is, semiconductor memory device 100 performs internal operations corresponding to the commands for the regions selected by the addresses.

[0040] For example, the semiconductor memory device 100 can perform programming operations, reading operations, and erasing operations. During a programming operation, the semiconductor memory device 100 can program data into an area selected by an address. During a reading operation, the semiconductor memory device 100 can read data from the area selected by an address. During an erasing operation, the semiconductor memory device 100 can erase the data stored in the area selected by an address.

[0041] The controller 200 of the storage device 1000 can control the garbage collection operation of the semiconductor memory device 100. For the garbage collection operation, the controller 200 of the storage device 100 can control the semiconductor memory device 100 to read valid data programmed in a victim block of the memory cell array and program the read data into a target block of the memory cell array. The garbage collection operation can be performed as a background operation of the storage device 1000.

[0042] The storage device 1000 according to embodiments of the present disclosure can support programming suspension and programming resumption functions related to programming operations of the semiconductor memory device 100. For example, while the semiconductor memory device is performing a programming operation that is a detailed operation such as a garbage collection operation, a read request can be sent from the host device 300 to the storage device 1000. In this case, the controller 200 can control the semiconductor memory device 100 to stop the programming operation being executed and perform a read operation corresponding to the read request received from the host device 300. More specifically, the controller 200 can send a programming suspension command to the semiconductor memory device 100 in response to the received read request. The semiconductor memory device 100 can stop the programming operation being executed in response to the received programming suspension command. Thereafter, the controller 200 can send a read command to the semiconductor memory device 100 corresponding to the read request received from the host device 300. The semiconductor memory device 100 can perform a read operation corresponding to the received read command. After the read data is sent from the semiconductor memory device 100 to the controller 200, the controller 200 can send a programming resumption command to the semiconductor memory device 100. The semiconductor memory device 100 can resume a stopped programming operation in response to a received programming recovery command.

[0043] Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0044] Reference Figure 2 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150. The control logic 140 can be implemented in hardware, software, or a combination of both. For example, the control logic 140 can be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0045] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells are non-volatile memory cells and can be configured with non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array. In another embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array. Furthermore, each of the plurality of memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a multi-level cell (MLC) storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to embodiments, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0046] Address decoder 120, read / write circuitry 130, control logic 140, and voltage generator 150 operate as peripheral circuitry to drive memory cell array 110. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control of control logic 140. Address decoder 120 receives addresses through input / output buffers (not shown) within semiconductor memory device 100.

[0047] Address decoder 120 is configured to decode block addresses in received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during a read operation, address decoder 120 applies a read voltage Vread generated by voltage generator 150 to the selected word lines in the selected memory block during a read voltage application operation, and applies a pass voltage Vpass to the remaining unselected word lines. Additionally, during a program verification operation, address decoder 120 applies a verification voltage generated by voltage generator 150 to the selected word lines in the selected memory block and applies a pass voltage Vpass to the remaining unselected word lines.

[0048] Address decoder 120 is configured to decode the column address in the received address. Address decoder 120 sends the decoded column address to read / write circuit 130.

[0049] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or programming operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read / write circuitry 130.

[0050] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0051] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cells, the multiple page buffers PB1 to PBm continuously provide sensing current to the bit lines connected to the memory cells, sense changes in the amount of current flowing according to the programming state of the corresponding memory cells through sensing nodes, and latch the sensed changes as sensing data. The read / write circuit 130 operates in response to page buffer control signals output from control logic 140.

[0052] During a read operation, the read / write circuit 130 senses the data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. As an implementation, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0053] Control logic 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110.

[0054] Voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from control logic 140. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and the multiple voltages are generated by selectively activating the multiple pump capacitors in response to control by control logic 140.

[0055] The address decoder 120, read / write circuit 130, and voltage generator 150 serve as "peripheral circuitry" for performing read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on the control logic 140.

[0056] Figure 3 This is an example Figure 2 A diagram illustrating an implementation of a memory cell array.

[0057] Reference Figure 3 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 4 A more detailed description of the structure of each storage block, which has a three-dimensional structure.

[0058] Figure 4 This is an example Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0059] Reference Figure 4 The storage block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. Within the storage block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 4 In this example, two unit strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0060] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0061] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As an embodiment, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As an embodiment, pillars for providing the channel layer may be provided in each cell string. As an embodiment, pillars for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film may be provided in each cell string.

[0062] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn.

[0063] As an implementation, source selection transistors in cell strings arranged in the same row are connected to source selection lines extending in the row direction, while source selection transistors in cell strings arranged in different rows are connected to different source selection lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0064] In another implementation, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0065] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0066] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The DST of cell strings arranged in the row direction is connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0067] A string of cells arranged in the column direction is connected to a bit line extending in the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0068] A page is configured for memory cells connected to the same word line in a cell string arranged in a row direction. For example, a page is configured for memory cells connected to the first word line WL1 in cell strings CS11 to CS1m in the first row. Another page is configured for memory cells connected to the first word line WL1 in cell strings CS21 to CS2m in the second row. A cell string arranged in a row direction can be selected by selecting either drain select line DSL1 or DSL2. A page in the selected cell string can be selected by selecting any of the word lines WL1 to WLn.

[0069] As another implementation, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, the even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, and the odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0070] As an implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. The more dummy memory cells provided, the higher the operational reliability of the memory block BLKa; however, the larger the size of the memory block BLKa. Conversely, the smaller the dummy memory cells provided, the smaller the size of the memory block BLKa; however, the lower the operational reliability of the memory block BLKa.

[0071] To efficiently control at least one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations on all or a portion of the dummy memory cells can be performed before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cells can have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0072] Figure 5 This is an example Figure 2 A circuit diagram illustrating an implementation of any one of the multiple memory blocks BLK1 to BLKz included in the memory cell array 110, namely memory block BLKb.

[0073] Reference Figure 5The memory block BLKb includes multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm can be connected to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0074] The selection transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selection transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. The source selection transistor SST of the cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0075] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0076] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0077] Memory cells connected to the same word line are configured as a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing any one of the word lines WL1 to WLn.

[0078] As another implementation, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. The even-numbered cell strings in the cell strings CS1 to CSm can be connected to the even-numbered bit lines respectively, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0079] like Figure 3 and Figure 4 As shown, the memory blocks BLK1 to BLKz of the semiconductor memory device 100 can be configured as memory blocks with a three-dimensional structure. However, this disclosure is not limited thereto, and as... Figure 5 As shown, the memory blocks BLK1 to BLKz of the semiconductor memory device 100 can be configured as memory blocks with a two-dimensional structure.

[0080] Figure 6 This is a diagram illustrating the threshold voltage distribution of a multi-level cell (MLC) and the primary and secondary verification voltages used to form the threshold voltage distribution.

[0081] Reference Figure 6For example, a data pattern stored in an MLC and the threshold voltage distribution of the target state corresponding to the data pattern are shown. The MLC storage includes two bits of data: the most significant bit (MSB) and the least significant bit (LSB). Figure 6 In the example, the memory cell corresponding to the erase state E stores a data pattern of "00", the memory cell corresponding to the first programming state PV1 stores a data pattern of "11", the memory cell corresponding to the second programming state PV2 stores a data pattern of "10", and the memory cell corresponding to the third programming state PV3 stores a data pattern of "01". To read the data from the MLC, a first read voltage R1, a second read voltage R2, and a third read voltage R3 can be used. Additionally, a pass voltage Vpass is applied to the unselected word line.

[0082] During the programming verification operation, primary verification voltages Vvf1, Vvf2, and Vvf3, and secondary verification voltages Vvf1*, Vvf2*, and Vvf3* can be used. The secondary verification voltages Vvf1*, Vvf2*, and Vvf3* can be used to distinguish the voltages of memory cells near the primary verification voltages Vvf1, Vvf2, and Vvf3 corresponding to the target state. By reducing the threshold voltage offset width of the memory cells near the primary verification voltages Vvf1, Vvf2, and Vvf3, the threshold voltage distribution width of each of the programming states PV1, PV2, and PV3 can be narrowed. In the following text, reference will be made to... Figures 7 to 11B This disclosure will be described in more detail.

[0083] Figure 7 This is a schematic illustration of a page buffer 131 according to an embodiment of the present disclosure. Specifically, the page buffer 131 is... Figure 2 The illustrated implementation shows page buffer PB1, which is connected to the first bit line BL1 among page buffers PB1 to PBm. Other page buffers PB2 to PBm can also be connected to... Figure 7 The page buffer 131 shown is configured similarly.

[0084] Reference Figure 7 Page buffer 131 may include multiple latches 1311 and 1312 for storing programming data input from external sources during programming operations. For example, in Figure 7 In the illustrated embodiment, page buffer 131 can store two bits of data. In this case, the first latch LAT1 (1311) can store the MSB, while the second latch LAT2 (1312) can store the LSB. The first latch 1311 and the second latch 1312 can maintain the stored data pattern until the programming of the memory cell connected to the first bit line BL1 is completed.

[0085] In addition, page buffer 131 may also include a third latch LAT3 (1313) and a fourth latch LAT4 (1314). The third latch LAT3 (1313) may store data indicating the auxiliary verification result of the memory cell connected to the first bit line BL1. The fourth latch LAT4 (1314) may be used for sensing operations of the first bit line BL1 to perform verification operations.

[0086] Furthermore, page buffer 131 may include a bit-line connection transistor 1316 that controls the connection between bit line BL and latches 1311, 1312, 1313, and 1314. Bit-line connection transistor 1316 is controlled by a bit-line connection control signal PB_SENSE. For example, when data is read from a memory cell, bit-line connection transistor 1316 is turned on to electrically connect bit line BL and the fourth latch 1314.

[0087] During the verification process of the memory cell programming operation, a value indicating whether the threshold voltage of the memory cell connected to the first bit line BL1 is greater than the auxiliary verification voltage corresponding to the target state can be stored in the third latch 1313. For example, when the threshold voltage of the memory cell connected to the first bit line BL1 is less than the auxiliary verification voltage corresponding to the target state, the value "0" can be stored in the third latch 1313. While the value "0" is stored in the third latch 1313, a first programming enable voltage is applied to the first bit line BL1 when a programming pulse is applied. Furthermore, as the programming process proceeds, when the threshold voltage of the memory cell connected to the first bit line BL1 is greater than the auxiliary verification voltage corresponding to the target state, the value "1" can be stored in the third latch 1313. When the value "1" is stored in the third latch 1313, a second programming enable voltage higher than the first programming enable voltage is applied to the first bit line BL1 when a programming pulse is applied in a subsequent programming cycle. Therefore, when the value "1" is stored in the third latch 1313, the threshold voltage offset width of the memory cell connected to the first bit line BL1 is reduced in subsequent programming cycles.

[0088] Furthermore, as the programming process progresses, when the threshold voltage of the memory cell connected to the first bit line BL1 is greater than the main verification voltage corresponding to the target state, the data mode stored in the first latch 1311 and the second latch 1312 can be changed to the data mode corresponding to the erase state E. For example, as shown in the reference... Figure 6As described, since the data mode corresponding to the erase state E is "00", the data mode stored in the first latch 1311 and the second latch 1312 can be changed to "00". When the data mode stored in the first latch 1311 and the second latch 1312 is "00", a programming inhibit voltage is applied to the first bit line BL1 when a programming pulse is applied in a subsequent programming cycle. Therefore, the threshold voltage of the memory cell connected to the first bit line BL1 is maintained in subsequent programming cycles.

[0089] In the following text, reference will be made to Figures 8A to 11B This disclosure will be described in more detail.

[0090] Figure 8A and Figure 8B This is a diagram illustrating the threshold voltage and latch data of the memory cell corresponding to the erase state E. Figure 8A The threshold voltage of the memory cell MCa corresponding to the erase state E is shown, while Figure 8B The data of latches LAT1 to LAT3 connected to the page buffer of the memory cell MCa corresponding to the erase state E is shown.

[0091] Reference Figure 8A The threshold voltage of memory cell MCa storing "00" is shown, where "00" corresponds to the data mode of erase state E. Initially, the threshold voltage of memory cell MCa is Va0. Furthermore, refer to... Figure 8B The data "00" is stored in the first latch 1311 and the second latch 1312 in the page buffer connected to the memory cell MCa. As described above, when the data mode stored in the first latch 1311 and the second latch 1312 is "00", the threshold voltage of the memory cell is maintained in subsequent programming cycles. Therefore, even if programming is performed, the threshold voltage of the memory cell MCa may not increase. Furthermore, it is irrelevant what value the indication of the auxiliary verification result is stored in the third latch LAT3. That is, the bit of the third latch LAT3 connected to the page buffer of the memory cell MCa corresponding to the erase state E can be an "irrelevant bit".

[0092] Figure 9A and Figure 9B This is a diagram illustrating the threshold voltage and latch data of the memory cell corresponding to the first programming state PV1. Figure 9A The threshold voltage change of the memory cell MCb is shown with the first programming state PV1 as the target, while Figure 9B The data changes of latches LAT1 to LAT3 in the page buffer of the memory cell MCb targeted in the first programming state PV1 are shown.

[0093] Reference Figure 9A Before the programming operation, the threshold voltage of the memory cell MCb can be Vb0 and can be included in the erase state E. Through the programming operation, the data pattern "11" can be stored in the memory cell MCb, and thus the memory cell MCb is targeted at the first programming state PV1. When the threshold voltage of the memory cell MCb is Vb0, since it is less than the first auxiliary verification voltage Vvf1* corresponding to the first programming state PV1, the bit "0" is stored in the third latch LAT3. As a result, in the state where the threshold voltage of the memory cell MCb is Vb0, the data pattern "11" is stored in the first latch LAT1 and the second latch LAT2, and the bit "0" is stored in the third latch LAT3.

[0094] As programming operations proceed, the threshold voltage of the memory cell MCb can be gradually increased. For example... Figure 9A As shown, as the programming operation proceeds, the threshold voltage of the memory cell MCb can become Vb1. Vb1 is a voltage greater than the first secondary verification voltage Vvf1* and less than the first primary verification voltage Vvf1. In this case, since the threshold voltage of the memory cell MCb is greater than the first secondary verification voltage Vvf1*, the bit stored in the third latch LAT3 changes from "0" to "1". As a result, with the threshold voltage of the memory cell MCb at Vb1, the data pattern "11" is stored in the first latch LAT1 and the second latch LAT2, and the bit "1" is stored in the third latch LAT3.

[0095] As programming continues, the threshold voltage of the memory cell MCb can be further increased. For example... Figure 9A As shown, as the programming operation proceeds, the threshold voltage of the memory cell MCb can become Vb2. Vb2 is a voltage greater than the first main verification voltage Vvf1. In this case, the threshold voltage of the memory cell MCb reaches the first programming state PV1 as the target, and the threshold voltage no longer needs to be increased. Therefore, the data pattern stored in the first latch LAT1 and the second latch LAT2 becomes the same as the data pattern corresponding to the erase state E, "00". As a result, in the state where the threshold voltage of the memory cell MCb is Vb2, the data pattern "00" can be stored in the first latch LAT1 and the second latch LAT2, and the bit "1" can be stored in the third latch LAT3. However, in this case, since the programming of the memory cell MCb is complete, it is irrelevant what value is stored in the third latch LAT3 indicating the secondary verification result of the memory cell MCb. That is, in the state where programming is complete, the bit of the third latch LAT3 connected to the page buffer of the memory cell MCb can be an "irrelevant bit".

[0096] Figure 10A and Figure 10B This is a diagram illustrating the threshold voltage and latch data of the memory cell corresponding to the second programming state PV2. Figure 10A The threshold voltage change of the memory cell MCc is shown with the second programming state PV2 as the target, while Figure 10B The data changes of latches LAT1 to LAT3 in the page buffer of the memory cell MCc, which is targeted at the second programming state PV2, are shown.

[0097] Reference Figure 10A Before the programming operation, the threshold voltage of the memory cell MCc can be Vc0 and can be included in the erase state E. Through the programming operation, the data pattern "10" can be stored in the memory cell MCc, and thus the memory cell MCc is targeted at the second programming state PV2. When the threshold voltage of the memory cell MCc is Vc0, since it is less than the second auxiliary verification voltage Vvf2* corresponding to the second programming state PV2, the bit "0" is stored in the third latch LAT3. As a result, in the state where the threshold voltage of the memory cell MCc is Vc0, the data pattern "10" is stored in the first latch LAT1 and the second latch LAT2, and the bit "0" is stored in the third latch LAT3.

[0098] As programming progresses, the threshold voltage of the memory cell MCC can be gradually increased. For example... Figure 10A As shown, during programming, the threshold voltage of the memory cell MCc can be Vc1. Vc1 is a voltage greater than the second auxiliary verification voltage Vvf2* and less than the second primary verification voltage Vvf2. In this case, since the threshold voltage of the memory cell MCc is greater than the second auxiliary verification voltage Vvf2*, the bit stored in the third latch LAT3 changes from "0" to "1". As a result, with the threshold voltage of the memory cell MCc at Vc1, the data pattern "10" is stored in the first latch LAT1 and the second latch LAT2, and the bit "1" is stored in the third latch LAT3.

[0099] As programming continues, the threshold voltage of the memory cell MCC can be further increased. For example... Figure 10AAs shown, as the programming operation proceeds, the threshold voltage of the memory cell MCc can become Vc2. Vc2 is a voltage greater than the second main verification voltage Vvf2. In this case, the threshold voltage of the memory cell MCc reaches the second programming state PV2 as the target, and the threshold voltage no longer needs to be increased. Therefore, the data pattern stored in the first latch LAT1 and the second latch LAT2 becomes the same as the data pattern corresponding to the erase state E, "00". As a result, in the state where the threshold voltage of the memory cell MCc is Vc2, the data pattern "00" can be stored in the first latch LAT1 and the second latch LAT2, and the bit "1" can be stored in the third latch LAT3. However, in this case, since the programming of the memory cell MCc is complete, it is irrelevant what value is stored in the third latch LAT3 indicating the secondary verification result of the memory cell MCc. That is, in the state where programming is complete, the bit of the third latch LAT3 connected to the page buffer of the memory cell MCc can be an "irrelevant bit".

[0100] Figure 11A and Figure 11B This is a diagram illustrating the threshold voltage and latch data of the memory cell corresponding to the third programming state PV3. Figure 11A The threshold voltage change of the memory cell MCd is shown with the third programming state PV3 as the target. Figure 11B The data changes of latches LAT1 to LAT3 in the page buffer of the memory cell MCd, which is targeted at the third programming state PV3, are shown.

[0101] Reference Figure 11A Before the programming operation, the threshold voltage of the memory cell MCd can be Vd0 and can be included in the erase state E. Through the programming operation, the data pattern "01" can be stored in the memory cell MCd, and thus the memory cell MCd is targeted at the third programming state PV3. When the threshold voltage of the memory cell MCd is Vd0, since Vd0 is less than the third auxiliary verification voltage Vvf3* corresponding to the third programming state PV3, the bit "0" is stored in the third latch LAT3. As a result, in the state where the threshold voltage of the memory cell MCd is Vd0, the data pattern "01" is stored in the first latch LAT1 and the second latch LAT2, and the bit "0" is stored in the third latch LAT3.

[0102] As programming progresses, the threshold voltage of the memory cell MCd can be gradually increased. For example... Figure 11AAs shown, during the programming operation, the threshold voltage of the memory cell MCd can become Vd1. Vd1 is a voltage greater than the third auxiliary verification voltage Vvf3* and less than the third main verification voltage Vvf3. In this case, since the threshold voltage of the memory cell MCd is greater than the third auxiliary verification voltage Vvf3*, the bit stored in the third latch LAT3 changes from "0" to "1". As a result, with the threshold voltage of the memory cell MCd at Vd1, the data pattern "01" is stored in the first latch LAT1 and the second latch LAT2, and the bit "1" is stored in the third latch LAT3.

[0103] As programming continues, the threshold voltage of the memory cell MCd can be further increased. For example... Figure 11A As shown, as the programming operation proceeds, the threshold voltage of the memory cell MCd can become Vd2. Vd2 is a voltage greater than the third main verification voltage Vvf3. In this case, the threshold voltage of the memory cell MCd reaches the target third programming state PV3, and the threshold voltage no longer needs to be increased. Therefore, the data pattern stored in the first latch LAT1 and the second latch LAT2 becomes the same as the data pattern corresponding to the erase state E, "00". As a result, in the state where the threshold voltage of the memory cell MCd is Vd2, the data pattern "00" can be stored in the first latch LAT1 and the second latch LAT2, and the bit "1" can be stored in the third latch LAT3. However, in this case, since the programming of the memory cell MCd is complete, it is irrelevant what value is stored in the third latch LAT3 indicating the secondary verification result of the memory cell MCd. That is, in the state where programming is complete, the bit of the third latch LAT3 connected to the page buffer of the memory cell MCd can be an "irrelevant bit".

[0104] As described above, the first latch LAT1 (1311) and the second latch LAT2 (1312) in the page buffer can store data patterns corresponding to the target programming state until the programming of the corresponding memory cell is completed. In addition, the third latch LAT3 (1313) in the page buffer stores a bit indicating whether the threshold voltage of the corresponding memory cell is greater than the auxiliary verification voltage corresponding to the target programming state.

[0105] Figure 12A and Figure 12B This is a graph illustrating the changes in data in the page buffer when a programming suspend command is received during a programming operation.

[0106] Reference Figure 12A The semiconductor memory device 100 can respond to a programming command (CMD) received from the controller 200. PGMThe controller 200 may require specific data from the semiconductor memory device 100 before the programming operation of the semiconductor memory device 100 is completed. In this case, the controller 200 sends a programming suspend command (CMD) to the semiconductor memory device 100. SUS The semiconductor memory device 100 responds to the programming suspend command CMD. SUS The ongoing programming operation is then stopped. With the semiconductor memory device 100 in a stopped programming state, the controller 200 sends a read command (CMD) to the semiconductor memory device 100. RD Semiconductor memory device 100 responds to read command CMD RD The corresponding data is read and sent to the controller 200. The controller 200 receives the corresponding read command CMD. RD After receiving the data, the controller 200 sends a programming recovery command (CMD) to the semiconductor memory device. RSM Responding to the programmatic recovery command CMD RSM The semiconductor memory device 100 resumes the programming operation that has been stopped.

[0107] Reference Figure 12B When a programming suspension command is received, the first latch LAT1 (1311) and the second latch LAT2 (1312) retain the stored data mode. This is to resume the stopped programming operation when a programming resume command is subsequently received. Furthermore, when a programming suspension command is received, the third latch LAT3 (1313) is reset. This is because the third latch LAT3 (1313) is used for read operations. Since the third latch is reset when the programming suspension command is received, the data indicating the previously stored secondary verification result is removed from the page buffer. Subsequently, when the programming operation is resumed, the corresponding secondary verification operation needs to be performed again.

[0108] However, when the time between programming suspension and programming resumption is long, stagnation occurs in the memory cells. Due to this stagnation, the threshold voltage of the memory cell is higher than the secondary verification voltage immediately preceding the programming suspension; however, when the secondary verification operation is performed again after programming resumption, the threshold voltage of the memory cell is lower than the secondary verification voltage. In this case, in the implementation, a widening of the threshold voltage distribution of the memory cells occurs because a relatively low first programming allow voltage is applied to the bit line connected to the corresponding memory cell.

[0109] It is possible to further include a method that retains the auxiliary verification results even if a programming suspend command is received. However, this increases the number of latches included in each page buffer and contributes to the increased manufacturing cost and size of the semiconductor memory device 100.

[0110] According to the semiconductor memory device 100 of the present disclosure, when a programming suspension command is received, the auxiliary verification result is held in the first latch LAT1 (1311) and the second latch LAT2 (1312) by utilizing the data pattern of the programming state that has been pre-verified. Therefore, during programming suspension, the auxiliary verification result can be held in the page buffer without the need for additional latches. Referring below... Figures 13 to 21B A method for operating a semiconductor memory device 100 according to an embodiment of the present disclosure is described.

[0111] Figure 13 This is a flowchart illustrating a method for operating a semiconductor memory device according to an embodiment of the present disclosure when a programming suspension command is received. Figure 14A and Figure 14B It provides a more detailed example based on... Figure 13 The method is illustrated in the diagram below. (Refer to the diagram below.) Figure 13 , Figure 14A and Figure 14B Let's describe this disclosure together.

[0112] Reference Figure 13 A method for operating a semiconductor memory device according to an embodiment of the present disclosure includes: starting a programming operation in response to a programming command (S110), receiving a programming suspension command (S130), determining whether the verification of a first programming state PV1 is passed (S150), changing an auxiliary verification data mode stored in a first page buffer to a first data mode corresponding to the first programming state, the first page buffer being connected to a memory cell in a memory cell to be programmed into a second programming state, the memory cell having a threshold voltage between a second main verification voltage and a second auxiliary verification voltage (S170), and resetting a third latch included in the page buffer (S190).

[0113] In step S110, the semiconductor memory device 100 may respond to the programming command CMD received from the controller 200. PGM The programming operation then begins. In this case, the semiconductor memory device 100 begins to perform a programming operation on the selected memory cell using the main verification voltages Vvf1, Vvf2, and Vvf3, and the auxiliary verification voltages Vvf1*, Vvf2*, and Vvf3*, which correspond to the corresponding first programming state PV1, second programming state PV2, and third programming state PV3.

[0114] In step S130, the semiconductor memory device 100 receives a programming suspension command (CMD) from the controller 200. SUS Responding to the programmatic suspend command CMD SUSThe semiconductor memory device 100 can stop the programming operation. Furthermore, the semiconductor memory device 100 determines whether a verification operation for the first programming state PV1 has passed among the first programming states PV1 to the third programming states PV3. When the verification operation for the first programming state PV1 passes (S150: Yes), this means that the memory cell targeted by the first programming state PV1 (e.g., ...) is... Figure 9A All threshold voltages of the memory cell MCb shown are higher than the first master verification voltage Vvf1. This situation means that all data modes of the first latch LAT1 (1311) and the second latch LAT2 (1312) in the page buffer connected to the memory cell targeted by the first programming state PV1 are changed to "00", as shown in the reference. Figure 9B As described. In other words, all latches corresponding to memory cell MCb that store the initial data pattern "11" (i.e., the first latch LAT1 (1311) and the second latch LAT2 (1312)) store the data pattern "00".

[0115] Therefore, when the verification operation of the first programming state PV1 passes (S150: Yes), the data mode stored in the first latch LAT1 (1311) and the second latch LAT2 (1312) of the page buffer (i.e., the first page buffer in step S170) of the memory cell MCc to be programmed into the second programming state PV2 changes from "10" to "11". In step S170, the first data mode can be the data mode corresponding to the first programming state PV1 where programming has been completed, and for example, it can be "11".

[0116] Reference Figure 14A The first latch LAT1 (1311) and the second latch LAT2 (1312) whose data modes are changed in step S170 correspond to the memory cells MCc to be programmed into the second programming state PV2, where the threshold voltage is between the second auxiliary verification voltage Vvf2* and the second main verification voltage Vvf2. That is, referring to Figure 14BIn step S170, for the page buffer (i.e., the first page buffer) where the data mode "10" is stored in the first latch LAT1 (1311) and the second latch LAT2 (1312) and the bit data "1" is stored in the third latch LAT3 (1313), the data mode stored in the first latch LAT1 (1311) and the second latch LAT2 (1312) is changed to "11". This is so that even if the third latch LAT3 is reset, when programming is resumed later, the memory cells in the memory cell MCc to be programmed into the second programming state PV2 with a threshold voltage less than the second auxiliary verification voltage Vvf2* are distinguished from the memory cells with threshold voltages between the second auxiliary verification voltage Vvf2* and the second main verification voltage Vvf2.

[0117] Since all programming of the memory cell MCb targeted by the first programming state PV1 has been completed, even if the data modes of the first latch LAT1 (1311) and the second latch LAT2 (1312) corresponding to the memory cell whose threshold voltage Vc1 corresponds to that of the memory cell MCc to be programmed into the second programming state PV2 are changed to "11", the memory cell with threshold voltage Vc1 will not be confused with the memory cell MCb targeted by the first programming state PV1. As described above, this is because all data modes of the first latch LAT1 (1311) and the second latch LAT2 (1312) corresponding to the memory cell MCb targeted by the first programming state PV1 are changed to "00". In this way, when the programming operation stops, the memory cell whose threshold voltage in the memory cell MCc to be programmed into the second programming state PV2 is between the second auxiliary verification voltage Vvf2* and the second main verification voltage Vvf2 can be distinguished from the memory cell whose threshold voltage is less than the second auxiliary verification voltage Vvf2*. In this method, the results of auxiliary verification operations for the second programming state PV2 can be maintained even during the period when programming operations are stopped.

[0118] After step S170, the third latch LAT3 (1313) included in page buffers PB1 to PBm is reset (S190). According to step S190, the data indicating the auxiliary verification results for the first programming state PV1 to the third programming state PV3 is lost. However, the data indicating the auxiliary verification results for the second programming state PV2 can be retained by step S170.

[0119] At this point, if, as a result of step S150, it is determined that the verification operation for the first programming state PV1 failed (S150: No), this means that in the page buffer corresponding to the memory cell MCb targeting the first programming state PV1, there exists a page buffer that still stores data mode "11" (i.e., the first data mode). In this case, when step S170 is executed, the memory cell in the memory cell MCc to be programmed into the second programming state PV2, whose threshold voltage is between the second auxiliary verification voltage Vvf2* and the second main verification voltage Vvf2, may not be distinguishable from the unprogrammed memory cell in the memory cell MCb targeting the first programming state PV1.

[0120] Therefore, in this case, the third latch LAT3 (1313) included in page buffers PB1 to PBm is reset (S190) without executing step S170. That is, when the verification operation for the first programming state PV1 fails (S150: No), data indicating the auxiliary verification result for the second programming state PV2 may not be held during the programming suspension. Although Figure 13 Not shown, but after step S190, the semiconductor memory device 100 can receive a read command from the controller 200 to perform a read operation.

[0121] Figure 15 This is a flowchart illustrating a method for operating a semiconductor memory device according to an embodiment of the present disclosure when a programming recovery command is received. Figure 16 It provides a more detailed example based on... Figure 15 The method is illustrated in the diagram below. (Refer to the diagram below.) Figure 15 and Figure 16 This disclosure is described together.

[0122] Reference Figure 15 A method for operating a semiconductor memory device according to embodiments of the present disclosure includes: receiving a programming recovery command (CMD). RSM (S210) Reset the third latch LAT3 (1313) included in the page buffer (S230), determine whether the first programming state has been verified (S250), store the auxiliary verification data pattern corresponding to the second programming state in the first page buffer (S270), and resume the programming operation (S290). Figure 13 Following the steps shown, after the semiconductor memory device 100 receives a read command from the controller 200 to perform a read operation, it can then execute... Figure 15 The steps.

[0123] In step S210, the semiconductor memory device 100 receives a programming recovery command (CMD) from the controller 200.RSM Responding to the programmatic recovery command CMD RSM The semiconductor memory device 100 can first reset the third latch LAT3 (1313) included in the page buffers PB1 to PBm. This is because unnecessary data may have been stored in the third latch LAT3 (1313) due to the previous read operation. In an embodiment, in step S230, the third latch LAT3 (1313) included in the page buffers PB1 to PBm can be reset to store the bit data "0".

[0124] like Figure 16 As shown. Through step S230, the bit stored in the third latch LAT3 (1313) in each of the page buffers PB1 to PBm is changed to "0".

[0125] In step S250, it can be determined whether the first programming state PV1 has passed verification before the programming operation is stopped. To this end, when the programming operation stops, the semiconductor memory device 100 can retain data indicating whether the verification of the first programming state PV1 has passed. When the programming operation stops and a programming resumption command is received, the semiconductor memory device 100 can refer to this data to determine whether the verification of the first programming state PV1 has passed. For example, the data indicating whether the verification of the first programming state PV1 has passed can be stored in a specific register in the control logic 140.

[0126] When the first programming state PV1 verification passes before the programming operation stops (S250: Yes), execution can be performed in response to the programming suspension command. Figure 13 Step S170. Therefore, in response to the execution of step S170, data indicating the auxiliary verification result for the second programming state PV2 is recovered. Specifically, through step S270, the first page buffer is identified, and the auxiliary verification data pattern corresponding to the second programming state is stored in the first page buffer.

[0127] As referenced above Figure 13 As described, the first page buffer refers to a page buffer connected to a memory cell MCc, which is to be programmed into the second programming state PV2, and whose threshold voltage is between the second primary verification voltage Vvf2 and the second secondary verification voltage Vvf2*. Through step S170, the first data mode "11" can be stored in the first latch LAT1 (1311) and the second latch LAT2 (1312) included in the first page buffer. As described above, the first data mode corresponds to the data mode of the first programming state PV1. Therefore, the page buffer in the first latch LAT1 (1311) and the second latch LAT2 (1312) storing the first data mode "11" can be identified as the first page buffer.

[0128] In step S270, the auxiliary verification data pattern corresponding to the second programming state is stored in the identified first page buffer. The auxiliary verification data pattern corresponding to the second programming state PV2 is corresponding to... Figure 10B The threshold voltage Vc1 in the table is in the data pattern "101". That is, in step S270, the data pattern "101" is stored in the first latch LAT1 (1311), the second latch LAT2 (1312) and the third latch LAT3 (1313) of the first page buffer.

[0129] Therefore, as Figure 16 As shown, by executing step S270, the auxiliary verification data corresponding to the second programming state PV2 can be recovered.

[0130] pass Figures 13 to 16 A method is described for maintaining the auxiliary verification result for the second programming state PV2 during programming suspension when the first programming state PV1 verification passes. However, this disclosure is not limited to this, and when the first programming state PV1 verification passes, the auxiliary verification result for the third programming state PV3 can be maintained during programming suspension. In such an implementation, during programming suspension, instead of Figure 13 Step S170 may involve performing the following steps: changing the secondary verification data mode stored in the first page buffer to a first data mode corresponding to the first programming state, wherein the first page buffer is connected to a memory cell in the memory cell to be programmed to the third programming state, and the threshold voltage is between the third primary verification voltage and the third secondary verification voltage. Furthermore, when reprogramming, instead of... Figure 15 Step S270 can be performed by identifying the first page buffer and storing the auxiliary verification data pattern corresponding to the third programming state in the first page buffer.

[0131] In addition, refer to Figures 13 to 16 A method is described for maintaining the auxiliary verification result for the second programming state PV2 during a programming suspension when the first programming state PV1 verification passes. In another embodiment, when the first programming state PV1 and the second programming state PV2 verification pass, the auxiliary verification result for the third programming state PV3 can be maintained. Referring below... Figures 17A to 18B This disclosure is described.

[0132] Figure 17A This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming suspension command is received. Figure 17B It provides a more detailed example based on... Figure 17A The method is illustrated in the diagram below. (Refer to the diagram below.) Figure 17A and Figure 17B This disclosure is described together.

[0133] Reference Figure 17A A method for operating a semiconductor memory device according to an embodiment of the present disclosure includes: initiating a programming operation in response to a programming command (S310); receiving a programming suspension command (S330); determining whether the verification of a first programming state PV1 and a second programming state PV2 has passed (S350); changing the auxiliary verification data mode stored in a second page buffer to a second data mode corresponding to the second programming state, wherein the second page buffer is connected to a memory cell to be programmed into a third programming state, the memory cell having a threshold voltage between a third primary verification voltage and a third auxiliary verification voltage (S370); and resetting a third latch included in the page buffer (S390). Figure 17A In the process, steps S310, S330, and S390 can be related to... Figure 13 Steps S110, S130, and S190 are essentially the same. Therefore, repeated descriptions are omitted.

[0134] In step S350, it is determined whether all verifications for the first programming state PV1 and the second programming state PV2 have passed. When all verifications for the first programming state PV1 and the second programming state PV2 have passed (S350: Yes), the auxiliary verification data mode corresponding to the third programming state can be changed to either the first data mode corresponding to the first programming state PV1 or the second data mode corresponding to the second programming state PV2. This is because all data modes of the page buffers connected to the memory cells corresponding to the first programming state PV1 and the second programming state PV2 are changed to "00". Figure 17A In the example, when all verifications for the first programming state PV1 and the second programming state PV2 pass (S350: Yes), the auxiliary verification data mode stored in the second page buffer is changed to the second data mode corresponding to the second programming state PV2. The second page buffer is connected to the memory cell in the memory cell to be programmed into the third programming state PV3, and the threshold voltage is between the third main verification voltage Vvf3 and the third auxiliary verification voltage Vvf3*.

[0135] Reference Figure 17BIn step S370, the data stored in the first latch LAT1 (1311) and the second latch LAT2 (1312) of the page buffer connected to the memory cell corresponding to the threshold voltage Vd1 in the memory cell MCd to be programmed into the third programming state PV3 is changed from "01" to "10". Therefore, even if the third latch LAT3 (1313) of the page buffers PB1 to PBm is reset by a programming suspension command, the memory cell corresponding to the threshold voltage Vd1 in the memory cell MCd to be programmed into the third programming state PV3 can be distinguished from the memory cell corresponding to the threshold voltage Vd0. That is, even if the third latch LAT3 (1313) of the page buffers PB1 to PBm is reset by a programming suspension command, the auxiliary verification result for the third programming state PV3 can be maintained.

[0136] Figure 18A This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming recovery command is received. Figure 18B It provides a more detailed example based on... Figure 18A The method is illustrated in the diagram below. (Refer to the diagram below.) Figure 18A and Figure 18B This disclosure is described together.

[0137] Reference Figure 18A A method for operating a semiconductor memory device according to embodiments of the present disclosure includes: receiving a programming recovery command (CMD). RSM (S410) Reset the third latch LAT3 (1313) included in the page buffer (S430), determine whether the second programming state has been verified (S450), store the auxiliary verification data pattern corresponding to the third programming state in the second page buffer (S470), and resume the programming operation (S490). Figure 18A In the process, steps S410, S430, and S490 can be related to... Figure 15 Steps S210, S230, and S290 are essentially the same. Therefore, repeated descriptions are omitted.

[0138] In step S410, the semiconductor memory device 100 receives a programming recovery command (CMD) from the controller 200. RSM Responding to the programmatic recovery command CMD RSMThe semiconductor memory device 100 can first reset the third latch LAT3 (1313) included in the page buffers PB1 to PBm. This is because unnecessary data may have been stored in the third latch LAT3 (1313) due to the previous read operation. In an embodiment, in step S230, the third latch LAT3 (1313) included in the page buffers PB1 to PBm can be reset to store the bit data "0".

[0139] like Figure 18B As shown, through step S430, the bit stored in the third latch LAT3 (1313) included in each of the page buffers PB1 to PBm becomes "0".

[0140] In step S450, it can be determined whether the second programming state PV2 has passed verification before the programming operation is stopped. To this end, when the programming operation stops, the semiconductor memory device 100 can retain data indicating whether the verification of the second programming state PV2 has passed. When the programming operation stops and a programming resumption command is received, the semiconductor memory device 100 can refer to this data to determine whether the verification of the second programming state PV2 has passed. For example, the data indicating whether the verification of the second programming state PV2 has passed can be stored in a specific register in the control logic 140.

[0141] When the second programming state PV2 verification passes (S450: Yes) before the programming operation stops, execution can be performed in response to the programming suspension command. Figure 17A Step S370. Therefore, in response to the execution of step S370, data indicating the auxiliary verification result for the third programming state PV3 is recovered. Specifically, through step S470, the second page buffer is identified, and the auxiliary verification data pattern corresponding to the third programming state is stored in the second page buffer.

[0142] The second page buffer refers to the page buffer of the memory cell connected to the memory cell MCd to be programmed into the third programming state PV3, whose threshold voltage is between the third main verification voltage Vvf3 and the third auxiliary verification voltage Vvf3*. In step S470, the auxiliary verification data pattern corresponding to the third programming state is stored in the identified second page buffer. The auxiliary verification data pattern corresponding to the third programming state PV3 is corresponding to... Figure 11B The threshold voltage Vd1 in the table is in the data pattern "011". That is, in step S470, the data pattern "011" is stored in the first latch LAT1 (1311), the second latch LAT2 (1312) and the third latch LAT3 (1313) of the second page buffer.

[0143] Therefore, as Figure 18BAs shown, by executing step S470, the auxiliary verification data corresponding to the third programming state PV3 can be recovered.

[0144] The above description describes a method for maintaining auxiliary verification results for a portion of the programming state when a programming suspension command is received during the programming operation of an MLC. However, this disclosure is not limited to this and can be applied to three-level cells (TLC), four-level cells (QLC), and memory cells storing five or more bits of data. Reference will be made below. Figures 19 to 21B This disclosure describes its application to TLC.

[0145] Figure 19 This is a diagram illustrating the threshold voltage distribution of a TLC and the primary and secondary verification voltages used to form the threshold voltage distribution.

[0146] Reference Figure 19 For example, a data pattern stored in a TLC and the corresponding threshold voltage distribution for the target state are shown. The TLC stores three bits of data: the most significant bit (MSB), the center significant bit (CSB), and the least significant bit (LSB). Figure 19 In the example, the memory cell corresponding to the erase state E can store the data pattern "000", and the memory cells corresponding to the first programming states PV1 to the seventh programming states PV7 can store the data patterns "111", "110", "011", "101", "100", "010", and "001", respectively. However, this is just an example, and various other combinations of data patterns can be applied.

[0147] To read data from the TLC, first read voltage R1 through seventh read voltage R7 can be used. Additionally, a pass voltage Vpass is applied to the unselected word line.

[0148] During the programming verification operation, primary verification voltages Vvf1, Vvf2, Vvf3, Vvf4, Vvf5, Vvf6, and Vvf7 and secondary verification voltages Vvf1*, Vvf2*, Vvf3*, Vvf4*, Vvf5*, Vvf6*, and Vvf7* can be used. The secondary verification voltages Vvf1*, Vvf2*, Vvf3*, Vvf4*, Vvf5*, Vvf6*, and Vvf7* can be used to distinguish memory cells near the primary verification voltages Vvf1, Vvf2, Vvf3, Vvf4, Vvf5, Vvf6, and Vvf7 corresponding to the target state. By reducing the threshold voltage offset width of memory cells near the main verification voltages Vvf1, Vvf2, Vvf3, Vvf4, Vvf5, Vvf6, and Vvf7, the threshold voltage distribution width of each of the programming states PV1 to PV7 can be narrowed.

[0149] Figure 20 This is a schematic illustration of a page buffer 131' according to another embodiment of the present disclosure. Specifically, page buffer 131' is... Figure 2 The illustrated implementation shows page buffer PB1, which is connected to the first bit line BL1, among page buffers PB1 to PBm. Other page buffers PB2 to PBm can be implemented similarly. Figure 20 The page buffer 131' shown is configured to be used.

[0150] Reference Figure 20 The page buffer 131' may include multiple latches 1311', 1312', and 1313' for storing programming data input from an external source during programming operations. For example, in Figure 20 In the illustrated embodiment, page buffer 131' can store three bits of data. In this case, the first latch LAT1 (1311') can store the MSB, the second latch LAT2 (1312') can store the CSB, and the third latch LAT3 (1313') can store the LSB. The first latch 1311' to the third latch 1313' can maintain the stored data pattern until the programming of the memory cell connected to the first bit line BL1 is completed.

[0151] Furthermore, the page buffer 131' may also include a fourth latch LAT4 (1314') and a fifth latch LAT5 (1315'). The fourth latch LAT4 (1314') may store data indicating the auxiliary verification result of the memory cell connected to the first bit line BL1. The fifth latch LAT5 (1315') may be used for sensing operations on the first bit line BL1 to perform verification operations.

[0152] Figure 21A This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming suspension command is received. (See also...) Figure 21A A method for operating a semiconductor memory device according to an embodiment of the present disclosure includes: initiating a programming operation in response to a programming command (S510); receiving a programming suspension command (S530); determining whether the verification of the first programming state to the qth programming state among the first programming state to the yth programming state has passed (S550); changing the auxiliary verification data mode stored in a third page buffer to a kth data mode corresponding to the kth programming state among the first programming state to the qth programming state, the third page buffer being connected to a memory cell in the memory cell to be programmed to the xth programming state, the memory cell having a threshold voltage between the xth primary verification voltage and the xth auxiliary verification voltage (S570); and resetting a fourth latch page included in the page buffer (S590). Figure 21AThe repeated descriptions of steps S510, S530 and S590 have been omitted.

[0153] In step S550, the y-th programming state can refer to the highest programming state. In TLC, the value of y can be 7. In QLC, the value of y can be 15. Furthermore, the value of q can be greater than 1 and less than y.

[0154] In step S570, the x-th programming state can be a programming state higher than the q-th programming state. That is, x can be greater than q and less than or equal to y. Furthermore, the value of k can be greater than or equal to 1 and less than or equal to q.

[0155] In other words, through Figure 21A The steps shown can maintain the auxiliary verification result of any programming state PVx among the programming states that are not yet fully programmed by using the k-th data pattern corresponding to any PVk among the verified programming states PV1 to PVq.

[0156] Figure 21B This is a flowchart illustrating a method for operating a semiconductor memory device according to another embodiment of the present disclosure when a programming recovery command is received.

[0157] Reference Figure 21B A method for operating a semiconductor memory device according to embodiments of the present disclosure includes: receiving a programming recovery command (CMD). RSM (S610) Reset the fourth latch LAT4 (1314') included in the page buffer (S630), determine whether the k-th programming state has passed verification (S650), store the auxiliary verification data pattern corresponding to the x-th programming state in the third page buffer (S670), and resume the programming operation (S690). Figure 21B Repeated descriptions of steps S610, S630, and S690 have been omitted.

[0158] In step S650, it can be determined whether the k-th programming state PVk has passed verification before the programming operation stops. When the k-th programming state PVk passes verification before the programming operation stops (S650: Yes), the third page buffer is identified, and the auxiliary verification data pattern corresponding to the x-th programming state is stored in the third page buffer. Therefore, the auxiliary verification data corresponding to the x-th programming state PVx can be recovered by executing step S670.

[0159] Figure 22 This is an example Figure 1 A block diagram illustrating an application example of a storage device.

[0160] Reference Figure 22The storage device 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0161] exist Figure 22 In this process, multiple groups communicate with the controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip can communicate with a reference... Figure 2 One of the described semiconductor memory devices 100 is similarly configured and can operate similarly thereto.

[0162] Each group is configured to communicate with controller 2200 via a common channel. Controller 2200 is configured to control multiple memory chips of semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0163] exist Figure 22 In this configuration, multiple semiconductor memory chips are connected to a single channel. However, it is understood that the storage device 2000 can be modified so that only one semiconductor memory chip is connected to a single channel.

[0164] Figure 23 This illustrates the example including references. Figure 22 A block diagram of a computing system describing a storage device.

[0165] Reference Figure 23 The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, user interface 3300, power supply 3400, system bus 3500 and storage device 2000.

[0166] Storage device 2000 is electrically connected to central processing unit 3100, RAM 3200, user interface 3300 and power supply 3400 via system bus 3500. Data provided through user interface 3300 or data processed by central processing unit 3100 is stored in storage device 2000.

[0167] exist Figure 23 In this configuration, the semiconductor memory device 2100 is connected to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the controller 2200 are performed by the central processing unit 3100 and the RAM 3200.

[0168] exist Figure 23 The reference is provided in the middle. Figure 22 The storage device 2000 is described. However, the storage device 2000 can be described using reference. Figure 1The described storage device 1000 is replaced. As an embodiment, the computing system 3000 can be configured to include the reference... Figure 1 and Figure 22 Both storage devices 1000 and 2000 are described.

[0169] Cross-reference to related applications

[0170] This application claims priority to Korean Patent Application No. 10-2022-0034320, filed on March 18, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A method of operating a semiconductor memory device, the method comprising the following steps: In response to the programming command, the programming operation on the selected memory cell is initiated using the primary verification voltage and the secondary verification voltage; Receive a programming suspension command during the programming operation; as well as In response to the programming suspension command, at least one auxiliary voltage verification result information in the unprogrammed threshold voltage state is changed to at least one data mode in the programmed threshold voltage state.

2. The method according to claim 1, wherein, The semiconductor memory device includes a multi-level cell (MLC), and the step of changing at least one auxiliary voltage verification result information of a threshold voltage state that has failed programming to at least one data mode of a threshold voltage state that has passed programming in response to the programming suspension command includes the following steps: Determine whether the verification operation for the first programming state (among the first, second, and third programming states) passed; and The data pattern stored in the page buffer corresponding to the memory cell in the memory cell to be programmed into the second programming state, where the threshold voltage is between the second auxiliary verification voltage and the second main verification voltage, is changed to the first data pattern corresponding to the first programming state.

3. The method according to claim 2, further comprising the following steps: Receive programming recovery command; Determine whether the first programming state has passed verification; and The auxiliary verification data pattern corresponding to the second programming state is stored in the page buffer.

4. The method according to claim 1, wherein, The semiconductor memory device includes a multi-level cell (MLC), and the step of changing at least one auxiliary voltage verification result information of a threshold voltage state that has failed programming to at least one data mode of a threshold voltage state that has passed programming in response to the programming suspension command includes the following steps: Determine whether the verification operation for the first programming state (among the first, second, and third programming states) passed; and The data pattern stored in the page buffer corresponding to the memory cell whose threshold voltage is between the third secondary verification voltage and the third primary verification voltage in the memory cell to be programmed into the third programming state is changed to the first data pattern corresponding to the first programming state.

5. The method according to claim 4, further comprising the following steps: Receive programming recovery command; Determine whether the first programming state has passed verification; and The auxiliary verification data pattern corresponding to the third programming state is stored in the page buffer.

6. The method according to claim 1, wherein, The semiconductor memory device includes a multi-level cell (MLC), and the step of changing at least one auxiliary voltage verification result information of a threshold voltage state that has failed programming to at least one data mode of a threshold voltage state that has passed programming in response to the programming suspension command includes the following steps: Determine whether the verification operation for the second programming state (out of the first, second, and third programming states) passes; and The data mode stored in the page buffer corresponding to the memory cell whose threshold voltage is between the third auxiliary verification voltage and the third primary verification voltage in the memory cell to be programmed into the third programming state is changed to the first data mode corresponding to the first programming state.

7. The method according to claim 6, further comprising the following step: Receive programming recovery command; Determine whether the second programming state has passed verification; and The auxiliary verification data pattern corresponding to the third programming state is stored in the page buffer.

8. The method according to claim 1, wherein, The semiconductor memory device includes a multi-level cell (MLC), and the step of changing at least one auxiliary voltage verification result information of a threshold voltage state that has failed programming to at least one data mode of a threshold voltage state that has passed programming in response to the programming suspension command includes the following steps: Determine whether the verification operation for the second programming state (out of the first, second, and third programming states) passes; and The data mode stored in the page buffer corresponding to the memory cell whose threshold voltage is between the third secondary verification voltage and the third primary verification voltage in the memory cell to be programmed into the third programming state is changed to the second data mode corresponding to the second programming state.

9. The method according to claim 8, further comprising the following step: Receive programming recovery command; Determine whether the second programming state has passed verification; and The auxiliary verification data pattern corresponding to the third programming state is stored in the page buffer.

10. The method according to claim 1, wherein, The semiconductor memory device includes a three-level cell (TLC), and the step of changing at least one auxiliary voltage verification result information of a threshold voltage state that has failed programming to at least one data mode of a threshold voltage state that has passed programming in response to the programming suspension command includes the following steps: Determine whether the verification operation for the k-th programming state (from the first to the seventh programming state) passes; and The data pattern stored in the page buffer corresponding to the memory cell whose threshold voltage is between the x-th secondary verification voltage and the x-th primary verification voltage in the memory cell to be programmed to the x-th programming state is changed to the k-th data pattern corresponding to the k-th programming state. Where k is an integer greater than 1 and less than or equal to 6, and x is an integer greater than k and less than or equal to 7.

11. The method of claim 10, further comprising the step of: Receive programming recovery command; Determine whether the k-th programming state has passed verification; and The auxiliary verification data pattern corresponding to the xth programming state is stored in the page buffer.

12. The method according to claim 1, wherein, The semiconductor memory device includes a memory cell for each storing N bits, and the step of changing at least one auxiliary voltage verification result information in the unprogrammed threshold voltage state to at least one data mode in the programmed threshold voltage state in response to the programming suspension command includes the following steps: Determine the first programming state up to the (2) N -1) Whether the verification operation of the k-th programming state in the programming state passed; and The data pattern stored in the page buffer corresponding to the memory cell whose threshold voltage is between the x-th secondary verification voltage and the x-th primary verification voltage in the memory cell to be programmed to the x-th programming state is changed to the k-th data pattern corresponding to the k-th programming state. Where k is greater than 1 and less than or equal to 2. N An integer of -2, where x is greater than k and less than or equal to 2. N An integer of -1.

13. The method of claim 12, further comprising the step of: Receive programming recovery command; Determine whether the k-th programming state has passed verification; and The auxiliary verification data pattern corresponding to the xth programming state is stored in the page buffer.

14. A method of operating a semiconductor memory device, the semiconductor memory device comprising memory cells storing N bits each, the method comprising the steps of: Receive programming recovery command; Determine the first programming state up to the (2) N -1) Whether the k-th programming state in the programming state has passed verification; and Identify the page buffer corresponding to the memory cell in the memory cell to be programmed to the x-th programming state, where the threshold voltage is between the x-th secondary verification voltage and the x-th primary verification voltage, and store the secondary verification data pattern corresponding to the x-th programming state in the identified page buffer. Where N is an integer greater than 1, and k is a number greater than 1 and less than or equal to 2. N An integer of -2, where x is greater than k and less than or equal to 2. N An integer of -1.

15. The method according to claim 14, wherein, The auxiliary verification data mode is a data mode that can distinguish memory cells with threshold voltages between the xth auxiliary verification voltage and the xth primary verification voltage from the remaining memory cells.

16. The method of claim 14, further comprising the step of: The programming operation resumes after the auxiliary verification data pattern corresponding to the xth programming state is stored in the identified page buffer.

17. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array comprising multiple memory cells, each storing N bits; Peripheral circuitry that performs programming operations on the memory cell array; as well as Control logic that controls the programming operations of the peripheral circuitry. Specifically, when a programming suspension command is received during programming operations on a selected memory cell among the plurality of memory cells, the control logic controls the peripheral circuitry to maintain the connection between the first programming state and the (2)th programming state. N -1) The auxiliary voltage verification result information corresponding to the xth threshold voltage state that has not been programmed in the programming state is changed to be consistent with the first programming state to the (2)th threshold voltage state. N -1) The k-th data pattern corresponding to the k-th programming state in the programming state. Where N is an integer greater than 1, and k is a number greater than 1 and less than or equal to 2. N An integer of -2, where x is greater than k and less than or equal to 2. N An integer of -1.

18. The semiconductor memory device according to claim 17, wherein, The control logic controls the peripheral circuitry to identify a first page buffer corresponding to a memory cell between the x-th primary verification voltage and the x-th secondary verification voltage corresponding to the x-th threshold voltage state, and changes the data pattern stored in the identified first page buffer to the k-th data pattern.

19. The semiconductor memory device of claim 18, wherein, When a programming recovery command is received, the control logic controls the peripheral circuit to identify the first page buffer and store the auxiliary verification data pattern corresponding to the xth programming state in the first page buffer.

20. The semiconductor memory device of claim 19, wherein, After storing the secondary verification data pattern corresponding to the xth programming state in the first page buffer, the control logic controls the peripheral circuitry to resume the programming operation on the selected memory cell using the xth secondary verification voltage and the xth primary verification voltage.

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