Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a page buffer circuit, a pass / fail determination circuit, and an operation control circuit. The page buffer circuit can include a sense latch circuit and a data latch circuit. The pass / fail determination circuit determines a pass / fail of a memory cell. The operation control circuit controls a program operation and a program verify operation to be performed on the memory cell.

Description

Technical Field

[0001] Various embodiments generally relate to a semiconductor memory device and a method of operating the same, and more specifically, to a semiconductor memory device and a method of operating the same capable of performing programming verification operations on a plurality of memory cells. Background Technology

[0002] Semiconductor memory devices are generally classified into volatile memory devices and non-volatile memory devices. Both volatile and non-volatile memory devices can perform data processing operations that receive power and store or output the stored data. Volatile memory devices have high data processing speeds but require continuous power to maintain the stored data. Conversely, non-volatile memory devices do not require continuous power to maintain the stored data, but their data processing speeds are lower.

[0003] Recent advancements in semiconductor memory device manufacturing processes and design technologies have significantly reduced the data processing speed difference between volatile and non-volatile memory devices. Consequently, considerable attention has recently been paid to non-volatile memory devices that do not require the power needed to retain the data stored within them.

[0004] A representative example of a non-volatile memory device may include a NAND flash memory device having a string structure in which multiple memory cells are connected in series. The memory cells of a NAND flash memory device all include a floating gate. Therefore, by injecting electrons into or emitting electrons from the floating gate using the Fowler-Nordheim tunneling method, the memory cell can store logic "high" data or logic "low" data.

[0005] Non-volatile memory devices, including NAND flash memory devices, perform programming operations to store data in memory cells and perform read operations to output the data stored in the memory cells. Furthermore, the non-volatile memory device performs an erase operation to erase the data stored in the memory cells before the programming operation. Specifically, the programming operation is accompanied by a verification operation. The verification operation refers to the operation of verifying whether the expected data has been accurately stored in the memory cells through the programming operation. In the following text, for ease of description, the verification operation performed during the programming operation will be referred to as the "programming verification operation".

[0006] When a memory cell degrades significantly, it no longer stores data. Therefore, volatile memory devices perform pass / fail checks to detect whether each memory cell has passed or failed, and control circuitry based on the detection results. Summary of the Invention

[0007] In one embodiment, a semiconductor memory device may include: a page buffer circuit comprising: a sense latch circuit configured to sense data programmed into a memory cell by a programming operation based on a pre-verification voltage and a final verification voltage during a programming verification operation; a data latch circuit storing a programming verification result corresponding to the pre-verification voltage, wherein the pre-verification voltage has a voltage level lower than the final verification voltage; a pass / fail determination circuit configured to determine the pass / fail status of a memory cell based on the programming verification result; and an operation control circuit configured to control the programming operation and the programming verification operation based on the pass / fail determination result.

[0008] In one embodiment, an operation method of a semiconductor memory device may include the following steps: performing a programming operation on a memory cell; performing a programming pre-verification operation on the memory cell; updating a data latch circuit based on the programming verification result from the programming pre-verification operation; determining the pass / fail status of the memory cell based on the programming verification result stored in the data latch circuit; and skipping subsequent programming verification operations on the memory cell and ending the programming operation based on the result of the pass / fail determination step. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating the configuration of a semiconductor memory device according to one embodiment.

[0010] Figure 2 It is shown Figure 1 A block diagram of some of the internal components of a multi-page buffer circuit.

[0011] Figure 3 It is shown Figure 2 The first page contains the circuit diagram of the buffer circuit configuration.

[0012] Figure 4 It is shown Figure 2 and Figure 3 The first page contains a schematic diagram of the buffer circuit's operation.

[0013] Figure 5 It is shown Figure 1 A flowchart of the operation method of a semiconductor memory device. Detailed Implementation

[0014] The description in this disclosure is a description of the implementation of the structure and / or function. The scope of this disclosure should not be construed as limited to the implementations described in the specification. That is, the scope of this disclosure should be understood to include equivalents that can achieve the technical spirit, as implementations can be modified in various ways and can take various forms. Furthermore, the purposes or effects set forth in this disclosure do not imply that a particular implementation should include all purposes or effects or only such effects. Therefore, the scope of this disclosure should not be construed as being limited thereto.

[0015] The meanings of the terms described in this application should be understood as follows.

[0016] Terms such as “first” and “second” are used to distinguish one element from another, and the scope of this disclosure should not be limited by these terms. For example, a first element may be named a second element. Similarly, a second element may be named a first element.

[0017] The singular form should be understood to include the plural form unless otherwise expressly stated in the context. Terms such as “including” or “having” should be understood to indicate the presence of a specified feature, number, step, operation, element, component, or combination thereof, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0018] In each step, symbols (e.g., a, b, and c) are used for ease of description, and these symbols do not describe the order of the steps. These steps may be performed in a different order than described in the context, unless the context explicitly describes a specific order. That is, these steps may be performed in the order described, substantially simultaneously, or in the reverse order of the described order.

[0019] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. Terms defined in common dictionaries shall be interpreted as having the same meaning as in the context of the relevant art and shall not be interpreted as having an ideal or overly formal meaning unless expressly defined in the application.

[0020] Various implementations relate to a semiconductor memory device and a method of operating the same that minimizes programming verification operations.

[0021] According to this embodiment, the semiconductor memory device and its operation method can minimize programming verification operations, thereby reducing the overall programming operation time.

[0022] Figure 1This is a block diagram illustrating the configuration of a semiconductor memory device according to one embodiment.

[0023] Reference Figure 1 The semiconductor memory device may include a memory cell array circuit 1000, an operation driving circuit 2000, and an operation control circuit 3000.

[0024] The memory cell array circuit 1000 can be configured to store data. The memory cell array circuit 1000 may include multiple memory block circuits BK1 to BKn, where n is a natural number. Each of the multiple memory block circuits BK1 to BKn may include multiple memory cells for storing data. The multiple memory cells may have a string structure, where the memory cells are connected in series vertically. The multiple memory cells may be respectively connected to multiple word lines WL1 to WLn and multiple bit lines BL1 to BLm (where m is a natural number) to have a matrix structure. Although described below, the multiple word lines WL1 to WLn can be driven to a preset voltage by the word line driving circuit 2200 according to a programming operation, a read operation, an erase operation, or a verification operation. The multiple bit lines BL1 to BLm can be driven to the preset voltage according to the data stored in the memory cells or the data to be stored in the memory cells.

[0025] The operation drive circuit 2000 can be driven to perform programming, reading, erasing, or verification operations on selected memory cells of the memory cell array circuit 1000. The operation drive circuit 2000 may include a voltage generation circuit 2100, a word line drive circuit 2200, a multiple page buffer circuit 2300, a column decoding circuit 2400, a data input / output circuit 2500, and a pass / fail determination circuit 2600. The components included in the operation drive circuit 2000 will be described in detail below.

[0026] The voltage generation circuit 2100 can be configured to generate the required internal voltage V_INN for each of the programming, reading, erasing, and verification operations. Based on the voltage control signal CTR_V generated by the operation control circuit 3000, the voltage generation circuit 2100 can generate internal voltages V_INN with various voltage levels corresponding to each operation.

[0027] The word line driving circuit 2200 can be configured to selectively drive multiple word lines WL1 to WLn to an internal voltage V_INN generated by the voltage generation circuit 2100. The word line driving circuit 2200 can receive the internal voltage V_INN from the voltage generation circuit 2100 and can receive a drive address signal ADD_D from the operation control circuit 3000. The drive address signal ADD_D can be a signal used to selectively enable a corresponding word line among the multiple word lines WL1 to WLn. Therefore, the word line driving circuit 2200 can selectively enable multiple word lines WL1 to WLn based on the drive address signal ADD_D and the internal voltage V_INN, and can drive the enabled word lines to the corresponding internal voltage V_INN.

[0028] Although not shown in the figure, the word line driver circuit 2200 can also be connected to the drain select line, source select line, and common source line included in the memory cell array circuit 1000. Therefore, the word line driver circuit 2200 can drive each of the drain select line, source select line, and common source line to a preset internal voltage V_INN according to a programming operation, a read operation, an erase operation, or a verification operation.

[0029] As described above, multiple memory cells can be connected to multiple word lines WL1 to WLn, respectively. The word line selected during a programming, reading, erasing, or verifying operation and connected to the memory cell can be driven by the corresponding internal voltage V_INN. In the following description, for ease of description, the memory cell selected during a programming, reading, erasing, or verifying operation is defined as the "selected memory cell," and the word line connected to the selected memory cell is defined as the "selected word line." Furthermore, memory cells other than the selected memory cells are defined as "unselected memory cells," and the word lines connected to the unselected memory cells are defined as "unselected word lines." In other words, the selected word line connected to the selected memory cell during a programming, reading, erasing, or verifying operation can be driven by the corresponding internal voltage V_INN.

[0030] For example, during a programming operation, the word line driver circuit 2200 can apply a programming voltage, which is one of the internal voltages V_INN, to a selected word line among multiple word lines WL1 to WLn, and can apply a programming pass voltage to other unselected word lines, the programming pass voltage having a lower voltage level than the programming voltage. Furthermore, during a read operation, the word line driver circuit 2200 can apply a read voltage to a selected word line and can apply a read pass voltage to unselected word lines, the read pass voltage having a higher voltage level than the read voltage. Furthermore, during an erase operation, the word line driver circuit 2200 can apply a ground voltage to a selected word line. Furthermore, during a verification operation, the word line driver circuit 2200 can apply a verification voltage, which is one of the internal voltages V_INN, to a selected word line and can apply a verification pass voltage to unselected word lines, the verification pass voltage having a higher voltage level than the verification voltage.

[0031] Multiple page buffer circuits 2300 can be connected to the memory cell array circuit 1000 via multiple bit lines BL1 to BLm. The multiple page buffer circuits 2300 can be configured to transfer data to the multiple bit lines BL1 to BLm during programming operations. Furthermore, the multiple page buffer circuits 2300 can be configured to receive data from the multiple bit lines BL1 to BLm during read and verification operations. The multiple page buffer circuits 2300 can each be configured as multiple latch circuits. Each of the multiple latch circuits can perform circuit operations based on programming, read, or verification operations on input / output data based on the operation control signal CTR_OP generated by the operation control circuit 3000.

[0032] The column decoding circuit 2400 can be configured to control the transmission path of input / output data. The column decoding circuit 2400 can receive data to be output to an external device from multiple page buffer circuits 2300, and can receive data to be input to a device within a semiconductor memory device from the data input / output circuit 2500. Furthermore, the column decoding circuit 2400 can receive a selection address signal ADD_S from the operation control circuit 3000, and can control the transmission path of input / output data. The selection address signal ADD_S can be a signal used to select a corresponding bit line among multiple bit lines BL1 to BLm.

[0033] The data input / output circuit 2500 can be configured to control the input / output of the internal data signal DAT_INN and the external data signal DATA_EXT. The internal data signal DAT_INN can include data input / output within the semiconductor memory device. The external data signal DAT_EXT can include data input / output outside the semiconductor memory device. The data input / output circuit 2500 can perform data input / output operations based on the input / output control signal CTR_IO generated by the operation control circuit 3000. For example, during a programming operation, the data input / output circuit 2500 can output the external data DAT_EXT received from the host device or control device as the internal data DAT_INN based on the input / output control signal CTR_IO. Furthermore, during a read operation, the data input / output circuit 2500 can output the internal data DAT_INN received from the column decoding circuit 2400 as the external data DAT_EXT based on the input / output control signal CTR_IO.

[0034] The pass / fail determination circuit 2600 can be configured to determine the pass / fail status of a memory cell in the memory cell array circuit 1000 based on the programming verification result of the data programmed into the memory cell array circuit 1000. The pass / fail determination circuit 2600 can generate a pass / fail result signal P / F corresponding to the programming verification result. The pass / fail determination circuit 2600 can transmit the pass / fail result signal P / F to the operation control circuit 3000.

[0035] The operation control circuit 3000 can be configured to control the voltage generation circuit 2100, word line driving circuit 2200, multiple page buffer circuit 2300, column decoding circuit 2400, data input / output circuit 2500, and pass / fail determination circuit 2600 included in the operation drive circuit 2000. For example, the operation control circuit 3000 can generate a voltage control signal CTR_V for controlling the voltage generation circuit 2100 based on a command signal CMD and an address signal ADD input via a host device or control device. Furthermore, the operation control circuit 3000 can generate a drive address signal ADD_D provided to the word line driving circuit 2200, an operation control signal CTR_OP for controlling the multiple page buffer circuit 2300, a selection address signal ADD_S for controlling the column decoding circuit 2400, and an input / output control signal CTR_IO for controlling the data input / output circuit 2500. The operation control circuit 3000 can generate various signals to control the overall operation of the semiconductor memory device. Furthermore, the operation control circuit 3000 can control the programming operation and the programming verification operation based on the pass / fail result signal P / F provided by the pass / fail determination circuit 2600.

[0036] Figure 2 It is shown Figure 1 A block diagram of some of the internal components of the multiple page buffer circuit 2300.

[0037] Reference Figure 2 Multiple page buffer circuits 2300 can be configured to store data based on the operation control signal CTR_OP according to programming operations, read operations, and verification operations. The multiple page buffer circuits 2300 may include first page buffer circuits 210_1 to m-th page buffer circuits 210_m, respectively connected to multiple bit lines BL1 to BLm. In the following description, for ease of description, the first page buffer circuit 210_1 connected to the first bit line BL1 will be described representatively among the first page buffer circuits 210_1 to the m-th page buffer circuit 210_m.

[0038] The first page buffer circuit 210_1 can be connected to the first bit line BL1 and can be configured to store data corresponding to programming, reading, or verification operations. The first page buffer circuit 210_1 may include a sense latch circuit 211 and multiple data latch circuits 212. In the following description, for ease of description, programming and verification operations in various operations of a semiconductor memory device will be described representatively.

[0039] The sense latch circuit 211 can be configured to store data transmitted via the first bit line BL1 during a programming verification operation. Based on the data transmitted via the first bit line BL1, the sense latch circuit 211 can either retain the data stored therein or invert the data and store the inverted data. The programming verification operation may include a programming pre-verification operation and a programming final verification operation. Therefore, the sense latch circuit 211 can sense data based on a pre-verification voltage during the programming pre-verification operation and can sense data based on a final verification voltage during the programming final verification operation. The pre-verification voltage may have a lower voltage level than the final verification voltage.

[0040] Multiple data latch circuits 212 can be configured to store programming verification results during a programming verification operation. According to this embodiment, the semiconductor memory device can store programming verification results corresponding to a pre-verification voltage in one or more of the multiple data latch circuits 212. Although described again below, Figure 1 The operation control circuit 3000 can control programming and programming verification operations based on programming verification results stored in multiple data latch circuits 212. In short, the operation control circuit 3000 can skip programming verification operations on memory cells that have already been determined to pass in response to a pre-verification voltage. Therefore, the semiconductor memory device can minimize programming verification operations, thereby reducing the overall programming operation time.

[0041] Multiple data latch circuits 212 can be configured to store the programmed verification results corresponding to the final verification voltage and the pre-verification voltage. The number of data latch circuits 212 can be designed differently depending on the amount of data distributed in the memory cells.

[0042] For reference, based on the number of data distributions stored in a memory cell during programming operations, the memory cell of a non-volatile memory device is defined as a single-level cell, a multi-level cell, a three-level cell, a four-level cell, etc. A single-level cell has two data distributions corresponding to either logic "high" or logic "low" data in response to a single bit. A multi-level cell has four data distributions corresponding to two bits, a three-level cell has eight data distributions corresponding to three bits, and a four-level cell has 16 data distributions corresponding to four bits. Therefore, when the number of data distributions stored in the memory cell is eight, three data latch circuits 212 can be provided.

[0043] The first page buffer circuit 210_1 may include a verification latch circuit 213.

[0044] The verification latch circuit 213 can be configured to store programming verification results corresponding to the pre-verification voltage and the final verification voltage during the programming verification operation. As described above, multiple data latch circuits 212 can store programming verification results during the programming verification operation. In this case, the verification latch circuit 213 can store the programming verification result before the corresponding programming verification result is stored in the multiple data latch circuits 212. The verification latch circuit 213 can receive the programming verification result from the sensing latch circuit 211. Furthermore, the verification latch circuit 213 can receive the programming verification result from the sensing node SO (see below), which will be described later. Figure 3 The program verification results are received without using the sensing latch circuit 211. In other words, during the program verification operation, the program verification results corresponding to the pre-verification voltage and the final verification voltage can be stored in the verification latch circuit 213. The verification latch circuit 213 can transfer the stored program verification results to multiple data latch circuits 212, and can update the multiple data latch circuits 212 according to the program verification results.

[0045] According to this embodiment, a semiconductor memory device can use the verification latch circuit 213 to update the programming verification results corresponding to the pre-verification voltage in a plurality of data latch circuits 212.

[0046] Figure 3 It is shown Figure 2The circuit diagram shows the circuit configuration of the first page buffer circuit 210_1. For ease of description, the case of setting up three data latch circuits 212 is used as an example. In other words, multiple data latch circuits 212 may include the first data latch circuit 212_1 to the third data latch circuit 212_3.

[0047] Reference Figure 3 The first page buffer circuit 210_1 may include a sensing latch circuit 211, a first data latch circuit 212_1 to a third data latch circuit 212_3 serving as multiple data latch circuits, a verification latch circuit 213, a bit line connection circuit 214, and a data sensing circuit 215. Prior to the description, it can be based on... Figure 1 The operation control circuit 3000 generates an operation control signal CTR_OP to control the first page buffer circuit 210_1. In other words, multiple control signals used to control the first page buffer circuit 210_1 can be included in the operation control signal CTR_OP.

[0048] The sense latch circuit 211 can be configured to sense and store data transmitted via the first bit line BL1. The sense latch circuit 211 can store data transmitted via the first bit line BL1 based on the sense reset signal SRST and the sense set signal SSET.

[0049] More specifically, the sense latch circuit 211 may include a fifth PMOS transistor P5 and a sixth NMOS transistor N6 connected in series between the core voltage terminal VCORE and the ground voltage terminal VSS. The sense latch circuit 211 may also include a sixth PMOS transistor P6 and a seventh NMOS transistor N7 connected in series between the core voltage terminal VCORE and the ground voltage terminal VSS. The gates of the fifth PMOS transistor P5 and the sixth NMOS transistor N6 may be commonly connected to an auxiliary sensing node QS_N, which in turn is connected to the sixth PMOS transistor P6 and the seventh NMOS transistor N7. The gates of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 may be commonly connected to a main sensing node QS, which in turn is connected to the fifth PMOS transistor P5 and the sixth NMOS transistor N6.

[0050] The sense latch circuit 211 may include an eighth NMOS transistor N8 and a ninth NMOS transistor N9 connected in series between the main sense node QS and the ground voltage terminal VSS. The eighth NMOS transistor N8 can receive a sense reset signal SRST through its gate, and the ninth NMOS transistor N9 can receive a page reset signal PBRST through its gate. The sense latch circuit 211 may include a tenth NMOS transistor N10 located between the auxiliary sense node QS_N and the first common node COM1. The tenth NMOS transistor N10 can receive a sense set signal SSET through its gate. Therefore, the sense latch circuit 211 can temporarily store programming verification data corresponding to the programming verification result based on the sense reset signal SRST and the sense set signal SSET during the programming verification operation.

[0051] The first data latch circuit 212_1 to the third data latch circuit 212_3 can be configured to store programming verification data transmitted from the sensing latch circuit 211. The first data latch circuit 212_1 to the third data latch circuit 212_3 can be connected together to the sensing node SO.

[0052] For reference, the first data latch circuit 212_1 can store programming verification data corresponding to the most significant bit (MSB), the second data latch circuit 212_2 can store programming verification data corresponding to the middle significant bit (CSB), and the third data latch circuit 212_3 can store programming verification data corresponding to the least significant bit (LSB). Depending on the operation, the third data latch circuit 212_3 can be used as a cache.

[0053] In other words, during a read operation, the third data latch circuit 212_3 can store the data stored in the first data latch circuit 212_1, the second data latch circuit 212_2, and the verification latch circuit 213, and transmit the stored data to the column decoding circuit 2400 (see...). Figure 1 Furthermore, during programming operations, the third data latch circuit 212_3 can store data to be stored in selected memory cells and can transmit the stored data to the sensing node SO. Additionally, during programming verification operations, the third data latch circuit 212_3 can receive programming verification data stored in the first data latch circuit 212_1 and the second data latch circuit 212_2, store the received data therein, and output the stored data to the pass / fail determination circuit 2600 (see...). Figure 1 ).

[0054] The first data latch circuit 212_1 may include a seventh PMOS transistor P7 and an eleventh NMOS transistor N11 connected in series between the core voltage terminal VCORE and the ground voltage terminal VSS. The first data latch circuit 212_1 may also include an eighth PMOS transistor P8 and a twelfth NMOS transistor N12 connected in series between the core voltage terminal VCORE and the ground voltage terminal VSS. The gates of the seventh PMOS transistor P7 and the eleventh NMOS transistor N11 may be commonly connected to the first auxiliary data node Q1_N. The gates of the eighth PMOS transistor P8 and the twelfth NMOS transistor N12 may be commonly connected to the first main data node Q1.

[0055] The first data latch circuit 212_1 may include a thirteenth NMOS transistor N13 and a fourteenth NMOS transistor N14 connected in series between the sensing node SO and the ground voltage terminal VSS. The thirteenth NMOS transistor N13 may receive the first main data transmission signal TRAN1 through its gate, and the fourteenth NMOS transistor N14 may have a gate connected to the first main data node Q1. The first data latch circuit 212_1 may include a fifteenth NMOS transistor N15 and a sixteenth NMOS transistor N16 connected in series between the sensing node SO and the ground voltage terminal VSS. The fifteenth NMOS transistor N15 may receive the first auxiliary data transmission signal TRAN1_N through its gate, and the sixteenth NMOS transistor N16 may have a gate connected to the first auxiliary data node Q1_N.

[0056] The first data latch circuit 212_1 may include a seventeenth NMOS transistor N17 connected between the first main data node Q1 and the first common node COM1. The seventeenth NMOS transistor N17 may receive a first data reset signal RST1 through its gate. The first data latch circuit 212_1 may include an eighteenth NMOS transistor N18 connected between the first auxiliary data node Q1_N and the first common node COM1. The eighteenth NMOS transistor N18 may receive a first data set signal SET1 through its gate.

[0057] Therefore, the first data latch circuit 212_1 can store the programming verification data transmitted from the sensing latch circuit 211 based on the first main data transmission signal TRAN1 / first auxiliary data transmission signal TRAN1_N and the first data reset signal RST1 / first data set signal SET1.

[0058] Since the first data latch circuit 212_1, the second data latch circuit 212_2, and the verification latch circuit 213 have similar circuit configurations to each other, except for the input control signals, detailed descriptions of the second data latch circuit 212_2 and the verification latch circuit 213 will be omitted here. However, the second data latch circuit 212_2 may have a second main data node Q2 / second auxiliary data node Q2_N formed therein, and may store programming verification data based on the second main data transmission signal TRAN2 / second auxiliary data transmission signal TRAN2_N and the second data reset signal RST2 / second data set signal SET2. The verification latch circuit 213 may have a main verification node QM / auxiliary verification node QM_N formed therein, and may store the programming verification data transmitted from the sensing latch circuit 211 based on the third main data transmission signal TRAN3 / third auxiliary data transmission signal TRAN3_N and the third data reset signal RST3 / third data set signal SET3.

[0059] A twenty-fourth NMOS transistor N24 can be connected between the first common node COM1, which is jointly connected to the sensing latch circuit 211 and the first data latch circuit 212_1, and the ground voltage terminal VSS. A twenty-fifth NMOS transistor N25 can be connected between the second common node COM2, which is jointly connected to the second data latch circuit 212_2 and the verification latch circuit 213, and the ground voltage terminal VSS. The gates of the twenty-fourth NMOS transistor N24 and the twenty-fifth NMOS transistor N25 can be connected to the sensing node SO. Therefore, the twenty-fourth NMOS transistor N24 and the twenty-fifth NMOS transistor N25 can form a current path connected to the ground voltage terminal VSS based on the voltage level of the sensing node SO.

[0060] As described above, depending on the operation, the third data latch circuit 212_3 can be used as a cache. The third data latch circuit 212_3 may include a first PMOS transistor P1 and a first NMOS transistor N1 connected in series between the power supply voltage terminal VCCI and the ground voltage terminal VSS. The third data latch circuit 212_3 may also include a third PMOS transistor P3 and a second NMOS transistor N2 connected in series between the power supply voltage terminal VCCI and the ground voltage terminal VSS. The gates of the first PMOS transistor P1 and the first NMOS transistor N1 may be commonly connected to the auxiliary cache node QC_N. The gates of the third PMOS transistor P3 and the second NMOS transistor N2 may be commonly connected to the main cache node QC.

[0061] The third data latch circuit 212_3 may include a third NMOS transistor N3 located between the main cache node QC and the ground voltage terminal VSS. The third NMOS transistor N3 can receive a cache reset signal CRST through its gate. Therefore, the third data latch circuit 212_3 can perform a reset operation on the main cache node QC based on the cache reset signal CRST. The third data latch circuit 212_3 may include a fourth NMOS transistor N4 and a fifth NMOS transistor N5 connected in series between the auxiliary cache node QC_N and the ground voltage terminal VSS. The fourth NMOS transistor N4 can receive a first cache transfer signal TRANC through its gate, and the fifth NMOS transistor N5 can receive a second cache transfer signal TRANAPB through its gate. Therefore, the third data latch circuit 212_3 can store the programming verification data transmitted through the sensing node SO based on the first cache transfer signal TRANC and the second cache transfer signal TRANAPB.

[0062] Bit line connection circuit 214 can be configured to connect the first bit line BL1 and the current sensing node CSO. Bit line connection circuit 214 can connect the first bit line BL1 to the current sensing node CSO based on the bit line selection signal SEL_BL, so that data transmitted through the first bit line BL1 can be transmitted to the current sensing node CSO.

[0063] More specifically, the bit line connection circuit 214 may include a twenty-seventh NMOS transistor N27 and a twenty-eighth NMOS transistor N28 connected in series between the first bit line BL1 and the ground voltage terminal VSS. The twenty-seventh NMOS transistor N27 may receive the bit line selection signal SEL_BL through its gate, and the twenty-eighth NMOS transistor N28 may receive the bit line discharge signal BLDIS through its gate.

[0064] Bit line connection circuit 214 may include a twenty-ninth NMOS transistor N29 connected between a buffer voltage terminal VEXT_PB and the first bit line BL1. The twenty-ninth NMOS transistor N29 may receive an erase control voltage BL_BIAS through its gate. Bit line connection circuit 214 may include a thirtieth NMOS transistor N30 connected between the current sensing node CSO and a common node BLCM located between the twenty-seventh NMOS transistor N27 and the twenty-eighth NMOS transistor N28. The thirtieth NMOS transistor N30 may receive a bit line sensing signal PB_SENSE through its gate.

[0065] Therefore, the bit line connection circuit 214 can transmit the data transmitted through the first bit line BL1 to the current sensing node CSO based on the bit line selection signal SEL_BL and the bit line sensing signal PB_SENSE.

[0066] The data sensing circuit 215 can be configured to connect the current sensing node CSO and the sensing node SO. The data sensing circuit 215 can connect the current sensing node CSO to the sensing node SO based on the sensing control signal SA_SENSE, so that the data transmitted through the first bit line BL1 can be transmitted to the sensing node SO.

[0067] More specifically, the data sensing circuit 215 may include an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, and a thirty-first NMOS transistor N31 connected in series between the core voltage terminal VCORE and the current sensing node CSO. The eleventh PMOS transistor P11 may have a gate connected to the main sensing node QS, the twelfth PMOS transistor P12 may receive a precharge control signal SA_PRECH_N through its gate, and the thirty-first NMOS transistor N31 may receive a sensing control signal SA_SENSE through its gate. The data sensing circuit 215 may include a thirty-second NMOS transistor N32 located between the drain of the eleventh PMOS transistor P11 and the current sensing node CSO. The thirty-second NMOS transistor N32 may receive a sense amplifier connection signal SA_CSOC through its gate.

[0068] The data sensing circuit 215 may include a thirty-third NMOS transistor N33 and a thirty-fourth NMOS transistor N34 connected in series between the sensing node SO and the ground voltage terminal VSS. The thirty-third NMOS transistor N33 may receive the sensing amplifier discharge signal SA_DISCH through its gate, and the thirty-fourth NMOS transistor N34 may have a gate connected to the main sensing node QS.

[0069] Therefore, the data sensing circuit 215 can transmit the data transmitted through the current sensing node CSO to the sensing node SO based on the sensing control signal SA_SENSE and the sensing amplifier connection signal SA_CSOC.

[0070] The first page buffer circuit 210_1 can transmit data transmitted via the first bit line BL1 to the sensing node SO through the bit line connection circuit 214 and the data sensing circuit 215. For reference, the bit line connection circuit 214 and the data sensing circuit 215 can be defined as a "data transmission circuit" for transmitting data stored in the memory cell to the sensing node SO.

[0071] The first-page buffer circuit 210_1 may include a thirteenth PMOS transistor P13 for pre-charging the sensing node SO. The thirteenth PMOS transistor P13 may be connected between the core voltage terminal VCORE and the sensing node SO, and may receive a pre-charge signal PRECHSO_N through its gate. Therefore, the thirteenth PMOS transistor P13 may pre-charge the sensing node SO based on the pre-charge signal PRECHSO_N at a voltage level corresponding to the core voltage terminal VCORE.

[0072] The semiconductor memory device according to this embodiment can update the programming verification results in multiple data latch circuits 212 via the verification latch circuit 213 during a programming verification operation or specifically during a pre-programming verification operation. Furthermore, the pass / fail determination circuit 2600 (see...) Figure 1 Based on the programming verification results stored in multiple data latch circuits 212, a pass / fail result signal P / F can be generated for the corresponding memory cell.

[0073] Figure 4 It is shown Figure 2 and Figure 3 A schematic diagram of the operation of the first page buffer circuit 210_1 is shown. For ease of description, the case where the number of data distributed in the memory cells is 2 is used as an example. In other words, Figure 2 The multiple data latch circuits 212 may include two data latch circuits (i.e., a first data latch circuit 212_1 and a second data latch circuit 212_2). In Figure 4 In this context, the pre-verification voltage is represented by "V1", and the final verification voltage is represented by "V2". As mentioned above, the pre-verification voltage V1 can have a lower voltage level than the final verification voltage V2.

[0074] exist Figure 4 In this context, case (A) can correspond to the programmed pre-test operation.

[0075] Case (A) can represent data programmed into the memory cell at a voltage level higher than the pre-verification voltage V1 and lower than the final verification voltage V2. Therefore, the sensing latch circuit 211 can store the programming verification result corresponding to passing P based on the pre-verification voltage V1. The verification latch circuit 213 can receive the programming verification result corresponding to passing P and can store the received programming verification result. For example, the verification latch circuit 213 can transmit the programming verification result to the first data latch circuit 212_1. Then, the pass / fail determination circuit 2600 (see...) Figure 1 This can generate a pass / fail result signal P / F corresponding to the pass / fail result of P. Furthermore, the operation control circuit 3000 (see...) Figure 1The system can apply a preset programming pulse to the corresponding memory cell based on the pass / fail result signal P / F. Then, the operation control circuit 3000 can skip the subsequent programming verification operation of the corresponding memory cell.

[0076] By performing a programming pre-verification operation on memory cells containing data formed at a voltage level higher than the pre-verification voltage V1 and lower than the final verification voltage V2, the semiconductor memory device according to this embodiment can generate a pass / fail result P / F corresponding to a pass P. The semiconductor memory device can skip subsequent programming verification operations on memory cells that have already been determined to pass. Therefore, the semiconductor memory device can reduce the overall programming operation time by the time spent performing the skipped programming verification operations.

[0077] exist Figure 4 In this context, case (B) can correspond to the final programming verification operation. The final programming verification operation can include the pre-programming verification operation corresponding to case (A).

[0078] Case (B) can indicate that the data programmed into the memory cell is formed at a voltage level lower than the pre-verification voltage V1. Therefore, the sensing latch circuit 211 can store the programming verification result corresponding to failure F based on the pre-verification voltage V1 through the programming pre-verification operation. For example, the verification latch circuit 213 can receive the programming verification result corresponding to failure F and can transmit the received programming verification result to the second data latch circuit 212_2. Then, the pass / fail determination circuit 2600 (see...) Figure 1 This can generate a pass / fail result signal P / F corresponding to failure F. Operation control circuit 3000 (see...) Figure 1 A preset programming pulse can be applied to the corresponding memory cell based on the failure voltage.

[0079] The corresponding memory cell can have data formed at a voltage level higher than the final verification voltage V2 according to a preset programming pulse. Therefore, the sensing latch circuit 211 can store the programming verification result corresponding to passing P based on the final verification voltage V2 through the programming final verification operation. The second data latch circuit 212_2 can store the programming verification result corresponding to passing P that has been transmitted by the verification latch circuit 213. Then, the pass / fail determination circuit 2600 (see...) Figure 1 This can generate a pass / fail result signal P / F corresponding to the pass / fail result of P. Operation control circuit 3000 (see...) Figure 1 A preset programming pulse can be applied to the corresponding memory cell based on the voltage V_PASS.

[0080] Semiconductor memory devices can complete the programming operation through a programming pre-verification operation (A) and a programming final verification operation (B). As described above, semiconductor memory devices can skip subsequent programming verification operations on memory cells determined to pass P during the programming pre-verification operation (A). Therefore, semiconductor memory devices can reduce the programming completion time by reducing the time spent performing the skipped programming verification operations.

[0081] exist Figure 4 In this embodiment, the verification latch circuit 213 is used to store the programming verification result in the first data latch circuit 212_1 and the second data latch circuit 212_2 as an example. However, when storing the programming verification result in the first data latch circuit 212_1 and the second data latch circuit 212_2, the semiconductor memory device according to this embodiment can... Figure 3 The sensing node SO receives the programming verification result without using the verification latch circuit 213. At this time, the programming verification result stored in the sensing latch circuit 211 can have already been transmitted to the sensing node SO.

[0082] Figure 5 It is shown Figure 1 A flowchart of the operation method of a semiconductor memory device 500.

[0083] Reference Figure 5 The operation method 500 of the semiconductor memory device may include the steps of performing a programming operation 510, performing a programming pre-verification operation 520, updating the data latch circuit 530, determining pass / fail 540, and skipping the programming verification operation and ending the programming operation 550.

[0084] Step 510 of performing the programming operation may include performing a programming operation on the memory cell. Step 510 of performing the programming operation may be performed by the recipient. Figure 1 The operation control circuit 3000 controls the operation drive circuit 2000 to perform the operation. The operation drive circuit 2000 can perform programming operations to store data in the various memory cells included in the memory cell array circuit 1000.

[0085] Step 520, which involves performing a programming pre-verification operation, may include performing a programming pre-verification operation on the memory cell. (Refer to the above...) Figure 4 The semiconductor memory device can perform a pre-verification operation on the memory cells by using a pre-verification voltage V1.

[0086] Step 530 of updating the data latch circuit may include, for example, updating the first data latch circuit 212_1 based on the programming verification result of the pre-verification operation. (Refer to the above...) Figure 4The first data latch circuit 212_1 can store the programming verification result corresponding to the pre-verification voltage V1. At this time, the first data latch circuit 212_1 can be updated using the verification latch circuit 213. This can be achieved by using a sensing node SO (see...). Figure 3 The first data latch circuit 212_1 is updated instead of the verification latch circuit 213.

[0087] Step 530, updating the data latch circuit, can be performed during the programming operation period for memory cells other than the corresponding memory cell. For example, the update operation for the memory cell can be separated from the programming operation for the memory cell, but the update period can overlap with the programming operation period, thereby reducing the programming operation time.

[0088] The pass / fail determination step 540 may include determining the pass / fail of a memory cell based on the programming verification result stored in the first data latch circuit 212_1. The pass / fail determination step 540 may be performed by… Figure 1 The pass / fail determination circuit 2600 performs this operation. The pass / fail determination circuit 2600 can determine the pass / fail of a memory cell based on the programming verification result stored in the first data latch circuit 212_1.

[0089] Step 550, which skips the programming verification operation and ends the programming operation, may include skipping the programming verification operation on the memory cell and ending the programming operation based on the result of step 540, which determines pass / fail. Step 550, which skips the programming verification operation and ends the programming operation, may be performed by the recipient... Figure 1 The operation control circuit 3000 controls the operation drive circuit 2000 to execute the operation. The operation drive circuit 2000 can apply a preset programming pulse to the corresponding memory cell based on the pass / fail result signal P / F, and skip the subsequent programming verification operation. The operation drive circuit 2000 can also terminate the programming operation on the corresponding memory cell.

[0090] According to this embodiment, the semiconductor memory device can update the programming verification result in the data latch circuit through a pre-verification operation on the memory cell. Furthermore, the semiconductor memory device can skip the programming verification operation on the corresponding memory cell based on the updated programming verification result, thereby reducing programming operation time.

[0091] While various embodiments have been described above, those skilled in the art should understand that the described embodiments are merely examples. Therefore, the semiconductor memory devices and operating methods described herein should not be limited to the described embodiments.

[0092] Cross-references to related applications

[0093] This application claims priority to Korean Application No. 10-2022-0029342, filed on March 8, 2022, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Page buffer circuit, the page buffer circuit comprising: A sensing latch circuit senses data programmed into a memory cell by a programming operation based on a pre-verification voltage and a final verification voltage during a programming verification operation; and A data latch circuit stores a programming verification result corresponding to the pre-verification voltage, wherein the pre-verification voltage has a voltage level lower than the final verification voltage; Pass / fail determination circuitry, which determines the pass / fail status of the memory cell based on the programming verification result; and An operation control circuit that controls the programming operation and the programming verification operation based on a pass / fail determination result.

2. The semiconductor memory device according to claim 1, wherein, The operation control circuit applies a preset programming pulse to the memory cell based on the pass / fail determination result corresponding to the pre-verification voltage, and then skips subsequent programming verification operations.

3. The semiconductor memory device according to claim 1, wherein, The programming verification operation includes a programming pre-verification operation corresponding to the pre-verification voltage and a programming final verification operation corresponding to the final verification voltage.

4. The semiconductor memory device of claim 1, further comprising a verification latch circuit that stores the programming verification result corresponding to the pre-verification voltage during the programming verification operation and transmits the programming verification result to the data latch circuit to update the programming verification result.

5. The semiconductor memory device of claim 1, further comprising a data transmission circuit that transmits data stored in the memory cell to a sensing node connected to the data latch circuit. in, The data latch circuit receives the programming verification result through the sensing node.

6. The semiconductor memory device according to claim 1, wherein, The data latch circuit includes multiple data latch circuits corresponding to the number of data distributions stored in the memory unit, and The multiple data latching circuits are all connected to the sensing node.

7. The semiconductor memory device of claim 1, further comprising a cache latch circuit, wherein the cache latch circuit receives the programming verification result stored in the data latch circuit during the programming verification operation, stores the received programming verification result, and outputs the stored programming verification result to the pass / fail determination circuit.

8. A method of operating a semiconductor memory device, the method comprising the following steps: Perform programming operations on memory cells; Perform a programming pre-verification operation on the memory cell; The data latch circuit is updated based on the programming verification results from the pre-verification operation; The pass / fail of the memory cell is determined based on the programming verification result stored in the data latch circuit; as well as Based on the result of determining that the pass / fail step is passed, the subsequent programming verification operation for the memory cell is skipped and the programming operation is terminated.

9. The operating method according to claim 8, further comprising the step of performing a final programming verification operation on the memory cell.

10. The operating method according to claim 9, wherein, The final verification operation of the program is performed based on the final verification voltage, and The programming pre-verification operation is performed based on a pre-verification voltage, which has a voltage level lower than the final verification voltage.

11. The operating method according to claim 8, wherein, The steps for updating the data latch circuit include the following: The programming verification result is stored in the sensing latch circuit; The programming verification result stored in the sensing latch circuit is stored in the verification latch circuit; and The programming verification result stored in the verification latch circuit is stored in the data latch circuit.

12. The operating method according to claim 8, wherein, The steps for updating the data latch circuit include the following: The programming verification result is stored in the sensing latch circuit; and The programming verification result stored in the sensing latch circuit is stored in the data latch circuit through the sensing node.

13. The operating method according to claim 8, wherein, The step of updating the data latch circuit is performed during the programming operation period of memory cells other than the memory cells mentioned above.

14. The operating method according to claim 8, further comprising the following steps: The programming verification result is stored in a cache latch circuit and provided to the pass / fail step.

15. The operating method according to claim 8, wherein, The steps to skip the subsequent programming verification operation and end the programming operation include the following steps: Apply a preset programming pulse to the memory cell; Skip the subsequent programming verification operation on the memory cell; and The programming operation on the memory cell is terminated.

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