High-voltage low-damping oscillation soft recovery diode and manufacturing method

Abstract

This invention, entitled "A High-Voltage, Low-Damping Oscillating Soft Recovery Diode and Its Manufacturing Method," uses an N-region as a substrate and includes an outer P+ ring at the anode, an anode P+ block, a P- buffer layer, an outer N-buffer layer at the cathode, an N-buffer layer block ring, an outer N+ ring at the cathode, an N+ region at the cathode, and a cathode P+ block. The N-region has N-buffer layer blocks and N-buffer layer rings uniformly disposed on the cathode K-side. High-density outer N+ rings, cathode N+ regions, and cathode P+ blocks are alternately disposed on the N-buffer layer ring, N-buffer layer blocks, and N-region. The N+ regions overlap and surround the N-buffer layer, and the N-buffer layer blocks surround the cathode P+ blocks. The cathode P+ blocks and cathode N+ regions are isolated by the N-buffer layer. A P-buffer layer is disposed between the N-region and the anode P+ block. The high-voltage diode produced by this invention exhibits higher reverse blocking voltage, ultra-soft reverse recovery characteristics, and lower reverse recovery damping oscillation. The outer N-buffer layer ring at the cathode improves resistance to dynamic avalanche and provides higher reliability.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor diode design and manufacturing technology, and in particular to a high-voltage, low-damping oscillating soft recovery diode and its manufacturing method. Background Technology

[0002] Traditional power semiconductor soft recovery diodes, such as Figure 1 As shown, PIN diodes are commonly formed by thinning the N-region thickness to reduce the base transit time of charge carriers. This is achieved through electron irradiation, proton irradiation, or heavy metal diffusion to reduce the minority carrier lifetime in the base region. Although this method reduces the reverse recovery time, the recovery characteristics are relatively 'hard' (i.e., the softness factor S is small). Reverse recovery is prone to generating high reverse voltage or damped oscillations in the circuit, which can damage the device. For high-voltage (≥3000V) soft recovery diodes, the effect of reducing reverse recovery time and reverse voltage is limited. If the minority carrier lifetime in the base region is further reduced, the reverse recovery softness and on-state voltage drop will continue to deteriorate.

[0003] The die structure of the SIOD fast soft recovery diode is adopted, such as... Figure 2 As shown, the surface of its anode P region is composed of high-concentration impurity P+ regions, and its cathode region is composed of multiple strip-shaped high-concentration N+ blocks. A narrow strip-shaped Schottky region is formed between two adjacent N+ regions. The N- thickness is limited by the punch-through voltage and cannot be too thin. In this structure, the Schottky region (the contact area between the N- layer and the metal) provides a hole extraction channel. Under high voltage, a large number of charge carriers accumulate at the N+ high-low junction. The N+ layer blocks the holes. Although the Schottky region provides a hole extraction channel, the holes still need to pass through a relatively wide low-doped N- layer, resulting in a long extraction time and the base region easily storing a large amount of charge. During reverse recovery, high reverse voltage and strong damped oscillations are easily generated. The higher the voltage, the thicker the N- layer, and the poor the recovery characteristics.

[0004] A diode die structure employing a self-regulating emission efficiency (SPEED) anode and a field-pumped charge (FCE) cathode, such as... Figure 3 As shown, its anode region consists of low-concentration P-type impurities and multiple uniformly distributed high-concentration P+ blocks, the base region consists of a low-concentration doped N-type substrate and an N-buffer layer, and the cathode region consists of a high-concentration impurity N+ region and a high-concentration P+ block. The low-concentration P-region on the anode side increases the electron throughput speed during reverse recovery of the diode, and the cathode P+ blocks provide a hole extraction channel, which can significantly improve the diode recovery softness factor. The N-buffer layer can also reduce the wafer thickness and reduce the base transit time of charge carriers. However, under high reverse voltage, due to the influence of the N-buffer layer and the high-concentration N+ region charge carriers, high reverse voltage and strong damped oscillations are easily generated during reverse recovery. The higher the reverse voltage, the more severe the damped oscillations. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention proposes a high-voltage, low-damping, oscillating soft-recovery diode structure with superior reverse recovery characteristics. Diodes manufactured using this structure not only improve the reverse blocking voltage and utilize the thinnest wafer thickness, but also exhibit shorter reverse recovery time and softer diode recovery characteristics, suppressing low-damping oscillations in recovery current and voltage. This can meet the pulse freewheeling requirements of high-voltage semiconductor devices above 6500V.

[0006] This invention provides a high-voltage, low-damping, oscillating soft recovery diode and its manufacturing method. The technical problem it solves is how to ensure that the reverse recovery characteristics of the diode are softened and how to reduce damping oscillations at high reverse voltage.

[0007] The technical solution of this invention is: a high-voltage, low-damping, oscillating soft-recovery diode, characterized in that: an N-region serves as the substrate, comprising an outer P+ ring of the anode, an anode P+ block, a P-buffer layer, an outer N-buffer layer ring of the cathode, an N-buffer block, an outer N+ ring of the cathode, a cathode N+ region, and a cathode P+ block; the N-region has N-buffer blocks and N-buffer layer rings uniformly disposed on the cathode K side, and high-concentration outer N+ rings, cathode N+ regions, and cathode P+ blocks are alternately disposed on the N-buffer layer ring, N-buffer blocks, and N-region, with N+ regions overlapping and surrounding N-buffer blocks, and N-buffer blocks surrounding cathode P+ blocks, with the cathode P+ blocks and cathode N+ regions isolated by N-buffer blocks; a P-buffer layer is disposed between the N-region and the anode P+ block, and the anode P+ blocks are evenly distributed on the surface of the anode P-buffer layer, with the outer P+ ring of the anode, the anode P+ block, and the P-buffer layer between the anode P+ blocks constituting the anode region.

[0008] The technical solution of the present invention can also be: a high-voltage, low-damping, oscillating soft recovery diode, characterized in that: an N-region is used as a substrate, including an outer P+ ring of the anode, an anode P+ block, a P-buffer layer, an outer N-buffer layer ring of the cathode, an N-buffer block, an outer N+ ring of the cathode, a cathode N+ region, and a cathode P+ block; the N-region has N-buffer blocks and N-buffer layer rings uniformly disposed on the cathode K side; high concentrations of outer N+ rings of the cathode, cathode N+ regions, and cathode P+ blocks are alternately disposed on the N-buffer layer ring, N-buffer blocks, and N-region; the N+ regions overlap and surround the N-buffer blocks; the N-buffer blocks surround the cathode P+ blocks; the cathode P+ blocks and the cathode N+ regions are isolated by the N-buffer blocks; a P-buffer layer is disposed between the N-region and the anode P+ block; the anode P+ region forms an anode region on the surface of the P-buffer layer.

[0009] In the technical solution of this invention, the cathode N+ region occupies 50-90% of the total cathode area, the cathode P+ block occupies 10-50% of the total cathode area, the cathode N+ region uniformly surrounds the cathode P+ block, the N buffer block occupies 25-60% of the total cathode plane area, the N buffer block uniformly surrounds the cathode P+ block, and the anode P+ block occupies 20-60% of the total anode area. The cathode N+ region, N buffer block, cathode P+ block, and anode P+ are cylindrical or square prisms.

[0010] The surface concentration of the anode P+ region or P+ block in the technical solution of this invention is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 4–10 μm; the impurity concentration on the surface of the anode P-buffer layer is 0.2–6.0 × 10⁻⁶. 16 / cm 3 The junction depth is 80–100 μm or 100–130 μm; the surface impurity concentration of the cathode N+ ring and cathode N+ region is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 6-15 μm; the impurity concentration on the surface of the cathode P+ block is 0.4-5.0 × 10⁻⁶. 20 / cm 3 The junction depth is 3-8 μm, and the impurity concentration on the surface of the N buffer block and the N buffer layer ring at the outer end of the cathode is 1.0-4.5 × 10⁻⁶. 16 / cm 3 The depth is 25-40 μm; the cathode P+ block is cylindrical or square prism-shaped with a width of 20-60 μm, and the anode P+ block spacing is 100-600 μm, with the anode P+ block being cylindrical or square prism-shaped.

[0011] The technical solution of this invention is a manufacturing method for a high-voltage, low-damping oscillating soft recovery diode, comprising the following steps:

[0012] (1) Select type N <100> or <111> High-resistivity monocrystalline silicon wafers, used as N-substrate materials, have a thickness of 700–970 μm or 1050–1300 μm and a resistivity of 160–320 Ω•cm or 360–530 Ω•cm. The silicon wafers are chemically etched or phosphorus absorbed on both sides.

[0013] (2) P-diffusion: After cleaning the silicon wafer, aluminum is pre-deposited on both sides of the silicon wafer at a temperature of 950-1150℃. Then, aluminum impurities are diffused and oxidized at a low concentration on both sides at a temperature of 1200-1250℃ for 10-30 hours to form a symmetrical PNP-structure. The junction depth of the P-region is 80-100μm or 100-120μm, and the surface impurity concentration is 0.35-8.5×10⁻⁶. 16 / cm 3 ;

[0014] (3) Single-sided thinning: The cathode side of the silicon wafer is thinned to remove the single-sided diffused P-layer, forming a PN-structure;

[0015] (4) Oxidation: After cleaning, the silicon wafer is oxidized at a temperature of 1050-1200℃ for 3-6 hours.

[0016] (5) N-buffer layer photolithography: Photoresist is applied to the cathode surface of the silicon wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode window area;

[0017] (6) N-buffer layer diffusion: After cleaning the silicon wafer, phosphorus is pre-deposited or implanted at a low temperature on the cathode surface of the silicon wafer. The phosphorus pre-deposition temperature is 1000-1125℃, followed by high-temperature diffusion and oxidation at 1120-1240℃ for 6-12 hours to form a PNN structure. The impurity concentration on the surface of the N-buffer layer is 1.0-5.0×10⁻⁶. 16 / cm 3 The N-buffer layer has a depth of 20-30 μm.

[0018] (7) N+ photolithography: Photoresist is applied to the cathode surface of the silicon wafer, the N+ region is photolithographically etched, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode window area;

[0019] (8) N+ diffusion: After cleaning the silicon wafer, phosphorus is pre-deposited and diffused on the cathode surface of the silicon wafer. The phosphorus pre-deposition temperature is 1100-1150℃, followed by high-temperature diffusion and oxidation at 1150-1240℃ for 30-120 minutes to form a deep junction PN-NN+ structure. The impurity concentration on the cathode N+ surface is 0.6-9.0×10⁻⁶. 20 / cm 3 The cathode N+ depth is 3–10 μm;

[0020] (9) Photolithography of the cathode and anode P+ blocks: Photoresist is applied to both sides of the silicon wafer, exposed, and developed to remove the oxide layer in the cathode and anode window areas;

[0021] (10) P+ diffusion: After cleaning the silicon wafer, boron is sprayed onto the anode surface of the silicon wafer. After the anode P+ and cathode P+ diffuse, an anode P+ layer and a cathode P+ layer are formed. The depth of the anode P+ layer is 5-10 μm and the junction depth of the cathode P+ layer is 4-8 μm. The impurity concentration on the surface of the anode P+ layer is 0.6-8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration of the cathode P+ layer is 0.4–5.0 × 10⁻⁶. 20 / cm 3 The anode P+ is formed by high-concentration boron diffusion, and the cathode P+ is formed by reverse diffusion from the anode P+ boron source. The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source. Boron is sprayed onto the anode surface of the silicon wafer, and a constant surface source diffusion method is used.

[0022] Propulsion conditions: 1180~1200℃, N2=6L / min, O2=0.5L / min, time 60~120min;

[0023] (11) A metal conductive layer is deposited on both surfaces of a silicon wafer. The thickness of the metal conductive layer is 8-15 μm or 15-30 μm, forming the cathode metal layer of cathode K and the anode metal layer of anode A.

[0024] (12) Chip table design, the design structure is a double positive angle design or a double negative angle design;

[0025] (13) Chemical etching of the chip mesa, followed by passivation and adhesive coating of the mesa edge surface;

[0026] (14) Perform final product parameter testing on semiconductor chips.

[0027] In the technical solution of the present invention, a manufacturing method of a high voltage low damping oscillating soft recovery diode and a manufacturing method thereof, wherein between steps (13) and (14), the recovery time and recovery charge of the chip are controlled to the required values ​​by means of electron irradiation, or proton irradiation, or electron and proton irradiation.

[0028] The present invention has the following effects:

[0029] 1. The N buffer layer between N+ and N- in the cathode region is made into a comb-shaped structure. Since the doping concentration at the comb opening is low, the carrier concentration on the cathode side during reverse recovery can be increased, resulting in a small and long tail current. By adjusting the opening width of the comb cathode, the slope of the tail current can be reduced, suppressing current and voltage oscillations and significantly weakening the damped oscillation characteristics.

[0030] 2. A high-concentration cathode P+ block region is added between two adjacent N+ regions of the cathode. The cathode N+ and P+ blocks are isolated by a low-concentration impurity N buffer layer. The boundary between the N buffer layer and N+ is due to the overlap formed by the lateral diffusion of doping. The doping depth of the high-concentration cathode P+ block is relatively shallow, and it will not have a significant impact on the reverse cutoff and conduction characteristics. During reverse recovery, as the anode voltage gradually increases, the cathode P+ block injects holes into the N buffer layer or into the side N+ layer and N-. The injection efficiency increases with the increase of the reverse voltage across the device, resulting in a softer reverse recovery characteristic.

[0031] 3. The N+ ring and N buffer layer ring at the outer end of the cathode can realize the mesa compression depletion layer widening and reduce the N- thickness. The P+ ring at the outer end of the anode can ensure that the widening of the depletion layer in the P region will not be punched through, thus achieving the thinnest emitter thickness, realizing high blocking voltage, and reducing the total thickness of the silicon wafer by up to 40%. At the same time, it reduces the number of carriers in the base region or reduces the reverse recovery time and reverse recovery current of the diode.

[0032] 4. A narrow strip of low-concentration P-region is formed between two adjacent P+ blocks of the anode. A high-concentration P+ region is embedded within the low-doped P-anode region. At low current densities, the injection efficiency of the pn junction is low, and the diode voltage drop is determined by the PN-N+ portion with the lower forward voltage drop. At high current densities, the injection efficiency of the P+PN- junction is high, and the diode voltage drop is composed of the P+PN-NN+ and P+PN-N+ portions with lower forward voltage drops. This structure results in a smaller increase in forward voltage drop at high current densities, which helps improve the device's surge current resistance, increases reverse recovery speed, reduces reverse recovery time, and optimizes the P+ block ratio. Without affecting the on-state voltage drop, it can significantly improve the diode's recovery softness.

[0033] 5. The semiconductor wafer of the present invention can be cut into circles with a diameter of Φ38 to Φ146, and its product blocking voltage reaches 4500 to 8500V. Its reverse recovery time is 5.0 to 20μS, the softness factor is increased to more than 1.2, the reverse recovery current is less than 50% of that of conventional soft recovery diodes, and the amplitude and time of damped oscillation are reduced by more than 50%. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a traditional fast diode structure.

[0035] Figure 2 This is a schematic diagram of a fast soft recovery SIOD diode structure.

[0036] Figure 3 This is a schematic diagram of a diode with an anode SPEED and a cathode FCD structure.

[0037] Figure 4 This is a cross-sectional view of the high-voltage, low-damping, oscillating soft recovery diode structure of the present invention.

[0038] Figure 5 This is a schematic diagram of the doping and electric field distribution of the high-voltage, low-damping, oscillating soft recovery diode of the present invention.

[0039] Figure 6 This is a schematic cross-sectional view of the high-voltage soft recovery diode according to an embodiment of the present invention.

[0040] Figure 7 This is a schematic diagram of the P+ and N+ arrangement structure of the diode cathode in an embodiment of the present invention.

[0041] Figure 8 This is a schematic diagram of the diode anode P+ arrangement structure according to an embodiment of the present invention.

[0042] In the diagram, A-anode, K-cathode, 1-anode metal layer, 2-anode P+ region, 20-anode P+ block, 21-anode outer end P+ ring, 3-P-buffer layer, 4-N- region, 5-N-buffer layer block, 50-N-buffer layer ring, 6-cathode P+ block, 7-N+ region, 70-outer end N+ ring, 8-cathode metal layer, 9-PN-N+ structure blocking electric field distribution, 10-P+PN-NP+ structure blocking electric field distribution. Detailed Implementation

[0043] The following is combined with Figures 4 to 8 The embodiments of the present invention will be described in full here. Obviously, the described embodiments are only a part of the present invention, and not all of them. Any other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0044] Embodiment 1 of the present invention is a high-voltage, low-damping, oscillating soft-recovery diode, as follows: Figure 4 , Figure 7 , Figure 8 As shown, using N-region 4 as a substrate, the structure includes an outer P+ ring 21 of the anode, an anode P+ block 20, a P-buffer layer 3, an outer N+ ring 70 of the cathode, an N+ region 7 of the cathode, a cathode P+ block 6, an N-buffer block 5, and an outer N-buffer layer ring 50 of the cathode. The N-buffer block 5 and the N-buffer layer ring 50 are uniformly disposed on the cathode K side of N-region 4. High concentrations of the outer N+ ring 70 of the cathode and the cathode are alternately disposed on the N-buffer block 5, the N-buffer layer ring 50, and N-region 4. N+ region 7 and cathode P+ block 6, N+ region 7 overlaps and surrounds N buffer block 5, N buffer block 5 surrounds cathode P+ block 6, cathode P+ block 6 and cathode N+ region 7 are isolated by N buffer block 5; P- buffer layer is provided between N- region 4 and anode P+ block 20, anode P+ blocks 20 are evenly distributed on the surface of anode P- buffer layer 3, anode outer end P+ ring 21, anode P+ block 20 and P- buffer layer 3 between anode P+ block 20 constitute anode region.

[0045] like Figure 7 As shown, the cathode N+ region 7 occupies 50-90% of the total cathode area, the cathode P+ block 6 occupies 10-50% of the total cathode area, the cathode N+ region 7 uniformly surrounds the cathode P+ block 6, the N buffer block 5 occupies 25-60% of the total cathode plane area, the N buffer block 5 uniformly surrounds the cathode P+ block 6, and the cathode N+ region 7, N buffer block 5, and cathode P+ block 6 are cylindrical or square prisms.

[0046] like Figure 8 As shown, the anode P+ block 20 occupies 20-60% of the total anode area, and the anode P+ block 20 is cylindrical or square.

[0047] Figure 5 yes Figure 4 The diagrams show the doping distribution at the corresponding BB' and CC' longitudinal sections and the electric field distribution of the depletion layer at the maximum blocking voltage. The junction depth of the anode P-buffer layer 3 is greater than that of the anode P+ block 20, while the junction depth of the cathode P+ block is less than that of the cathode N+ region. Utilizing the lateral diffusion effect of the N-buffer layer and the cathode N+ region, an overlap between the cathode N+ region and the N-buffer layer is formed. The surface concentration of the anode P+ region 2 or P+ block 20 is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 4–10 μm; the impurity concentration on the surface of the anode P-buffer layer 3 is 0.2–6.0 × 10⁻⁶. 16 / cm 3 The junction depth is 80–100 μm or 100–130 μm; the surface impurity concentration of the cathode N+ ring 70 and cathode N+ region 7 is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 6-15 μm; the impurity concentration on the surface of cathode P+ block 6 is 0.4-5.0 × 10⁻⁶. 20 / cm 3 The junction depth is 3-8 μm, and the impurity concentration on the surface of the N buffer block 5 and the N buffer layer ring 50 at the outer end of the cathode is 1.0-4.5 × 10⁻⁶. 16 / cm 3 The depth is 25-40 μm; the cathode P+ block 6 is cylindrical or square prism shaped with a width of 20-60 μm, and the anode P+ block 2 is spaced 100-600 μm apart, and the anode P+ block 2 is cylindrical or square prism shaped.

[0048] The working principle of the high-voltage, low-damping oscillating soft recovery diode of the present invention is as follows:

[0049] The cathode employs an alternating P+ and N+ structure, with a low-concentration impurity N buffer layer is used to separate the N+ and P+ blocks. The boundary between the N buffer layer and N+ is an overlap formed by the lateral diffusion of doping. The high-concentration cathode P+ block has a shallow doping depth, which does not significantly affect the reverse cutoff and conduction characteristics. During reverse recovery, as the anode voltage gradually increases, the cathode P+ block injects holes into the N buffer layer, the side N+ layer, and N-. The injection efficiency increases with the increase of the reverse voltage across the device, resulting in good reverse recovery softness. The N buffer layer between N+ and N- in the cathode region is made into a comb-like structure. Since the doping concentration at the comb opening is low, the carrier concentration on the cathode side during reverse recovery is increased, resulting in a small and long tail current. By adjusting the opening width of the comb-like cathode, the slope of the tail current is reduced, suppressing current and voltage oscillations and significantly weakening the damped oscillation characteristics.

[0050] The anode consists of a narrow strip of low-concentration P-region formed between two adjacent P+ blocks. A high-concentration P+ region is embedded in the low-doped P-anode region. Under high current density, the injection efficiency of the P+PN- junction is high. The diode voltage drop is composed of P+PN-NN+ and P+PN-N+ parts. The increase in forward voltage drop is small, which helps to improve the device's surge current resistance. Under low current density, the voltage drop is determined by the PN-N+ part with lower voltage drop. At the same time, the hole injection of the low-doped P-buffer layer is weak, which can achieve better recovery softness. Optimizing the P+ block ratio can improve the reverse recovery speed and reduce the reverse recovery time without affecting the on-state voltage drop, thereby improving the diode's recovery softness factor and reducing damped oscillation.

[0051] like Figure 5 As shown, the blocking electric field distribution 10 of the diode P+PN-NP+ structure and the blocking electric field distribution 9 of the diode PN-N+ structure, through the coordination of diffusion doping concentration and depth, form the optimal equipotential line distribution at high blocking voltage, and can achieve the best effects in blocking voltage, base thickness, on-state characteristics, reverse recovery characteristics and low-damped oscillation.

[0052] The N+ ring and N buffer layer ring at the outer end of the wafer can achieve mesa compression and depletion layer widening, reducing the N- thickness. The P+ ring at the outer end of the anode can ensure that the depletion layer widening in the P region does not penetrate, thus achieving the thinnest emitter thickness and high blocking voltage. This can reduce the total thickness of the silicon wafer by up to 40%, while reducing the number of carriers in the base region or reducing the reverse recovery time and reverse recovery current of the diode, significantly reducing the stored energy of damped oscillations and weakening the damped oscillation characteristics.

[0053] Example 2 Figure 6 , Figure 5 , Figure 7 , Figure 8 As shown, unlike Embodiment 1, the anode P+ region 2 forms an anode region on the surface of the P- buffer layer 3. The junction depth of the anode P+ region is 3-6 μm, which is shallower than the P+ block junction depth in Embodiment 1. When using reverse recovery, electrons can quickly pass through the anode region, reducing the reverse recovery time.

[0054] This invention provides a method for manufacturing a high-voltage, low-damping, oscillating soft-recovery diode, specifically including the following steps:

[0055] (1) Select type N <100> or <111> High-resistivity single-crystal silicon wafers, used as N-region substrate materials, have a thickness of 700–970 μm or 1050–1300 μm, a resistivity of 160–320 Ω•cm or 360–530 Ω•cm, and undergo double-sided chemical etching or phosphorus absorption treatment.

[0056] (2) P-diffusion: After cleaning the silicon wafer, aluminum is pre-deposited on both sides of the silicon wafer at a temperature of 950-1150℃. Then, aluminum impurities are diffused and oxidized at a low concentration on both sides at a temperature of 1200-1250℃ for 10-30 hours to form a symmetrical PNP-structure. The junction depth of the P-region is 80-100μm or 100-120μm, and the surface impurity concentration is 0.35-8.5×10⁻⁶. 16 / cm 3 ;

[0057] (3) Single-sided thinning: The cathode side of the silicon wafer is thinned to remove the single-sided diffused P-layer, forming a PN-structure;

[0058] (4) Oxidation: After cleaning, the silicon wafer is oxidized at a temperature of 1050-1200℃ for 3-6 hours.

[0059] (5) N-buffer layer photolithography: Photoresist is applied to the cathode surface of the silicon wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode window area;

[0060] (6) N-buffer layer diffusion: After cleaning the silicon wafer, phosphorus is pre-deposited at a low temperature or phosphorus ions are implanted on the cathode surface of the silicon wafer. The phosphorus pre-deposition temperature is 1000-1125℃, followed by high-temperature diffusion and oxidation at a temperature of 1120-1240℃ for 6-12 hours to form a PNN structure. The impurity concentration on the surface of the N-buffer layer is 1.0-5.0×10⁻⁶. 16 / cm 3 The N-buffer layer has a depth of 20-30 μm.

[0061] (7) N+ lithography: Photoresist is applied to the cathode surface of the silicon wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode window area;

[0062] (8) N+ diffusion: After cleaning the silicon wafer, phosphorus is pre-deposited and diffused on the cathode surface of the silicon wafer. The phosphorus pre-deposition temperature is 1100-1150℃, followed by high-temperature diffusion and oxidation at 1150-1240℃ for 30-120 minutes to form a deep junction PN-NN+ structure. The impurity concentration on the cathode N+ surface is 0.6-9.0×10⁻⁶. 20 / cm 3 The cathode N+ depth is 3–10 μm;

[0063] (9) Photolithography of the cathode and anode P+ blocks: Photoresist is applied to both sides of the silicon wafer, exposed, and developed to remove the oxide layer in the cathode and anode window areas;

[0064] (10) P+ diffusion: After cleaning the silicon wafer, boron is sprayed onto the anode surface of the silicon wafer. After the anode P+ and cathode P+ diffuse, an anode P+ layer and a cathode P+ layer are formed. The depth of the anode P+ layer is 5-10 μm and the junction depth of the cathode P+ layer is 4-8 μm. The impurity concentration on the surface of the anode P+ layer is 0.6-8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration of the cathode P+ layer is 0.4–5.0 × 10⁻⁶. 20 / cm 3 The anode P+ is formed by high-concentration boron diffusion, and the cathode P+ is formed by reverse diffusion from the anode P+ boron source. The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source. Boron is sprayed onto the anode surface of the silicon wafer, and a constant surface source diffusion method is used.

[0065] Propulsion conditions: 1180~1200℃, N2=6L / min, O2=0.5L / min, time 60~120min;

[0066] (11) A metal conductive layer is deposited on both surfaces of a silicon wafer, with a thickness of 8-15 μm or 15-30 μm, forming a cathode metal layer 8 of cathode K and an anode metal layer 1 of anode A;

[0067] (12) Chip table design, the design structure is a double positive angle design or a double negative angle design;

[0068] (13) Chemical etching of the chip mesa, followed by passivation and adhesive coating of the mesa edge surface;

[0069] (14) Perform final product parameter testing on semiconductor chips.

[0070] The present invention provides a method for manufacturing a high voltage low damping oscillating soft recovery diode. Between steps (13) and (14) above, the recovery time and recovery charge of the chip are controlled to the required values ​​by means of electron irradiation, proton irradiation, or electron and proton irradiation.

[0071] Electron irradiation can reduce the recovery charge, reverse recovery current, and recovery time of a diode; proton irradiation controls the minority carrier lifetime in the localization region and improves the recovery softness characteristics of the diode. The combination of the two can achieve the characteristics of high voltage fast soft recovery. Using this invention, a high voltage low-damping oscillation fast soft recovery diode can be realized.

[0072] As an embodiment of the present invention, a high-voltage, low-damping oscillating soft recovery diode can be used in reverse freewheeling devices for IGBTs, IGCTs, IEGTs, etc., and can also be used for discharge oscillation absorption and energy harvesting of high-voltage pulse devices.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications, equivalent substitutions, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A high-voltage, low-damping, oscillating soft-recovery diode, characterized in that: Using the N-region (4) as a substrate, it includes an outer P+ ring (21) of the anode, an anode P+ block (20), a P- buffer layer (3), an outer N- buffer layer ring (50) of the cathode, an N- buffer block (5), and an outer N-region of the cathode. + ring (70), cathode N+ region (7) and cathode P+ block (6), N buffer block (5) and N buffer layer ring (50) are uniformly arranged on the cathode K side of the N- region (4), and high concentration of cathode outer end N+ ring (70), cathode N+ region (7) and cathode P+ block (6) are alternately arranged on the N buffer layer ring (50), N buffer block (5) and N- region (4), N+ region (7) overlaps and surrounds N buffer block (5), N buffer block (5) surrounds cathode P+ block (6), cathode P+ block (6) and cathode N+ region (7) are isolated by N buffer block (5); P- buffer layer is arranged between N- region (4) and anode P+ block (20), anode P+ block (20) is evenly distributed on the surface of anode P- buffer layer (3), and anode outer end P+ ring (21), anode P+ block (20) and anode P+ block (20) P- buffer layer (3) constitute anode region.

2. The high-voltage, low-damping, oscillating soft-recovery diode according to claim 1, characterized in that: The cathode N+ region (7) occupies 50-90% of the total cathode area, the cathode P+ block (6) occupies 10-50% of the total cathode area, and the cathode N+ region (7) uniformly surrounds the cathode P+ block (6); the N buffer block (5) occupies 25-60% of the total cathode plane area, and the N buffer block (5) uniformly surrounds the cathode P+ block (6); the anode P+ block (20) occupies 20-60% of the total anode area, and the cathode N+ region (7), N buffer block (5), and cathode P+ block (6) are cylindrical or square.

3. A high-voltage, low-damping, oscillating soft-recovery diode according to claim 1 or 2, characterized in that: The surface concentration of the anode P+ block (20) is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 4-10 μm; the impurity concentration on the surface of the anode P-buffer layer (3) is 0.2-6.0×10⁻⁶. 16 / cm 3 The junction depth is 80–100 μm or 100–130 μm; the surface impurity concentration of the cathode N+ ring (70) and cathode N+ region (7) is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 6-15 μm; the impurity concentration on the surface of the cathode P+ block (6) is 0.4-5.0 × 10⁻⁶. 20 / cm 3 The junction depth is 3-8 μm, and the impurity concentration on the surface of the N buffer block (5) and the N buffer layer ring (50) at the outer end of the cathode is 1.0-4.5×10¹⁶ / cm. 3 The depth is 25-40 μm; the cathode P+ block (6) is cylindrical or square prism-shaped with a width of 20-60 μm, and the anode P+ block (20) is spaced 100-600 μm apart. The anode P+ block (20) is cylindrical or square prism-shaped.

4. A high-voltage, low-damping, oscillating soft-recovery diode, characterized in that: Using the N-region (4) as a substrate, the structure includes an outer P+ ring (21) of the anode, an anode P+ region (2), a P- buffer layer (3), an outer N- buffer layer ring (50) of the cathode, an N- buffer block (5), an outer N+ ring (70) of the cathode, and an outer N- region of the cathode. + region (7) and cathode P+ block (6), N buffer block (5) and N buffer layer ring (50) are uniformly arranged on the cathode K side of the N- region (4), and high concentration of cathode outer end N+ ring (70), cathode N+ region (7) and cathode P+ block (6) are alternately arranged on the N buffer layer ring (50), N buffer block (5) and N- region (4), N+ region (7) overlaps and surrounds N buffer block (5), N buffer block (5) surrounds cathode P+ block (6), cathode P+ block (6) and cathode N+ region (7) are isolated by N buffer block (5); P- buffer layer is arranged between N- region (4) and anode P+ region (2), and anode P+ region (2) forms anode region on the surface of P- buffer layer (3).

5. A high-voltage, low-damping, oscillating soft-recovery diode according to claim 4, characterized in that: The cathode N+ region (7) occupies 50-90% of the total cathode area, the cathode P+ block (6) occupies 10-50% of the total cathode area, and the cathode N+ region (7) uniformly surrounds the cathode P+ block (6); the N buffer block (5) occupies 25-60% of the total cathode plane area, and the N buffer block (5) uniformly surrounds the cathode P+ block (6). The cathode N+ region (7) and the N buffer block (5) are cylindrical or square.

6. A high-voltage, low-damping, oscillating soft-recovery diode according to claim 4 or 5, characterized in that: The surface concentration of the anode P+ region (2) is 0.6–8.0 × 10⁻⁶. 20 / cm 3 The junction depth is 4-10 μm; the impurity concentration on the surface of the anode P-buffer layer (3) is 0.2-6.0×10⁻⁶. 16 / cm 3 The junction depth is 80–100 μm or 100–130 μm; the surface impurity concentration of the cathode N+ ring (70) and cathode N+ region (7) is 0.9–8.8 × 10⁻⁶. 20 / cm 3 The depth is 6-15 μm; the impurity concentration on the surface of the cathode P+ block (6) is 0.4-5.0 × 10⁻⁶. 20 / cm 3 The junction depth is 3-8 μm, and the impurity concentration on the surface of the N buffer block (5) and the N buffer layer ring (50) at the outer end of the cathode is 1.0-4.5×10¹⁶ / cm. 3 The depth is 25-40 μm; the cathode P+ block (6) is cylindrical or square prism with a width of 20-60 μm.

7. A method for manufacturing a high-voltage, low-damping, oscillating soft-recovery diode, characterized in that... Includes the following steps: (1) Select N type <100> or <111> High-resistivity single-crystal silicon wafers, used as N-region substrate materials, have a thickness of 700–970 μm or 1050–1300 μm and a resistivity of 160–320 Ω•cm or 360–530 Ω•cm. The silicon wafers are chemically etched or phosphorus absorbed on both sides. (2) P-diffusion: After cleaning the silicon wafer, aluminum is pre-deposited on both sides of the silicon wafer at a temperature of 950-1150℃. Then, aluminum impurities are diffused and oxidized at a low concentration on both sides at a temperature of 1200-1250℃ for 10-30 hours, forming a symmetrical PNP-structure. The junction depth of the P-region is 80-100μm or 100-120μm, and the surface impurity concentration is 0.35-8.5×10⁻⁶. 16 / cm 3 ; (3) Single-sided thinning: The cathode side of the silicon wafer is thinned to remove the single-sided diffused P-layer, forming a PN-structure; (4) Oxidation: After cleaning, the silicon wafer is oxidized at a temperature of 1050-1200℃ for 3-6 hours. (5) N-buffer layer photolithography: Photoresist is applied to the cathode surface of the silicon wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode window area; (6) N-buffer layer diffusion: After cleaning the silicon wafer, phosphorus is pre-deposited or implanted at a low temperature on the cathode surface of the silicon wafer. The phosphorus pre-deposition temperature is 1000-1125℃, followed by high-temperature diffusion and oxidation at 1120-1240℃ for 6-12 hours to form a PNN structure. The impurity concentration on the surface of the N-buffer layer is 1.0-5.0×10⁻⁶. 16 / cm 3 The N-buffer layer has a depth of 20-30 μm. (7) N+ photolithography: Photoresist is applied to the cathode surface of the silicon wafer, exposed, and developed to protect the anodic oxide layer and remove the oxide layer in the cathode window area; (8) N+ diffusion: After cleaning the silicon wafer, phosphorus is pre-deposited and diffused onto the cathode surface of the silicon wafer. The phosphorus pre-deposition temperature is 1100-1150℃, followed by high-temperature diffusion and oxidation at 1150-1240℃ for 30-120 minutes, forming a deep junction PN-NN+ structure. The impurity concentration on the cathode N+ surface is 0.6-9.0×10⁻⁶. 20 / cm 3 The cathode N+ depth is 3–10 μm; (9) Photolithography of cathode and anode P+ blocks: Photoresist is applied to both sides of the silicon wafer, and photolithography is performed on cathode P+ blocks and anode P+ blocks. Exposure and development are performed to remove the oxide layer in the anode and cathode window areas. (10) P+ diffusion: After cleaning the silicon wafer, boron is sprayed onto the anode surface of the silicon wafer. After boron diffusion, anode P+ and cathode P+ layers are formed, with anode P+ layer depth of 5-10 μm and cathode P+ layer junction depth of 4-8 μm. The impurity concentration on the surface of anode P+ layer is 0.6-8.0 × 10⁻⁶. 20 / cm 3 The surface impurity concentration of the cathode P+ layer is 0.4–5.0 × 10⁻⁶. 20 / cm 3 The anode P+ is formed by high-concentration boron diffusion, and the cathode P+ is formed by reverse diffusion from the anode P+ boron source. The process conditions are as follows: the boron source is an alcohol source or a latex source, which is a saturated solution of boron oxide in alcohol or latex source. Boron is sprayed onto the anode surface of the silicon wafer, and a constant surface source diffusion method is used. Propulsion conditions: 1180~1200℃, N2=6L / min, O2=0.5L / min, time 60~120min; (11) A metal conductive layer is deposited on both surfaces of a silicon wafer. The thickness of the metal conductive layer is 8-15μm or 15-30μm, forming a cathode metal layer (8) of cathode K and an anode metal layer (1) of anode A. (12) Chip table design, the design structure is a double positive angle design or a double negative angle design; (13) Chemical etching of the chip mesa, followed by passivation and adhesive coating of the mesa edge surface; (14) Perform final product parameter testing on semiconductor chips.

8. The manufacturing method of a high-voltage, low-damping, oscillating soft-recovery diode according to claim 7, characterized in that: Between steps (13) and (14), the chip recovery time and recovery charge are controlled to the required values ​​by means of electron irradiation, proton irradiation, or electron and proton irradiation.

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