Power device detection system and method

Abstract

The application provides a power device detection system and method. The detection system comprises a multi-level converter, a control circuit and a loop switching circuit. The multi-level converter comprises a first power tube, a second power tube, a third power tube and a fourth power tube. The loop switching circuit comprises a first switch tube, a second switch tube, a capacitor and an inductor. The control circuit is used for controlling the conduction or turn-off of each switch tube in the loop switching circuit, inputting a detection signal to any power tube, and controlling the conduction or turn-off of the power tubes other than any power tube in the multi-level converter, so as to prevent any conducting switch tube from generating an induced voltage when the control circuit inputs the detection signal to any power tube. The application can prevent the switch tube of the detection system from generating an induced voltage when the power device being detected switches between the conducting and turn-off states, and improve the accuracy and safety of the detection system.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a power device detection system and method. Background Technology

[0002] In the field of power electronics, to avoid the risk of latch-up caused by rapid changes in the voltage between the signal input terminal and the voltage reference terminal of a power device (e.g., the voltage between the gate and source of an IGBT), it is usually necessary to simulate an environment with rapid voltage changes to test the latch-up resistance of the power device. During their research and practice, the inventors of this application discovered that in the prior art, power devices need to be detected by switching circuits using a switching device (e.g., a relay). However, switching devices have stray inductance. When the switching device switches states, the current within the switching device changes rapidly, easily generating a large induced voltage. This induced voltage is superimposed between the signal input terminal and the voltage reference terminal of the power device, which not only disrupts the voltage between the signal input terminal and the voltage reference terminal, reducing the accuracy of the detection, but also easily leads to excessively high signal input levels at the power device, damaging the power device. Summary of the Invention

[0003] This application provides a power device detection system and method, which can prevent the switching transistor of the detection system from generating induced voltage when the power device under test switches between on and off states, thereby improving the accuracy and safety of the detection system.

[0004] In a first aspect, this application provides a power device detection system, which includes a multilevel converter, a control circuit, and a loop switching circuit. The multilevel converter may include a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor. The loop switching circuit may include a first switching transistor, a second switching transistor, a capacitor, and an inductor. The first, second, third, and fourth power transistors can be connected in series. The first and second switching transistors can be connected in series and then in parallel with the capacitor. The voltage input terminal of the first power transistor can serve as the voltage input terminal of the multilevel converter, connected to the first switching transistor and the voltage input terminal of the detection system. The voltage reference terminal of the fourth power transistor can serve as the ground terminal of the multilevel converter, connected to the second switching transistor and a reference ground. One end of the inductor can be connected to the series connection point of the first and second switching transistors, and the other end of the inductor can be connected to the series connection point of the second and third power transistors. The control circuit can be connected to the control input terminals of each power transistor in the multilevel converter. The control circuit here can be used to turn on or off each switch in the control loop switching circuit and input a detection signal to any power transistor, and to control the turn on or off of other power transistors in the multilevel converter except for any power transistor, so as to prevent any conducting switch from generating an induced voltage when the control circuit inputs a detection signal to any power transistor.

[0005] In the embodiments provided in this application, the multilevel converter in the detection system can be a three-level converter circuit or a three-level converter circuit topology, or other multilevel converter circuits or other multilevel converter circuit topologies. The multilevel converter may include a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor (or include other numbers of power transistors). It is understood that when the detection system detects a power transistor in the multilevel converter, the control circuit can control the on / off state of each switch in the loop switching circuit to construct a loop for detecting this power transistor, and input a detection signal (e.g., a pulse signal) to this power transistor. Simultaneously, it controls the on / off state of the other power transistors in the multilevel converter besides this power transistor to establish the loop for detecting this power transistor. Furthermore, when the detection system detects a power transistor in a multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to that power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system changes from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for that power transistor changes from a detection loop that is active when the signal is high to a detection loop that is active when the signal is low (or vice versa). Further, it can be understood that in the detection loop when any power transistor is active at a high level and in the detection loop when it is active at a low level, the control circuit controls the same switching transistor to be active, ensuring that the current flowing through the active switching transistor does not change abruptly and does not generate an induced voltage. In other words, the detection system can prevent any active switching transistor from generating an induced voltage when the control circuit inputs a detection signal to any power transistor. By employing the embodiments provided in this application, the induced voltage generated by the switching transistor of the detection system when the power device under test (e.g., power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level) can be prevented, thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0006] In conjunction with the first aspect, in a first possible implementation, the control circuit can be used to control the second switch to be turned on and the first switch to be turned off, and to input a detection signal to the first power transistor, control the second power transistor to be normally on, and control the third and fourth power transistors to be turned off, so as to prevent the second switch from generating an induced voltage when the control circuit inputs a detection signal to the first power transistor. It can be understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can control the second switch to be turned on and the first switch to be turned off to establish a loop for detecting the first power transistor, and input a detection signal (e.g., a pulse signal) to the first power transistor, while simultaneously controlling the second power transistor to be normally on and controlling the third and fourth power transistors to be turned off, so as to conduct the loop for detecting the first power transistor. Furthermore, it can be understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the first power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the first power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the first power transistor is high-level on (e.g., inductor-second switch-capacitor-first power transistor-second power transistor-inductor) and the detection circuit when the first power transistor is low-level on (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-inductor), the second switch is always on, the current flowing through the second switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch from generating an induced voltage when the control circuit inputs a detection signal to the first power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the second switch) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the first power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0007] In conjunction with the first aspect, in a second possible implementation, the control circuit can be used to control the second switch to be turned on and the first switch to be turned off, and to input a detection signal to the second power transistor, control the first power transistor to be normally on, and control the third and fourth power transistors to be turned off, so as to prevent the second switch from generating an induced voltage when the control circuit inputs a detection signal to the second power transistor. It is understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can control the second switch to be turned on and the first switch to be turned off to establish a loop for detecting the second power transistor, and input a detection signal (e.g., a pulse signal) to the second power transistor, while simultaneously controlling the first power transistor to be normally on and controlling the third and fourth power transistors to be turned off, so as to complete the loop for detecting the second power transistor. Furthermore, it can be understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the second power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the second power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the second power transistor is high-level on (e.g., inductor-second switch-capacitor-first power transistor-second power transistor-inductor) and the detection circuit when the second power transistor is low-level on (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-inductor), the second switch transistor is always on, the current flowing through the second switch transistor will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch transistor from generating an induced voltage when the control circuit inputs a detection signal to the second power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the second switch transistor) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the second power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0008] In conjunction with the first aspect, in a third possible implementation, the control circuit can be used to control the first switch to be turned on and the second switch to be turned off, input a detection signal to the third power transistor, control the fourth power transistor to be turned on normally, and control the first and second power transistors to be turned off, so as to prevent the first switch transistor from generating an induced voltage when the control circuit inputs a detection signal to the third power transistor. It can be understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can control the first switch transistor to be turned on and the second switch transistor to be turned off to establish a loop for detecting the third power transistor, and input a detection signal (e.g., a pulse signal) to the third power transistor, while simultaneously controlling the fourth power transistor to be turned on normally and controlling the first and second power transistors to be turned off, so as to complete the loop for detecting the third power transistor. Furthermore, it can be understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the third power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the third power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the third power transistor is high-level conducting (e.g., inductor-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the third power transistor is low-level conducting (e.g., inductor-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first switch is always conducting, the current flowing through the first switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch from generating an induced voltage when the control circuit inputs a detection signal to the third power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the first switch) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the third power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0009] In conjunction with the first aspect, in a fourth possible implementation, the control circuit can be used to control the first switch to be turned on and the second switch to be turned off, inputting a detection signal to the fourth power transistor, controlling the third power transistor to be normally on, and controlling the first and second power transistors to be turned off, to prevent the first switch transistor from generating an induced voltage when the control circuit inputs a detection signal to the fourth power transistor. It can be understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can control the first switch transistor to be turned on and the second switch transistor to be turned off to establish a loop for detecting the fourth power transistor, and input a detection signal (e.g., a pulse signal) to the fourth power transistor, while simultaneously controlling the third power transistor to be normally on and controlling the first and second power transistors to be turned off, to complete the loop for detecting the fourth power transistor. Furthermore, it can be understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fourth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fourth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the fourth power transistor is high-level on (e.g., inductor-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the fourth power transistor is low-level on (e.g., inductor-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first switch is always on, the current flowing through the first switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch from generating an induced voltage when the control circuit inputs a detection signal to the fourth power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the first switch) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the fourth power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0010] In conjunction with the first aspect or any possible implementation thereof, in a fifth possible implementation, the multilevel converter may further include a first diode and a second diode. Here, the input terminal of the first diode may be connected in series with the output terminal of the second diode, the output terminal of the first diode may be connected to the series connection point of the first power transistor and the second power transistor, and the input terminal of the second diode may be connected to the series connection point of the third power transistor and the fourth power transistor.

[0011] The implementation method provided in this application can prevent the switching transistor of the detection system from generating induced voltage when the power device under test switches between the on and off states. While improving the accuracy and safety of the detection system, the multilevel converter has a flexible and diverse structure that can adapt to different application scenarios, thus improving the applicability of the detection system.

[0012] In conjunction with the first aspect or any of the first to fourth possible embodiments of the first aspect, in the sixth possible embodiment, the multilevel converter may further include a fifth power transistor and a sixth power transistor, and the loop switching circuit may further include a third switch and a fourth switch. Here, the fifth and sixth power transistors may be connected in series and then in parallel between the series connection point of the first and second power transistors and the series connection point of the third and fourth power transistors. The other end of the inductor may be connected to the series connection point of the second and third power transistors through the third switch, and the other end of the inductor may also be connected to the series connection point of the fifth and sixth power transistors through the fourth switch. The control circuit may be connected to the control input terminal of each power transistor in the multilevel converter. The control circuit may also be used to control the second and fourth switches to be turned on, control the first and third switches to be turned off and input a detection signal to the fifth power transistor, control the first power transistor to be normally turned on, and control the second, third, fourth, and sixth power transistors to be turned off, so as to prevent the second or fourth switch from generating an induced voltage when the control circuit inputs a detection signal to the fifth power transistor.

[0013] In the embodiments provided in this application, the multilevel converter in the detection system can be a three-level converter circuit or a three-level converter circuit topology, or other multilevel converter circuits or other multilevel converter circuit topologies. The multilevel converter may also include a fifth power transistor and a sixth power transistor (or include other numbers of power transistors), and the loop switching circuit may also include a third switch transistor and a fourth switch transistor. It is understood that when the detection system detects the fifth power transistor in the multilevel converter, the control circuit can control the second and fourth switch transistors to be turned on, and control the first and third switch transistors to be turned off, so as to construct a loop for detecting the fifth power transistor, and input a detection signal (e.g., a pulse signal) to the fifth power transistor, while controlling the first power transistor to be normally turned on, and controlling the second, third, fourth, and sixth power transistors to be turned off, so as to conduct the loop for detecting the fifth power transistor. Furthermore, it can be understood that when the detection system detects the fifth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fifth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fifth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the fifth power transistor is high-level conducting (e.g., inductor-second switch-capacitor-first power transistor-fifth power transistor-fourth switch-inductor) and the detection circuit when the fifth power transistor is low-level conducting (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-sixth power transistor (e.g., a diode connected in parallel with the sixth power transistor or a parasitic diode in the sixth power transistor)-fourth switch-inductor), the second and fourth switches are always conducting. The current flowing through the second and fourth switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second or fourth switch from generating an induced voltage when the control circuit inputs a detection signal to the fifth power transistor. By employing the embodiments provided in this application, the switching transistors (e.g., the second or fourth switching transistor) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fifth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0014] In conjunction with the sixth possible implementation of the first aspect, in the seventh possible implementation, the control circuit can also be used to control the first and fourth switching transistors to be turned on, control the second and third switching transistors to be turned off and input a detection signal to the sixth power transistor, control the fourth power transistor to be normally turned on, and control the first, second, third, and fifth power transistors to be turned off, so as to prevent the first or fourth switching transistor from generating an induced voltage when the control circuit inputs a detection signal to the sixth power transistor. It can be understood that when the detection system detects the sixth power transistor in the multilevel converter, the control circuit can control the first and fourth switching transistors to be turned on and control the second and third switching transistors to be turned off to construct a loop for detecting the sixth power transistor, and input a detection signal (e.g., a pulse signal) to the sixth power transistor, while simultaneously controlling the fourth power transistor to be normally turned on and controlling the first, second, third, and fifth power transistors to be turned off, so as to complete the loop for detecting the sixth power transistor. Furthermore, it can be understood that when the detection system detects the sixth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the sixth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the sixth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the sixth power transistor is high-level conducting (e.g., inductor-fourth switch-sixth power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the sixth power transistor is low-level conducting (e.g., inductor-fourth switch-fifth power transistor (e.g., a diode connected in parallel with the fifth power transistor or a parasitic diode in the fifth power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first and fourth switches are always conducting. The current flowing through the first and fourth switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first or fourth switch from generating an induced voltage when the control circuit inputs a detection signal to the sixth power transistor. By employing the embodiments provided in this application, the switching transistors (e.g., the first or fourth switching transistor) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the sixth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0015] In conjunction with any possible implementation of the first aspect, in the eighth possible implementation, each power transistor in the detection system can be an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a silicon carbide transistor (SiC), thus enriching the component selection and applicable scenarios of the detection system.

[0016] In conjunction with any possible implementation of the first aspect, in a ninth possible implementation, the detection system may further include at least one clamping circuit. Here, a clamping circuit may be connected to the voltage input terminal of a power transistor and the control input terminal of a power transistor. This clamping circuit can be used to control the voltage value between the voltage input terminal and the voltage reference terminal of any power transistor to be less than or equal to a voltage threshold. It is understandable that when the control circuit controls a power transistor being detected to switch from a high level to a low level, that is, when the power transistor changes from being on to being off, the voltage value between the voltage input terminal and the voltage reference terminal of the power transistor will increase. The clamping circuit can reduce the level of the voltage input terminal (e.g., the collector) and increase the level of the control input terminal (e.g., the gate) of the power transistor when the voltage value between the voltage input terminal (e.g., the collector) and the voltage reference terminal (e.g., the emitter) of the power transistor is too high (e.g., greater than or equal to the voltage threshold). This ensures that the voltage value between the voltage input terminal (e.g., the collector) and the voltage reference terminal (e.g., the emitter) of the power transistor does not exceed the voltage threshold, while not changing the rate of change of the voltage value of the power transistor during the detection period.

[0017] By adopting the implementation method provided in this application, the voltage value between the voltage input terminal and the voltage reference terminal of the power transistor can be guaranteed not to exceed the voltage threshold without changing the rate of change of the voltage value of the power transistor during the detection period, thereby further improving the safety of the detection system. Moreover, the connection method of the clamping circuit is simple and flexible, which can reduce the detection cost.

[0018] In conjunction with the ninth possible implementation of the first aspect, in the tenth possible implementation, the detection system may further include a detection circuit, which may be connected to a multilevel converter and a control circuit. The detection circuit can be used to acquire the output current value of any power transistor. The detection circuit can also be used to disconnect the multilevel converter via the control circuit when the output current value of any power transistor is greater than or equal to a current threshold. Using the implementation provided in this application, the system can prevent the switching transistors from generating induced voltages when the detected power device switches between on and off states, improving the accuracy and safety of the detection system. Furthermore, it can disconnect the multilevel converter when the output current value of the power transistor exceeds the current threshold, further improving the safety of the detection system. Moreover, the connection method of the detection circuit is simple and flexible, reducing detection costs.

[0019] In conjunction with the tenth possible implementation of the first aspect, in the eleventh possible implementation, the detection system may further include a temperature control module, which may be connected to the multilevel converter. The temperature control module can be used to control the detection temperature of the multilevel converter.

[0020] In conjunction with the eleventh possible implementation of the first aspect, in the twelfth possible implementation, the detection system may further include a voltage control module, which may be connected to a multilevel converter. The voltage control module can be used to control the detection voltage of the multilevel converter.

[0021] In conjunction with the twelfth possible implementation of the first aspect, in the thirteenth possible implementation, the detection system may further include a current control module, which may be connected to a multilevel converter. The current control module can be used to control the detection current of the multilevel converter.

[0022] In this application, the functional modules of the detection system are composed in a variety of flexible ways, and different detection environments can be set to improve the diversity of application scenarios of the detection system and enhance its adaptability.

[0023] Secondly, this application provides a power device detection method, which is applicable to the system in the first aspect or any possible implementation of the first aspect. The method includes: a control circuit controlling the switching circuit to turn on or off each switching transistor. The control circuit inputs a detection signal to any power transistor and controls the switching on or off of the other power transistors in the multilevel converter, except for that power transistor, to prevent any conducting switching transistor from generating an induced voltage when the control circuit inputs a detection signal to any power transistor.

[0024] In the embodiments provided in this application, when the detection system detects a power transistor in a multilevel converter, the control circuit can control the on or off of each switch in the loop switching circuit to construct a loop for detecting this power transistor, and input a detection signal (e.g., a pulse signal) to this power transistor. Simultaneously, it controls the on or off of the power transistors in the multilevel converter other than this power transistor to activate the loop for detecting this power transistor. Further, it can be understood that when the detection system detects a power transistor in a multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to this power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting this power transistor will change from a detection loop activated at a high level to a detection loop activated at a low level (or from a detection loop activated at a low level to a detection loop activated at a high level). Furthermore, it can be understood that in the detection circuit when any power transistor is high-level on and low-level on, the control circuit controls the same switching transistor to be on, ensuring that the current flowing through the on switching transistor does not change abruptly and does not generate induced voltage. In other words, the detection system can prevent any on switching transistor from generating induced voltage when the control circuit inputs a detection signal to any power transistor. Using the implementation method provided in this application, the detection system can prevent the switching transistors from generating induced voltage when the detected power device (e.g., a power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0025] In conjunction with the second aspect, in the first possible implementation, when the multilevel converter does not include the fifth and sixth power transistors, the control circuit's control of the switching circuit's switching of each switch includes: the control circuit controlling the second switch to turn on and the first switch to turn off. The control circuit inputs a detection signal to any power transistor and controls the turn-on or cut-off of the other power transistors in the multilevel converter, including: the control circuit inputs a detection signal to the first power transistor, controls the second power transistor to be normally on, and controls the third and fourth power transistors to be cut off. It can be understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can control the second switch to turn on and the first switch to turn off to construct a loop for detecting the first power transistor, and input a detection signal (e.g., a pulse signal) to the first power transistor, while simultaneously controlling the second power transistor to be normally on and controlling the third and fourth power transistors to be cut off to conduct the loop for detecting the first power transistor. Furthermore, it can be understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the first power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the first power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the first power transistor is high-level on (e.g., inductor-second switch-capacitor-first power transistor-second power transistor-inductor) and the detection circuit when the first power transistor is low-level on (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-inductor), the second switch is always on, the current flowing through the second switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch from generating an induced voltage when the control circuit inputs a detection signal to the first power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the second switch) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the first power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0026] In conjunction with the first possible implementation of the second aspect, in the second possible implementation, the control circuit inputs a detection signal to any one of the power transistors and controls the conduction or cutoff of the other power transistors in the multilevel converter, including: the control circuit inputs a detection signal to the first power transistor, controls the second power transistor to be normally on, and controls the third and fourth power transistors to be cut off. It can be understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can control the second switch to be on and the first switch to be off to establish a loop for detecting the second power transistor, and input a detection signal (e.g., a pulse signal) to the second power transistor, while simultaneously controlling the first power transistor to be normally on and controlling the third and fourth power transistors to be cut off to establish a loop for detecting the second power transistor. Furthermore, it can be understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the second power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the second power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the second power transistor is high-level on (e.g., inductor-second switch-capacitor-first power transistor-second power transistor-inductor) and the detection circuit when the second power transistor is low-level on (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-inductor), the second switch transistor is always on, the current flowing through the second switch transistor will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch transistor from generating an induced voltage when the control circuit inputs a detection signal to the second power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the second switch transistor) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the second power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0027] In conjunction with the second aspect, in a third possible implementation, when the multilevel converter does not include the fifth and sixth power transistors, the control circuit's control loop switching circuit's switching of each switch transistor includes: the control circuit controlling the second switch transistor to turn on and the first switch transistor to turn off. The control circuit inputs a detection signal to any power transistor and controls the turn-on or cut-off of the other power transistors in the multilevel converter, including: the control circuit inputs a detection signal to the second power transistor, controls the first power transistor to be normally on, and controls the third and fourth power transistors to be cut off. It can be understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can control the first switch transistor to turn on and the second switch transistor to turn off to construct a loop for detecting the third power transistor, and input a detection signal (e.g., a pulse signal) to the third power transistor, while simultaneously controlling the fourth power transistor to be normally on and controlling the first and second power transistors to be cut off to complete the loop for detecting the third power transistor. Furthermore, it can be understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the third power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the third power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the third power transistor is high-level conducting (e.g., inductor-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the third power transistor is low-level conducting (e.g., inductor-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first switch is always conducting, the current flowing through the first switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch from generating an induced voltage when the control circuit inputs a detection signal to the third power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the first switch) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the third power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0028] In conjunction with the third possible implementation of the second aspect, in the fourth possible implementation, the control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of the other power transistors in the multilevel converter, including: the control circuit inputs a detection signal to the third power transistor, controls the fourth power transistor to be normally on, and controls the first and second power transistors to be cut off. It can be understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can control the first switch to be on and the second switch to be off to establish a loop for detecting the fourth power transistor, and input a detection signal (e.g., a pulse signal) to the fourth power transistor, while simultaneously controlling the third power transistor to be normally on and controlling the first and second power transistors to be cut off, to establish a loop for detecting the fourth power transistor. Furthermore, it can be understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fourth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fourth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the fourth power transistor is high-level on (e.g., inductor-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the fourth power transistor is low-level on (e.g., inductor-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first switch is always on, the current flowing through the first switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch from generating an induced voltage when the control circuit inputs a detection signal to the fourth power transistor. Using the implementation method provided in this application, the switching transistor (e.g., the first switch) of the detection system can be prevented from generating an induced voltage when the detected power device (e.g., the fourth power transistor) switches between on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0029] In conjunction with the second aspect, in the fifth possible implementation, when the multilevel converter further includes a fifth power transistor and a sixth power transistor, the control circuit's control loop switching circuit's on / off control of each switch includes: the control circuit controlling the second and fourth switches to be on, and controlling the first and third switches to be off. The control circuit inputting a detection signal to any power transistor and controlling the on / off control of the other power transistors in the multilevel converter, excluding that power transistor, includes: the control circuit inputting a detection signal to the fifth power transistor, controlling the first power transistor to be normally on, and controlling the second, third, fourth, and sixth power transistors to be off.

[0030] In the embodiments provided in this application, the multilevel converter in the detection system can be a three-level converter circuit or a three-level converter circuit topology, or other multilevel converter circuits or other multilevel converter circuit topologies. The multilevel converter may also include a fifth power transistor and a sixth power transistor (or include other numbers of power transistors), and the loop switching circuit may also include a third switch transistor and a fourth switch transistor. It is understood that when the detection system detects the fifth power transistor in the multilevel converter, the control circuit can control the second and fourth switch transistors to be turned on, and control the first and third switch transistors to be turned off, so as to construct a loop for detecting the fifth power transistor, and input a detection signal (e.g., a pulse signal) to the fifth power transistor, while controlling the first power transistor to be normally turned on, and controlling the second, third, fourth, and sixth power transistors to be turned off, so as to conduct the loop for detecting the fifth power transistor. Furthermore, it can be understood that when the detection system detects the fifth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fifth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fifth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the fifth power transistor is high-level conducting (e.g., inductor-second switch-capacitor-first power transistor-fifth power transistor-fourth switch-inductor) and the detection circuit when the fifth power transistor is low-level conducting (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-sixth power transistor (e.g., a diode connected in parallel with the sixth power transistor or a parasitic diode in the sixth power transistor)-fourth switch-inductor), the second and fourth switches are always conducting. The current flowing through the second and fourth switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second and fourth switches from generating induced voltage when the control circuit inputs a detection signal to the fifth power transistor. By employing the embodiments provided in this application, the switching transistors (e.g., the second and fourth switching transistors) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fifth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0031] In conjunction with the fifth possible implementation of the second aspect, in the sixth possible implementation, the control circuit's control of the switching circuit's switching of each switch transistor includes: the control circuit controls the first and fourth switches to be turned on, and controls the second and third switches to be turned off. The control circuit inputs a detection signal to any power transistor and controls the turn-on or cut-off of the other power transistors in the multilevel converter, including: the control circuit inputs a detection signal to the sixth power transistor, controls the fourth power transistor to be normally on, and controls the first, second, third, and fifth power transistors to be turned off. It can be understood that when the detection system detects the sixth power transistor in the multilevel converter, the control circuit can control the first and fourth switches to be turned on, and control the second and third switches to be turned off to construct a loop for detecting the sixth power transistor, and input a detection signal (e.g., a pulse signal) to the sixth power transistor, while simultaneously controlling the fourth power transistor to be normally on, and controlling the first, second, third, and fifth power transistors to be turned off to complete the loop for detecting the sixth power transistor. Furthermore, it can be understood that when the detection system detects the sixth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the sixth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the sixth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the sixth power transistor is high-level conducting (e.g., inductor-fourth switch-sixth power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the sixth power transistor is low-level conducting (e.g., inductor-fourth switch-fifth power transistor (e.g., a diode connected in parallel with the fifth power transistor or a parasitic diode in the fifth power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first and fourth switches are always conducting. The current flowing through the first and fourth switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first and fourth switches from generating induced voltage when the control circuit inputs a detection signal to the sixth power transistor. By employing the embodiments provided in this application, the switching transistors (e.g., the first and fourth switching transistors) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the sixth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs. Attached Figure Description

[0032] Figure 1 This is a schematic diagram illustrating an application scenario of the detection system provided in this application embodiment;

[0033] Figure 2 This is a schematic diagram of the detection system provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of a power device detection circuit provided in an embodiment of this application;

[0035] Figure 4 This is another schematic diagram of the detection system provided in the embodiments of this application;

[0036] Figure 5 This is another schematic diagram of the detection system provided in the embodiments of this application;

[0037] Figure 6 This is another schematic diagram of the power device detection circuit provided in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram showing the connection relationship between the clamping circuit and the multilevel controller provided in the embodiments of this application;

[0039] Figure 8 This is a schematic diagram illustrating the working principle of the clamping circuit provided in the embodiments of this application;

[0040] Figure 9 This is another schematic diagram of the detection system provided in the embodiments of this application;

[0041] Figure 10 This is another schematic diagram of the detection system provided in the embodiments of this application;

[0042] Figure 11 This is a schematic flowchart of the detection method provided in the embodiments of this application. Detailed Implementation

[0043] The power device testing system provided in this application can test power devices (e.g., power transistors) in multilevel converters. Multilevel converters are applicable to various fields, including new energy smart microgrids, power transmission and distribution, new energy fields (such as photovoltaic grid connection or wind power grid connection), photovoltaic-storage power generation (such as supplying power to household appliances (such as refrigerators and air conditioners) or the power grid), wind-storage power generation, and high-power converters (such as converting DC power to high-power high-voltage AC power). The specific application can be determined based on the actual application scenario and is not limited here. The power device testing system provided in this application is adaptable to different application scenarios, such as testing power devices in photovoltaic-storage power supply environments, wind-storage power supply environments, pure energy storage power supply environments, or other application scenarios. The following explanation will use the application scenario of testing power devices in a pure energy storage power supply environment as an example; further details will not be elaborated upon here.

[0044] Please see also Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of the detection system provided in this application embodiment. In a pure energy storage power supply application scenario, such as... Figure 1 As shown, the detection system 2 includes a multilevel converter 11, a loop switching circuit 12, and a control circuit 13. The multilevel converter 11 can be connected to a power supply 1, the loop switching circuit 12, the control circuit 13, and a load 3. The loop switching circuit 12 can be connected to the control circuit 13. During the detection system 2's detection of the power device (e.g., a power transistor) in the multilevel converter 11, the control circuit 13 can control the on / off state of each switch in the loop switching circuit 12 to construct a loop for detecting the power device in the multilevel converter 11 and input a detection signal (e.g., a pulse signal) to this power device. Simultaneously, it controls the on / off state of other power transistors in the multilevel converter 11 besides this power device to establish a loop for detecting this power transistor. In some feasible embodiments, the power supply 1 can supply power to the load 3 through the multilevel converter 11. The multilevel converter 11 provided in this application is suitable for various application scenarios where the power supply 1 powers base station equipment in remote areas with no mains power or poor mains power, or powers batteries, or powers household appliances (such as refrigerators, air conditioners, etc.). The specific application scenario can be determined accordingly, and no limitations are imposed here. Furthermore, it can be understood that... Figure 1 Load 3 in the context can be a power grid, a battery, electrical equipment in a building, lighting equipment on a bridge or other electrical installation. The power grid here can include transmission lines, power transfer stations, batteries, communication base stations, or household appliances and other electrical equipment or power transmission equipment. Figure 1In the application scenario shown, the multilevel converter 11 typically includes multiple power devices (e.g., power transistors). During the operation of the power devices, to avoid the risk of latch-up caused by rapid changes in the voltage between the signal input terminal and the voltage reference terminal (e.g., the voltage between the gate and source of an insulated gate bipolar transistor, IGBT), it may be necessary to simulate a rapidly changing voltage environment to detect the latch-up resistance of the power devices. Using the implementation method provided in this application, the induced voltage generated by the switching transistor of the detection system when the detected power device switches between on and off states can be prevented, improving the accuracy and safety of the detection system.

[0045] The following will combine Figures 2 to 10 The power device detection system provided in this application and its working principle are illustrated with examples.

[0046] Please see Figure 2 , Figure 2 This is a schematic diagram of the detection system provided in an embodiment of this application. Figure 2 As shown, the detection system includes a multilevel converter 101, a control circuit 103, and a loop switching circuit 102. The multilevel converter 101 may include a first power transistor T1, a second power transistor T2, a third power transistor T3, and a fourth power transistor T4. The loop switching circuit 102 may include a first switching transistor R1, a second switching transistor R2, a capacitor, and an inductor. Here, the first power transistor T1, the second power transistor T2, the third power transistor T3, and the fourth power transistor T4 can be connected in series. The first switching transistor R1 and the second switching transistor R2 can be connected in series and then in parallel with the capacitor. The voltage input terminal of the first power transistor T1 can be used as the voltage input terminal of the multilevel converter 101, connected to the first switching transistor R1 and the voltage input terminal of the detection system. The voltage reference terminal of the fourth power transistor T4 can be used as the ground terminal of the multilevel converter 101, connected to the second switching transistor R2 and the reference ground. One end of the inductor can be connected to the series connection point of the first switching transistor R1 and the second switching transistor R2, and the other end of the inductor can be connected to the series connection point of the second power transistor T2 and the third power transistor T3. The control circuit 103 can be connected to the control input terminals of each power transistor in the multilevel converter 101. The control circuit 103 here can be used to control the turn-on or turn-off of each switch in the control loop switching circuit 102 and input a detection signal to any power transistor, and control the turn-on or turn-off of other power transistors in the multilevel converter 101 except for any power transistor, so as to prevent any turn-on switch from generating an induced voltage when the control circuit 103 inputs a detection signal to any power transistor.

[0047] In the embodiments provided in this application, the multilevel converter 101 in the detection system can be a three-level converter circuit or a three-level converter circuit topology, or other multilevel converter circuits or other multilevel converter circuit topologies. The multilevel converter 101 may include a first power transistor T1, a second power transistor T2, a third power transistor T3, and a fourth power transistor T4 (or include other numbers of power transistors). It is understood that when the detection system detects a certain power transistor in the multilevel converter 101, the control circuit 103 can control the on or off of each switch in the loop switching circuit 102 to construct a loop for detecting this power transistor, and input a detection signal (e.g., a pulse signal) to this power transistor, while controlling the on or off of the power transistors in the multilevel converter 101 other than this power transistor to conduct the loop for detecting this power transistor. Furthermore, when the detection system detects a power transistor in the multilevel converter 101, the control circuit 103 can input a detection signal (e.g., a pulse signal) to that power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for that power transistor will change from a detection loop that is active when the signal is high to a detection loop that is active when the signal is low (or from a detection loop that is active when the signal is low to a detection loop that is active when the signal is high). Further, it can be understood that in the detection loop when any power transistor is active at a high level and in the detection loop when it is active at a low level, the switching transistor controlled by the control circuit 103 is consistent, ensuring that the current flowing through the active switching transistor does not change abruptly and does not generate an induced voltage. In other words, the detection system can prevent any active switching transistor from generating an induced voltage when the control circuit 103 inputs a detection signal to any power transistor. By employing the embodiments provided in this application, the induced voltage generated by the switching transistor of the detection system when the power device under test (e.g., power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level) can be prevented, thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0048] In some feasible implementations, the power transistors in the detection system can be insulated gate bipolar transistors (IGBTs, such as IGBTs with diodes connected in parallel inside the device), metal oxide semiconductor field-effect transistors (MOSFETs, such as MOSFETs with parasitic diodes inside the device), or silicon carbide transistors (SiCs, such as SiCs with parasitic diodes inside the device), etc., which enriches the selection of components and applicable scenarios of the detection system.

[0049] Please see also Figure 3 , Figure 3This is a schematic diagram of a power device detection circuit provided in an embodiment of this application. In some feasible implementations, such as... Figure 3 As shown in part a, the control circuit 103 ( Figure 3 (Not shown in the diagram) can be used to control the second switch R2 to be turned on and the first switch R1 to be turned off, and to input a detection signal to the first power transistor T1, control the second power transistor T2 to be normally turned on, and control the third power transistor T3 and the fourth power transistor T4 to be turned off, so as to prevent the second switch R2 from generating an induced voltage when the control circuit 103 inputs a detection signal to the first power transistor T1.

[0050] It is understood that when the detection system detects the first power transistor T1 in the multilevel converter 101, the control circuit 103 can control the second switch R2 to be turned on and the first switch R1 to be turned off, so as to construct a loop for detecting the first power transistor T1 and input a detection signal (e.g., a pulse signal) to the first power transistor T1. At the same time, it controls the second power transistor T2 to be turned on and controls the third power transistor T3 and the fourth power transistor T4 to be turned off, so as to conduct the loop for detecting the first power transistor T1. Furthermore, it can be understood that when the detection system detects the first power transistor T1 in the multilevel converter 101, the control circuit 103 can input a detection signal (e.g., a pulse signal) to the first power transistor T1. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the first power transistor T1 will change from a detection circuit that is conducting when the level is high to a detection circuit that is conducting when the level is low (or from a detection circuit that is conducting when the level is low to a detection circuit that is conducting when the level is high). Further, it can be understood that the detection circuit when the first power transistor T1 is conducting at a high level (e.g., Figure 3 As shown by the gray solid line arrow in part a, the circuit includes the inductor-second switch R2-capacitor-first power transistor T1-second power transistor T2-inductor and the detection circuit when the low level is on (e.g., Figure 3 As shown by the gray dashed arrow in part a, in the sequence of inductor-second switch R2-fourth power transistor T4 (e.g., a diode connected in parallel with the fourth power transistor T4 or a parasitic diode in the fourth power transistor T4)-third power transistor T3 (e.g., a diode connected in parallel with the third power transistor T3 or a parasitic diode in the third power transistor T3)-inductor, the second switch R2 is always on, the current flowing through the second switch R2 will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch R2 from generating an induced voltage when the control circuit 103 inputs a detection signal to the first power transistor T1.

[0051] By employing the embodiments provided in this application, the switching transistors (e.g., the second switching transistor R2) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the first power transistor T1) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0052] In some feasible implementations, such as Figure 3 As shown in part b, the control circuit 103 ( Figure 3 (Not shown in the diagram) can be used to control the second switch R2 to be turned on and the first switch R1 to be turned off, and to input a detection signal to the second power transistor T2, control the first power transistor T1 to be normally turned on, and control the third power transistor T3 and the fourth power transistor T4 to be turned off, so as to prevent the second switch R2 from generating an induced voltage when the control circuit 103 inputs a detection signal to the second power transistor T2.

[0053] It is understood that when the detection system detects the second power transistor T2 in the multilevel converter 101, the control circuit 103 can control the second switch R2 to be turned on and the first switch R1 to be turned off, so as to construct a loop for detecting the second power transistor T2 and input a detection signal (e.g., a pulse signal) to the second power transistor T2. At the same time, it controls the first power transistor T1 to be turned on and controls the third power transistor T3 and the fourth power transistor T4 to be turned off, so as to conduct the loop for detecting the second power transistor T2. Furthermore, it can be understood that when the detection system detects the second power transistor T2 in the multilevel converter 101, the control circuit 103 can input a detection signal (e.g., a pulse signal) to the second power transistor T2. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the second power transistor T2 will change from a detection circuit that is conducting when the signal is high level to a detection circuit that is conducting when the signal is low level (or from a detection circuit that is conducting when the signal is low level to a detection circuit that is conducting when the signal is high level). Further, it can be understood that the detection circuit when the second power transistor T2 is conducting at a high level (e.g., Figure 3 As shown by the gray solid line arrow in part b, the circuit includes the inductor-second switch R2-capacitor-first power transistor T1-second power transistor T2-inductor and the detection circuit when the low level is on (e.g., Figure 3As shown by the gray dashed arrow in part b, in the sequence (inductor-second switch R2-fourth power transistor T4 (e.g., a diode connected in parallel with the fourth power transistor T4 or a parasitic diode in the fourth power transistor T4)-third power transistor T3 (e.g., a diode connected in parallel with the third power transistor T3 or a parasitic diode in the third power transistor T3)-inductor), the second switch R2 is always on, and the current flowing through the second switch R2 will not change abruptly, thus preventing the generation of an induced voltage. In other words, the detection system can prevent the second switch R2 from generating an induced voltage when the control circuit 103 inputs a detection signal to the second power transistor T2.

[0054] By employing the embodiments provided in this application, the switching transistor (e.g., the second switching transistor R2) of the detection system can be prevented from generating induced voltage when the power device under test (e.g., the second power transistor T2) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0055] In some feasible implementations, such as Figure 3 As shown in section c, the control circuit 103 ( Figure 3 (Not shown in the diagram) can be used to control the first switch R1 to be turned on and the second switch R2 to be turned off, and to input a detection signal to the third power transistor T3, control the fourth power transistor T4 to be turned on, and control the first power transistor T1 and the second power transistor T2 to be turned off, so as to prevent the first switch R1 from generating an induced voltage when the control circuit 103 inputs a detection signal to the third power transistor T3.

[0056] It is understood that when the detection system detects the third power transistor T3 in the multilevel converter 101, the control circuit 103 can control the first switch R1 to turn on and the second switch R2 to turn off, so as to form a loop for detecting the third power transistor T3 and input a detection signal (e.g., a pulse signal) to the third power transistor T3. At the same time, it controls the fourth power transistor T4 to be normally on and controls the first power transistor T1 and the second power transistor T2 to be turned off, so as to conduct the loop for detecting the third power transistor T3. Furthermore, it can be understood that when the detection system detects the third power transistor T3 in the multilevel converter 101, the control circuit 103 can input a detection signal (e.g., a pulse signal) to the third power transistor T3. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the third power transistor T3 will change from a detection circuit that is conducting when the signal is high level to a detection circuit that is conducting when the signal is low level (or from a detection circuit that is conducting when the signal is low level to a detection circuit that is conducting when the signal is high level). Further, it can be understood that the detection circuit when the third power transistor T3 is conducting at a high level (e.g., Figure 3 The gray solid line arrow in section c indicates the inductor-third power transistor T3-fourth power transistor T4-capacitor-first switching transistor R1-inductor) and the detection circuit when the low level is turned on (such as... Figure 3 As shown by the gray dashed arrow in section c, in the sequence (inductor - second power transistor T2 (e.g., a diode connected in parallel with the second power transistor T2 or a parasitic diode in the second power transistor T2) - first power transistor T1 (e.g., a diode connected in parallel with the first power transistor T1 or a parasitic diode in the first power transistor T1) - first switch transistor R1 - inductor), the first switch transistor R1 is always on, and the current flowing through the first switch transistor R1 will not change abruptly, thus preventing the generation of an induced voltage. In other words, the detection system can prevent the first switch transistor R1 from generating an induced voltage when the control circuit 103 inputs a detection signal to the third power transistor T3.

[0057] By employing the embodiments provided in this application, the switching transistors (e.g., the first switching transistor R1) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the third power transistor T3) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0058] In some feasible implementations, such as Figure 3 As shown in part d, the control circuit 103 ( Figure 3 (Not shown in the diagram) can be used to control the first switch R1 to be turned on and the second switch R2 to be turned off, and to input a detection signal to the fourth power transistor T4, control the third power transistor T3 to be turned on, and control the first power transistor T1 and the second power transistor T2 to be turned off, so as to prevent the first switch R1 from generating an induced voltage when the control circuit 103 inputs a detection signal to the fourth power transistor T4.

[0059] It is understood that when the detection system detects the fourth power transistor T4 in the multilevel converter 101, the control circuit 103 can control the first switch R1 to turn on and the second switch R2 to turn off, so as to form a loop for detecting the fourth power transistor T4 and input a detection signal (e.g., a pulse signal) to the fourth power transistor T4. At the same time, it controls the third power transistor T3 to be normally on and controls the first power transistor T1 and the second power transistor T2 to be turned off, so as to conduct the loop for detecting the fourth power transistor T4. Furthermore, it can be understood that when the detection system detects the fourth power transistor T4 in the multilevel converter 101, the control circuit 103 can input a detection signal (e.g., a pulse signal) to the fourth power transistor T4. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the fourth power transistor T4 will change from a detection circuit that is conducting when the level is high to a detection circuit that is conducting when the level is low (or from a detection circuit that is conducting when the level is low to a detection circuit that is conducting when the level is high). Further, it can be understood that the detection circuit when the fourth power transistor T4 is conducting at a high level (e.g., Figure 3 The gray solid line arrow in part d indicates the inductor-third power transistor T3-fourth power transistor T4-capacitor-first switching transistor R1-inductor) and the detection circuit when the low level is turned on (such as... Figure 3 As shown by the gray dashed arrow in part d, in the inductor-second power transistor T2 (e.g., a diode connected in parallel with the second power transistor T2 or a parasitic diode in the second power transistor T2)-first power transistor T1 (e.g., a diode connected in parallel with the first power transistor T1 or a parasitic diode in the first power transistor T1)-first switch transistor R1-inductor), the first switch transistor R1 is always on, and the current flowing through the first switch transistor R1 will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch transistor R1 from generating an induced voltage when the control circuit 103 inputs a detection signal to the fourth power transistor T4.

[0060] By employing the embodiments provided in this application, the switching transistors (e.g., the first switching transistor R1) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fourth power transistor T4) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0061] Please see Figure 4 , Figure 4 This is another structural schematic diagram of the detection system provided in the embodiments of this application. For example... Figure 4As shown, the multilevel converter 201 may further include a first diode D1 and a second diode D2. The connection relationship and function of the loop switching circuit 202 and the control circuit 203 are the same as those of the aforementioned loop switching circuit 102 and control circuit 103, and will not be repeated here. Here, the input terminal of the first diode D1 can be connected in series with the output terminal of the second diode D2, the output terminal of the first diode D1 can be connected to the series connection point of the first power transistor T1 and the second power transistor T2, and the input terminal of the second diode D2 can be connected to the series connection point of the third power transistor T3 and the fourth power transistor T4.

[0062] The implementation method provided in this application can prevent the switching transistor of the detection system from generating induced voltage when the power device under test switches between the on and off states. While improving the accuracy and safety of the detection system, the multilevel converter has a flexible and diverse structure that can adapt to different application scenarios, thus improving the applicability of the detection system.

[0063] Please see Figure 5 , Figure 5 This is another structural schematic diagram of the detection system provided in the embodiments of this application. For example... Figure 5 As shown, the multilevel converter 301 may further include a fifth power transistor T5 and a sixth power transistor T6, and the loop switching circuit 302 may further include a third switch R3 and a fourth switch R4. Here, the fifth power transistor T5 and the sixth power transistor T6 can be connected in series and then in parallel between the series connection point of the first power transistor T1 and the second power transistor T2, and the series connection point of the third power transistor T3 and the fourth power transistor T4. The other end of the inductor can be connected to the series connection point of the second power transistor T2 and the third power transistor T3 through the third switch R3, and the other end of the inductor can also be connected to the series connection point of the fifth power transistor T5 and the sixth power transistor T6 through the fourth switch R4. The control circuit 303 can be connected to the control input terminal of each power transistor in the multilevel converter 301.

[0064] Please see also Figure 6 , Figure 6 This is another schematic diagram of the power device detection circuit provided in an embodiment of this application. In some feasible implementations, such as... Figure 6 As shown in part a, the control circuit 303 ( Figure 6 (Not shown in the diagram) It can also be used to control the second switch R2 and the third switch R3 to be turned on, control the first switch R1 and the fourth switch R4 to be turned off and input a detection signal to the first power transistor T1, control the second power transistor T2 to be turned on normally, and control the third power transistor T3, the fourth power transistor T4, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to prevent the second switch R2 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the first power transistor T1.

[0065] It is understood that when the detection system detects the first power transistor T1 in the multilevel converter 301, the control circuit 303 can control the second switch R2 and the third switch R3 to be turned on, and control the first switch R1 and the fourth switch R4 to be turned off, so as to construct a loop for detecting the first power transistor T1 and input a detection signal (e.g., a pulse signal) to the first power transistor T1. At the same time, it controls the second power transistor T2 to be turned on normally, and controls the third power transistor T3, the fourth power transistor T4, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to conduct the loop for detecting the first power transistor T1. Furthermore, it can be understood that when the detection system detects the first power transistor T1 in the multilevel converter 301, the control circuit 303 can input a detection signal (e.g., a pulse signal) to the first power transistor T1. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the first power transistor T1 will change from a detection circuit that is conducting when the signal is high level to a detection circuit that is conducting when the signal is low level (or from a detection circuit that is conducting when the signal is low level to a detection circuit that is conducting when the signal is high level). Further, it can be understood that the detection circuit when the first power transistor T1 is conducting at a high level (e.g., Figure 6 As shown by the gray solid line arrow in part a, the circuit includes the inductor-second switch R2-capacitor-first power transistor T1-second power transistor T2-third switch R3-inductor and the detection circuit when the low level is on (e.g., Figure 6 As shown by the gray dashed arrow in part a, in the sequence (inductor-second switch R2-fourth power transistor T4 (e.g., a diode connected in parallel with the fourth power transistor T4 or a parasitic diode in the fourth power transistor T4)-third power transistor T3 (e.g., a diode connected in parallel with the third power transistor T3 or a parasitic diode in the third power transistor T3)-third switch R3-inductor), the second switch R2 and the third switch R3 are always on. The current flowing through the second switch R2 and the third switch R3 will not change abruptly and will not generate an induced voltage. In other words, the detection system can prevent the second switch R2 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the first power transistor T1.

[0066] By employing the embodiments provided in this application, the switching transistors (e.g., the second switching transistor R2 or the third switching transistor R3) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the first power transistor T1) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0067] In some feasible implementations, such as Figure 6As shown in part b, the control circuit 303 ( Figure 6 (Not shown in the diagram) It can also be used to control the second switch R2 and the third switch R3 to be turned on, control the first switch R1 and the fourth switch R4 to be turned off and input a detection signal to the second power transistor T2, control the first power transistor T1 to be turned on normally, and control the third power transistor T3, the fourth power transistor T4, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to prevent the second switch R2 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the second power transistor T2.

[0068] It is understood that when the detection system detects the second power transistor T2 in the multilevel converter 301, the control circuit 303 can control the second switch R2 and the third switch R3 to be turned on, and control the first switch R1 and the fourth switch R4 to be turned off, so as to construct a loop for detecting the second power transistor T2, and input a detection signal (e.g., a pulse signal) to the second power transistor T2. At the same time, it controls the first power transistor T1 to be turned on, and controls the third power transistor T3, the fourth power transistor T4, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to conduct the loop for detecting the second power transistor T2. Furthermore, it can be understood that when the detection system detects the second power transistor T2 in the multilevel converter 301, the control circuit 303 can input a detection signal (e.g., a pulse signal) to the second power transistor T2. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the second power transistor T2 will change from a detection circuit that is conducting when the signal is high level to a detection circuit that is conducting when the signal is low level (or from a detection circuit that is conducting when the signal is low level to a detection circuit that is conducting when the signal is high level). Further, it can be understood that the detection circuit when the second power transistor T2 is conducting at a high level (e.g., Figure 6 As shown by the gray solid line arrow in part b, the circuit includes the inductor-second switch R2-capacitor-first power transistor T1-second power transistor T2-third switch R3-inductor and the detection circuit when the low level is on (e.g., Figure 6 As shown by the gray dashed arrow in part b, in the sequence (inductor-second switch R2-fourth power transistor T4 (e.g., a diode connected in parallel with the fourth power transistor T4 or a parasitic diode in the fourth power transistor T4)-third power transistor T3 (e.g., a diode connected in parallel with the third power transistor T3 or a parasitic diode in the third power transistor T3)-third switch R3-inductor), the second switch R2 and the third switch R3 are always on. The current flowing through the second switch R2 and the third switch R3 will not change abruptly and will not generate an induced voltage. In other words, the detection system can prevent the second switch R2 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the second power transistor T2.

[0069] By employing the embodiments provided in this application, the switching transistors (e.g., the second switching transistor R2 or the third switching transistor R3) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the second power transistor T2) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0070] In some feasible implementations, such as Figure 6 As shown in section c, the control circuit 303 ( Figure 6 (Not shown in the diagram) It can also be used to control the first switch R1 and the third switch R3 to be turned on, control the second switch R2 and the fourth switch R4 to be turned off and input a detection signal to the third power transistor T3, control the fourth power transistor T4 to be turned on normally, and control the first power transistor T1, the second power transistor T2, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to prevent the first switch R1 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the third power transistor T3.

[0071] It is understood that when the detection system detects the third power transistor T3 in the multilevel converter 301, the control circuit 303 can control the first switch R1 and the third switch R3 to be turned on, and control the second switch R2 and the fourth switch R4 to be turned off, so as to construct a loop for detecting the third power transistor T3, and input a detection signal (e.g., a pulse signal) to the third power transistor T3, while controlling the fourth power transistor T4 to be normally turned on, and controlling the first power transistor T1, the second power transistor T2, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to conduct the loop for detecting the third power transistor T3. Furthermore, it can be understood that when the detection system detects the third power transistor T3 in the multilevel converter 301, the control circuit 303 can input a detection signal (e.g., a pulse signal) to the third power transistor T3. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the third power transistor T3 will change from a detection circuit that is conducting when the signal is high level to a detection circuit that is conducting when the signal is low level (or from a detection circuit that is conducting when the signal is low level to a detection circuit that is conducting when the signal is high level). Further, it can be understood that the detection circuit when the third power transistor T3 is conducting at a high level (e.g., Figure 6 As shown by the gray solid line arrow in section c, the circuit includes the inductor-third switch R3-third power transistor T3-fourth power transistor T4-capacitor-first switch R1-inductor and the detection circuit when the low level is on (e.g., Figure 6As shown by the gray dashed arrow in section c, in the sequence (inductor-third switch R3-second power transistor T2 (e.g., a diode connected in parallel with the second power transistor T2 or a parasitic diode in the second power transistor T2)-first power transistor T1 (e.g., a diode connected in parallel with the first power transistor T1 or a parasitic diode in the first power transistor T1)-first switch R1-inductor), the first switch R1 and the third switch R3 are always on. The current flowing through the first switch R1 and the third switch R3 will not change abruptly and will not generate an induced voltage. In other words, the detection system can prevent the first switch R1 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the third power transistor T3.

[0072] By employing the embodiments provided in this application, the switching transistors (e.g., the first switching transistor R1 or the third switching transistor R3) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the third power transistor T3) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0073] In some feasible implementations, such as Figure 6 As shown in part d, the control circuit 303 ( Figure 6 (Not shown in the diagram) It can also be used to control the first switch R1 and the third switch R3 to be turned on, control the second switch R2 and the fourth switch R4 to be turned off and input a detection signal to the fourth power transistor T4, control the third power transistor T3 to be turned on normally, and control the first power transistor T1, the second power transistor T2, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to prevent the first switch R1 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the fourth power transistor T4.

[0074] It is understood that when the detection system detects the fourth power transistor T4 in the multilevel converter 301, the control circuit 303 can control the first switch R1 and the third switch R3 to be turned on, and control the second switch R2 and the fourth switch R4 to be turned off, so as to construct a loop for detecting the fourth power transistor T4, and input a detection signal (e.g., a pulse signal) to the fourth power transistor T4. At the same time, it controls the third power transistor T3 to be turned on, and controls the first power transistor T1, the second power transistor T2, the fifth power transistor T5 and the sixth power transistor T6 to be turned off, so as to conduct the loop for detecting the fourth power transistor T4. Furthermore, it can be understood that when the detection system detects the fourth power transistor T4 in the multilevel converter 301, the control circuit 303 can input a detection signal (e.g., a pulse signal) to the fourth power transistor T4. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection circuit for the fourth power transistor T4 will change from a detection circuit that is conducting when the level is high to a detection circuit that is conducting when the level is low (or from a detection circuit that is conducting when the level is low to a detection circuit that is conducting when the level is high). Further, it can be understood that the detection circuit when the fourth power transistor T4 is conducting at a high level (e.g., Figure 6 The gray solid line arrow in part d indicates the inductor-third switch R3-third power transistor T3-fourth power transistor T4-capacitor-first switch R1-inductor) and the detection circuit when the low level is turned on (such as... Figure 6 As shown by the gray dashed arrow in part d, in the sequence (inductor-third switch R3-second power transistor T2 (e.g., a diode connected in parallel with the second power transistor T2 or a parasitic diode in the second power transistor T2)-first power transistor T1 (e.g., a diode connected in parallel with the first power transistor T1 or a parasitic diode in the first power transistor T1)-first switch R1-inductor), the first switch R1 and the third switch R3 are always on. The current flowing through the first switch R1 and the third switch R3 will not change abruptly and will not generate an induced voltage. In other words, the detection system can prevent the first switch R1 or the third switch R3 from generating an induced voltage when the control circuit 303 inputs a detection signal to the fourth power transistor T4.

[0075] By employing the embodiments provided in this application, the switching transistors (e.g., the first switching transistor R1 or the third switching transistor R3) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fourth power transistor T4) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0076] In some feasible implementations, such as Figure 6As shown in part e, the control circuit 303 ( Figure 6 (Not shown in the diagram) It can also be used to control the second switch R2 and the fourth switch R4 to be turned on, control the first switch R1 and the third switch R3 to be turned off and input a detection signal to the fifth power transistor T5, control the first power transistor T1 to be turned on normally, and control the second power transistor T2, the third power transistor T3, the fourth power transistor T4 and the sixth power transistor T6 to be turned off, so as to prevent the second switch R2 or the fourth switch R4 from generating an induced voltage when the control circuit 303 inputs a detection signal to the fifth power transistor T5.

[0077] It is understood that when the detection system detects the fifth power transistor T5 in the multilevel converter 101, and when the detection system detects the fifth power transistor T5 in the multilevel converter 301, the control circuit 303 can control the second switch R2 and the fourth switch R4 to be turned on, and control the first switch R1 and the third switch R3 to be turned off, so as to construct a loop for detecting the fifth power transistor T5, and input a detection signal (e.g., a pulse signal) to the fifth power transistor T5. At the same time, it controls the first power transistor T1 to be normally turned on, and controls the second power transistor T2, the third power transistor T3, the fourth power transistor T4 and the sixth power transistor T6 to be turned off, so as to conduct the loop for detecting the fifth power transistor T5. Furthermore, it can be understood that when the detection system detects the fifth power transistor T5 in the multilevel converter 301, the control circuit 303 can input a detection signal (e.g., a pulse signal) to the fifth power transistor T5. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fifth power transistor T5 will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the fifth power transistor T5 is high-level conducting (e.g., inductor-second switch transistor R2-capacitor-first power transistor T1-fifth power transistor T5-fourth switch transistor R4-inductor) and the detection circuit when it is low-level conducting (e.g., inductor-second switch transistor R2-fourth power transistor T4 (e.g., a diode connected in parallel with the fourth power transistor T4 or a parasitic diode in the fourth power transistor T4)-sixth power transistor T6 (e.g., a diode connected in parallel with the sixth power transistor T6 or a parasitic diode in the sixth power transistor T6)-fourth switch transistor R4-inductor), the second switch transistor R2 and the fourth switch transistor R4 are always conducting. The current flowing through the second switch transistor R2 and the fourth switch transistor R4 will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch transistor R2 or the fourth switch transistor R4 from generating an induced voltage when the control circuit 303 inputs a detection signal to the fifth power transistor T5.

[0078] By employing the embodiments provided in this application, the switching transistors (e.g., the second switching transistor R2 or the fourth switching transistor R4) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fifth power transistor T5) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0079] In some feasible implementations, such as Figure 6 As shown in part f, the control circuit 303 ( Figure 6 (Not shown in the diagram) It can also be used to control the first switch R1 and the fourth switch R4 to be turned on, control the second switch R2 and the third switch R3 to be turned off and input a detection signal to the sixth power transistor T6, control the fourth power transistor T4 to be turned on, and control the first power transistor T1, the second power transistor T2, the third power transistor T3 and the fifth power transistor T5 to be turned off, so as to prevent the first switch R1 or the fourth switch R4 from generating an induced voltage when the control circuit 303 inputs a detection signal to the sixth power transistor T6.

[0080] It is understood that when the detection system detects the sixth power transistor T6 in the multilevel converter 301, the control circuit 303 can control the first switch R1 and the fourth switch R4 to be turned on, and control the second switch R2 and the third switch R3 to be turned off, so as to construct a loop for detecting the sixth power transistor T6, and input a detection signal (e.g., a pulse signal) to the sixth power transistor T6. At the same time, it controls the fourth power transistor T4 to be turned on, and controls the first power transistor T1, the second power transistor T2, the third power transistor T3 and the fifth power transistor T5 to be turned off, so as to conduct the loop for detecting the sixth power transistor T6. Furthermore, it can be understood that when the detection system detects the sixth power transistor T6 in the multilevel converter 301, the control circuit 303 can input a detection signal (e.g., a pulse signal) to the sixth power transistor T6. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the sixth power transistor T6 will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the sixth power transistor T6 is high-level conducting (e.g., inductor-fourth switch R4-sixth power transistor T6-fourth power transistor T4-capacitor-first switch R1-inductor) and the detection circuit when the sixth power transistor T6 is low-level conducting (e.g., inductor-fourth switch R4-fifth power transistor T5 (e.g., a diode connected in parallel with the fifth power transistor T5 or a parasitic diode in the fifth power transistor T5)-first power transistor T1 (e.g., a diode connected in parallel with the first power transistor T1 or a parasitic diode in the first power transistor T1)-first switch R1-inductor), the first switch R1 and the fourth switch R4 are always conducting. The current flowing through the first switch R1 and the fourth switch R4 will not change abruptly and will not generate an induced voltage. In other words, the detection system can prevent the first switch R1 and the fourth switch R4 from generating an induced voltage when the control circuit 303 inputs a detection signal to the sixth power transistor T6.

[0081] By employing the embodiments provided in this application, the switching transistors (e.g., the first switching transistor R1 and the fourth switching transistor R4) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the sixth power transistor T6) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0082] In some feasible implementations, the detection system may also include at least one clamping circuit. See also... Figure 7 , Figure 7This is a schematic diagram showing the connection relationship between the clamping circuit and the multilevel controller provided in an embodiment of this application. Figure 7 As shown in parts a and b, a clamping circuit can connect the voltage input terminal (e.g., collector) of a power transistor to a control input terminal (e.g., gate) of the power transistor. This clamping circuit can be used to control the voltage value between the voltage input terminal (e.g., collector) and the voltage reference terminal (e.g., emitter) of a power transistor to be less than or equal to a voltage threshold.

[0083] Please see also Figure 8 , Figure 8 This is a schematic diagram illustrating the working principle of the clamping circuit provided in an embodiment of this application. Figure 8 As shown, when the control circuit (e.g., at time t0) controls a detected power transistor to switch from a high level to a low level, that is, when the power transistor changes from being on to being off, the voltage value between the voltage input terminal and the voltage reference terminal of the power transistor will increase. The clamping circuit can, when the voltage value between the voltage input terminal (e.g., collector) and the voltage reference terminal (e.g., emitter) of the power transistor is too high (e.g., greater than or equal to the voltage threshold) (e.g., at time t1), reduce the level of the voltage input terminal (e.g., collector) of the power transistor and increase the level of the control input terminal (e.g., gate) of the power transistor, so that the voltage value between the voltage input terminal (e.g., collector) and the voltage reference terminal (e.g., emitter) of the power transistor does not exceed the voltage threshold, while not changing the rate of change of the voltage value of the power transistor during the detection period (e.g., between time t0 and time t1).

[0084] By adopting the implementation method provided in this application, the voltage value between the voltage input terminal and the voltage reference terminal of the power transistor can be guaranteed not to exceed the voltage threshold without changing the rate of change of the voltage value of the power transistor during the detection period, thereby further improving the safety of the detection system. Moreover, the connection method of the clamping circuit is simple and flexible, which can reduce the detection cost.

[0085] In some feasible implementations, the detection system may also include a detection circuit to promptly disconnect the multilevel converter from the power supply in the event of a fault (e.g., latch-up). See also Figure 9 , Figure 9 This is another structural schematic diagram of the detection system provided in the embodiments of this application. For example... Figure 9As shown, the detection circuit 405 can be connected to the multilevel converter 401 and the control circuit 403. The connection relationship and function of the loop switching circuit 402 are the same as those of the aforementioned loop switching circuit 302, and will not be repeated here. Here, the detection circuit 405 can be connected to the series connection point of the second power transistor T2 and the third power transistor T3 in the multilevel converter 401, or the detection circuit 405 can be connected to the series connection point of the fifth power transistor T5 and the sixth power transistor T6 in the multilevel converter 401, or the detection circuit 405 can be connected to the connection point of the fourth power transistor T4 and the reference ground in the multilevel converter 401, or the detection circuit 405 can also be connected to other points that can detect the output current value of each power transistor in the multilevel converter 401. The specific connection can be determined according to the application scenario, and is not limited here. The detection circuit 405 can be used to obtain the output current value of any power transistor. The detection circuit 405 can also be used to disconnect the multilevel converter 401 through the control circuit 403 when the output current value of any power transistor is greater than or equal to the current threshold. It is understood that when the output current value of any power transistor is greater than or equal to the current threshold, disconnecting the multilevel converter 401 through the control circuit 403 is only one feasible implementation method provided by this application. The detection circuit 405 may also transmit a system protection signal to the control circuit 403, or the control circuit 403 may also take other corresponding protection measures. The specific implementation method can be determined according to the actual application scenario, and no specific restrictions are made here.

[0086] The implementation method provided in this application can prevent the switching transistor of the detection system from generating induced voltage when the power device under test switches between the on and off states, thereby improving the accuracy and safety of the detection system. At the same time, when the output current value of the power transistor exceeds the current threshold, the multilevel converter 401 is disconnected, further improving the safety of the detection system. Moreover, the connection method of the detection circuit 405 is simple and flexible, which can reduce the detection cost.

[0087] In some feasible implementations, to simulate the operating environment of a multilevel converter (e.g., high temperature, high voltage, or high input current), the detection system may also include a temperature control module, a voltage control module, or a current control module. See also... Figure 10 , Figure 10 This is another structural schematic diagram of the detection system provided in the embodiments of this application.

[0088] like Figure 10As shown, the detection system may further include a temperature control module 506, which can be connected to the multilevel converter 501. Here, the connection relationship and function of the loop switching circuit 502, control circuit 503, clamping circuit 504, and detection circuit 505 can be the same as those in any of the aforementioned feasible embodiments, and will not be repeated here. The temperature control module 506 can be used to control the detection temperature of the multilevel converter 501 (e.g., simulating the high-temperature operating environment of the multilevel converter).

[0089] In some feasible implementations, the detection system may also include a voltage control module 507, which may be connected to the multilevel converter 501. The voltage control module 507 can be used to control the detection voltage of the multilevel converter 501 (e.g., to simulate the high-voltage operating environment of the multilevel converter).

[0090] In some feasible implementations, the detection system may also include a current control module 508, which may be connected to the multilevel converter 501. The current control module 508 can be used to control the detection current of the multilevel converter 501 (e.g., to simulate the operating environment of a high input current of the multilevel converter).

[0091] In the embodiments provided in this application, the functional modules of the detection system can be composed in a variety of flexible ways, and different detection environments can be set to improve the diversity of application scenarios of the detection system and enhance the adaptability of the detection system.

[0092] Please see Figure 11 , Figure 11 This is a schematic flowchart of the detection method provided in an embodiment of this application. Figure 11 As shown, this detection method is applicable to the above-mentioned... Figures 1-10 The detection system shown in any of the accompanying figures, and the detection method, include the following steps:

[0093] S701: Control circuit controls the switching of each switching transistor in the control loop to turn on or off.

[0094] S702: The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter, except for any power transistor, to prevent any conducting switch from generating an induced voltage when the control circuit inputs a detection signal to any power transistor.

[0095] In the embodiments provided in this application, when the detection system detects a power transistor in a multilevel converter, the control circuit can control the on or off of each switch in the loop switching circuit to construct a loop for detecting this power transistor, and input a detection signal (e.g., a pulse signal) to this power transistor. Simultaneously, it controls the on or off of the power transistors in the multilevel converter other than this power transistor to activate the loop for detecting this power transistor. Further, it can be understood that when the detection system detects a power transistor in a multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to this power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting this power transistor will change from a detection loop activated at a high level to a detection loop activated at a low level (or from a detection loop activated at a low level to a detection loop activated at a high level). Furthermore, it can be understood that in the detection circuit when any power transistor is high-level on and in the detection circuit when it is low-level on, the control circuit controls the same switching transistor to be on, ensuring that the current flowing through the on switching transistor will not change abruptly and will not generate induced voltage. In other words, the detection system can prevent any on switching transistor from generating induced voltage when the control circuit inputs a detection signal to any power transistor.

[0096] By employing the embodiments provided in this application, the induced voltage generated by the switching transistor of the detection system when the power device under test (e.g., power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level) can be prevented, thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0097] In some feasible implementations, when the multilevel converter does not include the fifth and sixth power transistors, in step S701, the control circuit controlling the switching circuit of each switch transistor in the control loop to turn on or off includes: the control circuit controlling the second switch transistor to turn on and the first switch transistor to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the first power transistor, controls the second power transistor to be normally on, and controls the third and fourth power transistors to be off.

[0098] It is understandable that when the detection system detects the first power transistor in the multilevel converter, the control circuit can control the second switch to turn on and the first switch to turn off to construct a detection loop for the first power transistor, and input a detection signal (e.g., a pulse signal) to the first power transistor. Simultaneously, it controls the second power transistor to remain on and controls the third and fourth power transistors to turn off, thus activating the detection loop for the first power transistor. Further, it is understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the first power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the first power transistor will change from a detection loop activated at a high level to a detection loop activated at a low level (or from a detection loop activated at a low level to a detection loop activated at a high level). Furthermore, it can be understood that in the detection circuit when the first power transistor is high-level conducting (e.g., inductor-second switch-capacitor-first power transistor-second power transistor-inductor) and the detection circuit when the first power transistor is low-level conducting (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-inductor), the second switch transistor is always conducting, the current flowing through the second switch transistor will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch transistor from generating an induced voltage when the control circuit inputs a detection signal to the first power transistor.

[0099] By employing the embodiments provided in this application, the switching transistor (e.g., the second switching transistor) of the detection system can be prevented from generating induced voltage when the power device under test (e.g., the first power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0100] In some feasible implementations, when the multilevel converter does not include the fifth and sixth power transistors, in step S701, the control circuit controlling the switching circuit of each switch transistor in the control loop to turn on or off includes: the control circuit controlling the second switch transistor to turn on and the first switch transistor to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the first power transistor, controls the second power transistor to be normally on, and controls the third and fourth power transistors to be off.

[0101] It is understandable that when the detection system detects the second power transistor in the multilevel converter, the control circuit can control the second switch to be turned on and the first switch to be turned off to construct a detection loop for the second power transistor, and input a detection signal (e.g., a pulse signal) to the second power transistor, while controlling the first power transistor to be constantly on and controlling the third and fourth power transistors to be turned off to conduct the detection loop for the second power transistor. Further, it is understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the second power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the second power transistor will change from a detection loop that is on when the level is high to a detection loop that is on when the level is low (or from a detection loop that is on when the level is low to a detection loop that is on when the level is high). Furthermore, it can be understood that in the detection circuit when the second power transistor is high-level conducting (e.g., inductor-second switch-capacitor-first power transistor-second power transistor-inductor) and the detection circuit when the second power transistor is low-level conducting (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-inductor), the second switch transistor is always conducting, the current flowing through the second switch transistor will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second switch transistor from generating an induced voltage when the control circuit inputs a detection signal to the second power transistor.

[0102] By employing the embodiments provided in this application, the switching transistor (e.g., the second switching transistor) of the detection system can be prevented from generating induced voltage when the power device under test (e.g., the second power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0103] In some feasible implementations, when the multilevel converter does not include the fifth and sixth power transistors, in step S701, the control circuit controlling the switching circuit of each switch transistor in the switching circuit to turn on or off includes: the control circuit controlling the second switch transistor to turn on and the first switch transistor to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the second power transistor, controls the first power transistor to be normally on, and controls the third and fourth power transistors to be off.

[0104] It is understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can control the first switch to turn on and the second switch to turn off to establish a detection loop for the third power transistor, and input a detection signal (e.g., a pulse signal) to the third power transistor. Simultaneously, it controls the fourth power transistor to remain on and controls the first and second power transistors to turn off, thus activating the detection loop for the third power transistor. Further, it is understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the third power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the third power transistor will change from a detection loop activated at a high level to a detection loop activated at a low level (or from a detection loop activated at a low level to a detection loop activated at a high level). Furthermore, it can be understood that in the detection circuit when the third power transistor is high-level conducting (e.g., inductor-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the third power transistor is low-level conducting (e.g., inductor-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first switch is always conducting, the current flowing through the first switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch from generating an induced voltage when the control circuit inputs a detection signal to the third power transistor.

[0105] By employing the embodiments provided in this application, the switching transistor (e.g., the first switching transistor) of the detection system can be prevented from generating induced voltage when the power device under test (e.g., the third power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0106] In some feasible implementations, when the multilevel converter does not include the fifth and sixth power transistors, in step S701, the control circuit controlling the switching circuit of each switch transistor in the control loop to turn on or off includes: the control circuit controlling the second switch transistor to turn on and the first switch transistor to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the third power transistor, controls the fourth power transistor to be normally on, and controls the first and second power transistors to be off.

[0107] It is understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can control the first switch to turn on and the second switch to turn off to establish a detection loop for the fourth power transistor, and input a detection signal (e.g., a pulse signal) to the fourth power transistor. Simultaneously, it controls the third power transistor to remain on and controls the first and second power transistors to turn off, thus activating the detection loop for the fourth power transistor. Further, it is understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fourth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fourth power transistor will change from a detection loop activated at a high level to a detection loop activated at a low level (or from a detection loop activated at a low level to a detection loop activated at a high level). Furthermore, it can be understood that in the detection circuit when the fourth power transistor is high-level conducting (e.g., inductor-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the fourth power transistor is low-level conducting (e.g., inductor-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first switch is always conducting, the current flowing through the first switch will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first switch from generating an induced voltage when the control circuit inputs a detection signal to the fourth power transistor.

[0108] By employing the embodiments provided in this application, the switching transistor (e.g., the first switching transistor) of the detection system can be prevented from generating induced voltage when the power device under test (e.g., the fourth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0109] In some feasible implementations, when the multilevel converter includes a fifth power transistor and a sixth power transistor, in step S701, the control circuit controlling the switching circuit of each switch transistor in the switching circuit to turn on or off includes: the control circuit controlling the second and third switch transistors to turn on, and controlling the first and fourth switch transistors to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the first power transistor, controls the second power transistor to be normally on, and controls the third, fourth, fifth, and sixth power transistors to be off.

[0110] It can be understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can control the second and third switches to be turned on, and control the first and fourth switches to be turned off, to construct a loop for detecting the first power transistor. A detection signal (e.g., a pulse signal) is input to the first power transistor, while the second power transistor is kept on, and the third, fourth, fifth, and sixth power transistors are turned off, to conduct the loop for detecting the first power transistor. Further, it can be understood that when the detection system detects the first power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the first power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting the first power transistor will change from a detection loop that is active when the signal is high to a detection loop that is active when the signal is low (or from a detection loop that is active when the signal is low to a detection loop that is active when the signal is high). Furthermore, it can be understood that the detection circuit when the first power transistor is high-level conducting (such as...) Figure 6 As shown by the gray solid line arrow in part a, the circuit consists of inductor-second switch-capacitor-first power transistor-second power transistor-third switch-inductor and the detection circuit when the low level is on (e.g., Figure 6 As shown by the gray dashed arrow in part a, in the sequence (inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-third switch-inductor), the second and third switches are always on, and the current flowing through the second and third switches will not change abruptly, thus preventing the generation of induced voltage. In other words, the detection system can prevent the second or third switch from generating induced voltage when the control circuit inputs a detection signal to the first power transistor.

[0111] By employing the embodiments provided in this application, the switching transistors (e.g., the second or third switching transistor) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the first power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0112] In some feasible implementations, when the multilevel converter includes a fifth power transistor and a sixth power transistor, in step S701, the control circuit controlling the switching circuit of each switch transistor in the control loop to turn on or off includes: the control circuit controlling the second and third switch transistors to turn on, and controlling the first and fourth switch transistors to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the second power transistor, controls the first power transistor to be normally on, and controls the third, fourth, fifth, and sixth power transistors to be off.

[0113] It can be understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can control the second and third switching transistors to turn on, and control the first and fourth switching transistors to turn off, to construct a loop for detecting the second power transistor. A detection signal (e.g., a pulse signal) is input to the second power transistor, while the first power transistor is kept on, and the third, fourth, fifth, and sixth power transistors are turned off, to conduct the loop for detecting the second power transistor. Further, it can be understood that when the detection system detects the second power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the second power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting the second power transistor will change from a detection loop that conducts when the signal is high to a detection loop that conducts when the signal is low (or from a detection loop that conducts when the signal is low to a detection loop that conducts when the signal is high). Furthermore, it can be understood that the detection circuit when the second power transistor is high-level conducting (such as...) Figure 6 As shown by the gray solid line arrow in part b, the circuit consists of inductor-second switch-capacitor-first power transistor-second power transistor-third switch-inductor and the detection circuit when the low-level conduction is enabled (e.g., Figure 6 As shown by the gray dashed arrow in part b, in the sequence (inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-third power transistor (e.g., a diode connected in parallel with the third power transistor or a parasitic diode in the third power transistor)-third switch-inductor), the second and third switches are always on. The current flowing through the second and third switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second or third switch from generating an induced voltage when the control circuit inputs a detection signal to the second power transistor.

[0114] By employing the embodiments provided in this application, the switching transistors (e.g., the second or third switching transistor) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the second power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0115] In some feasible implementations, when the multilevel converter includes a fifth power transistor and a sixth power transistor, in step S701, the control circuit controlling the switching circuit of each switch transistor in the control loop to turn on or off includes: the control circuit controlling the first and third switch transistors to turn on, and controlling the second and fourth switch transistors to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the third power transistor, controls the fourth power transistor to be normally on, and controls the first, second, fifth, and sixth power transistors to be off.

[0116] It is understandable that when the detection system detects the third power transistor in the multilevel converter, the control circuit can control the first and third switching transistors to turn on, and control the second and fourth switching transistors to turn off, to construct a loop for detecting the third power transistor. A detection signal (e.g., a pulse signal) is input to the third power transistor, while the fourth power transistor is kept on, and the first, second, fifth, and sixth power transistors are turned off, to conduct the loop for detecting the third power transistor. Further, it is understood that when the detection system detects the third power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the third power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting the third power transistor will change from a detection loop that conducts when the signal is high to a detection loop that conducts when the signal is low (or from a detection loop that conducts when the signal is low to a detection loop that conducts when the signal is high). Furthermore, it can be understood that the detection circuit when the third power transistor is high-level conducting (such as...) Figure 6 The gray solid line arrow in section c indicates the inductor-third switch-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the low level is turned on (such as...). Figure 6As shown by the gray dashed arrow in section c, in the sequence (inductor-third switch-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first and third switches are always on. The current flowing through the first and third switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first or third switch from generating an induced voltage when the control circuit inputs a detection signal to the third power transistor.

[0117] By employing the embodiments provided in this application, the switching transistors (e.g., the first switching transistor or the third switching transistor) of the detection system can be prevented from generating induced voltages when the power device being detected (e.g., the third power transistor) switches between the on and off states (e.g., the detection signal changes from a high level to a low level or from a low level to a high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0118] In some feasible implementations, when the multilevel converter includes a fifth power transistor and a sixth power transistor, in step S701, the control circuit controlling the switching circuit of each switch transistor in the switching circuit to turn on or off includes: the control circuit controlling the first and third switch transistors to turn on, and controlling the second and fourth switch transistors to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the fourth power transistor, controls the third power transistor to be normally on, and controls the first, second, fifth, and sixth power transistors to be off.

[0119] It is understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can control the first and third switching transistors to turn on, and control the second and fourth switching transistors to turn off, to construct a loop for detecting the fourth power transistor. A detection signal (e.g., a pulse signal) is input to the fourth power transistor, while the third power transistor is kept constantly on, and the first, second, fifth, and sixth power transistors are turned off, to conduct the loop for detecting the fourth power transistor. Further, it is understood that when the detection system detects the fourth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fourth power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting the fourth power transistor will change from a detection loop that conducts when the signal is high to a detection loop that conducts when the signal is low (or from a detection loop that conducts when the signal is low to a detection loop that conducts when the signal is high). Furthermore, it can be understood that the detection circuit when the fourth power transistor is high-level conducting (such as...) Figure 6 The gray solid line arrow in part d indicates the inductor-third switch-third power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the low level is turned on (such as... Figure 6 As shown by the gray dashed arrow in part d, in the sequence (inductor-third switch-second power transistor (e.g., a diode connected in parallel with the second power transistor or a parasitic diode in the second power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first and third switches are always on. The current flowing through the first and third switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first or third switch from generating an induced voltage when the control circuit inputs a detection signal to the fourth power transistor.

[0120] By employing the embodiments provided in this application, the switching transistors (e.g., the first or third switching transistor) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fourth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0121] In some feasible implementations, when the multilevel converter includes a fifth power transistor and a sixth power transistor, in step S701, the control circuit controlling the switching circuit of each switch transistor in the control loop to turn on or off includes: the control circuit controlling the second and fourth switch transistors to turn on, and controlling the first and third switch transistors to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the fifth power transistor, controls the first power transistor to be normally on, and controls the second, third, fourth, and sixth power transistors to be off.

[0122] It is understood that when the detection system detects the fifth power transistor in the multilevel converter 101, the control circuit can control the second and fourth switching transistors to be turned on, and control the first and third switching transistors to be turned off, so as to construct a loop for detecting the fifth power transistor, and input a detection signal (e.g., a pulse signal) to the fifth power transistor, while controlling the first power transistor to be normally turned on, and controlling the second, third, fourth and sixth power transistors to be turned off, so as to conduct the loop for detecting the fifth power transistor. Furthermore, it can be understood that when the detection system detects the fifth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the fifth power transistor. When the detection signal switches from high level to low level (or from low level to high level), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the detection loop for the fifth power transistor will change from a detection loop that is conducting when the level is high to a detection loop that is conducting when the level is low (or from a detection loop that is conducting when the level is low to a detection loop that is conducting when the level is high). Furthermore, it can be understood that in the detection circuit when the fifth power transistor is high-level conducting (e.g., inductor-second switch-capacitor-first power transistor-fifth power transistor-fourth switch-inductor) and the detection circuit when the fifth power transistor is low-level conducting (e.g., inductor-second switch-fourth power transistor (e.g., a diode connected in parallel with the fourth power transistor or a parasitic diode in the fourth power transistor)-sixth power transistor (e.g., a diode connected in parallel with the sixth power transistor or a parasitic diode in the sixth power transistor)-fourth switch-inductor), the second and fourth switches are always conducting. The current flowing through the second and fourth switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the second or fourth switch from generating an induced voltage when the control circuit inputs a detection signal to the fifth power transistor.

[0123] By employing the embodiments provided in this application, the switching transistors (e.g., the second or fourth switching transistor) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the fifth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0124] In some feasible implementations, when the multilevel converter includes a fifth power transistor and a sixth power transistor, in step S701, the control circuit controlling the switching circuit of each switch transistor in the switching circuit to turn on or off includes: the control circuit controlling the first and fourth switch transistors to turn on, and controlling the second and third switch transistors to turn off. In step S702, the control circuit inputs a detection signal to any power transistor and controls the other power transistors in the multilevel converter to turn on or off, including: the control circuit inputs a detection signal to the sixth power transistor, controls the fourth power transistor to be normally on, and controls the first, second, third, and fifth power transistors to be off.

[0125] It is understandable that when the detection system detects the sixth power transistor in the multilevel converter, the control circuit can control the first and fourth switching transistors to turn on, and control the second and third switching transistors to turn off, to construct a loop for detecting the sixth power transistor. A detection signal (e.g., a pulse signal) is input to the sixth power transistor, while the fourth power transistor is kept constantly on, and the first, second, third, and fifth power transistors are turned off, to conduct the loop for detecting the sixth power transistor. Further, it is understood that when the detection system detects the sixth power transistor in the multilevel converter, the control circuit can input a detection signal (e.g., a pulse signal) to the sixth power transistor. When the detection signal switches from high to low (or from low to high), the inductor in the detection system will switch from a charged state to a discharged state (or from a discharged state to a charged state). At this time, the loop for detecting the sixth power transistor will change from a detection loop that conducts when the signal is high to a detection loop that conducts when the signal is low (or from a detection loop that conducts when the signal is low to a detection loop that conducts when the signal is high). Furthermore, it can be understood that in the detection circuit when the sixth power transistor is high-level conducting (e.g., inductor-fourth switch-sixth power transistor-fourth power transistor-capacitor-first switch-inductor) and the detection circuit when the sixth power transistor is low-level conducting (e.g., inductor-fourth switch-fifth power transistor (e.g., a diode connected in parallel with the fifth power transistor or a parasitic diode in the fifth power transistor)-first power transistor (e.g., a diode connected in parallel with the first power transistor or a parasitic diode in the first power transistor)-first switch-inductor), the first and fourth switches are always conducting. The current flowing through the first and fourth switches will not change abruptly, and no induced voltage will be generated. In other words, the detection system can prevent the first and fourth switches from generating induced voltage when the control circuit inputs a detection signal to the sixth power transistor.

[0126] By employing the embodiments provided in this application, the switching transistors (e.g., the first and fourth switching transistors) of the detection system can be prevented from generating induced voltages when the power device under test (e.g., the sixth power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0127] In this application, the detection system can prevent the switching transistor of the detection system from generating induced voltage when the power device under test (e.g., power transistor) switches between the on and off states (e.g., the detection signal changes from high level to low level or from low level to high level), thereby improving the accuracy and safety of the detection system, increasing detection efficiency, and reducing detection costs.

[0128] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A power device detection system, characterized by, The detection system includes a multilevel converter, a control circuit, and a loop switching circuit. The multilevel converter includes a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor. The loop switching circuit includes a first switching transistor, a second switching transistor, a capacitor, and an inductor. The first power transistor, the second power transistor, the third power transistor, and the fourth power transistor are connected in series. The first switching transistor and the second switching transistor are connected in series and then in parallel with the capacitor. The voltage input terminal of the first power transistor serves as the voltage input terminal of the multilevel converter and is connected to the voltage input terminal of the first switching transistor and the detection system. The voltage reference terminal of the fourth power transistor serves as the ground terminal of the multilevel converter and is connected to the second switching transistor and the reference ground. One end of the inductor is connected to the series connection point of the first switching transistor and the second switching transistor, and the other end of the inductor is connected to the series connection point of the second power transistor and the third power transistor. The control circuit is connected to the control input terminals of each power transistor in the multilevel converter. The control circuit is used to control the on or off of each switch in the loop switching circuit and to input a detection signal to any power transistor, and to control the on or off of other power transistors in the multilevel converter except for the power transistor, so as to prevent any on switch from generating an induced voltage when the control circuit inputs the detection signal to the power transistor.

2. The detection system of claim 1, wherein, The control circuit is used to control the second switch to be turned on and the first switch to be turned off, and to input the detection signal to the first power transistor, control the second power transistor to be normally on, and control the third power transistor and the fourth power transistor to be turned off, so as to prevent the second switch from generating an induced voltage when the control circuit inputs the detection signal to the first power transistor.

3. The detection system of claim 1, wherein, The control circuit is used to control the second switch to be turned on and the first switch to be turned off, and to input the detection signal to the second power transistor, control the first power transistor to be normally turned on, and control the third power transistor and the fourth power transistor to be turned off, so as to prevent the second switch from generating an induced voltage when the control circuit inputs the detection signal to the second power transistor.

4. The detection system of claim 1, wherein, The control circuit is used to control the first switch to be turned on and the second switch to be turned off, and to input the detection signal to the third power transistor, control the fourth power transistor to be turned on, and control the first power transistor and the second power transistor to be turned off, so as to prevent the first switch from generating an induced voltage when the control circuit inputs the detection signal to the third power transistor.

5. The detection system of claim 1, wherein, The control circuit is used to control the first switch to be turned on and the second switch to be turned off, and to input the detection signal to the fourth power transistor, control the third power transistor to be turned on normally, and control the first power transistor and the second power transistor to be turned off, so as to prevent the first switch from generating an induced voltage when the control circuit inputs the detection signal to the fourth power transistor.

6. The detection system of claim 1, wherein, The multilevel converter also includes a first diode and a second diode; The input terminal of the first diode and the output terminal of the second diode are connected in series. The output terminal of the first diode is connected to the series connection point of the first power transistor and the second power transistor. The input terminal of the second diode is connected to the series connection point of the third power transistor and the fourth power transistor.

7. The detection system of claim 1, wherein, The multilevel converter also includes a fifth power transistor and a sixth power transistor, and the loop switching circuit also includes a third switch transistor and a fourth switch transistor; The fifth and sixth power transistors are connected in series and then in parallel between the series connection point of the first and second power transistors and the series connection point of the third and fourth power transistors. The other end of the inductor is connected to the series connection point of the second and third power transistors through the third switch transistor. The other end of the inductor is also connected to the series connection point of the fifth and sixth power transistors through the fourth switch transistor. The control circuit is connected to the control input terminal of each power transistor in the multilevel converter. The control circuit is also used to control the second and fourth switching transistors to be turned on, control the first and third switching transistors to be turned off and input the detection signal to the fifth power transistor, control the first power transistor to be normally turned on, and control the second, third, fourth and sixth power transistors to be turned off, so as to prevent the second or fourth switching transistor from generating an induced voltage when the control circuit inputs the detection signal to the fifth power transistor.

8. The detection system of claim 7, wherein, The control circuit is also used to control the first switch and the fourth switch to be turned on, control the second switch and the third switch to be turned off and input the detection signal to the sixth power transistor, control the fourth power transistor to be turned on normally, and control the first power transistor, the second power transistor, the third power transistor and the fifth power transistor to be turned off, so as to prevent the first switch or the fourth switch from generating an induced voltage when the control circuit inputs the detection signal to the sixth power transistor.

9. The detection system according to any one of claims 1 to 8, characterized in that The power transistors in the detection system are insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field-effect transistors (MOSFETs), or silicon carbide transistors (SiCs).

10. The detection system according to any one of claims 1-8, characterized in that, The detection system also includes at least one clamping circuit, which is connected to the voltage input terminal of a power transistor and the control input terminal of the power transistor. The clamping circuit is used to control the voltage value between the voltage input terminal and the voltage reference terminal of any power transistor to be less than or equal to a voltage threshold.

11. The detection system of claim 10, wherein, The detection system further includes a detection circuit, which is connected to the multilevel converter and the control circuit. The detection circuit is used to obtain the output current value of any one of the power transistors; The detection circuit is also used to disconnect the multilevel converter via the control circuit when the output current value of any power transistor is greater than or equal to the current threshold.

12. The detection system of claim 11, wherein, The detection system also includes a temperature control module, which is connected to the multilevel converter. The temperature control module is used to control the detection temperature of the multilevel converter.

13. The detection system of claim 12, wherein, The detection system also includes a voltage control module, which is connected to the multilevel converter. The voltage control module is used to control the detection voltage of the multilevel converter.

14. The detection system of claim 13, wherein, The detection system also includes a current control module, which is connected to the multilevel converter. The current control module is used to control the detection current of the multilevel converter.

15. A power device detection method, characterized by, The detection method is applicable to the detection system as described in any one of claims 1-14, and the method includes: The control circuit controls the on or off of each switching transistor in the loop switching circuit; The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter, except for the power transistor mentioned above, to prevent any conducting switch from generating an induced voltage when the control circuit inputs the detection signal to the power transistor.

16. The detection method of claim 15, wherein, When the multilevel converter does not include the fifth and sixth power transistors, the control circuit controls the on or off of each switch in the loop switching circuit, including: The control circuit controls the second switch to be turned on and the first switch to be turned off. The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter besides the stated power transistor, including: The control circuit inputs the detection signal to the first power transistor, controls the second power transistor to be constantly on, and controls the third and fourth power transistors to be turned off.

17. The detection method of claim 16, wherein, The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter besides the stated power transistor, including: The control circuit inputs the detection signal to the first power transistor, controls the second power transistor to be constantly on, and controls the third and fourth power transistors to be turned off.

18. The method of claim 15, wherein, When the multilevel converter does not include the fifth and sixth power transistors, the control circuit controls the on or off of each switch in the loop switching circuit, including: The control circuit controls the second switch to be turned on and the first switch to be turned off. The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter besides the stated power transistor, including: The control circuit inputs the detection signal to the second power transistor, controls the first power transistor to be constantly on, and controls the third and fourth power transistors to be turned off.

19. The detection method of claim 18, wherein, The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter besides the stated power transistor, including: The control circuit inputs the detection signal to the third power transistor, controls the fourth power transistor to be constantly on, and controls the first power transistor and the second power transistor to be off.

20. The method of claim 15, wherein, When the multilevel converter further includes a fifth power transistor and a sixth power transistor, the control circuit controls the on or off of each switching transistor in the loop switching circuit, including: The control circuit controls the second and fourth switching transistors to turn on, and controls the first and third switching transistors to turn off; The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter besides the stated power transistor, including: The control circuit inputs the detection signal to the fifth power transistor, controls the first power transistor to be constantly on, and controls the second, third, fourth and sixth power transistors to be off.

21. The method of claim 20, wherein, The control circuit controls the on or off of each switch in the loop switching circuit, including: The control circuit controls the first and fourth switching transistors to turn on, and controls the second and third switching transistors to turn off; The control circuit inputs a detection signal to any power transistor and controls the conduction or cutoff of other power transistors in the multilevel converter besides the stated power transistor, including: The control circuit inputs the detection signal to the sixth power transistor, controls the fourth power transistor to be constantly on, and controls the first power transistor, the second power transistor, the third power transistor, and the fifth power transistor to be off.

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