Pixel circuit, driving method thereof and display panel

Abstract

The application discloses a pixel circuit and a driving method thereof, and a display panel. The pixel circuit comprises a first initialization unit, a writing unit, a multiplexing unit and a first storage capacitor. The first storage capacitor is electrically connected to a first node and a second node. The writing unit writes a signal of a data signal end into the first node and writes a potential of a set signal end into a fourth node based on the control of a writing control end. The multiplexing unit writes a potential of a first power signal end into the fourth node in a compensation stage based on the control of a first multiplexing control end, writes a potential of a fifth node into a third node in an initialization stage based on the control of a second multiplexing control end, and transmits a driving current to the fifth node in a light-emitting stage based on the control of the first multiplexing control end and the second multiplexing control end, so as to drive a light-emitting unit to emit light. The pixel circuit can perform threshold compensation and data writing in different time periods, and can improve the conflict between compensation time and high refresh rate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit and its driving method, as well as a display panel. Background Technology

[0002] In existing pixel circuits, threshold compensation for the driving transistor is performed simultaneously during the data writing phase to the transistor's gate. The compensation process is only complete when the control gate potential of the driving transistor reaches Data + Vth (the sum of the data signal voltage and the threshold voltage). Because this compensation time is relatively long, when a higher display refresh rate is required, the significantly reduced data scanning pulse width leads to insufficient threshold compensation; conversely, ensuring sufficient compensation fails to meet high refresh rate requirements. Therefore, a conflict exists between the effectiveness of threshold compensation and the need to increase the refresh rate, ultimately affecting the display quality. Summary of the Invention

[0003] To address at least one of the aforementioned problems, a first aspect of this application provides a pixel circuit, comprising: a first initialization unit, a drive control unit, a writing unit, a multiplexing unit, a first storage capacitor, and a light-emitting unit, wherein...

[0004] The first initialization unit is electrically connected to the first node, the first initialization signal terminal, and the first initialization control terminal, and is configured to initialize the potential of the first node based on the signal input to the first initialization control terminal.

[0005] The drive control unit is electrically connected to the drive control terminal, the second node, the third node, the fourth node, and the first power signal terminal, and is configured to generate drive current in response to the signal from the drive control terminal.

[0006] The first storage capacitor is electrically connected to the first node and the second node;

[0007] The writing unit includes a first writing unit and a second writing unit. The first writing unit is electrically connected to a data signal terminal, a write control terminal, and a first node. The second writing unit is electrically connected to a fourth node, a write control terminal, and a set signal terminal. It is configured to write the signal from the data signal terminal to the first node and write the potential of the set signal terminal to the fourth node based on the control of the write control terminal.

[0008] The multiplexing unit is electrically connected to a first power signal terminal, a first multiplexing control terminal, a second multiplexing control terminal, a fourth node, a third node, and a fifth node. It is configured to write the potential of the first power signal terminal to the fourth node during the compensation phase based on the control of the first multiplexing control terminal, write the potential of the fifth node to the third node during the initialization phase based on the control of the second multiplexing control terminal, and transmit the driving current to the fifth node during the light emission phase based on the control of the first multiplexing control terminal and the second multiplexing control terminal to drive the light emission unit to emit light.

[0009] In some optional embodiments, the first write unit includes a first transistor, and the second write unit includes a second transistor, wherein,

[0010] The first electrode of the first transistor is electrically connected to the data signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the write control terminal.

[0011] The first electrode of the second transistor is connected to the set signal terminal, the second electrode is connected to the fourth node, and the control electrode is connected to the write control terminal.

[0012] In some optional embodiments, the pixel circuit further includes: a second initialization unit electrically connected to the fifth node, the second initialization signal terminal, and the second initialization control terminal, configured to initialize the potential of the fifth node based on the signal accessed by the second initialization control terminal.

[0013] In some optional embodiments, the multiplexing unit includes a third transistor and a fourth transistor, wherein,

[0014] The first electrode of the third transistor is connected to the first power signal terminal, the second electrode is connected to the fourth node, and the control electrode is connected to the first multiplexing control terminal.

[0015] The first electrode of the fourth transistor is connected to the third node, the second electrode is connected to the fifth node, and the control electrode is connected to the second multiplexed control terminal.

[0016] In some alternative embodiments, the drive control unit includes: a fifth transistor, a sixth transistor, and a second storage capacitor, wherein,

[0017] The first electrode of the fifth transistor is connected to the fourth node, the second electrode is connected to the third node, and the control electrode is connected to the second node.

[0018] The first electrode of the sixth transistor is connected to the third node, the second electrode is connected to the second node, and the control electrode is connected to the drive control terminal.

[0019] The first end of the second storage capacitor is electrically connected to the first power signal terminal, and the second end is electrically connected to the second node.

[0020] In some alternative embodiments, the first initialization unit includes: a seventh transistor, wherein,

[0021] The first electrode of the seventh transistor is connected to the first initialization signal terminal, the second electrode is connected to the first node, and the control electrode is connected to the first initialization control terminal.

[0022] In some optional embodiments, the second initialization unit includes: an eighth transistor, wherein,

[0023] The first electrode of the eighth transistor is connected to the second initialization signal terminal, the second electrode is connected to the fifth node, and the control electrode is connected to the second initialization control terminal.

[0024] A second aspect of this application provides a display panel including the pixel circuit described above.

[0025] A second aspect of this application provides a driving method for the pixel circuit described above, comprising:

[0026] Initialization phase: The first initialization unit responds to the signal accessed by the first initialization control terminal and initializes the first node using the potential of the initialization signal terminal; the multiplexing unit responds to the signal accessed by the second multiplexing control terminal and writes the potential of the fifth node into the third node to initialize the second node.

[0027] Compensation phase: The multiplexing unit responds to the signal accessed by the first multiplexing control terminal by writing the potential of the first power signal terminal into the fourth node, and the drive control unit responds to the signal accessed by the drive control terminal by using the potential of the fourth node to compensate the voltage of the second node.

[0028] Write phase: In response to the signal received by the write control terminal, the signal at the data signal terminal is written to the first node, and the signal at the set signal terminal is written to the fourth node; and

[0029] Light emission stage: In response to the signals connected to the first multiplexing control terminal and the second multiplexing control terminal, the multiplexing unit transmits the resulting driving current to the light emission unit to drive the light emission unit to emit light.

[0030] In some optional embodiments, the pixel circuit further includes a second initialization unit configured to initialize the potential of the fifth node based on a signal received from the second initialization control terminal, wherein,

[0031] During the initialization phase, the signal connected to the second initialization control terminal becomes active earlier than the signal connected to the first initialization control terminal.

[0032] During the writing phase, the signal connected to the second initialization control terminal becomes invalid earlier than the signal connected to the second multiplexing control terminal becomes valid.

[0033] The beneficial effects of this application are as follows:

[0034] This application addresses existing problems by providing a pixel circuit, its driving method, and a display panel. By providing a first storage capacitor disposed between a first node and a second node, including a first writing unit, a second writing unit, and a multiplexing unit, the data writing and compensation stages can be separated. The first writing unit writes the data signal, and the multiplexing unit cooperates with the input compensation voltage during the compensation stage to achieve staged threshold compensation and data writing. This not only fully compensates the threshold voltage of the driving transistor but also meets the requirements of high refresh rates, improving the display effect and showing broad application prospects. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A pixel circuit block diagram according to an embodiment of this application is shown;

[0037] Figure 2 A circuit schematic diagram of a pixel circuit according to an embodiment of this application is shown;

[0038] Figure 3 A timing diagram of a key port in a pixel circuit according to an embodiment of this application is shown; and

[0039] Figures 4 to 7 This diagram illustrates the on / off states of each stage of a pixel circuit according to an embodiment of this application. Detailed Implementation

[0040] To more clearly illustrate this application, the following description, in conjunction with preferred embodiments and accompanying drawings, further clarifies the application. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this application.

[0041] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," etc., mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms "connected," "linked," etc., are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0042] To address at least one of the above problems, embodiments of this application provide a pixel circuit, comprising: a first initialization unit, a drive control unit, a writing unit, a multiplexing unit, a first storage capacitor, and a light-emitting unit, wherein...

[0043] The first initialization unit is electrically connected to the first node, the first initialization signal terminal, and the first initialization control terminal, and is configured to initialize the potential of the first node based on the signal input to the first initialization control terminal.

[0044] The drive control unit is electrically connected to the drive control terminal, the second node, the third node, the fourth node, and the first power signal terminal, and is configured to generate drive current in response to the signal from the drive control terminal.

[0045] The first storage capacitor is electrically connected to the first node and the second node;

[0046] The writing unit includes a first writing unit and a second writing unit. The first writing unit is electrically connected to a data signal terminal, a write control terminal, and a first node. The second writing unit is electrically connected to a fourth node, a write control terminal, and a set signal terminal. It is configured to write the signal from the data signal terminal to the first node and write the potential of the set signal terminal to the fourth node based on the control of the write control terminal.

[0047] The multiplexing unit is electrically connected to a first power signal terminal, a first multiplexing control terminal, a second multiplexing control terminal, a fourth node, a third node, and a fifth node. It is configured to write the potential of the first power signal terminal to the fourth node during the compensation phase based on the control of the first multiplexing control terminal, write the potential of the fifth node to the third node during the initialization phase based on the control of the second multiplexing control terminal, and transmit the driving current to the fifth node during the light emission phase based on the control of the first multiplexing control terminal and the second multiplexing control terminal to drive the light emission unit to emit light.

[0048] In this embodiment, by providing a first storage capacitor disposed between the first node and the second node, including a first writing unit and a second writing unit, as well as a multiplexing unit, the data writing and compensation stages can be separated. The first writing unit is used to write the data signal, and the multiplexing unit is used to cooperate with the input compensation voltage in the compensation stage to realize staged threshold compensation and data writing. This can not only fully compensate the threshold voltage of the driving transistor, but also meet the high refresh rate requirements, improve the display effect, and has broad application prospects.

[0049] To illustrate the structure and function of the pixel circuits in the embodiments of this application in detail, the following description is provided with specific examples.

[0050] It should be noted that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the gate of the transistor is called the control electrode, and one of the source and drain is called the first electrode, and the other is called the second electrode. In the embodiments of this application, the first end of the transistor is called the source, and the second end is called the drain, as an example. In addition, the following example uses a pixel circuit based on Low-Temperature Polycrystalline Oxide (LPTO) panel technology as an example, that is, some transistors are N-type transistors and some transistors are P-type transistors. In fact, this application is not limited to this. Pixel circuits based on Low-Temperature Polycrystalline Silicon (LPTS) panel technology are also allowed, that is, all transistors in the pixel circuit are N-type transistors based on LPTS technology or all transistors are P-type transistors based on LPTS technology. The specific circuit structure topology is similar, only the type of transistor used is changed, and the driving timing of the specific ports only needs to be analogous to the timing in the example in this article, and the corresponding effective level is changed according to the transistor type, which will not be elaborated on below.

[0051] In a specific example, refer to Figure 1 and Figure 2 As shown, the pixel circuit includes: a first initialization unit 10, a drive control unit 20, a writing unit 30 (when there is no need to distinguish, 30 represents the sum of 30-1 and 30-2), a multiplexing unit 40, a first storage capacitor C1, and a light-emitting unit 50.

[0052] The light-emitting unit 50 can be an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro light-emitting diode (Micro LED), etc. Figure 2 In the specific circuit, the light-emitting diode D is used for illustration.

[0053] Reference Figure 1 As shown, the first storage capacitor C1 is connected between the first node N1 and the second node N2, that is, the first end of the first storage capacitor C1 is electrically connected to the first node N1 and the second end is electrically connected to the second node N2.

[0054] The first initialization unit 10 is electrically connected to the first node N1, the first initialization signal terminal Vinit1, and the first initialization control terminal S5. It is configured to initialize the potential of the first node N1 based on the signal connected to the first initialization control terminal S5 and the signal connected to the first initialization signal terminal Vinit1. In other words, the first terminal of the first storage capacitor C1 is initialized using the signal connected to the first initialization signal terminal Vinit1.

[0055] The drive control unit 20 is electrically connected to the drive control terminal S6, the second node N2, the third node N3, the fourth node N4, and the first power signal terminal ELVDD, and is configured to generate drive current in response to the signal of the drive control terminal S6.

[0056] The write unit 30 includes a first write unit 30-1 and a second write unit 30-2. The first write unit 30-1 is electrically connected to the data signal terminal Data, the write control terminal S2, and the first node N1, and is configured to write the data signal from the data signal terminal to the first node N2 based on the control of the write control terminal S2. The second write unit 30-2 is electrically connected to the fourth node N4, the write control terminal S2, and the set signal terminal Vinit2, and is configured to write the set signal from the set signal terminal Vinit2 to the fourth node N4.

[0057] In this application, the drive control unit 20 is electrically connected to the drive control terminal S6 to generate a drive current under the control of the drive control terminal S6, and the writing unit 30 is electrically connected to the writing control terminal S2. The writing unit 30 is divided into a first writing unit 30-1 that writes data signals to the first node N1 and a second writing unit 30-2 that writes set signals to the fourth node N4, so as to write signals under the control of the writing control terminal S2. This allows the compensation stage and the data writing stage to be divided into two independent time intervals. The specific process is described in the timing analysis section below.

[0058] The multiplexing unit 40 is electrically connected to the first power signal terminal ELVSS, the first multiplexing control terminal S1, the second multiplexing control terminal S3, the fourth node N4, the third node N3, and the fifth node N5. It is configured to write the potential of the first power signal terminal ELVSS to the fourth node N4 during the compensation phase based on the control of the first multiplexing control terminal S1; to write the potential of the fifth node N5 to the third node N3 during the initialization phase based on the control of the second multiplexing control terminal S3; and to transmit the driving current to the fifth node N5 during the light-emitting phase based on the control of the first and second multiplexing control terminals S1 and S3, thereby driving the light-emitting unit 50 to emit light. In the embodiments of this application, by setting the multiplexing unit 40 electrically connected to the first and second multiplexing control terminals S1 and S3, and through different control timing sequences, the multiplexing unit 40 functions in three phases, thereby cooperating with other structures to complete threshold compensation and data writing for discrete time intervals. The specific process is described in the timing analysis section below.

[0059] In addition, refer to Figure 1 As shown, the pixel circuit also includes a second initialization unit 60, which is electrically connected to the fifth node N5, the second initialization signal terminal Vinit3, and the second initialization control terminal S4, and is configured to initialize the potential of the fifth node N5 based on the signal accessed by the second initialization control terminal S4.

[0060] Specifically, refer to Figure 2 As shown, the first initialization unit 10 includes a seventh transistor T7. The first electrode of the seventh transistor T7 is electrically connected to the first initialization signal terminal Vinit1, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first initialization control terminal S5. It is configured to initialize the first node N1, i.e., the first terminal of the first storage capacitor C1, using the potential of the first initialization signal terminal Vinit1 in response to a signal input to the first initialization control terminal S5.

[0061] The drive control unit 20 includes a fifth transistor T5, a sixth transistor T6, and a second storage capacitor C2. The first electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second node N2. The first electrode of the sixth transistor T6 is electrically connected to the third node N3, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the drive control terminal S6. The first terminal of the second storage capacitor C2 is electrically connected to the first power supply signal terminal ELVDD, and the second terminal is electrically connected to the second node N2. When a valid level signal is applied to the drive control terminal S6, the sixth transistor T6, acting as a compensation transistor, is turned on, performing threshold compensation on the control electrode of the fifth transistor T5, which acts as a drive transistor, to generate a drive current.

[0062] The first write unit 30-1 in the write unit 30 includes a first transistor T1, and the second write unit 30-2 includes a second transistor T2. The first transistor T1 has its first electrode connected to the data signal terminal Data, its second electrode connected to the first node N1, and its control electrode connected to the write control terminal S2. The second transistor T2 has its first electrode connected to the set signal terminal Vinit2, its second electrode connected to the fourth node N4, and its control electrode connected to the write control terminal S2. When a valid level signal is applied to the write control terminal S2, the data signal applied to the data signal terminal Data is written to the first node N1, i.e., the first terminal of the first storage capacitor C1; simultaneously, the potential applied to the set signal terminal Vinit2 is written to the fourth node N4.

[0063] The multiplexing unit 40 includes a third transistor T3 and a fourth transistor T4. The first electrode of the third transistor T3 is electrically connected to the first power supply signal terminal ELVDD, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first multiplexing control terminal S1. The first electrode of the fourth transistor T4 is electrically connected to the third node N3, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second multiplexing control terminal S3. When only the first multiplexing control terminal S1 receives a valid level signal, the potential of the first power supply signal terminal ELVDD is written to the fourth node N4. When only the second multiplexing control terminal S3 receives a valid level signal, the potential of the fifth node N5 is written to the third node N3. When both the first multiplexing control terminal S1 and the second multiplexing control terminal S3 receive valid level signals simultaneously, the unit is in the light-emitting stage, and the driving current generated by the fifth transistor T5 is transmitted to the anode of the light-emitting unit D, driving the light-emitting unit D to emit light.

[0064] The second initialization unit 60 includes an eighth transistor T8. The first electrode of the eighth transistor T8 is electrically connected to the second initialization signal terminal Vinit3, the second electrode is electrically connected to the fifth node N5, and the control electrode is electrically connected to the second initialization control terminal S4. When the control electrode receives a valid level signal, it initializes the fifth node N5, i.e., the anode of the light-emitting unit D, using the potential connected to the second initialization signal terminal Vinit3.

[0065] It should be noted that the specific configurations of the drive control unit, the first initialization unit, and the second initialization unit in this example are merely exemplary. Other structures that can initialize the first node N1 and the fifth node N5, and compensate the gate potential of the drive transistor to generate drive current based on the control of the drive control terminal, are also permissible. As long as they can work in conjunction with the writing unit, the multiplexing unit, and the first storage capacitor to achieve time-segmented threshold compensation and data writing, this article will not elaborate further.

[0066] To further understand the functional advantages of the pixel circuit in the embodiments of this application, the following further combines... Figure 3 The timing diagram and Figures 4 to 7 The specific circuit continuity diagram shown is explained in detail.

[0067] It should be noted that the pixel circuit in this example is based on LPTO panel technology. The sixth transistor T6, serving as the compensation transistor, and the seventh transistor T7, serving as the first initialization unit, are N-type transistors, while the other transistors are P-type transistors. The effective conduction level of the sixth transistor T6 and the seventh transistor T7 is high, while the effective conduction level of the other transistors is low.

[0068] Specific reference Figure 3 As shown, the signals connected to the initialization control terminal S5 and the drive control terminal S6 are the same, and the data signal terminal Data is connected to the data signal.

[0069] The driving process of the pixel circuit includes four stages: initialization stage T1, compensation stage T2, writing stage T3, and light emission stage T4.

[0070] During the initialization phase T1, refer to... Figure 3 and Figure 4 As shown, the first multiplexing control terminal S1 and the write control terminal S2 are connected to an invalid level signal, turning off the first transistor T1 constituting the first write unit 30-1, the second transistor T2 constituting the second write unit 30-2, and the third transistor T3, while turning on the other transistors. At the beginning of this stage, each signal terminal changes from an effective level to an invalid level, indicating the end of the previous light emission cycle and the beginning of the current light emission cycle.

[0071] When the first initialization control terminal S5 receives a high-level signal, the seventh transistor of the first initialization unit 10, responding to the signal received by the first initialization control terminal S5, initializes the first node N1 using the potential V1 of the initialization signal terminal Vinit1, that is, discharges the first terminal of the first storage capacitor C1. When the second multiplexing control terminal S4 in the multiplexing unit 40 receives a low-level signal, the fourth transistor T4 is turned on, and the third node N3 is initialized using the anode potential of the fifth node N5, that is, the light-emitting unit D. Since the driving control terminal S6 also receives a valid level signal, an initialization path is formed from the fifth node N5 to the third node N3 to the second node N2 to initialize and discharge the second terminal of the first storage capacitor C1.

[0072] Preferably, when the second initialization unit 60 is included, in this stage, the second initialization control terminal S4 is connected to a valid low-level signal, and the potential of the second initialization signal terminal Vinit3 is used to initialize the fifth node N5, i.e., the anode of the light-emitting unit D. Then, in the initialization stage, the potentials of the second node N2, the third node N3, and the fifth node N5 are all the potential V3 of the second initialization signal terminal Vinit3.

[0073] Preferably, the signal connected to the second initialization control terminal S4 becomes effective earlier than the signal connected to the first initialization control terminal S5, so as to avoid premature discharge of the second terminal of the first storage capacitor C1, which would cause a change in the potential of the second terminal of the capacitor and thus avoid affecting the brightness of the light-emitting unit.

[0074] In compensation phase T2, refer to Figure 3 and Figure 5 As shown, the second multiplexing control terminal S3 and the write control terminal S2 are connected to an invalid level signal, which turns off the first transistor T1 constituting the first write unit 30-1, the second transistor T2 constituting the second write unit 30-2, and the fourth transistor T4, while the other transistors are turned on.

[0075] The signal connected to the first initialization control terminal S5 is still at a high level, and the potential of the first node N1, i.e., the first end of the first storage capacitor C1, is still V1. Since neither the first write unit 30-1 nor the second write unit 30-2 is active at this time, to complete threshold compensation, a valid level signal is connected to the first multiplexing control terminal S1, and a high-level signal VDD is written to the fourth node N4 using the first power signal terminal ELVDD. Because the drive control terminal S6 is still connected to a valid level signal, the sixth transistor T6 is turned on, thereby using the high-level signal VDD and the sixth transistor T6 to perform threshold compensation on the gate of the fifth transistor T5. The length of the low-level time interval of the first multiplexing control terminal S1 is the threshold compensation time length, which can be extended as needed to ensure that the gate potential of the fifth transistor T5 can reach VDD+Vth, where Vth represents its threshold voltage. Those skilled in the art should understand that the compensation stage is completed by charging the substrate of the second storage capacitor C2; therefore, the presence of the second storage capacitor C2 in the drive control unit 20 is essential.

[0076] During the write phase T3, refer to... Figure 3 and Figure 6 As shown, the first initialization control terminal S5, the drive control terminal S6, the second multiplexing control terminal S3, and the write control terminal S2 are connected to an invalid level signal, which turns off the seventh transistor T7 constituting the first initialization unit 10, the second transistor T2 constituting the second write unit 30-2, the sixth transistor T6, and the fourth transistor T4, while the other transistors are turned on.

[0077] In this stage, in response to a valid level signal being received at the write control terminal S2, the data signal terminal Data writes its received data signal to the first node N1, i.e., the first terminal of the first storage capacitor C1. Of course, in this stage, refer to... Figure 3As shown, the invalid level signal connected to the first initialization control terminal S5 should be earlier than the invalid level signal connected to the write control terminal S2 to ensure that the data signal can be successfully written to the first node N1.

[0078] In this stage, threshold compensation is stopped, and only data writing is performed. To ensure the formation of drive current, since no data is written to the fourth node N4, the second write unit 30-2 sets the fourth node N4 using the set signal terminal Vinit2. Because the potential of the first terminal of the first storage capacitor C1 changes from V1 to Vdata, the potential of the second terminal of the first storage capacitor C1 (i.e., the second node N2) changes from the original VDD+Vth due to the influence of the potential of the first terminal. Under its bootstrap function, the potential of the second node N2 will become VDD+Vth+(Vdata-V1)×C1 / (C1+C2), where C1 represents the capacitance value of the first storage capacitor, C2 represents the capacitance value of the second storage capacitor, Vdata represents the level of the data signal, and VDD represents the potential of the first power supply signal terminal ELVDD. It can be seen that by utilizing the bootstrap function of the first storage capacitor C1, the data signal Vdata input at the data signal terminal Data is coupled to the gate of the fifth transistor T5, completing the data writing.

[0079] Preferably, when the second initialization unit 60 is included, in this stage, the second initialization control terminal S4 can be connected to a valid low-level signal, and the potential of the second initialization signal terminal Vinit3 can be used to keep the fifth node N5, i.e. the anode of the light-emitting unit D, low.

[0080] However, at the end of the writing phase, the signal connected to the second initialization control terminal S4 needs to be changed to an invalid high-level signal, and the signal connected to the second multiplexing control terminal S3 needs to be changed to an valid low-level signal to prepare for the light emission phase. Preferably, the signal connected to the second initialization control terminal S4 becomes invalid earlier than the signal connected to the second multiplexing control terminal S3 becomes valid. This ensures that the initialization signal of the second initialization signal terminal Vinit3 has completed the anode reset of the light-emitting unit D before the fourth transistor T4 is turned on, preventing the voltage from the third node N3 from impacting the anode of the light-emitting unit D.

[0081] During the luminescence phase T4, refer to Figure 3 and Figure 7 As shown, the multiplexing unit 40 transmits the generated driving current to the light-emitting unit D in response to the signals connected to the first multiplexing control terminal S1 and the second multiplexing control terminal S3, so as to drive the light-emitting unit D to emit light.

[0082] Based on the above analysis, it can be seen that by providing the first writing unit 30-1 and the second writing unit 30-2, as well as the first storage capacitor C1, the data writing stage and the compensation stage are separated into two time periods. By providing a multiplexing unit, the unit is used to complete the reset of the two ends of the first storage capacitor C1 in the initialization stage T1 in conjunction with the first initialization unit 10. In the compensation stage T2, the potential of the first power signal terminal ELVDD is used to replace the data signal to complete the threshold compensation. In the light emission stage T4, it forms a current path as a light emission control transistor to drive the light emission unit D to emit light.

[0083] The above settings ensure that all light-emitting units have sufficient compensation time to maintain balanced light-emitting current in a single frame of image display, while also meeting the requirements of high refresh rates and improving display quality.

[0084] Based on the same inventive concept, embodiments of this application also provide the display panel described above, including the pixel circuit described above.

[0085] It should be noted that the specific structure of the display panel has been described in detail above when describing the structure and function of the pixel circuit, and will not be repeated here.

[0086] By providing a first storage capacitor between the first node and the second node in the pixel circuit of the display panel, including a first writing unit, a second writing unit, and a multiplexing unit, the data writing and compensation stages can be separated. The first writing unit writes the data signal, and the multiplexing unit cooperates with the input compensation voltage in the compensation stage to realize staged threshold compensation and data writing. This can not only fully compensate the threshold voltage of the driving transistor, but also meet the high refresh rate requirements, improve the display effect, and has broad application prospects.

[0087] Based on the same inventive concept, embodiments of this application also provide a driving method for using the display panel described in the above embodiments, including:

[0088] Initialization phase: The first initialization unit responds to the signal accessed by the first initialization control terminal and initializes the first node using the potential of the initialization signal terminal; the multiplexing unit responds to the signal accessed by the second multiplexing control terminal and writes the potential of the fifth node into the third node to initialize the second node.

[0089] Compensation phase: The multiplexing unit responds to the signal accessed by the first multiplexing control terminal by writing the potential of the first power signal terminal into the fourth node, and the drive control unit responds to the signal accessed by the drive control terminal by using the potential of the fourth node to compensate the voltage of the second node.

[0090] Write phase: In response to the signal received by the write control terminal, the data signal terminal is written to the first node, and the set signal terminal is written to the fourth node; and

[0091] Light emission stage: In response to the signals connected to the first multiplexing control terminal and the second multiplexing control terminal, the multiplexing unit transmits the resulting driving current to the light emission unit to drive the light emission unit to emit light.

[0092] The driving methods and processes described above have already been detailed in the description of the structure and function of the specific pixel circuit, and will not be repeated here.

[0093] By using this driving method, the data writing process and the threshold compensation process can be separated by the signals of the write control terminal, the first initialization control terminal, the first multiplexing control terminal and the second multiplexing control terminal of the write unit in the pixel circuit, in combination with the structure of each unit. This makes the pixel circuit more suitable for high refresh rate requirements, while providing a balanced display effect.

[0094] Preferably, when the pixel circuit includes a second initialization unit, during the initialization phase, the signal accessed by the second initialization control terminal becomes an effective level earlier than the signal accessed by the first initialization control terminal.

[0095] During the writing phase, the signal connected to the second initialization control terminal becomes invalid earlier than the signal connected to the second multiplexing control terminal becomes valid.

[0096] This setting avoids premature discharge of the second terminal of the first storage capacitor, which would cause a change in the potential of the second terminal and thus affect the brightness of the light-emitting unit. At the same time, it ensures that the initialization signal at the second initialization signal terminal has completed the anode reset of the light-emitting unit before the fourth transistor is turned on, thus preventing the voltage from the third node from impacting the anode of the light-emitting unit.

[0097] This application addresses existing problems by providing a pixel circuit, its driving method, and a display panel. By providing a first storage capacitor disposed between a first node and a second node, including a first writing unit, a second writing unit, and a multiplexing unit, the data writing and compensation stages can be separated. The first writing unit writes the data signal, and the multiplexing unit cooperates with the input compensation voltage during the compensation stage to achieve staged threshold compensation and data writing. This not only fully compensates the threshold voltage of the driving transistor but also meets the requirements of high refresh rates, improving the display effect and showing broad application prospects.

[0098] Obviously, the above embodiments of this application are merely examples for clearly illustrating this application, and are not intended to limit the implementation of this application. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this application are still within the protection scope of this application.

Claims

1. A pixel circuit, characterized in that, The application relates to a display driving circuit, comprising: a first initialization unit, a drive control unit, a write unit, a multiplexing unit, a first storage capacitor and a light-emitting unit, wherein the first initialization unit is electrically connected to a first node, a first initialization signal terminal and a first initialization control terminal, and is configured to initialize the potential of the first node based on a signal inputted from the first initialization control terminal, the drive control unit is electrically connected to a drive control terminal, a second node, a third node, a fourth node and a first power signal terminal, and is configured to generate a drive current in response to a signal of the drive control terminal; the first storage capacitor is electrically connected to the first node and the second node; the write unit comprises a first write unit and a second write unit, the first write unit is electrically connected to a data signal terminal, a write control terminal and the first node, and the second write unit is electrically connected to the fourth node, the write control terminal and a set signal terminal, and is configured to write a signal of the data signal terminal into the first node and write the potential of the set signal terminal into the fourth node based on the control of the write control terminal; the multiplexing unit is electrically connected to the first power signal terminal, a first multiplexing control terminal, a second multiplexing control terminal, the fourth node, the third node and a fifth node, and is configured to write the potential of the first power signal terminal into the fourth node in a compensation stage based on the control of the first multiplexing control terminal, write the potential of the fifth node into the third node in an initialization stage based on the control of the second multiplexing control terminal, and transmit the drive current to the fifth node in a light-emitting stage based on the control of the first multiplexing control terminal and the second multiplexing control terminal, so as to drive the light-emitting unit to emit light.

2. The pixel circuit of claim 1, wherein, The first write unit comprises a first transistor, and the second write unit comprises a second transistor, wherein the first electrode of the first transistor is electrically connected to the data signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the write control terminal; the first electrode of the second transistor is electrically connected to the set signal terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the write control terminal.

3. The pixel circuit of claim 1, wherein, Further comprising: a second initialization unit electrically connected to the fifth node, a second initialization signal terminal and a second initialization control terminal, and configured to initialize the potential of the fifth node based on a signal inputted from the second initialization control terminal.

4. The pixel circuit of claim 1, wherein, The multiplexing unit comprises a third transistor and a fourth transistor, wherein the first electrode of the third transistor is electrically connected to the first power signal terminal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first multiplexing control terminal; the first electrode of the fourth transistor is electrically connected to the third node, the second electrode is electrically connected to the fifth node, and the control electrode is electrically connected to the second multiplexing control terminal.

5. The pixel circuit of claim 1, wherein, The drive control unit comprises a fifth transistor, a sixth transistor and a second storage capacitor, wherein the first electrode of the fifth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; A first electrode of the sixth transistor is electrically connected to the third node, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the driving control end; A first end of the second storage capacitor is electrically connected to the first power supply signal end, and a second end is electrically connected to the second node.

6. The pixel circuit of claim 1, wherein, The first initialization unit comprises a seventh transistor, wherein A first electrode of the seventh transistor is electrically connected to the first initialization signal end, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the first initialization control end.

7. The pixel circuit of claim 3, wherein, The second initialization unit comprises an eighth transistor, wherein A first electrode of the eighth transistor is electrically connected to the second initialization signal end, a second electrode is electrically connected to the fifth node, and a control electrode is electrically connected to the second initialization control end.

8. A display panel, characterized by, The pixel circuit comprises any one of claims 1-7.

9. A driving method applied to the pixel circuit according to any one of claims 1 to 7, characterized by, The pixel circuit comprises: An initialization stage: the first initialization unit initializes the first node by using the potential of the initialization signal end in response to the signal inputted into the first initialization control end, and the multiplexing unit writes the potential of the fifth node into the third node in response to the signal inputted into the second multiplexing control end, so as to initialize the second node; A compensation stage: the multiplexing unit writes the potential of the first power supply signal end into the fourth node in response to the signal inputted into the first multiplexing control end, and the driving control unit compensates the voltage of the second node by using the potential of the fourth node in response to the signal inputted into the driving control end; A writing stage: in response to the signal inputted into the writing control end, the signal of the data signal end is written into the first node, and the signal of the setting signal end is written into the fourth node; And An emitting stage: the multiplexing unit transmits the driving current formed to the emitting unit in response to the signals inputted into the first multiplexing control end and the second multiplexing control end, so as to drive the emitting unit to emit light.

10. The driving method according to claim 9, wherein The pixel circuit further comprises a second initialization unit configured to initialize the potential of the fifth node based on the signal inputted into the second initialization control end, wherein In the initialization stage, the signal inputted into the second initialization control end becomes valid level earlier than the signal inputted into the first initialization control end; In the writing stage, the time when the signal inputted into the second initialization control end becomes invalid level is earlier than the time when the signal inputted into the second multiplexing control end becomes valid level.

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