Power saving system for battery charger

Abstract

This invention provides a power-saving system for a battery charger. A first transistor's control terminal receives a wake-up signal. A counter is connected to the first terminal of the first transistor. The counter determines whether the operating period of the wake-up signal received from the first transistor is greater than a time threshold, and outputs a counting signal. When the counting signal indicates that the operating period of the wake-up signal is not greater than the time threshold, the counter is turned off, and multiple electronic components of the electronic device remain off to save battery power. When the counting signal indicates that the operating period of the wake-up signal is greater than the time threshold, the electronic device switches from power-saving mode to normal operation mode, at which point the battery can supply power to the electronic device.

Description

Technical Field

[0001] This invention relates to battery chargers, and more particularly to a power-saving system for battery chargers. Background Technology

[0002] With the rapid development of electronic technology, various electronic products such as mobile phones, desktop computers, and laptops are widely used in people's daily lives. Most of these electronic products are powered by rechargeable batteries. Whenever the power of an electronic product is low, the rechargeable battery can provide the necessary power for its operation. However, during the transportation of electronic products, such as during shipping, when the electronic product is not in use, the battery continuously supplies power, resulting in unnecessary power consumption. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a power-saving system for a battery charger, addressing the shortcomings of existing technologies. The system includes a first transistor, a second transistor, a counter, and an operation management circuit. The control terminal of the first transistor is connected to an external power supply circuit to receive a wake-up signal from the external power supply circuit. A first terminal of the first transistor is coupled to an input voltage. The first terminal and control terminal of the second transistor are connected to a second terminal of the first transistor. The second terminal of the second transistor is grounded. The trigger terminal of the counter is connected to the first terminal of the first transistor. When the counter is awakened by a wake-up signal received from the first transistor in power-saving mode, the counter determines whether the working period of the wake-up signal is greater than a time threshold and outputs a counting signal. The operation management circuit connects the counter and an electronic device. The electronic device is coupled to a battery. The operation management circuit is configured to receive a counting signal from the counter. When the operation management circuit receives a counting signal in power-saving mode indicating that the working period of the wake-up signal is not greater than the time threshold, the operation management circuit shuts down the counter and keeps the multiple electronic components included in the electronic device off. When the operation management circuit receives a count signal indicating that the wake-up signal's working cycle in power-saving mode exceeds a time threshold, the operation management circuit decides to switch the battery from power-saving mode to normal operation mode, triggering the electronic device to turn on and receive power from the external power supply circuit or the battery.

[0004] In one embodiment, the power-saving system of the battery charger further includes a first resistor. A first terminal of the first resistor is connected to the control terminal of the first transistor. A second terminal of the first resistor is grounded.

[0005] In one embodiment, the power-saving system of the battery charger further includes a current source. A first terminal of the current source is coupled to the input voltage. A second terminal of the current source is connected to a first terminal of a first transistor.

[0006] In one embodiment, the power-saving system of the battery charger further includes a third transistor and an input resistor. The first terminal of the third transistor and the first terminal of the input resistor are connected to the cathodes of a first diode and a second diode, respectively. The anode of the first diode is connected to the battery. The anode of the second diode is connected to an external power supply circuit. The second terminal of the input resistor is connected to the control terminal of the third transistor. The second terminal of the third transistor is connected to a current source. The voltage at the second terminal of the third transistor is the input voltage.

[0007] In one embodiment, the power-saving system of the battery charger further includes a fourth transistor and a fifth transistor. A first terminal of the fourth transistor is connected to a second terminal of the input resistor and a control terminal of the fourth transistor. A second terminal of the fourth transistor is connected to a first terminal of the fifth transistor and a control terminal of the fifth transistor, and the second terminal of the fifth transistor is grounded.

[0008] In one embodiment, the power-saving system of the battery charger further includes a first inverter. The input terminal of the first inverter is connected to the first terminal of a first transistor. The output terminal of the first inverter is connected to the trigger terminal of a counter. The positive power supply terminal of the first inverter is connected to the second terminal of a third transistor. The negative power supply terminal of the first inverter is grounded.

[0009] In one embodiment, the power-saving system of the battery charger further includes a voltage detection circuit. The voltage detection circuit is connected to the second terminal of the third transistor. The voltage detection circuit is configured to detect whether the voltage at the second terminal of the third transistor is greater than a voltage threshold, and to output a voltage detection signal.

[0010] In one embodiment, the power-saving system of the battery charger further includes a first edge-triggered circuit. The power supply terminal of the first edge-triggered circuit is connected to the second terminal of the third transistor. The input terminal of the first edge-triggered circuit is connected to the output terminal of the voltage detection circuit. The first edge-triggered circuit determines the level of a first trigger signal based on the voltage detection signal and outputs the first trigger signal.

[0011] In one embodiment, the power-saving system of the battery charger further includes a first flip-flop. The power supply terminal of the first flip-flop is connected to the second terminal of the third transistor. The first input terminal of the first flip-flop is connected to the output terminal of the first edge-triggered circuit. The output terminal of the first flip-flop is connected to the enable terminal of the counter.

[0012] In one embodiment, the power-saving system of the battery charger further includes a first OR gate and a second inverter. The input of the second inverter is connected to the output of a voltage detection circuit and receives a voltage detection signal. The output of the second inverter is connected to the first input of the first OR gate. The second input of the first OR gate is connected to the output of a counter. The output of the first OR gate is connected to the second input of a first flip-flop.

[0013] In one embodiment, the power-saving system of the battery charger further includes a second OR gate. The first input of the second OR gate is connected to the output of a counter. The second input of the second OR gate is connected to the output of a control circuit. The output of the second OR gate is connected to the second input of the first OR gate. The control circuit determines whether the battery switches from normal operating mode to power-saving mode, and outputs a control signal to the second input of the second OR gate.

[0014] In one embodiment, the power-saving system of the battery charger further includes a storage circuit. The input of the storage circuit is connected to the output of the control circuit. The output of the storage circuit is connected to the second input of a second OR gate.

[0015] In one embodiment, the power-saving system of the battery charger further includes a third OR gate and a second flip-flop. The first input of the third OR gate is connected to the output of the second OR gate. The second input of the third OR gate is connected to the output of the second flip-flop. The output of the third OR gate is connected to the first input of the second flip-flop. The power supply terminal of the second flip-flop is connected to the second terminal of the third transistor. The output of the second flip-flop is connected to the input of the operation management circuit.

[0016] In this embodiment, the power-saving system of the battery charger further includes an AND gate and a fourth OR gate. The first input of the AND gate is connected to the output of the voltage detection circuit and receives a voltage detection signal. The second input of the AND gate is connected to the output of the first inverter. The first input of the fourth OR gate is connected to the output of the first edge-triggered circuit. The second input of the fourth OR gate is connected to the output of the AND gate. The output of the fourth OR gate is connected to the second input of the second flip-flop.

[0017] In one embodiment, the power-saving system of the battery charger further includes a second edge-triggered circuit. The power supply terminal of the second edge-triggered circuit is connected to the second terminal of the third transistor. The input terminal of the second edge-triggered circuit is connected to the output terminal of the first inverter. The output terminal of the second edge-triggered circuit is connected to the second input terminal of an AND gate.

[0018] As described above, the present invention provides a power-saving system for a battery charger, which can automatically shut down multiple electronic components (e.g., power conversion circuits) contained in an electronic device in shipping or other power-saving modes, stopping the battery from supplying power to these electronic components to save battery power. Simultaneously, upon receiving a wake-up signal from an external power supply circuit, it determines whether the working cycle of the wake-up signal exceeds a time threshold to determine whether the system should continue in power-saving mode or enter normal operation mode.

[0019] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0020] Figure 1 This is a circuit layout diagram of the operation management circuit, electronic device, and battery of the power-saving system of the battery charger according to an embodiment of the present invention.

[0021] Figure 2 This is a circuit layout diagram of the power-saving system of the battery charger according to an embodiment of the present invention.

[0022] Figure 3 The waveform diagram shows the signal of the power-saving system of the battery charger according to an embodiment of the present invention.

[0023] Figure 4 The waveform diagram shows the signal of the power-saving system of the battery charger according to an embodiment of the present invention.

[0024] Figure 5 The waveform diagram shows the signal of the power-saving system of the battery charger according to an embodiment of the present invention. Detailed Implementation

[0025] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any combination of any one or more of the associated listed items.

[0026] Please see Figure 1 and Figure 2 ,in Figure 1 This is a circuit layout diagram of the operation management circuit, electronic device, and battery of the power-saving system of the battery charger according to an embodiment of the present invention. Figure 2 This is a circuit layout diagram of the power-saving system of the battery charger according to an embodiment of the present invention.

[0027] In this embodiment, the operation management circuit 20 of the battery charger can directly control or instruct the main control circuit 40 to control the operation state of the electronic device 90. The electronic device 90 may include multiple electronic components 101 to 10n, such as, but not limited to, power converters, low dropout regulators, analog-to-digital converters, etc.

[0028] For example, during the transport of electronic device 90 (by ship), the operation management circuit 20 can shut down multiple electronic components 101 to 10n of electronic device 90. In this case, the battery BAT does not need to supply power to electronic device 90, thus saving battery BAT power. Additionally, the operation management circuit 20 can control the operation of the power switch 30 to manage the continuous supply or interruption of the power supply voltage Vbus to electronic device 90 from the external power circuit.

[0029] It is worth noting that the power-saving system of the battery charger in this embodiment may include a first transistor T1, a second transistor T2, a counter CNT, and an operation management circuit 20.

[0030] The first terminal of the first transistor T1 is connected to the second terminal of the current source IS, and the first terminal of the current source IS is coupled to the input voltage Vpp. This input voltage Vpp can be either the battery voltage Vbat (after processing by the third transistor T3 described below) or the power supply voltage Vbus. The first terminal of the second transistor T2 and the control terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1. The second terminal of the second transistor T2 can be grounded.

[0031] The control terminal of the first transistor T1 can be directly connected to an external power supply circuit, or it can be connected to an external power supply circuit through circuit components such as the first switch SW1 or the first capacitor C1. This external power supply circuit is any suitable electronic circuit capable of activating some circuit components of the power-saving system of the battery charger in this embodiment. The control terminal of the first transistor T1 can receive the power supply voltage Vbus and the wake-up signal WAP from the external power supply circuit.

[0032] The first terminal of the first transistor T1 can be directly connected to the trigger terminal of the counter CNT. Or, as... Figure 2 As shown, a first inverter NT1 can be provided between the first terminal of the first transistor T1 and the trigger terminal of the counter CNT. The first terminal of the first transistor T1 can be connected to the input terminal of the first inverter NT1. The output terminal of the first inverter NT1 can be connected to the trigger terminal of the counter CNT. The positive power supply terminal of the first inverter NT1 can be coupled to the input voltage Vpp. The negative power supply terminal of the first inverter NT1 can be grounded.

[0033] The wake-up signal WAP is processed by the first transistor T1 (and inverted by the first inverter NT1) and then output to the counter CNT. When the counter CNT is woken up by the wake-up signal WAP in power-saving mode (e.g., shipping mode), the counter CNT determines whether the working period of the received wake-up signal WAP is greater than a time threshold and outputs a counting signal.

[0034] For example, when the counter CNT determines that the working period of the wake-up signal WAP is not greater than a time threshold, the counter CNT outputs a count signal with the first logic level (e.g., "1"). Conversely, when the counter CNT determines that the working period of the wake-up signal WAP is greater than the time threshold, the counter CNT outputs a count signal with the second logic level (e.g., "0").

[0035] The operation management circuit 20 can be directly connected to the counter CNT, or as follows: Figure 2 The counter CNT is connected via several circuit components. When the operation management circuit 20 receives a counting signal in power-saving mode, and the counting signal indicates that the duty cycle of the wake-up signal WAP is no greater than a time threshold (e.g., but not limited to 500µs), the operation management circuit 20 can shut down and stop power supply to the counter CNT, and keep the multiple electronic components 101 to 10n included in the electronic device 90 off. At this time, the battery BAT can stop powering the electronic device 90 to save the power of the battery BAT.

[0036] Conversely, when the operation management circuit 20 receives a counting signal in power-saving mode, and the counting signal indicates that the working cycle of the wake-up signal WAP is greater than a time threshold, the operation management circuit 20 decides to switch the electronic device from power-saving mode to normal operation mode. Accordingly, the operation management circuit 20 can output a first clock enable signal to each of the electronic components 101 to 10n to trigger the multiple electronic components 101 to 10n included in the electronic device 90 to turn on and operate, and can output a second clock enable signal to the counter CNT to trigger the counter CNT to turn off. At this time, the battery BAT can supply the power required for operation to the multiple electronic components 101 to 10n included in the electronic device.

[0037] If necessary, the power-saving system of the battery charger in this embodiment may include one or more of the following: a first resistor R1, a second resistor R2, a first diode D1, a second diode D2, a third transistor T3, and an input resistor Rin.

[0038] The first terminal of the first resistor R1 and the first terminal of the second resistor R2 can be connected to the control terminal of the first transistor T1. The second terminals of the first resistor R1 and the second terminal of the second resistor R2 can be grounded.

[0039] The anode of the first diode D1 can be connected to the battery BAT. The anode of the second diode D2 can be connected to an external power supply circuit. The first terminal of the input resistor Rin can be connected to the cathodes of both the first diode D1 and the second diode D2. The second terminal of the input resistor Rin can be connected to the control terminal of the third transistor T3.

[0040] The cathodes of the first diode D1 and the second diode D2 can be connected to the first terminal of the third transistor T3. The voltage at the first terminal of the third transistor T3 is the higher of the battery voltage Vbat and the power supply voltage Vbus.

[0041] The voltage at the second terminal of the third transistor T3 can be the aforementioned input voltage Vpp. That is, the first terminal of the current source IS and the positive power supply terminal of the first inverter NT1 can be connected to the second terminal of the third transistor T3, and the input voltage Vpp required for operation can be obtained from the second terminal of the third transistor T3.

[0042] If necessary, the power-saving system of the battery charger in this embodiment may include a fourth transistor T4, a fifth transistor T5, or both.

[0043] The first terminal of the fourth transistor T4 can be connected to the second terminal of the input resistor Rin and the control terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 can be connected to the first terminal of the fifth transistor T5 and the control terminal of the fifth transistor T5. The second terminal of the fifth transistor T5 can be grounded.

[0044] If necessary, the power-saving system of the battery charger in this embodiment may include one or more of the following: voltage detection circuit DVR, first edge trigger circuit ET1, first flip-flop FF1, first OR gate OR1, second inverter NT2, control circuit CTR, second OR gate OR2, storage circuit REC, third OR gate OR3, second flip-flop FF2, AND gate AND1, fourth OR gate OR4, and second edge trigger circuit ET2.

[0045] It should be understood that, as described herein, the power-saving system of the battery charger in this embodiment may include, for example, Figure 2 All circuit components are shown, but the invention is not limited thereto. In fact, the battery charger of the present invention may be appropriately omitted. Figure 2 Some circuit components in it.

[0046] like Figure 2 As shown, the power supply terminal of the voltage detection circuit DVR, the power supply terminal of the first edge trigger circuit ET1, and the power supply terminal of the first flip-flop FF1 can be connected to the second terminal of the third transistor T3, and the input voltage Vpp required for operation can be obtained from the second terminal of the third transistor T3.

[0047] The voltage detection circuit DVR can detect whether the input voltage Vpp at the second terminal of the third transistor T3 is greater than a voltage threshold, and output a voltage detection signal.

[0048] The input terminal of the first edge-triggered circuit ET1 can be connected to the output terminal of the voltage detection circuit DVR. The first edge-triggered circuit ET1 can determine the level of the first trigger signal based on the voltage detection signal and output the first trigger signal.

[0049] For example, when the first edge-triggered circuit ET1 determines that the input voltage Vpp is greater than the voltage threshold based on the voltage detection signal, it outputs a high-level first trigger signal, such as a first trigger signal with a pulse. Conversely, when the first edge-triggered circuit ET1 determines that the input voltage Vpp is not greater than the voltage threshold based on the voltage detection signal, it outputs a low-level first trigger signal.

[0050] Additionally, the output of the voltage detection circuit DVR can be connected to the input of the second inverter NT2, and can output a voltage detection signal to the input of the second inverter NT2. The output of the second inverter NT2 can be connected to the first input of the first OR gate OR1. The second input of the first OR gate OR1 can be directly connected to the output of the counter CNT, or connected to the output of the second OR gate OR2. The output of the first OR gate OR1 can be connected to the second input R of the first flip-flop FF1.

[0051] If a second OR gate OR2 is provided, its first input can be connected to the output of the counter CNT. The second input of OR2 can be directly connected to the output of the control circuit CTR. Alternatively, as... Figure 2 As shown, a storage circuit REC, such as a buffer, is provided between the second input of the second OR gate OR2 and the output of the control circuit CTR. The input of the storage circuit REC can be connected to the output of the control circuit CTR. The output of the storage circuit REC can be connected to the second input of the second OR gate OR2. The storage circuit REC can be used to store the control signals output by the control circuit CTR.

[0052] The first input terminal S of the first flip-flop FF1 can be connected to the output terminal of the first edge-triggered circuit ET1. The output terminal Q of the first flip-flop FF1 can be connected to the enable terminal SHD of the counter CNT.

[0053] The first flip-flop FF1 described herein may be an SR flip-flop, but this invention is not limited thereto. In fact, it can be replaced with other types of flip-flops.

[0054] The first flip-flop FF1 can determine the level of the first logic signal based on the first trigger signal received from the first edge trigger circuit ET1 and the signal output by the first OR gate OR1, and output this first logic signal to the enable terminal SHD of the counter CNT to enable or stop the counter CNT operation.

[0055] The first input of the third OR gate OR3 can be connected to the output of the second OR gate OR2. The second input of the third OR gate OR3 can be connected to the output of the second inverter NT2. The output of the third OR gate OR3 can be connected to the first input S of the second flip-flop FF2. The power supply terminal of the second flip-flop FF2 can be connected to the second terminal of the third transistor T3 to receive the voltage from the second terminal of the third transistor T3.

[0056] The first input of AND gate AND1 can be connected to the output of voltage detection circuit DVR, and can receive voltage detection signals from voltage detection circuit DVR. The second input of AND gate AND1 can be connected to the output of second edge-triggered circuit ET2.

[0057] The input terminal of the second edge-triggered circuit ET2 can be connected to the output terminal of the first inverter NT1. The power supply terminal of the second edge-triggered circuit ET2 can be connected to the second terminal of the third transistor T3 to receive the input voltage Vpp from the second terminal of the third transistor T3.

[0058] The output of AND gate AND1 can be connected to the second input of the fourth OR gate OR4. The first input of the fourth OR gate OR4 can be connected to the output of the first edge-triggered circuit ET1. The output of the fourth OR gate OR4 is connected to the second input R of the second flip-flop FF2. The output Q of the second flip-flop FF2 can be connected to the enable terminal of the operation management circuit 20. The output of the operation management circuit 20 can be connected to the input of the counter CNT.

[0059] If needed, the first terminal of the second switch SW2 (e.g., the sixth transistor) can be connected to the battery BAT, and the second terminal of the second switch SW2 can be connected to the first terminals of the third resistor R3 and the fourth resistor R4. The node between the second terminal of the second switch SW2 and the first terminal of the fourth resistor R4 has the system voltage Vsys. The control terminal of the second switch SW2 is connected to the output terminal Q of the second flip-flop FF2. The second terminal of the third resistor R3 can be connected to the first input terminal of the storage circuit REC. The second terminal of the fourth resistor R4 can be connected to the second input terminal of the storage circuit REC.

[0060] Please see Figures 1 to 4 ,in Figure 3 and Figure 4 The waveform diagram shows the signal of the power-saving system of the battery charger according to an embodiment of the present invention.

[0061] First, when the battery charger's power-saving system is turned on, it enters the normal operating mode. In normal operating mode, the external power supply circuit can be connected to the anode of the second diode D2, supplying a power supply voltage Vbus to the anode of the second diode D2. This power supply voltage Vbus is processed by the third transistor T3 to form the input voltage Vpp. The input voltage Vpp can supply the voltage detection circuit DVR, the first edge-triggered circuit ET1, the first flip-flop FF1, the second edge-triggered circuit ET2, and the second flip-flop FF2 as the power required for their operation.

[0062] During the initial supply of input voltage Vpp by the external power supply circuit, the voltage detection circuit DVR outputs a detection signal to the first edge trigger circuit ET1. The first edge trigger circuit ET1 outputs a first trigger signal to the first flip-flop FF1, which triggers the counter CNT to turn off. When the counter CNT is off, it does not detect the wake-up signal WAP during its working cycle, thus completing the normal power-on process.

[0063] After the battery charger system has been powered on for a period of time, the control circuit CTR can control whether the battery BAT switches from normal operation mode to power saving mode. When the control circuit CTR decides to switch the battery BAT from normal operation mode to power saving mode based on the overall system power saving requirements, it outputs a high-level control signal to the storage circuit REC for storage. The storage circuit REC outputs the stored control signal to the second input of the second OR gate OR2. The first OR gate OR1 resets the first flip-flop signal of the first flip-flop FF1 to a low level based on the logic signal output by the second OR gate OR2, and sets the counter CNT to the working cycle that can detect the count wake-up signal WAP. The third OR gate OR3 triggers the second flip-flop FF2 to output a high-level second flip-flop signal based on the logic signal output by the second OR gate OR2. The operation management circuit 20 outputs a low-level clock enable signal CKEN and a low-level power ready signal POK based on the high-level second flip-flop signal, and shuts down the operation management circuit 20 and the electronic device 90, entering power saving mode to save power. Figure 3 As shown. At this time, the current Ibat consumed by battery BAT is less than 1.5uA.

[0064] In power-saving mode, the control terminal of the first transistor T1 is connected to the external power supply circuit. When the control terminal of the first transistor T1 receives the wake-up signal WAP from the external power supply circuit, it will activate the detection mechanism. The wake-up signal WAP is processed by the first transistor T1 and transmitted to the first inverter NT1. Then, the wake-up signal WAP can be inverted by the first inverter NT1 and output to the second edge trigger circuit ET2. The second edge trigger circuit ET2 can output a second trigger signal to the second input terminal of the AND gate AND1 based on the received wake-up signal WAP. The fourth OR gate OR4 resets the second flip-flop signal of the second flip-flop FF2 to a low level based on the logic signal output by the AND gate AND1. When the second flip-flop signal is at a low level, the operation management circuit 20 and the electronic device 90 will be activated, and the operation management circuit 20 will output a high-level clock enable signal CKEN and a high-level power ready signal POK. Then, the counter CNT will start detection counting and determine whether the working period of one pulse of the wake-up signal WAP is greater than the time threshold. Figure 3 As shown.

[0065] In the power-saving mode startup detection mechanism, the counter CNT receives a pulse of the wake-up signal WAP after passing through the first inverter NT1. The working cycle is as follows: Figure 3 and Figure 4 As shown. When the wake-up signal WAP is not greater than the time threshold, the counter CNT can output a high-level counting signal SHP. The third OR gate OR3 triggers the second flip-flop FF2 to output a high-level second flip-flop signal to the operation management circuit 20 based on the logic signal output by the second OR gate OR2. The operation management circuit 20 outputs a low-level clock enable signal CKEN and a low-level power ready signal POK to the counter CNT (and each electronic component 101 to 10n of the electronic device 90) based on the high-level second flip-flop signal FF2. Then, the operation management circuit 20 is turned off. As a result, the counter CNT and each electronic component 101 to 10n of the electronic device 90 are turned off for a period of time. At this time, the power supplied by the battery BAT to the counter CNT and the electronic device 90 can be saved.

[0066] When the control terminal of the first transistor T1 receives the high-level wake-up signal WAP again, the above-mentioned start detection mechanism is repeated to determine whether the working period of the wake-up signal WAP after being inverted by the first inverter NT1 is greater than the time threshold. This determines whether the operation management circuit 20 outputs a high-level or low-level clock enable signal CKEN and a power ready signal POK to the counter CNT (and each electronic component 101 to 10n of the electronic device 90).

[0067] Please see Figure 1 , Figure 2 and Figure 5,in Figure 2 This is a circuit layout diagram of the power-saving system of the battery charger according to an embodiment of the present invention; Figure 5 The waveform diagram shows the signal of the power-saving system of the battery charger according to an embodiment of the present invention.

[0068] When the counter CNT counts to the value after passing through the first inverter NT1, as shown below... Figure 5 When the working period of the first pulse of the wake-up signal WAP is not greater than the time threshold, the counter CNT can output a high-level counting signal SHP. Then, the second flip-flop FF2 outputs the second flip-flop signal SHS to the operation management circuit 20 to turn off the counter CNT (and each electronic component 101 to 10n of the electronic device 90).

[0069] Next, when the counter CNT receives the second pulse of the wake-up signal WAP after it has been inverted by the first inverter NT1, the working cycle is as follows: Figure 5 When the time threshold is exceeded, the counter CNT outputs a low-level counting signal SHP. As a result, the battery BAT switches from power-saving mode to normal operating mode.

[0070] In normal operating mode, the battery BAT can power the multiple electronic components 101 to 10n included in the electronic device 90. At this time, the multiple electronic components 101 to 10n of the electronic device 90, such as multiple power converters, can perform voltage conversion operations to output voltage conversion voltages DCS1 to DCS4 respectively. At this time, the counter CNT no longer counts.

[0071] In summary, this invention provides a power-saving system for a battery charger that can automatically shut down multiple electronic components (e.g., power conversion circuits) within an electronic device during shipping or other power-saving modes, stopping the battery from supplying power to these components to conserve battery power. Simultaneously, upon receiving a wake-up signal from an external power circuit, it determines whether the wake-up signal's operating cycle exceeds a time threshold to decide whether the system should continue in power-saving mode or enter normal operation mode.

[0072] The above-disclosed content is only a preferred and feasible embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power-saving system for a battery charger, characterized in that, The power-saving system of the battery charger includes: A first transistor, the control terminal of the first transistor is connected to an external power supply circuit to receive a wake-up signal from the external power supply circuit, and the first terminal of the first transistor is coupled to an input voltage; The second transistor has its first terminal and control terminal connected to the second terminal of the first transistor, and its second terminal is grounded. A counter, wherein a trigger terminal of the counter is connected to a first terminal of the first transistor, and when the counter receives the wake-up signal from the first transistor in a power-saving mode and is awakened by the wake-up signal, the counter determines whether the working period of the wake-up signal is greater than a time threshold, and outputs a counting signal; as well as An operation management circuit is connected to the counter and an electronic device coupled to a battery, and the operation management circuit is configured to receive the counting signal from the counter. When the operation management circuit receives the counting signal indicating that the working period of the wake-up signal is not greater than the time threshold in the power-saving mode, the operation management circuit turns off the counter and keeps the multiple electronic components included in the electronic device off. When the operation management circuit receives the counting signal indicating that the working cycle of the wake-up signal is greater than the time threshold in the power-saving mode, the operation management circuit decides to switch the battery from the power-saving mode to the normal operation mode, triggering the electronic device to turn on and receive power from the external power circuit or the battery.

2. The power-saving system of the battery charger according to claim 1, characterized in that, The power-saving system of the battery charger also includes a first resistor, the first end of which is connected to the control terminal of the first transistor, and the second end of which is grounded.

3. The power-saving system of the battery charger according to claim 1, characterized in that, The power-saving system of the battery charger also includes a current source, a first terminal of which is coupled to the input voltage, and a second terminal of which is connected to the first terminal of the first transistor.

4. The power-saving system of the battery charger according to claim 3, characterized in that, The power-saving system of the battery charger also includes a third transistor and an input resistor. The first terminal of the third transistor and the first terminal of the input resistor are connected to the cathodes of the first diode and the second diode, respectively. The anode of the first diode is connected to the battery, and the anode of the second diode is connected to the external power supply circuit. The second terminal of the input resistor is connected to the control terminal of the third transistor, and the second terminal of the third transistor is connected to the current source. The voltage at the second terminal of the third transistor is the input voltage.

5. The power-saving system of the battery charger according to claim 4, characterized in that, The power-saving system of the battery charger also includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor is connected to the second terminal of the input resistor and the control terminal of the fourth transistor. The second terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the control terminal of the fifth transistor. The second terminal of the fifth transistor is grounded.

6. The power-saving system of the battery charger according to claim 4, characterized in that, The power-saving system of the battery charger also includes a first inverter, the input terminal of which is connected to the first terminal of the first transistor, the output terminal of which is connected to the trigger terminal of the counter, the positive power supply terminal of which is connected to the second terminal of the third transistor, and the negative power supply terminal of which is grounded.

7. The power-saving system of the battery charger according to claim 6, characterized in that, The power-saving system of the battery charger also includes a voltage detection circuit connected to the second terminal of the third transistor, configured to detect whether the voltage at the second terminal of the third transistor is greater than a voltage threshold, so as to output a voltage detection signal.

8. The power-saving system of the battery charger according to claim 7, characterized in that, The power-saving system of the battery charger also includes a first edge-triggered circuit. The power supply terminal of the first edge-triggered circuit is connected to the second terminal of the third transistor, and the input terminal of the first edge-triggered circuit is connected to the output terminal of the voltage detection circuit. The first edge-triggered circuit determines the level of the first trigger signal based on the voltage detection signal and outputs the first trigger signal.

9. The power-saving system of the battery charger according to claim 8, characterized in that, The power-saving system of the battery charger also includes a first flip-flop, the power supply terminal of the first flip-flop is connected to the second terminal of the third transistor, the first input terminal of the first flip-flop is connected to the output terminal of the first edge-triggered circuit, and the output terminal of the first flip-flop is connected to the enable terminal of the counter.

10. The power-saving system of the battery charger according to claim 9, characterized in that, The power-saving system of the battery charger also includes a first OR gate and a second inverter. The input terminal of the second inverter is connected to the output terminal of the voltage detection circuit and receives the voltage detection signal. The output terminal of the second inverter is connected to the first input terminal of the first OR gate. The second input terminal of the first OR gate is connected to the output terminal of the counter. The output terminal of the first OR gate is connected to the second input terminal of the first inverter.

11. The power-saving system of the battery charger according to claim 10, characterized in that, The power-saving system of the battery charger also includes a second OR gate. The first input of the second OR gate is connected to the output of the counter. The second input of the second OR gate is connected to the output of a control circuit. The output of the second OR gate is connected to the second input of the first OR gate. The control circuit determines whether the battery switches from the normal operating mode to the power-saving mode and outputs a control signal to the second input of the second OR gate.

12. The power-saving system of the battery charger according to claim 11, characterized in that, The power-saving system of the battery charger also includes a storage circuit, the input of which is connected to the output of the control circuit, and the output of which is connected to the second input of the second OR gate.

13. The power-saving system of the battery charger according to claim 12, characterized in that, The power-saving system of the battery charger also includes a third OR gate and a second flip-flop. The first input terminal of the third OR gate is connected to the output terminal of the second OR gate, the second input terminal of the third OR gate is connected to the output terminal of the second flip-flop, the output terminal of the third OR gate is connected to the first input terminal of the second flip-flop, the power supply terminal of the second flip-flop is connected to the second terminal of the third transistor, and the output terminal of the second flip-flop is connected to the input terminal of the operation management circuit.

14. The power-saving system of the battery charger according to claim 13, characterized in that, The power-saving system of the battery charger also includes an AND gate and a fourth OR gate. The first input of the AND gate is connected to the output of the voltage detection circuit and receives the voltage detection signal. The second input of the AND gate is connected to the output of the first inverter. The first input of the fourth OR gate is connected to the output of the first edge-triggered circuit. The second input of the fourth OR gate is connected to the output of the AND gate. The output of the fourth OR gate is connected to the second input of the second flip-flop.

15. The power-saving system of the battery charger according to claim 14, characterized in that, The power-saving system of the battery charger also includes a second edge-triggered circuit. The power supply terminal of the second edge-triggered circuit is connected to the second terminal of the third transistor, the input terminal of the second edge-triggered circuit is connected to the output terminal of the first inverter, and the output terminal of the second edge-triggered circuit is connected to the second input terminal of the AND gate.

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