Display panel and display device

Abstract

A display panel (100) and a display device, the display panel (100) comprises a driving chip (105) and a fan-out wire (107), the fan-out wires (107) in a first fan-out wire group (11) are electrically connected to corresponding output terminals (106) through the second side (1052) of the adjacent driving chip (105); the fan-out wires (107) in the first fan-out wire group (11) comprise a first fan-out segment (1071) and a second fan-out segment (1072) which are connected and located at different layers. By adopting the wire changing and jumping design, the signal disorder caused by the inconsistent order of the output terminals (106) and the fan-out wires (107) is avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the technological development of full-screen displays, the screen-to-body ratio of displays is constantly increasing, and the bottom bezel of displays is getting smaller and smaller.

[0003] There are various ways to achieve narrow bezels in existing technologies. Figure 1 This is one of many ways to achieve narrow bezels in existing display panels. Figure 1 In the display panel 100' shown, the fan-out area 104' is provided with multiple fan-out traces 107', and the driver chip 105' includes multiple output terminals 106'. The signal lines of the display area 101' are electrically connected to the output terminals 106' through the fan-out traces 107'. Since there is still room for compression of the fan-out traces 107' connected to the output terminals 106' located in the middle area of ​​the driver chip 105', but the fan-out traces 107' connected to the output terminals 106' located on the left and right sides of the driver chip 105' cannot be further compressed, by electrically connecting the fan-out traces 107' connected to the output terminals 106' on the sides of the driver chip 105' to the output terminals 106', the bonding area 103' of the display panel 100' can be moved upward as a whole, thereby achieving a narrow bezel.

[0004] However, in order to avoid short circuits between multiple fan-out traces 107', the outer fan-out traces 107' need to be electrically connected to the inner output terminal 106', and the inner fan-out traces 107' need to be electrically connected to the outer output terminal 106'. As a result, each of the aforementioned fan-out traces 107' cannot be electrically connected to the corresponding output terminal 106', which leads to signal transmission errors and causes display defects.

[0005] In summary, there is an urgent need to provide a new display panel and display device to solve the above-mentioned technical problems. Invention Overview

[0007] Technical issues

[0008] This application provides a display panel and display device to solve the technical problem in existing display panels where each outgoing line cannot be electrically connected to the corresponding output terminal, resulting in signal transmission errors and poor display.

[0009] Solution to the problem

[0010] Technical solutions

[0011] To solve the above problems, the technical solution provided in this application is as follows:

[0012] This application provides a display panel, including a substrate, the substrate including a display area and a non-display area surrounding the display area, the non-display area including a bonding area and a fan-out area connecting the bonding area and the display area;

[0013] The bonding area is provided with a driver chip. The driver chip includes a first side near the display area and two second sides connected to the first side. The driver chip includes multiple output terminals, and the multiple output terminals include at least a first output terminal group.

[0014] The fan-out area is provided with multiple fan-out traces, and the multiple fan-out traces include at least a first fan-out trace group. Each fan-out trace in the first fan-out trace group extends from the fan-out area to the bonding area and is electrically connected to the corresponding output terminal in the first output terminal group via the adjacent second side.

[0015] Each fan-out trace in the first fan-out trace group includes a first fan-out segment and a second fan-out segment connected to each other. The first fan-out segment and the second fan-out segment are located on different layers. Each first fan-out segment is electrically connected to the display area, and each second fan-out segment is electrically connected to the corresponding output terminal in the first output terminal group.

[0016] According to the display panel provided in this application, a plurality of second fan-out sections are electrically connected to the corresponding output terminals in the first output terminal group via adjacent second sides;

[0017] Multiple first fan-out segments are arranged along a preset direction, and multiple second fan-out segments are arranged along the preset direction at the ends not connected to the first fan-out segments. In the preset direction, the arrangement order of each first fan-out segment is the same as the arrangement order of the ends of the corresponding connected second fan-out segments not connected to the first fan-out segments; wherein, the preset direction is perpendicular to the direction from the display area to the fan-out area.

[0018] According to the display panel provided in this application, a plurality of first fan-out sections are connected to corresponding second fan-out sections via adjacent second sides, and a plurality of second fan-out sections are electrically connected to the corresponding output terminals in the first output terminal group;

[0019] Multiple first fan-out segments are arranged along a preset direction at their ends not connected to the second fan-out segments, and multiple second fan-out segments are arranged along the preset direction. In the preset direction, the arrangement order of the ends of each first fan-out segment not connected to the second fan-out segment is the same as the arrangement order of the corresponding connected second fan-out segments. The preset direction is perpendicular to the direction from the display area to the fan-out area.

[0020] According to the display panel provided in this application, the plurality of output terminals further include a second output terminal group, and the plurality of fan-out traces further include a second fan-out trace group; each of the fan-out traces in the second fan-out trace group is electrically connected to the corresponding output terminal in the second output terminal group.

[0021] According to the display panel provided in this application, a plurality of output terminals of the first output terminal group and a plurality of output terminals of the second output terminal group are arranged along the extending direction of the first side, and the second output terminal group is disposed on the side of the first output terminal group away from the adjacent second side.

[0022] According to the display panel provided in this application, a plurality of output terminals of the first output terminal group and a plurality of output terminals of the second output terminal group are arranged along the extending direction of the first side, and at least a portion of the output terminals of the second output terminal group are disposed on the side of the first output terminal group near the adjacent second side.

[0023] According to the display panel provided in this application, a plurality of output terminals of the first output terminal group are arranged along the extension direction of the adjacent second side, and a plurality of output terminals of the second output terminal group are arranged along the extension direction of the first side.

[0024] According to the display panel provided in this application, the output terminals of the second output terminal group are arranged along the extending direction of the first side, and the output terminals of the first output terminal group are located on the side of the second output terminal group away from the display area.

[0025] According to the display panel provided in this application, the display panel further includes a test pad disposed on the substrate, the test pad including a first segment and a second segment, the first segment being located in the fan-out area and the second segment being located in the bonding area.

[0026] According to the display panel provided in this application, the orthographic projection of the first segment on the substrate overlaps with the orthographic projection of the first fan-out segment on the substrate, and the orthographic projection of the second segment on the substrate is located on the side of the orthographic projection of the second output terminal group on the substrate that is away from the display area.

[0027] According to the display panel provided in this application, the display panel further includes multiple test pad connection traces for connecting the first segment and the second segment; there is a gap between two adjacent output terminals of the first output terminal group, and at least a portion of the test pad connection traces pass through the gap from the side of the first side near the display area to connect with the second segment.

[0028] According to the display panel provided in this application, the driver chip further includes a third side away from the display area; the driver chip further includes a plurality of input terminals, the plurality of input terminals being arranged along the extending direction of the third side.

[0029] According to the display panel provided in this application, the output terminals of the second output terminal group are arranged along the extension direction of the first side, and the output terminals of the first output terminal group are arranged along the extension direction of the third side.

[0030] According to the display panel provided in this application, at least a portion of the output terminals of the first output terminal group are disposed among the plurality of input terminals.

[0031] According to the display panel provided in this application, the display panel further includes a flexible circuit board disposed on the side of the driver chip away from the display area, and the flexible circuit board is electrically connected to the input terminal.

[0032] This application provides a display device, including a display panel, the display panel including a substrate, the substrate including a display area and a non-display area surrounding the display area, the non-display area including a bonding area and a fan-out area connecting the bonding area and the display area;

[0033] The bonding area is provided with a driver chip. The driver chip includes a first side near the display area and two second sides connected to the first side. The driver chip includes multiple output terminals, and the multiple output terminals include at least a first output terminal group.

[0034] The fan-out area is provided with multiple fan-out traces, and the multiple fan-out traces include at least a first fan-out trace group. Each fan-out trace in the first fan-out trace group extends from the fan-out area to the bonding area and is electrically connected to the corresponding output terminal in the first output terminal group via the adjacent second side.

[0035] Each fan-out trace in the first fan-out trace group includes a first fan-out segment and a second fan-out segment connected to each other. The first fan-out segment and the second fan-out segment are located on different layers. Each first fan-out segment is electrically connected to the display area, and each second fan-out segment is electrically connected to the corresponding output terminal in the first output terminal group.

[0036] According to the display device provided in this application, a plurality of second fan-out sections are electrically connected to the corresponding output terminals in the first output terminal group via adjacent second sides;

[0037] Multiple first fan-out segments are arranged along a preset direction, and multiple second fan-out segments are arranged along the preset direction at the ends not connected to the first fan-out segments. In the preset direction, the arrangement order of each first fan-out segment is the same as the arrangement order of the ends of the corresponding connected second fan-out segments not connected to the first fan-out segments; wherein, the preset direction is perpendicular to the direction from the display area to the fan-out area.

[0038] According to the display device provided in this application, a plurality of first fan-out sections are connected to corresponding second fan-out sections via adjacent second sides, and a plurality of second fan-out sections are electrically connected to the corresponding output terminals in the first output terminal group;

[0039] Multiple first fan-out segments are arranged along a preset direction at their ends not connected to the second fan-out segments, and multiple second fan-out segments are arranged along the preset direction. In the preset direction, the arrangement order of the ends of each first fan-out segment not connected to the second fan-out segment is the same as the arrangement order of the corresponding connected second fan-out segments. The preset direction is perpendicular to the direction from the display area to the fan-out area.

[0040] According to the display device provided in this application, the plurality of output terminals further include a second output terminal group, and the plurality of fan-out traces further include a second fan-out trace group; each of the fan-out traces in the second fan-out trace group is electrically connected to the corresponding output terminal in the second output terminal group.

[0041] According to the display device provided in this application, a plurality of output terminals of the first output terminal group and a plurality of output terminals of the second output terminal group are arranged along the extending direction of the first side, and the second output terminal group is disposed on the side of the first output terminal group away from the adjacent second side.

[0042] Beneficial effects of the invention

[0043] Beneficial effects

[0044] The beneficial effects of this application are as follows: The display panel and display device provided in this application have multiple fan-out traces in the fan-out area of ​​the display panel. These multiple fan-out traces include at least a first fan-out trace group. Each fan-out trace in the first fan-out trace group extends from the fan-out area to the bonding area and is electrically connected to a corresponding output terminal in the first output terminal group via an adjacent second side. This application employs a jumper design for each fan-out trace in the first fan-out trace group. Each fan-out trace in the first fan-out trace group includes an interconnected first fan-out segment and a second fan-out segment. The first and second fan-out segments are located on different layers. Each first fan-out segment is electrically connected to the display area, and each second fan-out segment is electrically connected to a corresponding output terminal in the first output terminal group. While achieving a narrow bezel, this ensures that the fan-out traces are electrically connected to their corresponding output terminals, preventing short circuits between multiple fan-out traces and avoiding display defects caused by signal misalignment due to inconsistent arrangement of output terminals and fan-out traces.

[0045] Brief description of the accompanying drawings Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the planar structure of an existing display panel;

[0048] Figure 2 A simplified planar structural diagram of a display panel provided in an embodiment of this application;

[0049] Figure 3 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application;

[0050] Figure 4 for Figure 3 A schematic diagram of the cross-sectional structure of the display area of ​​the display panel in the image;

[0051] Figure 5 for Figure 3 A schematic diagram of the cross-sectional structure of the non-display area of ​​the display panel in the diagram;

[0052] Figure 6 This is a schematic diagram of a first partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0053] Figure 7 This is a schematic diagram of a second partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0054] Figure 8 This is a schematic diagram of a third partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of a fourth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0056] Figure 10 This is a schematic diagram of a fifth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0057] Figure 11 This is a schematic diagram of a sixth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0058] Figure 12 This is a schematic diagram of a seventh partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0059] Figure 13 This is a schematic diagram of an eighth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application;

[0060] Figure 14 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this application.

[0061] Explanation of reference numerals in the attached figures:

[0062] 100' Display panel; 103' Bonding area; 104' Fan-out area; 105' Driver chip; 106' Output terminal; 107' Fan-out wiring;

[0063] 100. Display panel; 101. Display area; 102. Non-display area; 103. Bonding area; 104. Fan-out area; 105. Driver chip; 1051. First side; 1052. Second side; 1053. Third side; 106. Output terminal; 107. Fan-out trace; 1071. First fan-out section; 1072. Second fan-out section; 108. Input terminal; 1091. First segment; 1092. Second segment; 110. Flexible circuit board; 111. First signal trace; 112. Second signal trace; 113. Test pad connection trace;

[0064] 10. First output terminal group; 11. First sector outgoing cabling group; 12. Second output terminal group; 13. Second sector outgoing cabling group;

[0065] 1. Substrate; 2. First metal layer; 21. Gate; 3. Gate insulating layer; 31. Insulating layer; 32. Connecting hole; 4. Semiconductor layer; 5. Second metal layer; 51. Source; 52. Drain.

[0066] Invention Embodiments

[0067] Embodiments of the present invention

[0068] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0069] Please see Figure 2 and Figure 3 , Figure 2 This is a simplified planar structural diagram of a display panel provided in an embodiment of this application. Figure 3 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application.

[0070] This application provides a display panel 100, which includes a substrate 1. The substrate 1 includes a display area 101 and a non-display area 102 surrounding the display area 101. The non-display area 102 includes a bonding area 103 and a fan-out area 104 connecting the bonding area 103 and the display area 101. The fan-out area 104 is located between the display area 101 and the bonding area 103.

[0071] The binding area 103 is provided with a driver chip 105. The driver chip 105 includes a first side 1051 near the display area 101 and two second sides 1052 connected to the first side 1051. The two second sides 1052 are arranged opposite to each other. The driver chip 105 includes a plurality of output terminals 106, and the plurality of output terminals 106 form a first output terminal group 10.

[0072] The fan-out area 104 is provided with a plurality of fan-out traces 107, and the plurality of fan-out traces 107 include at least a first fan-out trace group 11. Each fan-out trace 107 in the first fan-out trace group 11 extends from the fan-out area 104 to the bonding area 103 and is electrically connected to the corresponding output terminal 106 in the first output terminal group 10 via the adjacent second side 1052.

[0073] Optionally, the driving chip 105 is rectangular in shape, with the first side 1051 and the second side 1052 perpendicular to each other, and the two second sides 1052 parallel to each other.

[0074] On the one hand, to avoid short circuits between the fan-out traces 107 in multiple first fan-out trace groups 11, each fan-out trace 107 in the first fan-out trace group 11 must not make contact with each other. On the other hand, it is also necessary to avoid display defects caused by signal transmission errors between the fan-out traces 107 and the fan-out traces 107 in the first fan-out trace group 11. Therefore, each fan-out trace 107 in each first fan-out trace group 11 needs to be electrically connected to the corresponding output terminal 106 in the first output terminal group 10. Thus, the fan-out traces 107 located on the outer side need to be electrically connected to the output terminal 106 located on the outer side, and the fan-out traces 107 located on the inner side need to be electrically connected to the output terminal 106 located on the inner side. Furthermore, the fan-out cable 107 in the first fan-out cable group 11 located on the outer side needs to be electrically connected to the output terminal 106 in the first output terminal group 10 located on the outer side, and the fan-out cable 107 in the first fan-out cable group 11 located on the inner side needs to be electrically connected to the output terminal 106 in the first output terminal group 10 located on the inner side.

[0075] In view of this, the present application embodiment achieves the above objective by using a jumper connection for the plurality of fan-out cables 107 in the first fan-out cable group 11. The specific solution is described below.

[0076] Each fan-out trace 107 in the first fan-out trace group 11 includes an adjacent first fan-out segment 1071 and a second fan-out segment 1072. The first fan-out segment 1071 and the second fan-out segment 1072 are located on different layers to ensure that even if the first fan-out segment 1071 and the second fan-out segment 1072 overlap in a plane direction perpendicular to the display panel, the first fan-out segment and the second fan-out segment 1072 will not come into contact, thereby avoiding short circuits between the fan-out traces 107 in multiple first fan-out trace groups 11.

[0077] Each of the first fan-out segments 1071 is electrically connected to the display area 101, and each of the second fan-out segments 1072 is electrically connected to the corresponding output terminal 106 in the first output terminal group 10. That is, the display area 101 is first electrically connected to the first fan-out segment 1071, and then electrically connected to the output terminal 106 in the first output terminal group 10 through the second fan-out segment 1072.

[0078] It is understood that, compared to the prior art where each part of the output line 107 in the first output line group 11 is located in the same film layer, each output line 107 in this application can be electrically connected to the corresponding output terminal 106, thereby avoiding display defects caused by signal transmission disorder due to inconsistent order of the two.

[0079] To more clearly illustrate the structure of the fan-out cable 107 in the first fan-out cable group 11, the following is in conjunction with... Figure 4 The structure of the display panel 100 in the embodiments of this application will be described. Figure 4 This is a cross-sectional structural diagram of the display area 101 of the display panel 100 provided in the embodiments of this application.

[0080] It should be noted that the display panel 100 in the embodiments of this application can be a bottom-gate type display panel or a top-gate type display panel, and this application is not limited thereto. In order to clearly describe the technical solutions in this application, the embodiments of this application take the display panel 100 as a bottom-gate type display panel as an example for illustration.

[0081] Specifically, the display panel 100 includes a substrate 1 and a thin-film transistor array layer. The thin-film transistor array layer is disposed on the substrate 1 and includes a plurality of thin-film transistors arranged in an array and a plurality of signal traces. The substrate 1 can be made of any suitable insulating material with flexibility, and can be transparent, translucent, or opaque.

[0082] The thin-film transistor array layer includes a first metal layer 2, a gate insulating layer 3, a semiconductor layer 4, and a second metal layer 5. Specifically, the first metal layer 2 is located on the substrate 1 and includes a gate 21 and scan signal traces (not shown in the figure). The gate insulating layer 3 is located on the first metal layer 2 and covers the substrate 1 and the gate 21. The semiconductor layer 4 is located on the gate insulating layer 3, and the material of the semiconductor layer 4 can be low-temperature polycrystalline silicon or amorphous silicon. The second metal layer 5 is located on the semiconductor layer 4 and covers the gate insulating layer 3 and the semiconductor layer 4. The second metal layer 5 includes a source 51, a drain 52, and data signal traces (not shown in the figure).

[0083] Specifically, the materials of the first metal layer 2 and the second metal layer 5 can be the same or different. The material of the first metal layer 2 can be a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (5i), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or alloys such as aluminum (Al): neodymium (5d) alloys or molybdenum (Mo): tungsten (W) alloys; the material of the second metal layer 5 can be a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (5i), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or alloys such as aluminum (Al): neodymium (5d) alloys or molybdenum (Mo): tungsten (W) alloys.

[0084] As one example, please refer to Figure 5 , Figure 5 for Figure 3 A schematic diagram of the cross-sectional structure of the non-display area of ​​the display panel.

[0085] Specifically, the first fan-out segment 1071 is located on the substrate 1, and the second fan-out segment 1072 is located on the side of the first fan-out segment 1071 away from the substrate 1. That is, the first fan-out segment 1071 is disposed in the same layer as the first metal layer 2, and the second fan-out segment 1072 is disposed in the same layer as the second metal layer 5. Alternatively, in other embodiments, the second fan-out segment 1072 is located on the substrate 1, and the first fan-out segment 1071 is located on the side of the second fan-out segment 1072 away from the substrate 1. That is, the first fan-out segment 1071 is disposed in the same layer as the second metal layer 5, and the second fan-out segment 1072 is disposed in the same layer as the first metal layer 2.

[0086] Furthermore, an insulating layer 31 is provided between the first fan-out section 1071 and the second fan-out section 1072 to prevent short circuits between them. The first fan-out section 1071 and the second fan-out section 1072 are electrically connected through connection holes 32 formed in the insulating layer 31. The insulating layer 31 and the gate insulating layer 3 are disposed in the same layer and are fabricated using the same process.

[0087] Please see Figures 6-13 , Figures 6-13 These are schematic diagrams illustrating various partial structures of the non-display area of ​​a display panel provided in embodiments of this application.

[0088] Specifically, Figures 6-13The first fan-out routing group 11 includes multiple fan-out routing lines 107, and the first output terminal group 10 includes multiple output terminals 106. It should be noted that, for ease of description, this application embodiment uses the example of the first fan-out routing group 11 including 5 fan-out routing lines 107 and the first output terminal group 10 including 5 output terminals 106 for illustration, but this application should not be considered limiting.

[0089] The following will be about Figures 6-13 The various embodiments provided will be described one by one.

[0090] As one example, please refer to Figure 6 , Figure 6 This is a schematic diagram of a first partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0091] Specifically, a plurality of second fan-out segments 1072 are electrically connected to the corresponding output terminals 106 in the first output terminal group 10 via adjacent second side 1052. A plurality of first fan-out segments 1071 are arranged along a preset direction, and the ends of a plurality of second fan-out segments 1072 not connected to the first fan-out segments 1071 are arranged along the preset direction. In the preset direction, the arrangement order of each first fan-out segment 1071 is the same as the arrangement order of the corresponding connected ends of the second fan-out segments 1072 not connected to the first fan-out segment 1071.

[0092] Specifically, the preset direction is perpendicular to the direction from the display area 101 to the fan-out area 104, and the preset direction can be referred to as... Figure 6 The first direction in which the display area 101 points to the fan-out area 104 can be referred to Figure 6 The second direction in, Figures 7-13 The first and second directions are similar, and will not be described again below.

[0093] Generally, the extension direction of the first side 1051 is perpendicular to the direction of the display area 101 pointing to the fan-out area 104, so the preset direction can be parallel to the extension direction of the first side 1051.

[0094] Specifically, the first fan-out segment 1071 of the first fan-out line, the first fan-out segment 1071 of the second fan-out line, ..., the first fan-out segment 1071 of the fifth fan-out line are arranged sequentially along the preset direction. The end of the second fan-out segment 1072 of the first fan-out line that is not connected to the first fan-out segment 1071, the end of the second fan-out segment 1072 of the second fan-out line that is not connected to the first fan-out segment 1071, ..., the end of the second fan-out segment 1072 of the fifth fan-out line that is not connected to the first fan-out segment 1071 are arranged sequentially along the preset direction. The first output terminal, the second output terminal, ..., the fifth output terminal of the first output terminal group 10 are arranged sequentially along the extension direction of the first side 1051. The first fan-out segment of the first fan-out line is electrically connected to the first output terminal through the second fan-out segment 1072 of the first fan-out line; the first fan-out segment 1071 of the second fan-out line is electrically connected to the second output terminal through the second fan-out segment 1072 of the second fan-out line; and so on. The first fan-out segment 1071 of the fifth fan-out line is electrically connected to the fifth output terminal through the second fan-out segment 1072 of the fifth fan-out line.

[0095] It is understood that the embodiments of this application adopt a jumper design to avoid short circuits between the fan-out traces 107, so that each fan-out trace 107 of the first fan-out trace group 11 can be connected to a corresponding output terminal 106 in the first output terminal group 10, thereby ensuring that each fan-out trace 107 can be electrically connected to the corresponding output terminal 106, thus avoiding display defects caused by signal transmission disorder due to inconsistent order.

[0096] As one example, please refer to Figure 7 , Figure 7 This is a schematic diagram of a second partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0097] Specifically, multiple first fan-out segments 1071 are connected to corresponding second fan-out segments 1072 via adjacent second sides 1052, and multiple second fan-out segments 1072 are electrically connected to corresponding output terminals 106 in the first output terminal group 10. The ends of multiple first fan-out segments 1071 not connected to second fan-out segments 1072 are arranged along the preset direction, and multiple second fan-out segments 1072 are arranged along the preset direction. In the preset direction, the arrangement order of the ends of each first fan-out segment 1071 not connected to the second fan-out segment 1072 is the same as the arrangement order of the corresponding connected second fan-out segments 1072.

[0098] Specifically, the ends of the first fan-out segment 1071 of the first fan-out cable that are not connected to the second fan-out segment 1072, the ends of the first fan-out segment 1071 of the second fan-out cable that are not connected to the second fan-out segment 1072, ..., the ends of the first fan-out segment 1071 of the fifth fan-out cable that are not connected to the second fan-out segment 1072 are arranged sequentially along the preset direction. The second fan-out segments 1072 of the first fan-out cable, the second fan-out segment 1072 of the second fan-out cable, ..., the second fan-out segment 1072 of the fifth fan-out cable are arranged sequentially along the preset direction. The first output terminal, the second output terminal, ..., the fifth output terminal of the first output terminal group 10 are arranged sequentially along the extension direction of the first side 1051. Specifically, the first fan-out section 1071 of the first fan-out line is electrically connected to the first output terminal through the second fan-out section 1072 of the first fan-out line; the first fan-out section 1071 of the second fan-out line is electrically connected to the second output terminal through the second fan-out section 1072 of the second fan-out line; and so on, the first fan-out section 1071 of the fifth fan-out line is electrically connected to the fifth output terminal through the second fan-out section 1072 of the fifth fan-out line.

[0099] It is understood that the embodiments of this application adopt a jumper design to avoid short circuits between the fan-out traces 107, so that each fan-out trace 107 of the first fan-out trace group 11 can be connected to a corresponding output terminal 106 in the first output terminal group 10, thereby ensuring that each fan-out trace 107 can be electrically connected to the corresponding output terminal 106, thus avoiding display defects caused by signal transmission disorder due to inconsistent order.

[0100] Furthermore, the outermost first fan-out trace is electrically connected to the first output terminal closest to the second side 1052, and the innermost fifth fan-out trace is electrically connected to the fifth output terminal furthest from the second side 1052. This reduces the length of the outermost first fan-out trace. Since the impedance of the fan-out trace is positively correlated with its length, the design of this application can reduce the impedance of the outermost first fan-out trace.

[0101] Similarly, the lengths of the 2nd / 3rd / 4th fan-out traces located between the 1st and 5th fan-out traces are similar to the lengths of the 1st and 5th fan-out traces, and their impedances are also similar. Therefore, compared to the fan-out traces 107 in the first fan-out trace group 11 of the prior art, which are located in the same film layer, the impedances of the multiple fan-out traces 107 in the first fan-out trace group 11 of this application are approximately equal, thereby achieving impedance uniformity and improving the uniformity of signal transmission.

[0102] Please continue reading. Figure 6 and Figure 7 The plurality of output terminals 106 further include a second output terminal group 12, and the plurality of fan-out traces 107 further include a second fan-out trace group 13. Each fan-out trace 107 of the second fan-out trace group 13 is electrically connected to the corresponding output terminal 106 in the second output terminal group 12. The plurality of fan-out traces 107 of the second fan-out trace group 13 are consistent with the design of fan-out traces in the prior art and are arranged in a single layer.

[0103] Specifically, the plurality of output terminals 106 of the first output terminal group 10 and the plurality of output terminals 106 of the second output terminal group 12 are arranged along the extending direction of the first side 1051, and the second output terminal group 12 is disposed on the side of the first output terminal group 10 away from the second side 1052. Compared with existing conventional driver chips, the arrangement order of the plurality of output terminals 106 of the driver chip 105 in this application is fixed and unchanged, and the arrangement order of the fan-out traces 107 is the same as the arrangement order of the output terminals 106, so that each fan-out trace 107 can be electrically connected to the corresponding output terminal 106, thereby avoiding display defects caused by signal transmission errors due to inconsistent order. Therefore, the display panel 100 of this application can directly use existing conventional driver chips without any need to redesign the arrangement order of the output terminals of the driver chip, saving costs and facilitating mass production.

[0104] Furthermore, the technical solution provided in this application is also applicable to the display panel 100 using the newly designed driver chip 105. The structure of the display panel 100 that may be involved in the embodiments of this application will be illustrated below. The structure of the fan-out trace 107 of the first fan-out trace group 11 and the connection relationship between it and the output terminal 106 of the first output terminal group 10 can be referred to the above discussion, and will not be repeated here.

[0105] As one example, please refer to Figure 8 , Figure 8 This is a schematic diagram of a third partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0106] Specifically, the plurality of output terminals 106 of the first output terminal group 10 and the plurality of output terminals 106 of the second output terminal group 12 are arranged along the extending direction of the first side 1051, and at least a portion of the output terminals 106 of the second output terminal group 12 are disposed on the side of the first output terminal group 10 near the adjacent second side 1052.

[0107] It is understandable that, since the output terminals 106 of the second output terminal group 12 are located in the middle area of ​​the driver chip 105, and the output terminals 106 of the first output terminal group 10 are located on the left and right sides of the driver chip 105, there is still room for compression of the fan-out traces 107 in the second fan-out trace group 13 connected to the output terminals 106 of the second output terminal group 12, while the fan-out traces 107 in the first fan-out trace group 11 connected to the output terminals 106 of the first output terminal group 10 cannot be further compressed. Therefore, in this embodiment, by setting at least a portion of the output terminals 106 of the second output terminal group 12 on the side of the first output terminal group 10 near the second side 1052, the bonding area 103 can be further moved upward as a whole, thereby reducing the lower bezel of the display panel 100.

[0108] As one example, please refer to Figure 9 , Figure 9 This is a schematic diagram of a fourth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0109] Specifically, the plurality of output terminals 106 of the first output terminal group 10 are arranged along the extension direction of the adjacent second side 1052, and the plurality of output terminals 106 of the second output terminal group 12 are arranged along the extension direction of the first side 1051.

[0110] Specifically, the first output terminal, the second output terminal... the fifth output terminal of the first output terminal group 10 are arranged sequentially along the preset direction (second direction). The first fan-out section 1071 is electrically connected to the first output terminal through the first second fan-out section 1072, the second fan-out section 1071 is electrically connected to the second output terminal through the second second fan-out section 1072... the fifth fan-out section 1071 is electrically connected to the fifth output terminal through the fifth second fan-out section 1072.

[0111] As one example, please refer to Figure 10 , Figure 10 This is a schematic diagram of a fifth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0112] Specifically, the output terminals 106 of the second output terminal group 12 are arranged along the extending direction of the first side 1051, and the output terminals 106 of the first output terminal group 10 are located on the side of the second output terminal group 12 away from the display area 101.

[0113] That is, the output terminals 106 of the first output terminal group 10 and the output terminals 106 of the second output terminal group 12 are arranged side by side. In the extending direction (first direction) of the first side 1051, the arrangement order of the output terminals 106 of the first output terminal group 10 is the opposite of the arrangement order of the output terminals 106 of the second output terminal group 12.

[0114] Specifically, the first output terminal, the second output terminal... the fifth output terminal of the first output terminal group 10 are arranged sequentially in the opposite direction of the first direction. The first fan-out section 1071 is electrically connected to the first output terminal through the first second fan-out section 1072, the second fan-out section 1071 is electrically connected to the second output terminal through the second second fan-out section 1072... the fifth fan-out section 1071 is electrically connected to the fifth output terminal through the fifth second fan-out section 1072.

[0115] Further, please refer to Figures 2-12 The driver chip 105 further includes a third side 1053 located away from the display area 101. The third side 1053 is disposed opposite to the first side 1051 and is connected to two second sides 1052. The driver chip 105 also includes a plurality of input terminals 108 for transmitting external signals to output terminals 106. The plurality of input terminals 108 are arranged along the extending direction of the third side 1053.

[0116] As one example, please refer to Figure 11 , Figure 11 This is a schematic diagram of a sixth partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0117] Specifically, the output terminals 106 of the second output terminal group 12 are arranged along the extension direction of the first side 1051, the output terminals 106 of the first output terminal group 10 are arranged along the extension direction of the third side 1053, and the second output terminal group 12 is located on the side of the input terminal 108 near the second side 1052.

[0118] As one example, please refer to Figure 12 , Figure 12 This is a schematic diagram of a seventh partial structure of the non-display area of ​​a display panel provided in an embodiment of this application.

[0119] Specifically, the output terminals 106 of the second output terminal group 12 are arranged along the extension direction of the first side 1051, the output terminals 106 of the first output terminal group 10 are arranged along the extension direction of the third side 1053, and at least a portion of the output terminals 106 of the second output terminal group 12 are disposed between the plurality of input terminals 108.

[0120] Further, please refer to Figure 3 , Figure 6 and Figure 12 The display panel 100 also includes a test pad disposed on the substrate 1 for performing image detection on the display panel.

[0121] Specifically, before bonding the integrated circuit chip to the display panel 100, data signals and clock signals can be sent to the display area 101 of the display panel 100 through the test pad to detect the screen of the display panel 100. By detecting the screen, it can be determined whether there is a display abnormality in the display panel 100. If there is a display abnormality, the cause of the display abnormality can be found in time and the abnormality can be handled before bonding. Bonding can be carried out after the display is normal to ensure that the display function of the display panel 100 is normal after bonding. This is beneficial to improving the production yield of the display panel 100. If the detection is carried out after bonding, the workload of rework when the display is abnormal is large and will greatly reduce the production yield of the display panel 100.

[0122] To accommodate the jumper design of the fan-out cable 107 in this embodiment, the test pad in this embodiment also adopts a segmented design.

[0123] Specifically, the test pad includes a first segment 1091 and a second segment 1092, where the first segment 1091 is located in the fan-out area 104 and the second segment 1092 is located in the bonding area 103. Compared to the prior art, this application, by placing a portion of the test pad outside the bonding area 103, allows for more space on the substrate corresponding to the driver chip 105 to arrange the fan-out traces 107, thereby further reducing the bottom bezel of the display panel 100.

[0124] Understandably, since the first fan-out segment 1071 is a vertical trace, it does not restrict the setting of the test pad. Therefore, the first segment 1091 is correspondingly set with the first fan-out segment 1071, and the orthographic projection of the first segment 1091 on the substrate 1 overlaps with the orthographic projection of the first fan-out segment 1071 on the substrate 1. The fan-out trace 107 in the first fan-out trace group 11 is first electrically connected to the first segment 1091, and then electrically connected to the output terminal 106 of the first output terminal group 10. Before binding the driver chip 105, the first segment 1091 is used to provide test signals to the fan-out trace 107 in the first fan-out trace group 11 to detect the image.

[0125] Conversely, since the second fan-out segment 1072 is a horizontal trace, it restricts the placement of the test pad. Therefore, the orthographic projection of the second segment 1092 on the substrate 1 does not overlap with the orthographic projections of the output terminal 106 and the input terminal 108 on the substrate 1. The orthographic projection of the second segment 1092 on the substrate 1 is located on the side of the second output terminal group 12 on the substrate 1 that is furthest from the display area 101. The fan-out trace 107 in the second fan-out trace group 13 is first electrically connected to the plurality of output terminals 106 of the second output terminal group 12, and then electrically connected to the second segment 1092. The second segment 1092 is used to provide test signals to the fan-out trace 107 in the second fan-out trace group 13 for image detection before bonding the integrated circuit chip.

[0126] Further, please refer to Figure 13 , Figure 13 This is a schematic diagram of the eighth partial structure of the non-display area of ​​the display panel provided in the embodiments of this application. Figure 13 Is Figure 6 This improvement is based on the previous one, and of course, such improvement can also be applied to other embodiments.

[0127] The display panel 100 also includes multiple test pad connection traces 113 for connecting the first segment 1091 and the second segment 1092. A gap exists between two adjacent output terminals 106 of the first output terminal group 10, and at least a portion of the test pad connection traces 113 pass through the gap from the side of the first side 1051 near the display area 101 to connect to the second segment 1092.

[0128] It is understood that the test pad connection trace 113 is routed on the side of the first side 1051 near the display area 101, which helps to save space below the first output terminal group 10, thereby increasing the routing space for the fan-out trace 107 in the first fan-out trace group 11, reducing the number of fan-out traces 107 in the second fan-out trace group 13, and further reducing the lower bezel of the display panel 100.

[0129] Please see Figure 14 , Figure 14 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this application.

[0130] Furthermore, the display panel 100 also includes a flexible circuit board 110 disposed on the side of the driver chip 105 away from the display area 101, and the flexible circuit board 110 is electrically connected to the input terminal 108. Signals transmitted to the display area 101 are typically first transmitted to the input terminal 108 via the flexible circuit board 110, then transmitted to the output terminal 106 via the traces inside the input terminal 108 and the driver chip 105, and finally transmitted to the display area 101 via the output terminal 106 and the fan-out trace 107.

[0131] For further information, please refer to [link / reference]. Figure 3 and Figure 14 The display panel 100 also includes multiple signal lines, which are disposed in the display area 101, and each signal line is electrically connected to the corresponding fan-out line 107.

[0132] In terms of location, the multiple signal traces include a first signal trace 111 and a second signal trace 112. The first signal trace 111 is electrically connected to the output terminal 106 of the first output terminal group 10 through the fan-out trace 107 of the first fan-out trace group 11. The second signal trace 112 is electrically connected to the output terminal of the second output terminal group 12 through the fan-out trace 107 of the second fan-out trace group 13.

[0133] Functionally, the multiple signal traces may include multiple data signal traces and multiple touch signal traces. The data signal traces are arranged in the same way as the touch signal traces, and the data signal traces are insulated from the touch signal traces. In this application, the flexible circuit board 110 sends control signals to the touch signal traces via the driver chip 105, and the driver chip 105 sends data signals to the data signal traces.

[0134] This application embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, and navigator.

[0135] The beneficial effects are as follows: The display panel and display device provided in this application embodiment have multiple fan-out traces in the fan-out area of ​​the display panel. These multiple fan-out traces include at least a first fan-out trace group. Each fan-out trace in the first fan-out trace group extends from the fan-out area to the bonding area and is electrically connected to a corresponding output terminal in the first output terminal group via an adjacent second side. This application employs a jumper design for each fan-out trace in the first fan-out trace group. Each fan-out trace in the first fan-out trace group includes an interconnected first fan-out segment and a second fan-out segment. The first fan-out segment and the second fan-out segment are located on different layers. Each first fan-out segment is electrically connected to the display area, and each second fan-out segment is electrically connected to a corresponding output terminal in the first output terminal group. While achieving a narrow bezel, this ensures that the fan-out traces are electrically connected to their corresponding output terminals, preventing short circuits between multiple fan-out traces and avoiding display defects caused by signal misalignment due to inconsistent arrangement of output terminals and fan-out traces.

[0136] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A display panel, characterized in that, The system includes a substrate on which multiple signal traces are disposed, a driver chip located on one side of the multiple signal traces, and multiple fan-out traces for electrically connecting the multiple signal traces and the driver chip. The driver chip includes a first side near the signal trace and a plurality of output terminals arranged along the extending direction of the first side, wherein the plurality of output terminals includes at least a first output terminal group. The plurality of fan-out routing lines include at least a first fan-out routing line group, wherein the fan-out routing line in the first fan-out routing line group is electrically connected to the end of the corresponding output terminal in the first output terminal group that is away from the first side. The display panel further includes a test pad disposed on the substrate, wherein the orthographic projection of the test pad on the driver chip does not overlap with the orthographic projection of the first fan-out trace group on the driver chip; The test pad includes a first segment and a second segment that are electrically connected. The orthographic projection of the first segment on the substrate is outside the orthographic projection of the driver chip on the substrate, and the orthographic projection of the second segment on the substrate is inside the orthographic projection of the driver chip on the substrate. The fan-out traces in the first fan-out trace group are electrically connected to the first segment and the output terminals in the first output terminal group in turn.

2. The display panel according to claim 1, characterized in that, The first segment is electrically connected to the first fan-out routing group, and the orthographic projection of the first fan-out routing group on the substrate overlaps with the orthographic projection of the first segment on the substrate.

3. The display panel according to claim 1, characterized in that, The display panel also includes multiple test pad connection lines for connecting the first segment and the second segment; There is a gap between two adjacent output terminals of the first output terminal group, and at least part of the test pad connection traces pass through the gap from the side of the first side near the plurality of signal traces and connect to the second segment.

4. The display panel according to claim 1, characterized in that, The plurality of output terminals further includes a second output terminal group, and the plurality of fan-out routing lines further includes a second fan-out routing line group. Each fan-out routing line of the second fan-out routing line group is electrically connected to the end of the corresponding output terminal in the second output terminal group that is close to the first side. The driver chip also includes a third side disposed opposite to the first side, and the orthographic projection of the second segment on the driver chip is located in the region between the second output terminal group and the third side.

5. The display panel according to claim 4, characterized in that, The driver chip also includes two second sides that connect the first side and the third side; In this configuration, each fan-out cable in the first fan-out cable group is electrically connected to the corresponding output terminal in the first output terminal group via an adjacent second side, and each fan-out cable in the second fan-out cable group is electrically connected to the output terminal in the second output terminal group via the first side.

6. The display panel according to claim 5, characterized in that, Each of the fan-out traces in the first fan-out trace group includes a first fan-out segment and a second fan-out segment connected to each other. The first fan-out segment is electrically connected to the corresponding signal trace, and the second fan-out segment is electrically connected to the end of the corresponding output terminal in the first output terminal group that is away from the first side. The first fan-out segment and the second fan-out segment are located on different layers, and the orthographic projection of the first fan-out segment on the substrate and the orthographic projection of the second fan-out segment on the substrate at least partially overlap.

7. The display panel according to claim 6, characterized in that, The second fan-out section is located on the side of the first fan-out section away from the substrate.

8. The display panel according to claim 6, characterized in that, The first fan-out section is located on the side of the second fan-out section away from the substrate.

9. The display panel according to claim 6, characterized in that, The multiple signal traces include multiple first signal traces and multiple second signal traces. The multiple first signal traces are located on the side of the multiple second signal traces near the edge of the display panel. The first signal traces are electrically connected to the output terminals of the first output terminal group through the fan-out traces of the first fan-out trace group. The second signal traces are electrically connected to the output terminals of the second output terminal group through the fan-out traces of the second fan-out trace group. Among the plurality of first signal traces, the first fan-out segment electrically connected to the first signal trace near the edge of the display panel is electrically connected to the corresponding output terminal in the first output terminal group located near the second side through a second fan-out segment, and the first fan-out segment electrically connected to the first signal trace located away from the edge of the display panel is electrically connected to the corresponding output terminal in the first output terminal group located away from the second side through a second fan-out segment.

10. The display panel according to claim 6, characterized in that, Multiple second fan-out sections are electrically connected to the side of the corresponding output terminal in the first output terminal group away from the first side via an adjacent second side; Wherein, the overlapping portion between the orthographic projection of the first fan-out segment on the substrate and the orthographic projection of the second fan-out segment on the substrate is located outside the orthographic projection of the driver chip on the substrate.

11. The display panel according to claim 6, characterized in that, Multiple first fan-out sections are electrically connected to corresponding second fan-out sections via adjacent second sides; Wherein, the overlapping portion between the orthographic projection of the first fan-out segment on the substrate and the orthographic projection of the second fan-out segment on the substrate is located within the orthographic projection of the driver chip on the substrate.

12. The display panel according to any one of claims 5-11, characterized in that, The second output terminal group is located on the side of the first output terminal group away from the adjacent second side.

13. The display panel according to any one of claims 5-11, characterized in that, At least a portion of the output terminals of the second output terminal group are disposed on the side of the first output terminal group near the adjacent second side.

14. The display panel according to any one of claims 4-11, characterized in that, The output terminal of the first output terminal group is located on the side of the second output terminal group that is away from the first side.

15. The display panel according to claim 1, characterized in that, The lengths of any two fan-out cables in the first fan-out cable group are approximately equal.

16. The display panel according to claim 4, characterized in that, The driver chip also includes multiple input terminals, which are arranged along the extension direction of the third side.

17. The display panel according to claim 16, characterized in that, The display panel also includes a flexible circuit board disposed on the side of the driver chip away from the multiple signal lines, and the flexible circuit board is electrically connected to the input terminal.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

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