A multi-scale PCB board surface defect detection model and method

Abstract

This invention discloses a multi-scale PCB surface defect detection model and method. The model and method involve preprocessing an initial PCB image to extract feature maps at multiple scales, fusing these feature maps to obtain a fused feature map, obtaining a prediction result based on the fused feature map, and then filtering the prediction result to obtain the actual detection result of PCB surface defects. Compared to existing technologies, efficient feature extraction and fusion significantly reduce resource requirements; simultaneously, effective filtering of the prediction results improves the accuracy of defect detection.

Description

Technical Field

[0001] This invention relates to the field of PCB board inspection technology, and in particular to a multi-scale PCB board surface defect detection model and method. Background Technology

[0002] Printed circuit boards (PCBs) are the carriers that connect electronic components, and the standardization of their manufacturing determines whether electronic components can operate reliably. Limited by current technological levels and production environments, some PCBs inevitably have defects. Putting these defective PCBs into use may cause equipment to malfunction or even damage it. Therefore, PCB surface defect detection is a crucial step in the PCB manufacturing process.

[0003] The six common PCB surface defects are missing hole (MS), mouse bite (MB), open circuit (OC), short circuit, spur, and spurious copper (SC).

[0004] Currently, reference-based PCB surface defect detection methods heavily rely on standard PCB images. In practical applications, these methods are easily affected by environmental noise and lighting conditions. Furthermore, reference methods require aligning the standard PCB image with the image of the PCB to be inspected, which is difficult to achieve in real-world operations. CNN-based methods aim to improve defect detection accuracy but neglect the model's parameters and computational cost. Due to limitations imposed by real-world production scenarios and cost factors, defect detection equipment often struggles to meet the computational resource requirements of large-scale detection models.

[0005] Therefore, providing a multi-scale PCB surface defect detection model and method that can effectively solve the above problems is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a multi-scale PCB board surface defect detection model and method. The model has a simple structure, is safe, effective, reliable and easy to operate, and can effectively reduce resource requirements while improving defect detection accuracy.

[0007] Based on the above objectives, the technical solution provided by the present invention is as follows:

[0008] A multi-scale PCB board surface defect detection model includes: a feature extraction module, a feature fusion module, a defect prediction module, and a filtering module;

[0009] The feature extraction module is used to extract features from the preprocessed PCB image to obtain feature maps at multiple scales.

[0010] The feature fusion module is used to fuse feature maps at multiple scales to obtain a feature map after feature fusion.

[0011] The defect prediction module is used to obtain the prediction result of PCB surface defects based on the feature map after feature fusion.

[0012] The filtering module is used to filter the predicted results of PCB surface defects in order to obtain the actual detection results of PCB surface defects.

[0013] Preferably, it further includes: a preprocessing module;

[0014] The preprocessing module is used to perform data enhancement and cropping on the original PCB image to obtain a preprocessed PCB image.

[0015] Preferably, the feature extraction module includes: a CSPV2 module, a channel submodule, and a Focus module;

[0016] The feature extraction module is used to perform a first-stage feature extraction on the preprocessed PCB model, then a second-stage feature extraction, and so on until the Nth-stage feature extraction is performed to obtain feature maps at N scales.

[0017] The CSPV2 module is used to extract fine-grained features of the feature map in the second stage to the Nth stage.

[0018] The channel submodule is used to determine whether the feature map size of any stage is less than a preset threshold in the first stage to the Nth stage. If so, the number of channels of the output feature map of the corresponding stage is reduced.

[0019] The Focus module is used to extract features through a preset slicing method.

[0020] Preferably, the preset slicing method is as follows:

[0021] The first feature map output by the CSPV2 module is sliced ​​into slices at intervals of one pixel to output a second feature map.

[0022] The second feature map is concatenated along the channel dimension;

[0023] Adjust the number of channels in the second feature map.

[0024] Preferably, the feature fusion module includes: an attention module, a CSP-S module, an upsampling module, and a downsampling module;

[0025] Each of the upsampling modules and each of the downsampling modules is connected to each of the attention modules.

[0026] The attention module is connected to the CSP-S module;

[0027] The upsampling module and the downsampling module are used to construct the fusion paths of upsampling and downsampling, respectively.

[0028] The attention module is used to assign weights to the feature maps of the multiple scales output by the feature extraction module in order to obtain a mixed-domain feature map.

[0029] The CSP-S module is used to extract features from the hybrid domain feature map to obtain the feature map after feature fusion.

[0030] Preferably, the attention module includes: a channel attention module and a spatial attention module;

[0031] Both the channel attention module and the spatial attention module are used to simplify the feature map using a preset formula;

[0032] The preset formula is specifically as follows:

[0033]

[0034]

[0035] SAM(F)=Conv(Concat(AP(F),MP(F))),

[0036] Where F′ and F represent the input and output feature maps, respectively; Conv1D and Conv represent one-dimensional convolution and standard convolution, respectively; GAP and GMP represent global average pooling and global max pooling, respectively; and AP and MP represent average pooling and max pooling, respectively. and σ represents dot product and summation, respectively, and σ represents the sigmoid function.

[0037] Preferably, the CSP-S module includes: a DWConv module and a channel shuffling module;

[0038] The DWConv module is used to replace standard convolution to reduce computational cost;

[0039] The channel shuffling module is used to enhance information exchange between channels.

[0040] A multi-scale PCB board surface defect detection method includes the following steps:

[0041] Feature extraction is performed on the preprocessed PCB image to obtain feature maps at multiple scales;

[0042] Feature fusion is performed on feature maps at multiple scales to obtain a fused feature map.

[0043] Based on the feature map after feature fusion, the prediction result of PCB surface defects is obtained;

[0044] The predicted results of the PCB surface defects are filtered to obtain the actual detection results of the PCB surface defects.

[0045] The multi-scale PCB surface defect detection model provided by this invention includes a feature extraction module, a feature fusion module, a defect prediction module, and a filtering module. During operation, the feature extraction module extracts features from the preprocessed PCB image to obtain feature maps at multiple scales, which are then transmitted to the feature fusion module. The feature fusion module fuses these feature maps at multiple scales to obtain a fused feature map, which is then transmitted to the defect prediction module. Based on the acquired fused feature map, the defect prediction module obtains a prediction result for the PCB surface defects and transmits this prediction result to the filtering module. The filtering module filters the predicted result for the PCB surface defects, thereby obtaining the actual detection result for the PCB surface defects.

[0046] This invention extracts feature maps at multiple scales after preprocessing an initial PCB image, fuses these feature maps to obtain a fused feature map, and then obtains a prediction result based on the fused feature map. This prediction result is then filtered to obtain the actual detection result of PCB surface defects. Compared to existing technologies, this invention significantly reduces resource requirements through efficient feature extraction and fusion; simultaneously, by effectively filtering the prediction results, it improves the accuracy of defect detection.

[0047] This invention also provides a multi-scale PCB board surface defect detection method. Since it shares the same technical concept and solves the same technical problem as the system, this defect detection method should have the same beneficial effects, and will not be elaborated further here. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the structure of a multi-scale PCB board surface defect detection model provided in an embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of another multi-scale PCB board surface defect detection model provided in an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the feature extraction module provided in an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the feature fusion module provided in an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of the structure of the attention module provided in an embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of the CSP-S module provided in an embodiment of the present invention;

[0055] Figure 7 A flowchart of a multi-scale PCB board surface defect detection method provided in an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of the specific structure of LDD-Net provided in an embodiment of the present invention;

[0057] Figure 9 A schematic diagram of the specific structure of the MAN provided in the embodiments of the present invention;

[0058] Figure 10 This is a schematic diagram of the specific structure of the LD-Head provided in an embodiment of the present invention;

[0059] Figure 11 This is a schematic diagram of the specific structure of the Focus module provided in an embodiment of the present invention;

[0060] Figure 12 This is a schematic diagram of the specific structure of the CSPV2 module provided in an embodiment of the present invention;

[0061] Figure 13 This is a schematic diagram of the specific structure of the attention (EAM) module provided in an embodiment of the present invention;

[0062] Figure 14 This is a schematic diagram of the specific structure of the CSP-S module provided in an embodiment of the present invention. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] The embodiments of this invention are written in a progressive manner.

[0065] This invention provides a multi-scale PCB board surface defect detection model and method. It primarily addresses the technical problems of excessive resource requirements and insufficient accuracy in PCB board surface defect detection in existing technologies.

[0066] like Figure 1 As shown, a multi-scale PCB board surface defect detection model includes: a feature extraction module, a feature fusion module, a defect prediction module, and a filtering module.

[0067] The feature extraction module is used to extract features from the preprocessed PCB image to obtain feature maps at multiple scales.

[0068] The feature fusion module is used to fuse feature maps at multiple scales to obtain a feature map after feature fusion.

[0069] The defect prediction module is used to obtain the prediction result of PCB surface defects based on the feature map after feature fusion.

[0070] The filtering module is used to filter the predicted results of PCB surface defects in order to obtain the actual detection results of PCB surface defects.

[0071] In this embodiment, the multi-scale PCB surface defect detection model is specifically an accurate and lightweight PCB image defect detection network (LDD-Net). The structure of LDD-Net is as follows: Figure 8 As shown; wherein, the feature extraction module is specifically a lightweight feature extraction network (LFEN); the feature fusion module is specifically a multi-scale aggregation network (MAN). The structure of MAN is as follows: Figure 9As shown; the defect prediction module specifically uses a lightweight decoupled head (LD-Head) to detect three sets of shallow feature maps rich in information about small targets. The structure of the LD-Head is as follows. Figure 10 As shown; the filtering module is specifically non-maximum suppression (NMS).

[0072] It's important to note that Non-Maximum Suppression (NMS), as the name suggests, suppresses elements that are not local maxima; it can be understood as a local maximum search. This "local" refers to a neighborhood, which has two variable parameters: its dimension and its size.

[0073] like Figure 2 As shown, preferably, it further includes: a preprocessing module;

[0074] The preprocessing module is used to perform data enhancement and cropping on the original PCB image to obtain a preprocessed PCB image.

[0075] In practical applications, a preprocessing module is also set up. After acquiring the original PCB image, the original PCB image is enhanced and cropped using existing preprocessing methods, such as grayscale conversion and binarization, to obtain the preprocessed PCB module.

[0076] like Figure 3 As shown, preferably, the feature extraction module includes: a CSPV2 module, a channel submodule, and a Focus module;

[0077] The feature extraction module is used to perform a first-stage feature extraction on the preprocessed PCB model, then a second-stage feature extraction, and so on until the Nth-stage feature extraction is performed to obtain feature maps at N scales.

[0078] The CSPV2 module is used to extract fine-grained features of the feature map in the second stage to the Nth stage.

[0079] The channel submodule is used to determine whether the feature map size of any stage is less than a preset threshold in the first stage to the Nth stage. If so, the number of channels of the output feature map of the corresponding stage is reduced.

[0080] The Focus module is used to extract features through a preset slicing method.

[0081] In practical applications, large feature extraction networks, such as CSPDarkNet (cross-stage partial DarkNet) and ResNet (residual network), achieve high detection accuracy, but their parameter count is large. Furthermore, the stages of stacking convolutional layers in these models are located in stages 3 and 4, as shown in Table 1. The feature maps in stages 3 and 4 are relatively small, so stacking convolutional layers does not significantly increase the network complexity while still extracting useful feature information. This design approach is highly effective for datasets where large and medium-sized targets constitute the majority. However, for scenarios like PCB surface defect detection, which primarily involve small targets, this design leads to insufficient extraction of shallow features, resulting in the loss of fine-grained feature information.

[0082] Considering the above issues, LFEN was set up, and its network structure is shown in Table 1. Size represents the size of the convolution kernel, N is the number of times the module is repeated, S is the downsampling factor, and Input and Output represent the size of the feature maps input and output of the module, respectively.

[0083] LFEN includes the CSPV2 module, the channel submodule, and the Focus module;

[0084] The CSPV2 module is mainly used for feature extraction, which can preserve rich intermediate information; using the channel submodule can reduce the number of channels, thus reducing the network parameters, and has little impact on accuracy.

[0085] Replace the convolution with stride 2 using the Focus module to perform the downsampling operation;

[0086] It's important to note that CSPV stands for Cross-Stage Partial Network with Various Views (CSPV2), a variant of VoVNet (VoVNet consists of OSA modules, with three different configurations as shown in the table below. VoVNet begins with a stem block of three 3x3 convolutional layers, followed by four stages of OSA modules. Each stage ends with a 3x3 max pooling layer with a stride of 2 for downsampling, resulting in a final output stride of 32. Similar to other networks, the number of feature channels is increased after each downsampling. VoVNet-27-slim is a lightweight model, while VoVNet-39 / 57 contains more OSA modules in stages 4 and 5, making the model larger). CSPV2 not only addresses the model design issues mentioned earlier but also analyzes the gradient flow path within the model, enabling different layers to learn more diverse features. These methods are effective in both training and inference phases, especially in inference, improving both inference speed and accuracy.

[0087] Stage Module S N Size Input Output Stage 1 Conv 2 1 3×3 3×640×640 40×320×320 Focus 2 1 - 40×320×320 80×160×160 Stage 2 CSPV2 1 1 - 80×160×160 80×160×160 Focus 2 1 - 80×160×160 160×80×80 Stage 3 CSPV2 1 1 - 160×80×80 160×80×80 Focus 2 1 - 160×80×80 320×40×40 Stage 4 CSPV2 1 1 - 320×40×40 320×40×40 Focus 2 1 - 320×40×40 640×20×20 Stage 5 CSPV2 1 1 - 640×20×20 320×20×20

[0088] Table 1

[0089] Preferably, the preset slicing method is as follows:

[0090] The first feature map output by the CSPV2 module is sliced ​​into slices at intervals of one pixel to output a second feature map.

[0091] The second feature map is concatenated along the channel dimension;

[0092] Adjust the number of channels in the second feature map.

[0093] The structure of the CSPV2 module is as follows: Figure 12As shown, α and β represent the number of input and output channels of CSPV2, respectively. The CSPV2 module combines the advantages of cross-stage partial network (CSPNet) and VOVNet. In the main path, a 1×1 convolution is first used to reduce the number of channels to β / 2, followed by four 3×3 convolution operations. On the other path, a 1×1 convolution is also used to reduce the number of channels to β / 2. Then, the four sets of feature maps are concatenated along the channel dimension to retain more network gradient information. Furthermore, CSPV2 aggregates the feature maps generated by the four different convolutions, so the fused feature map contains multiple receptive fields and rich intermediate information, resulting in a feature map with 2×β channels. Finally, a 1×1 convolution is used to adjust the number of channels to β. The CSPV2 structure can reduce the size of the Focus module, the structure of which is shown below. Figure 11 As shown, H, W, and C represent the length, width, and number of channels of the feature map, respectively.

[0094] First, Focus slices the input feature map, dividing it into segments every single pixel. This downsampling process outputs four feature maps with their length and width halved. Next, these four feature maps are concatenated along the channel dimension. This quadruples the number of channels in the output feature map. Finally, a 1×1 convolution adjusts the number of channels to 2×C. The Focus module is equivalent to a 3×3 convolution with a stride of 2 and a 1×1 convolution. Therefore, Focus significantly reduces the number of parameters and improves detection speed. Furthermore, unlike the downsampling method of 3×3 convolution, Focus's slicing method preserves more fine-grained information about small targets.

[0095] like Figure 4 As shown, preferably, the feature fusion module includes: an attention module, a CSP-S module, an upsampling module, and a downsampling module;

[0096] Each of the upsampling modules and each of the downsampling modules is connected to each of the attention modules.

[0097] The attention module is connected to the CSP-S module;

[0098] The upsampling module and the downsampling module are used to construct the fusion paths of upsampling and downsampling, respectively.

[0099] The attention module is used to assign weights to the feature maps of the multiple scales output by the feature extraction module in order to obtain a mixed-domain feature map.

[0100] The CSP-S module is used to extract features from the hybrid domain feature map to obtain the feature map after feature fusion.

[0101] In practical applications, shallow feature maps in CNNs contain rich spatial information, while deep feature maps possess rich semantic information. During multiple downsampling processes, the size of the feature maps becomes increasingly smaller. Many small targets are less than a pixel in size in deep feature maps. Therefore, deep convolutional layers cannot effectively extract minute PCB surface defect features. Based on the Path Aggregation Network (PAN) structure, MAN was proposed. MAN improves upon PAN in the following three aspects.

[0102] First, MAN incorporates the shallow feature map (F2) output from stage 2 into the fusion path. F2 has a larger size, preserving richer information about small targets. Second, an attention (EAM) module is added after each upsampling module to suppress background interference and highlight PCB surface defects. Finally, the CSP-S module is used for further feature extraction. CSP-S significantly reduces the number of parameters compared to the CSP module. In the top-to-bottom fusion path, feature maps at four different scales are fully fused. In the bottom-to-top fusion path, the deep feature map (F5) output from stage 5 is not involved. Because F5 has sparse feature information about small defects, MAN uses the larger-scale P2 as input to the detection head.

[0103] It should be noted that the CSP-S module is specifically used for cross-stage partial and channelshuffle (CSP-S).

[0104] Among them, the Cross-Stage Partial Network (CSPNet) integrates gradient changes from start to finish into the feature map, reducing computation while maintaining accuracy. CSPNet is not just a network, but also a processing concept that can be combined with ResNet, ResNeXt, and DenseNet.

[0105] Conventional convolution performs convolution on all input feature maps, which can be described as full-channel convolution, a type of channel-dense connection. Group convolution, on the other hand, groups different feature maps of the input layer and then convolves each group with a different kernel. This reduces the computational cost of convolution but hinders information flow between channel groups. Therefore, compared to conventional convolution, group convolution is a type of channel-sparse connection. To overcome the side effects of group convolution, ShuffleNet v1 introduced a channel shuffle operation to "reorganize" the feature maps after group convolution. This ensures that the input for the next group convolution comes from different groups, allowing information to flow between different groups.

[0106] like Figure 5 As shown, preferably, the attention module includes: a channel attention module and a spatial attention module;

[0107] Both the channel attention module and the spatial attention module are used to simplify the feature map using a preset formula;

[0108] The preset formula is specifically as follows:

[0109]

[0110]

[0111] SAM(F)=Conv(Concat(AP(F),MP(F))),

[0112] Where F′ and F represent the input and output feature maps, respectively; Conv1D and Conv represent one-dimensional convolution and standard convolution, respectively; GAP and GMP represent global average pooling and global max pooling, respectively; and AP and MP represent average pooling and max pooling, respectively. and σ represents dot product and summation, respectively, and σ represents the sigmoid function.

[0113] Attention modules suppress useless information and highlight useful features by assigning weights to different parts of the feature map. The convolutional block attention module (CBAM) is a hybrid domain convolutional attention module. CBAM extracts global features channel by channel, generating channel attention feature maps. Then, using the channel attention feature maps as input for spatial attention, a hybrid domain feature map is generated. CBAM can effectively improve the convergence speed and detection accuracy of the model. However, the sequential information exchange between spatial and channel attention in CBAM ignores the different degrees of attention different convolutional layers give to channel and spatial features. Therefore, this paper proposes a hybrid domain attention module, EAM, that balances channel and spatial attention. Figure 13 As shown, EAM consists of a Channel Attention Module (CAM) and a Spatial Attention Module (SAM). CAM focuses on important channels in the feature map, while SAM focuses on key spatial locations in the feature map. CAM and SAM are connected in parallel to suppress invalid features and highlight defective features.

[0114] like Figure 6 As shown, preferably, the CSP-S module includes: a DWConv module and a channel shuffling module;

[0115] The DWConv module is used to replace standard convolution to reduce computational cost;

[0116] The channel shuffling module is used to enhance information exchange between channels.

[0117] CSP-S uses depthwise convolution (DWConv) and channel shuffling instead of standard convolution. For example... Figure 14 As shown in (b), CSP-S uses a skip connection structure for its bottleneck. In this bottleneck structure, the feature map output after a 3×3 DWConv and a 1×1 convolution is added to the input feature map. Although DWConv reduces computation by replacing standard convolution, it lacks inter-channel information exchange, leading to decreased detection accuracy. Therefore, CSP-S uses a channel shuffling module to enhance inter-channel information exchange. The structure of the CSP-S module is as follows: Figure 14 As shown in (a), where N represents the number of times bottleneck is repeated.

[0118] It should be noted that DWConv (depthwise convolution): DWConv, short for Depthwise Convolution, is an important computational mode in convolutional neural networks, and is often considered a highlight algorithm in MobileNet. When implementing depthwise separable convolution, MobileNet first performs independent convolution (depth convolution) on each channel, and then merges all channels into an output feature map through point convolution, thereby reducing the amount of computation and improving computational efficiency.

[0119] LD-Head separates object classification and location regression. This approach improves model convergence speed and detection accuracy, but also increases the complexity of the detection head. Therefore, LD-Head replaces standard convolutions with 3×3 DWConv to avoid a significant increase in computation. The Classification branch predicts the category of the object in the feature map, where Cls represents the number of object categories in the dataset. The Regression branch performs location regression of the predicted bounding box, where B represents the location information of the predicted bounding box (center coordinates and width and height of the predicted box). The IoU branch determines whether the predicted bounding box is an object or background, where Conf represents the confidence score.

[0120] like Figure 7 As shown, a multi-scale PCB board surface defect detection method includes the following steps:

[0121] S1. Perform feature extraction on the preprocessed PCB image to obtain feature maps at multiple scales;

[0122] S2. Perform feature fusion on feature maps of multiple scales to obtain a feature map after feature fusion;

[0123] S3. Based on the feature map after feature fusion, obtain the prediction result of PCB surface defects;

[0124] S4. Filter the predicted results of the PCB surface defects to obtain the actual detection results of the PCB surface defects.

[0125] In step S1, the PCB image is preprocessed by the preprocessing module. After preprocessing, the LFEN is used to extract features from the preprocessed PCB image to obtain feature maps at multiple scales.

[0126] In step S2, the feature maps extracted by LFEN are fused at multiple scales using MAN to obtain the feature maps after feature fusion.

[0127] In step S3, the LD-Head is used to detect three sets of shallow feature maps with rich information about small targets in order to improve the accuracy of defect detection.

[0128] In step S4, the predicted results of PCB surface defects are filtered by the non-maximum suppression method through the filtering module to obtain the actual detection results of PCB surface defects.

[0129] In the embodiments provided in this application, it should be understood that the disclosed methods and systems can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical, or other forms.

[0130] Furthermore, in the various embodiments of the present invention, each functional module can be fully integrated into a processor, or each module can be a separate device, or two or more modules can be integrated into a device; each functional module in the various embodiments of the present invention can be implemented in hardware or in the form of hardware plus software functional units.

[0131] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by program instructions and related hardware. The aforementioned program instructions can be stored in a computer-readable storage medium. When the program instructions are executed, they perform the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0132] It should be understood that the use of terms such as "system," "device," "unit," and / or "module" in this application is merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0133] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "a," and / or "the" are not specifically singular and may include the plural. Generally, the terms "comprising" and "including" only indicate the inclusion of expressly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. An element defined by the phrase "comprising an..." does not exclude the presence of other identical elements in the process, method, product, or apparatus that includes the element.

[0134] If a flowchart is used in this application, it is used to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0135] The foregoing has provided a detailed description of a multi-scale PCB board surface defect detection model and method provided by the present invention. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-scale PCB board surface defect detection system, characterized in that, include: The module includes a feature extraction module, a feature fusion module, a defect prediction module, and a filtering module. The feature extraction module is used to extract features from the preprocessed PCB image to obtain feature maps at multiple scales. The feature fusion module is used to fuse feature maps at multiple scales to obtain a feature map after feature fusion. The defect prediction module is used to obtain the prediction result of PCB surface defects based on the feature map after feature fusion. The filtering module is used to filter the predicted results of the PCB surface defects in order to obtain the actual detection results of the PCB surface defects. The feature extraction module includes: a CSPV2 module, a channel sub-module, and a Focus module; The feature extraction module is used to perform a first-stage feature extraction on the preprocessed PCB model, then a second-stage feature extraction, and so on until the Nth-stage feature extraction is performed to obtain feature maps at N scales. The CSPV2 module is used to extract fine-grained features of the feature map in the second stage to the Nth stage. The channel submodule is used to determine whether the feature map size of any stage is less than a preset threshold in the first stage to the Nth stage. If so, the number of channels of the output feature map of the corresponding stage is reduced. The Focus module is used to extract features through a preset slicing method; In the main path, the CSPV2 module first uses a 1×1 convolution to reduce the number of channels to β / 2, and then performs four 3×3 convolution operations. On the other path, it also uses a 1×1 convolution to reduce the number of channels to β / 2. The four sets of feature maps are concatenated along the channel dimension to retain more network gradient information. The feature maps generated by the four different convolutions are aggregated to obtain a feature map with 2×β channels. The number of channels is then adjusted to β using a 1×1 convolution.

2. The multi-scale PCB board surface defect detection system as described in claim 1, characterized in that, Also includes: Preprocessing module; The preprocessing module is used to perform data enhancement and cropping on the original PCB image to obtain a preprocessed PCB image.

3. The multi-scale PCB board surface defect detection system as described in claim 1, characterized in that, The preset slicing method is specifically as follows: The first feature map output by the CSPV2 module is sliced ​​into slices at intervals of one pixel to output a second feature map. The second feature map is concatenated along the channel dimension; Adjust the number of channels in the second feature map.

4. The multi-scale PCB board surface defect detection system as described in claim 1, characterized in that, The feature fusion module includes: an attention module, a CSP-S module, an upsampling module, and a downsampling module; Each of the upsampling modules and each of the downsampling modules is connected to each of the attention modules. The attention module is connected to the CSP-S module; The upsampling module and the downsampling module are used to construct the fusion paths of upsampling and downsampling, respectively. The attention module is used to assign weights to the feature maps of the multiple scales output by the feature extraction module in order to obtain a mixed-domain feature map. The CSP-S module is used to extract features from the hybrid domain feature map to obtain the feature map after feature fusion.

5. The multi-scale PCB board surface defect detection system as described in claim 4, characterized in that, The attention module includes: a channel attention module and a spatial attention module; Both the channel attention module and the spatial attention module are used to simplify the feature map using a preset formula; The preset formula is as follows: in, and These represent the input feature map and the output feature map, respectively. and These represent one-dimensional convolution and standard convolution, respectively. and These represent global equal pooling and global max pooling, respectively. and These represent equal pooling and max pooling, respectively. and These represent dot product and summation, respectively. This represents the sigmoid function.

6. The multi-scale PCB board surface defect detection system as described in claim 5, characterized in that, The CSP-S module includes: a DWConv module and a channel shuffling module; The DWConv module is used to replace standard convolution to reduce computational cost; The channel shuffling module is used to enhance information exchange between channels.

7. A multi-scale PCB board surface defect detection method, implemented based on the multi-scale PCB board surface defect detection system as described in any one of claims 1 to 6, characterized in that, Includes the following steps: Feature extraction is performed on the preprocessed PCB image to obtain feature maps at multiple scales; Feature fusion is performed on feature maps at multiple scales to obtain a fused feature map. Based on the feature map after feature fusion, the prediction result of PCB surface defects is obtained; The predicted results of the PCB surface defects are filtered to obtain the actual detection results of the PCB surface defects.

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