Drive Circuit, Driving Method, and Display Device

Abstract

The present invention provides a driving circuit, a driving method and a display device. The driving circuit includes a first node control circuit, a second node control circuit and an output circuit; the first node control circuit controls the connection between the first node and the first voltage terminal, and under the control of the first clock signal, controls the connection between the first node and the second voltage terminal; the second node control circuit controls the connection between the second node and the first voltage terminal under the control of the input signal, and controls the connection between the second node and the third voltage terminal under the control of the control signal; the output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node. The present invention can meet the requirements of pixel driving while simplifying the circuit.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a driving circuit, a driving method, and a display device. Background Art

[0002] In related technologies, the driving circuit is an 8T2C driving circuit, which uses a relatively large number of transistors and capacitors, making it unfavorable for realizing a narrow border and saving costs. The related technologies cannot meet the requirements of pixel driving while simplifying the driving circuit. Summary of the Invention

[0003] In one aspect, an embodiment of the present invention provides a driving circuit, including a first node control circuit, a second node control circuit, and an output circuit;

[0004] The first node control circuit is electrically connected to a first node, a first clock signal terminal, a first voltage terminal, and a second voltage terminal respectively, and is configured to control the connection between the first node and the first voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and control the connection between the first node and the second voltage terminal under the control of the first clock signal;

[0005] The second node control circuit is electrically connected to a second node, an input terminal, a first voltage terminal, a control terminal, and a third voltage terminal respectively, and is configured to control the connection between the second node and the first voltage terminal under the control of an input signal provided by the input terminal, and control the connection between the second node and the third voltage terminal under the control of a control signal provided by the control terminal;

[0006] The output circuit is electrically connected to the first node, the second node, and a driving output terminal respectively, and is configured to control the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node.

[0007] Optionally, the output circuit is further electrically connected to the second voltage terminal and a second clock signal terminal respectively, and is configured to control the connection between the driving output terminal and the second voltage terminal under the control of the potential of the first node, and control the connection between the driving output terminal and the second clock signal terminal under the control of the potential of the second node.

[0008] Optionally, the driving circuit according to at least one embodiment of the present invention further includes an energy storage circuit;

[0009] The energy storage circuit is electrically connected to the second node and the driving output terminal respectively, and is configured to store electrical energy.

[0010] Optionally, the control terminal is a first reset terminal; the first reset terminal is electrically connected to the adjacent lower n - level driving output terminals, where n is a positive integer.

[0011] Optionally, the control terminal is a second reset terminal;

[0012] The second reset terminal is configured to provide an effective voltage signal during at least two reset time periods included in the reset phase, so that the second node control circuit controls the connection between the second node and the third voltage terminal under the control of the second reset signal provided by the second reset terminal.

[0013] Optionally, the first node control circuit includes a first transistor and a second transistor;

[0014] The gate of the first transistor is electrically connected to the first clock signal terminal, the first pole of the first transistor is electrically connected to the first voltage terminal, and the second pole of the first transistor is electrically connected to the first node;

[0015] The gate of the second transistor is electrically connected to the first clock signal terminal, the first pole of the second transistor is electrically connected to the second voltage terminal, and the second pole of the second transistor is electrically connected to the first node;

[0016] The first transistor is a p-type transistor and the second transistor is an n-type transistor; or, the first transistor is an n-type transistor and the second transistor is a p-type transistor.

[0017] Optionally, the second node control circuit includes a third transistor and a fourth transistor;

[0018] The gate of the third transistor is electrically connected to the input terminal, the first pole of the third transistor is electrically connected to the first voltage terminal, and the second pole of the third transistor is electrically connected to the second node;

[0019] The gate of the fourth transistor is electrically connected to the first reset terminal, the first pole of the fourth transistor is electrically connected to the third voltage terminal, and the second pole of the fourth transistor is electrically connected to the second node.

[0020] Optionally, the second node control circuit includes a third transistor and a fourth transistor;

[0021] The gate of the third transistor is electrically connected to the input terminal, the first pole of the third transistor is electrically connected to the first voltage terminal, and the second pole of the third transistor is electrically connected to the second node;

[0022] The gate of the fourth transistor is electrically connected to the second reset terminal, the first pole of the fourth transistor is electrically connected to the third voltage terminal, and the second pole of the fourth transistor is electrically connected to the second node.

[0023] Optionally, the output circuit includes a fifth transistor and a sixth transistor;

[0024] The gate of the fifth transistor is electrically connected to the first node, the first pole of the fifth transistor is electrically connected to the second voltage terminal, and the second pole of the fifth transistor is electrically connected to the drive output terminal;

[0025] The gate of the sixth transistor is electrically connected to the second node, the first pole of the sixth transistor is electrically connected to the drive output terminal, and the second pole of the sixth transistor is electrically connected to the second clock signal terminal.

[0026] Optionally, the sixth transistor is a p-type transistor, and the voltage value of the third voltage signal provided by the third voltage terminal is greater than the voltage value of the second voltage signal provided by the second voltage terminal; or,

[0027] The sixth transistor is an n-type transistor, and the voltage value of the third voltage signal provided by the third voltage terminal is less than the voltage value of the second voltage signal provided by the second voltage terminal.

[0028] Optionally, the energy storage circuit includes a storage capacitor;

[0029] The first end of the storage capacitor is electrically connected to the second node, and the second voltage end of the storage capacitor is electrically connected to the drive output terminal.

[0030] Optionally, the drive circuit according to an embodiment of the present invention further includes a seventh transistor; the output circuit is electrically connected to the first node through the seventh transistor;

[0031] The gate of the seventh transistor is electrically connected to the fourth voltage terminal, the first pole of the seventh transistor is electrically connected to the first node, and the second pole of the seventh transistor is electrically connected to the output circuit.

[0032] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above driving circuit. The driving method includes:

[0033] The first node control circuit controls the connection between the first node and the first voltage terminal under the control of the first clock signal, and the first node control circuit controls the connection between the first node and the second voltage terminal under the control of the first clock signal;

[0034] The second node control circuit controls the connection between the second node and the first voltage terminal under the control of the input signal, and the second node control circuit controls the connection between the second node and the third voltage terminal under the control of the control signal;

[0035] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node.

[0036] Optionally, the step in which the output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node includes:

[0037] The output circuit controls the connection between the driving output terminal and the second voltage terminal under the control of the potential of the first node, and the output circuit controls the connection between the driving output terminal and the second clock signal terminal under the control of the potential of the second node.

[0038] In a third aspect, an embodiment of the present invention provides a display device, including the above-mentioned driving circuit.

[0039] The driving circuit described in the embodiment of the present invention adopts a minimalist structure, which can meet the requirements of pixel driving while simplifying the circuit. At the same time, the simplified circuit and its driving ability, as well as the process Margin, are equivalent to those of the existing mass-produced driving circuits, which is beneficial to realizing a narrow border and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural diagram of the driving circuit described in the embodiment of the present invention;

[0041] Figure 2 is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0042] Figure 3 is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0043] Figure 4 is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0044] Figure 5 is a structural diagram of the driving circuit described in at least one embodiment of the present invention;

[0045] Figure 6 is a circuit diagram of the driving circuit described in at least one embodiment of the present invention;

[0046] Figure 7 is Figure 6 the working timing diagram of at least one embodiment of the driving circuit shown;

[0047] Figure 8A is Figure 6 the schematic diagram of the working state of at least one embodiment of the driving circuit shown in the input stage;

[0048] Figure 8B is Figure 6Schematic diagram of the operating state of at least one embodiment of the driving circuit shown in the output stage;

[0049] Figure 8C is Figure 6 Schematic diagram of the operating state of at least one embodiment of the driving circuit shown in the reset stage;

[0050] Figure 8D is Figure 6 Schematic diagram of the operating state of at least one embodiment of the driving circuit shown in the set stage;

[0051] Figure 9 is the circuit diagram of at least one embodiment of the driving circuit according to the present invention;

[0052] Figure 10 is Figure 9 Timing diagram of the operation of at least one embodiment of the driving circuit shown;

[0053] Figure 11 is the circuit diagram of at least one embodiment of the driving circuit according to the present invention;

[0054] Figure 12 is the circuit diagram of at least one embodiment of the driving circuit according to the present invention. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0056] The transistors used in all embodiments of the present invention can be thin-film transistors or field-effect transistors or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two poles of the transistor other than the gate, one pole is called the first pole and the other pole is called the second pole.

[0057] During actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first pole can be the drain and the second pole can be the source; or, the first pole can be the source and the second pole can be the drain.

[0058] As Figure 1 shown, the driving circuit described in the embodiments of the present invention includes a first node control circuit 11, a second node control circuit 12, and an output circuit 13;

[0059] The first node control circuit 11 is electrically connected to the first node N1, the first clock signal terminal GCK, the first voltage terminal V1, and the second voltage terminal V2 respectively, and is configured to control the connection between the first node N1 and the first voltage terminal V1 under the control of the first clock signal provided by the first clock signal terminal GCK, and control the connection between the first node N1 and the second voltage terminal V2 under the control of the first clock signal;

[0060] The second node control circuit 12 is electrically connected to the second node N2, the input terminal GSTV, the first voltage terminal V1, the control terminal Ct, and the third voltage terminal V3 respectively, and is configured to control the connection between the second node N2 and the first voltage terminal V1 under the control of the input signal provided by the input terminal GSTV, and control the connection between the second node N2 and the third voltage terminal V3 under the control of the control signal provided by the control terminal Ct;

[0061] The output circuit 13 is electrically connected to the first node N1, the second node N2, and the drive output terminal GU respectively, and is configured to control the drive output terminal GU to output a drive signal under the control of the potential of the first node N1 and the potential of the second node N2.

[0062] In the related art, the drive circuit is an 8T2C drive circuit, and the number of transistors and capacitors used is relatively large. The drive circuit according to at least one embodiment of the present invention adopts a minimalist structure, can meet the requirements of pixel driving while simplifying the circuit, and at the same time, the simplified circuit and its driving ability, as well as the process Margin, are comparable to the existing mass-produced drive circuits.

[0063] In at least one embodiment of the present invention, the output circuit is further electrically connected to the second voltage terminal and the second clock signal terminal respectively, and is configured to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the first node, and control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the second node.

[0064] In specific implementation, the output circuit can control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the first node, and control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the second node.

[0065] As Figure 2 shown, in Figure 1Based on the embodiment of the driving circuit shown, the output circuit is further electrically connected to the second voltage terminal V2 and the second clock signal terminal GCB respectively, and is configured to control the connection between the driving output terminal GU and the second voltage terminal V2 under the control of the potential of the first node N1, and control the connection between the driving output terminal GU and the second clock signal terminal GCB under the control of the potential of the second node N2.

[0066] The driving circuit according to at least one embodiment of the present invention further includes an energy storage circuit;

[0067] The energy storage circuit is electrically connected to the second node and the driving output terminal respectively, and is used for storing electric energy.

[0068] In specific implementation, the driving circuit may further include an energy storage circuit;

[0069] The energy storage circuit is configured to control the potential of the second node according to the driving signal provided by the driving output terminal.

[0070] As Figure 3 shown, based on at least one embodiment of the driving circuit shown, the driving circuit according to at least one embodiment of the present invention further includes an energy storage circuit 31; Figure 2

[0071] The energy storage circuit 31 is electrically connected to the second node N2 and the driving output terminal GU respectively, and is used for storing electric energy.

[0072] In at least one embodiment of the present invention, the control terminal is a first reset terminal; the first reset terminal is electrically connected to the adjacent lower n-level driving output terminals, and n is a positive integer.

[0073] Optionally, n may be equal to 1, but not limited thereto. In actual operation, n may also be an integer greater than 1.

[0074] Figure 4 As Figure 4 shown, based on at least one embodiment of the driving circuit shown, the control terminal is a first reset terminal R1; Figure 3

[0075] The first reset terminal R1 is electrically connected to the adjacent lower-level driving output terminal.

[0076] In at least one embodiment of the present invention, the control terminal is a second reset terminal;

[0077] The second reset terminal is configured to provide an effective voltage signal during at least two reset time periods included in the reset stage, so that the second node control circuit controls the connection between the second node and the third voltage terminal under the control of the second reset signal provided by the second reset terminal.

[0078] In specific implementation, the control terminal can be the second reset terminal; the second node control circuit can include at least two reset time periods in the reset stage, and under the control of the second reset signal, control the connection between the second node and the third voltage terminal.

[0079] As Figure 5 shown, based on at least one embodiment of the driving circuit shown in Figure 3 the control terminal is the second reset terminal R2;

[0080] The second reset terminal R2 is used to provide an effective voltage signal in at least two reset time periods included in the reset stage, so that the second node control circuit 12 controls the connection between the second node N2 and the third voltage terminal V3 under the control of the second reset signal provided by the second reset terminal R2.

[0081] In specific implementation, when the transistor whose gate is electrically connected to the second reset terminal R2 included in the second node control circuit 12 is a p-type transistor, the effective voltage signal is a low voltage signal; when the transistor whose gate is electrically connected to the second reset terminal R2 included in the second node control circuit 12 is an n-type transistor, the effective voltage signal is a high voltage signal.

[0082] In at least one embodiment of the present invention, the second reset signal provided by the second reset terminal can be a high-frequency reset signal, so that the effect of resetting the potential of the second node is better.

[0083] Optionally, the first node control circuit includes a first transistor and a second transistor;

[0084] The gate of the first transistor is electrically connected to the first clock signal terminal, the first pole of the first transistor is electrically connected to the first voltage terminal, and the second pole of the first transistor is electrically connected to the first node;

[0085] The gate of the second transistor is electrically connected to the first clock signal terminal, the first pole of the second transistor is electrically connected to the second voltage terminal, and the second pole of the second transistor is electrically connected to the first node;

[0086] The first transistor is a p-type transistor and the second transistor is an n-type transistor; or, the first transistor is an n-type transistor and the second transistor is a p-type transistor.

[0087] Optionally, the second node control circuit includes a third transistor and a fourth transistor;

[0088] The gate of the third transistor is electrically connected to the input terminal, the first pole of the third transistor is electrically connected to the first voltage terminal, and the second pole of the third transistor is electrically connected to the second node;

[0089] The gate of the fourth transistor is electrically connected to the first reset terminal, the first pole of the fourth transistor is electrically connected to the third voltage terminal, and the second pole of the fourth transistor is electrically connected to the second node.

[0090] Optionally, the second node control circuit includes a third transistor and a fourth transistor;

[0091] The gate of the third transistor is electrically connected to the input terminal, the first pole of the third transistor is electrically connected to the first voltage terminal, and the second pole of the third transistor is electrically connected to the second node;

[0092] The gate of the fourth transistor is electrically connected to the second reset terminal, the first pole of the fourth transistor is electrically connected to the third voltage terminal, and the second pole of the fourth transistor is electrically connected to the second node.

[0093] Optionally, the output circuit includes a fifth transistor and a sixth transistor;

[0094] The gate of the fifth transistor is electrically connected to the first node, the first pole of the fifth transistor is electrically connected to the second voltage terminal, and the second pole of the fifth transistor is electrically connected to the drive output terminal;

[0095] The gate of the sixth transistor is electrically connected to the second node, the first pole of the sixth transistor is electrically connected to the drive output terminal, and the second pole of the sixth transistor is electrically connected to the second clock signal terminal.

[0096] In at least one embodiment of the present invention, the sixth transistor is a p-type transistor, and the voltage value of the third voltage signal provided by the third voltage terminal is greater than the voltage value of the second voltage signal provided by the second voltage terminal; or,

[0097] The sixth transistor is an n-type transistor, and the voltage value of the third voltage signal provided by the third voltage terminal is less than the voltage value of the second voltage signal provided by the second voltage terminal.

[0098] In specific implementation, when the sixth transistor is a p-type transistor, the voltage value of the third voltage signal can be set to be greater than the voltage value of the second voltage signal, so that when the fifth transistor is turned on, the sixth transistor can be turned off;

[0099] When the sixth transistor is an n-type transistor, the voltage value of the third voltage signal can be set to be less than the voltage value of the second voltage signal, so that when the fifth transistor is turned on, the sixth transistor can be turned off.

[0100] Optionally, the energy storage circuit includes a storage capacitor;

[0101] The first end of the storage capacitor is electrically connected to the second node, and the second voltage end of the storage capacitor is electrically connected to the drive output end.

[0102] The drive circuit according to at least one embodiment of the present invention further includes a seventh transistor; the output circuit is electrically connected to the first node through the seventh transistor;

[0103] The gate of the seventh transistor is electrically connected to the fourth voltage terminal, the first pole of the seventh transistor is electrically connected to the first node, and the second pole of the seventh transistor is electrically connected to the output circuit.

[0104] In specific implementation, a normally-open seventh transistor can be provided between the first node and the output circuit for protecting the first transistor and the second transistor.

[0105] Optionally, the seventh transistor can be a p-type transistor, and the gate of the seventh transistor can be electrically connected to the low voltage terminal, that is, the fourth voltage terminal can be the low voltage terminal, but not limited thereto. In actual operation, the seventh transistor can also be an n-type transistor.

[0106] As Figure 6 shown, on the basis of at least one embodiment of the drive circuit shown in Figure 4 shown, the first node control circuit includes a first transistor T1 and a second transistor T2;

[0107] The gate of the first transistor T1 is electrically connected to the first clock signal terminal GCK, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the first node N1;

[0108] The gate of the second transistor T2 is electrically connected to the first clock signal terminal GCK, the source of the second transistor T2 is electrically connected to the first high voltage terminal VGH, and the drain of the second transistor T2 is electrically connected to the first node N1;

[0109] The second node control circuit includes a third transistor T3 and a fourth transistor T4;

[0110] The gate of the third transistor T3 is electrically connected to the input terminal GSTV, the source of the third transistor T3 is electrically connected to the low voltage terminal VGL, and the drain of the third transistor T3 is electrically connected to the second node N2;

[0111] The gate of the fourth transistor T4 is electrically connected to the first reset terminal R1, the source of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH, and the drain of the fourth transistor T4 is electrically connected to the second node N2;

[0112] The output circuit includes a fifth transistor T5 and a sixth transistor T6;

[0113] The gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the first high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the drive output terminal GU;

[0114] The gate of the sixth transistor T6 is electrically connected to the second node N2, the source of the sixth transistor T6 is electrically connected to the drive output terminal GU, and the drain of the sixth transistor T6 is electrically connected to the second clock signal terminal GCB;

[0115] The energy storage circuit includes a storage capacitor C1;

[0116] The first end of C1 is electrically connected to the second node N2, and the second end of C1 is electrically connected to the drive output terminal GU.

[0117] In Figure 6 In at least one embodiment of the shown driving circuit, T1, T3, T4, T5, and T6 are all p-type transistors, and T2 is an n-type transistor.

[0118] The driving circuit according to at least one embodiment of the present invention is provided for an LTPO (Low Temperature Polycrystalline Oxide) framework, and a driving circuit for driving an Oxide (oxide) pixel circuit is provided to support LTPO driving.

[0119] In Figure 6 In at least one embodiment of the shown driving circuit, the first reset terminal R1 is electrically connected to the drive output terminal of the adjacent next-stage driving circuit.

[0120] As Figure 7 shown, the present invention Figure 6 When at least one embodiment of the shown driving circuit is working, the driving cycle may include an input stage S1, an output stage S2, a reset stage S3, and a set stage S4 set in sequence;

[0121] In the input stage S1, GSTV provides a low voltage signal, GCK provides a low voltage signal, and GCB provides a high voltage signal. AsFigure 8A As shown, T1 is turned on, T2 is turned off, the first node N1 is connected to the low-voltage terminal VGL, T5 is turned on, and GU is connected to VGH; T3 is turned on, the second node N2 is connected to VGL, T6 is turned on, and GU is connected to GCB; GU outputs a high-voltage signal; R1 provides a high-voltage signal, and T4 is turned off;

[0122] In the output stage S2, GSTV provides a high-voltage signal, GCK provides a high-voltage signal, and GCB provides a low-voltage signal, as Figure 8B shown, T1 is turned off, T2 is turned on, the first node N1 is connected to the first high-voltage terminal VGH, and T5 is turned off; T6 is turned on, GU is connected to GCB, GU outputs a low-voltage signal, and the potential of N2 is pulled down through C1; R1 provides a high-voltage signal, and T4 is turned off;

[0123] In the reset stage S3, GSTV provides a high-voltage signal, GCK provides a low-voltage signal, and GCB provides a high-voltage signal, as Figure 8C shown, T1 is turned on, T2 is turned off, the first node N1 is connected to the low-voltage terminal VGL, T5 is turned on, and GU outputs a high-voltage signal; R1 provides a low-voltage signal, T4 is turned on, the second node N2 is connected to VGH, and T6 is turned off;

[0124] In the set stage S4, GSTV provides a high-voltage signal, GCK provides a high-voltage signal, and GCB provides a low-voltage signal, as Figure 8D shown, T1 is turned off, T2 is conducting, the first node N1 is connected to VGH, T5 is turned off, T6 is turned off, and GU continuously outputs a high-voltage signal; T3 is turned off, R1 provides a high-voltage signal, and T4 is turned off.

[0125] By simulating at least one embodiment of the drive circuit shown in Figure 6 When the threshold voltage is negatively biased from -3V to 2V, the rise time and fall time of the drive signal output by the drive circuit meet the requirements.

[0126] Figure 9 The difference between at least one embodiment of the drive circuit shown in Figure 6 and at least one embodiment of the drive circuit shown in

[0127] The gate of T4 is electrically connected to the second reset terminal R2.

[0128] As Figure 10 shown, in at least one embodiment of the drive circuit of the present invention during operation, the drive cycle may include an input stage S1, an output stage S2, and a reset stage S3 that are set successively; Figure 9

[0129] ​In the input stage S1, GSTV provides a low-voltage signal, GCK provides a low-voltage signal, GCB provides a high-voltage signal, T1 is turned on, T2 is turned off, the first node N1 is connected to the low-voltage terminal VGL, T5 is turned on, and GU is connected to VGH; T3 is turned on, the second node N2 is connected to VGL, T6 is turned on, and GU is connected to GCB; GU outputs a high-voltage signal.

[0130] In the output stage S2, GSTV provides a high-voltage signal, GCK provides a high-voltage signal, GCB provides a low-voltage signal, T1 is turned off, T2 is turned on, the first node N1 is connected to the first high-voltage terminal VGH, and T5 is turned off; T6 is turned on, GU is connected to GCB, GU outputs a low-voltage signal, and the potential of N2 is pulled down through C1.

[0131] In the reset stage S3, GSTV provides a high-voltage signal. When GCK provides a low-voltage signal and GCB provides a high-voltage signal, T1 is turned on, T2 is turned off, the first node N1 is connected to the low-voltage terminal VGL, T5 is turned on, and GU outputs a high-voltage signal.

[0132] In the reset stage S3, the second reset signal provided by R2 is a high-frequency reset signal. When R2 provides a low-voltage signal, T4 is turned on, and the second node N2 is connected to VGH, and T6 is turned off.

[0133] In Figure 10 Among them, the label S31 is the first reset time period, the label S32 is the second reset time period, the label S33 is the third reset time period, and the label S34 is the fourth reset time period.

[0134] Figure 11 At least one embodiment of the driving circuit shown in Figure 9 differs from at least one embodiment of the driving circuit shown in

[0135] In Figure 11 At least one embodiment of the driving circuit shown, the voltage value of the second high-voltage signal provided by the second high-voltage terminal VGH2 is greater than the voltage value of the first high-voltage signal provided by the first high-voltage terminal VGH, so as to ensure that T6 can be turned off in the reset stage S3.

[0136] Figure 12 At least one embodiment of the driving circuit shown in Figure 9 differs from at least one embodiment of the driving circuit shown in

[0137] Figure 12 At least one embodiment of the driving circuit shown further includes a seventh transistor T7;

[0138] The gate of T7 is electrically connected to the low voltage terminal VGL, the source of T7 is electrically connected to the first node N1, and the drain of T7 is electrically connected to the gate of T5.

[0139] In Figure 12 In at least one embodiment of the driving circuit shown, T7 is a p-type transistor, and T7 is a normally open transistor for protecting T1 and T2.

[0140] The driving method described in the embodiments of the present invention is applied to the above driving circuit, and the driving method includes:

[0141] The first node control circuit controls the connection between the first node and the first voltage terminal under the control of the first clock signal, and the first node control circuit controls the connection between the first node and the second voltage terminal under the control of the first clock signal;

[0142] The second node control circuit controls the connection between the second node and the first voltage terminal under the control of the input signal, and the second node control circuit controls the connection between the second node and the third voltage terminal under the control of the control signal;

[0143] The output circuit controls the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node.

[0144] In at least one embodiment of the present invention, the step of the output circuit controlling the driving output terminal to output a driving signal under the control of the potential of the first node and the potential of the second node includes:

[0145] The output circuit controls the connection between the driving output terminal and the second voltage terminal under the control of the potential of the first node, and the output circuit controls the connection between the driving output terminal and the second clock signal terminal under the control of the potential of the second node.

[0146] The display device described in the embodiments of the present invention includes the above driving circuit.

[0147] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A drive circuit, characterized in that, It includes a first node control circuit, a second node control circuit and an output circuit; The first node control circuit is electrically connected to a first node, a first clock signal terminal, a first voltage terminal and a second voltage terminal respectively, and is used to control the connection between the first node and the first voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and control the connection between the first node and the second voltage terminal under the control of the first clock signal; The second node control circuit is electrically connected to a second node, an input terminal, a first voltage terminal, a control terminal and a third voltage terminal respectively, and is used to control the connection between the second node and the first voltage terminal under the control of an input signal provided by the input terminal, and control the connection between the second node and the third voltage terminal under the control of a control signal provided by the control terminal; The output circuit is electrically connected to the first node, the second node and a drive output terminal respectively, and is used to control the drive output terminal to output a drive signal under the control of the potential of the first node and the potential of the second node.

2. The drive circuit according to claim 1, wherein The output circuit is also electrically connected to the second voltage terminal and a second clock signal terminal respectively, and is used to control the connection between the drive output terminal and the second voltage terminal under the control of the potential of the first node, and control the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the second node.

3. The drive circuit according to claim 1, wherein It further includes an energy storage circuit; The energy storage circuit is electrically connected to the second node and the drive output terminal respectively, and is used to store electrical energy.

4. The drive circuit according to claim 1, wherein The control terminal is a first reset terminal; the first reset terminal is electrically connected to the adjacent lower n-level drive output terminals, where n is a positive integer.

5. The drive circuit according to claim 1, wherein The control terminal is a second reset terminal; The second reset terminal is used to provide an effective voltage signal during at least two reset time periods included in the reset stage, so that the second node control circuit controls the connection between the second node and the third voltage terminal under the control of a second reset signal provided by the second reset terminal.

6. The drive circuit according to claim 1, characterized in that, The first node control circuit includes a first transistor and a second transistor; The gate of the first transistor is electrically connected to the first clock signal terminal, the first pole of the first transistor is electrically connected to the first voltage terminal, and the second pole of the first transistor is electrically connected to the first node; The gate of the second transistor is electrically connected to the first clock signal terminal, the first pole of the second transistor is electrically connected to the second voltage terminal, and the second pole of the second transistor is electrically connected to the first node; The first transistor is a p-type transistor and the second transistor is an n-type transistor; or, the first transistor is an n-type transistor and the second transistor is a p-type transistor.

7. The drive circuit according to claim 4, wherein The second node control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the input terminal, the first pole of the third transistor is electrically connected to the first voltage terminal, and the second pole of the third transistor is electrically connected to the second node; The gate of the fourth transistor is electrically connected to the first reset terminal, a first pole of the fourth transistor is electrically connected to the third voltage terminal, and a second pole of the fourth transistor is electrically connected to the second node.

8. The drive circuit according to claim 5, wherein The second node control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the input terminal, a first pole of the third transistor is electrically connected to the first voltage terminal, and a second pole of the third transistor is electrically connected to the second node; The gate of the fourth transistor is electrically connected to the second reset terminal, a first pole of the fourth transistor is electrically connected to the third voltage terminal, and a second pole of the fourth transistor is electrically connected to the second node.

9. The drive circuit according to claim 2, wherein The output circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is electrically connected to the first node, a first pole of the fifth transistor is electrically connected to the second voltage terminal, and a second pole of the fifth transistor is electrically connected to the drive output terminal; The gate of the sixth transistor is electrically connected to the second node, a first pole of the sixth transistor is electrically connected to the drive output terminal, and a second pole of the sixth transistor is electrically connected to the second clock signal terminal.

10. The drive circuit according to claim 9, characterized in that, The sixth transistor is a p-type transistor, and the voltage value of the third voltage signal provided by the third voltage terminal is greater than the voltage value of the second voltage signal provided by the second voltage terminal; or, The sixth transistor is an n-type transistor, and the voltage value of the third voltage signal provided by the third voltage terminal is less than the voltage value of the second voltage signal provided by the second voltage terminal.

11. The drive circuit according to claim 3, characterized in that, The energy storage circuit includes a storage capacitor; A first end of the storage capacitor is electrically connected to the second node, and a second voltage end of the storage capacitor is electrically connected to the drive output terminal.

12. The drive circuit according to any one of claims 1 to 11, characterized in that, It further includes a seventh transistor; the output circuit is electrically connected to the first node through the seventh transistor; The gate of the seventh transistor is electrically connected to the fourth voltage terminal, a first pole of the seventh transistor is electrically connected to the first node, and a second pole of the seventh transistor is electrically connected to the output circuit.

13. A driving method, applied to the driving circuit according to any one of claims 1 to 12, characterized in that, The driving method includes: The first node control circuit controls the connection between the first node and the first voltage terminal under the control of the first clock signal, and the first node control circuit controls the connection between the first node and the second voltage terminal under the control of the first clock signal; The second node control circuit controls the connection between the second node and the first voltage terminal under the control of the input signal, and the second node control circuit controls the connection between the second node and the third voltage terminal under the control of the control signal; The output circuit controls the drive output terminal to output a drive signal under the control of the potential of the first node and the potential of the second node.

14. The driving method according to claim 13, characterized in that, The step that the output circuit controls the drive output terminal to output a drive signal under the control of the potential of the first node and the potential of the second node includes: The output circuit controls the connection between the drive output terminal and the second voltage terminal under the control of the potential of the first node, and the output circuit controls the connection between the drive output terminal and the second clock signal terminal under the control of the potential of the second node.

15. A display device, characterized in that, Comprising a drive circuit as described in any one of claims 1 to 10.

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