Display panel and display device

Abstract

The application discloses a display panel and a display device. In the display panel, a compensation module of a pixel circuit is kept on in a bias adjustment stage and a data writing stage, and a time period between the bias adjustment stage and the data writing stage; and / or, a reset module of the pixel circuit is kept on in the bias adjustment stage and a reset stage, and the reset module is turned off at least after the compensation module is turned on. The display panel and the display device provided by the application have the compensation module turned on only once in one picture refreshing frame, so that the jump frequency of a scanning signal for controlling the compensation transistor to be turned on and turned off can be reduced, the driving process is simplified, the processing capacity requirement of a driving circuit for providing the scanning signal is reduced, and the process complexity and the process manufacturing cost of the driving circuit are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] The display panel of self-luminous generally has a light emitting element, so that it does not need to set a backlight module for providing a light source, and the self-luminous display panel has the characteristics of thin and simple structure, and becomes the research focus in the current display field.

[0003] The pixel circuit is a very key component in the display panel, which plays an important role in providing driving current for the light emitting element of the display panel. The driving process of the existing pixel circuit is relatively complex, and the driving circuit for driving the pixel circuit needs to have higher processing capability, so that the process complexity and process manufacturing cost of the driving circuit in the display panel are higher. SUMMARY

[0004] The present application provides a display panel and a display device to simplify the driving process and reduce the process complexity and process manufacturing cost of the driving circuit in the display panel.

[0005] According to an aspect of the present application, a display panel is provided, comprising:

[0006] a pixel circuit and a light emitting element;

[0007] The pixel circuit comprises a driving module, a compensation module, a reset module, a data writing module and a bias adjustment module;

[0008] The driving module comprises a driving transistor, the driving transistor comprises a gate, a first electrode and a second electrode, and the compensation module is connected between the gate and the second electrode of the driving transistor;

[0009] The working process of the display panel comprises a reset stage, a data writing stage and a bias adjustment stage;

[0010] In the reset stage, the reset module provides a reset signal for the driving transistor;

[0011] In the data writing stage, the data writing module provides a data signal for the driving transistor;

[0012] In the bias adjustment stage, the bias adjustment module is turned on, and the bias adjustment module provides a bias adjustment signal for the driving transistor; wherein,

[0013] In the bias adjustment stage and the data writing stage, and the time period between the bias adjustment stage and the data writing stage, the compensation module remains turned on; and / or,

[0014] In the bias adjustment stage and the reset stage, the reset module keeps on, and the reset module is turned off at least after the compensation module is turned on.

[0015] According to another aspect of the present application, a display device is provided, comprising the display panel of the first aspect.

[0016] The display panel and the display device provided by the embodiments of the present application keep the compensation module on in the bias adjustment stage and the data writing stage, and in the time period between the bias adjustment stage and the data writing stage; and / or keep the reset module on in the bias adjustment stage and the reset stage, and turn off the reset module at least after the compensation module is turned on, so that the compensation module in the pixel circuit is turned on only once in one frame of picture refreshing, and correspondingly, the scanning signal for controlling the compensation module to turn on and turn off only needs to provide one effective pulse in one frame of picture refreshing, thereby reducing the frequency of the scanning signal, simplifying the driving process, reducing the requirement for the processing capability of the driving circuit for providing the scanning signal, and further reducing the process complexity and the process manufacturing cost of the driving circuit.

[0017] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0019] Figure 1 A structural schematic diagram of a display panel provided by the embodiments of the present application is shown in the figure;

[0020] Figure 2 A structural schematic diagram of a display panel provided by the embodiments of the present application is shown in the figure; Figure 1 A sectional structural schematic diagram along the A-A' direction is shown in the figure;

[0021] Figure 3 A structural schematic diagram of a pixel circuit provided by the embodiments of the present application is shown in the figure;

[0022] Figure 4 A structural schematic diagram of another pixel circuit provided by the embodiments of the present application is shown in the figure;

[0023] Figure 5 A structural schematic diagram of another pixel circuit provided by the embodiments of the present application is shown in the figure;

[0024] Figure 6 A structure diagram of another pixel circuit provided by an embodiment of the present application is shown in FIG. 6;

[0025] Figure 7 A driving timing diagram of a pixel circuit provided by an embodiment of the present application is shown in FIG. 7;

[0026] Figure 8 A driving timing diagram of another pixel circuit provided by an embodiment of the present application is shown in FIG. 8;

[0027] Figure 9 A driving timing diagram of a pixel circuit in the related art is shown in FIG. 9;

[0028] Figure 10 A driving timing diagram of another pixel circuit in the related art is shown in FIG. 10;

[0029] Figure 11 A driving timing diagram of yet another pixel circuit provided by an embodiment of the present application is shown in FIG. 11;

[0030] Figure 12 A driving timing diagram of yet another pixel circuit provided by an embodiment of the present application is shown in FIG. 12;

[0031] Figure 13 A driving timing diagram of yet another pixel circuit provided by an embodiment of the present application is shown in FIG. 13;

[0032] Figure 14 A structure diagram of a display device provided by an embodiment of the present application is shown in FIG. 14. DETAILED DESCRIPTION

[0033] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the personnel in the art without creative labor should belong to the protection scope of the present application.

[0034] It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application and above-described accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular sequential or chronological order. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the present application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprise" and "have", and any variations thereof, are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus that comprises a list of steps or units is not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, products, or apparatuses.

[0035] Figure 1 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 2 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 1 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 3 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 4 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 5 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 6 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 7 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figure 8 A structural schematic diagram of a display panel provided by an embodiment of the present application, Figures 1-8 As shown in the accompanying drawings, the display panel provided by the embodiment of the present application comprises a pixel circuit 10 and a light emitting element 11, the pixel circuit 10 comprises a driving module 101, a compensation module 102, a reset module 103, a data writing module 104, and a bias adjustment module 105. The driving module 101 comprises a driving transistor T2, the driving transistor T2 comprises a gate, a first electrode, and a second electrode, and the compensation module 102 is connected between the gate and the second electrode of the driving transistor T2.

[0036] The working process of the display panel comprises a reset stage t10, a data writing stage t20, and a bias adjustment stage t30. In the reset stage t10, the reset module 103 provides a reset signal Vref for the driving transistor T2. In the data writing stage t20, the data writing module 104 provides a data signal Vdata for the driving transistor T2. In the bias adjustment stage t30, the bias adjustment module 105 is turned on, and the bias adjustment module 105 provides a bias adjustment signal V0 for the driving transistor T2.

[0037] In the bias adjustment stage t30 and the data write stage t20, and the time period t40 between the bias adjustment stage t30 and the data write stage t20, the compensation module 102 is kept on; and / or, in the bias adjustment stage t30 and the reset stage t10, the reset module 103 is kept on, and the reset module 103 is turned off at least after the compensation module 102 is turned on.

[0038] Specifically, as shown in Figure 1 and Figure 2 , the display panel can include a plurality of pixel circuits 10 arranged in an array and a plurality of light emitting elements 11 arranged in an array, and the arrangement of the plurality of pixel circuits 10 and the plurality of light emitting elements 11 can be set according to actual needs.

[0039] Among them, as shown in Figure 2 , when the light emitting element 11 is an organic light emitting diode (OLED), the light emitting element 11 can include an anode 111, a light emitting layer 112 and a cathode 113 arranged in a stack, but is not limited thereto. In other embodiments, the light emitting element 11 can also include a micro light emitting diode (such as Micro-LED, Mini-LED) or other types of light emitting devices.

[0040] Continuing to refer to Figure 1 and Figure 2 , the plurality of pixel circuits 10 and the plurality of light emitting elements 11 are correspondingly electrically connected, and the pixel circuit 10 is used to provide a driving current for the light emitting element 11 electrically connected thereto to realize driving the light emitting element 11 to emit light. For example, taking the light emitting element 11 as an organic light emitting diode, when the pixel circuit 10 provides a driving current for the light emitting element 11, electrons are injected into the light emitting layer 112 through the cathode 113, and holes are injected into the light emitting layer 112 through the anode 111, and the electrons and holes recombine in the light emitting layer 112 to release energy and emit light.

[0041] Continuing to refer to Figures 3-6 , the pixel circuit 10 can specifically include a driving module 101, a compensation module 102, a reset module 103, a data write module 104 and a bias adjustment module 105.

[0042] The driving module 101 can be a driving transistor T2 configured to provide a driving current for the light emitting element 11. Specifically, the driving transistor T2 includes a gate (i.e., the N1 node), a first electrode (i.e., the N2 node), and a second electrode (i.e., the N3 node). The driving transistor T2 can be turned on according to a potential of the gate (i.e., the N1 node) of the driving transistor T2. The driving current formed by the turning on of the driving transistor T2 is configured to drive the light emitting element 11 to emit light. The driving transistor T2 is configured as a driving transistor. The potential of the gate of the driving transistor T2 determines the size of the driving current of the driving transistor T2. Thus, the brightness of the light emitting element 11 can be adjusted by controlling the gate voltage of the driving transistor T2 to achieve gray scale control.

[0043] The reset module 103 can be connected to the gate (i.e., the N1 node) of the driving transistor T2 and configured to provide a reset signal Vref for the gate of the driving transistor T2. The data writing module 104 can be connected to the first electrode (i.e., the N2 node) of the driving transistor T2 and configured to provide a data signal Vdata for the driving transistor T2. The compensation module 102 can be connected between the gate (i.e., the N1 node) and the second electrode (i.e., the N3 node) of the driving transistor T2 and configured to compensate for the threshold voltage of the driving transistor T2. The bias adjustment module 105 can be connected to the first electrode (i.e., the N2 node) or the second electrode (i.e., the N3 node) of the driving transistor T2 and configured to provide a bias adjustment signal V0 for the driving transistor T2.

[0044] In addition, with reference to Figures 3-6 the pixel circuit 10 can further include an initialization module 106 and a light emitting control module 107. The initialization module 106 can be connected to the anode of the light emitting element 11 and configured to provide an initialization signal Vini for the light emitting element 11.

[0045] The light emitting control module 107, the driving transistor T2, and the light emitting element 11 are connected in series between a first power signal terminal and a second power signal terminal and configured to selectively allow the light emitting element 11 to enter a light emitting stage. The first power signal terminal can be configured to provide a first power signal PVDD. The second power signal terminal can be configured to provide a second power signal PVEE. The voltage of the first power signal PVDD is greater than the voltage of the second power signal PVEE.

[0046] With reference to Figures 3-6Optionally, the light-emitting control module 107 includes a first light-emitting control module 1071 and a second light-emitting control module 1072. The first light-emitting control module 1071 is connected between the first power signal terminal and one terminal of the driving transistor T2, and can be used to control the conduction or disconnection between the driving transistor T2 and the first power signal terminal. The second light-emitting control module 1072 is connected between the other terminal of the driving transistor T2 and the light-emitting element 11, and can be used to control the conduction or disconnection between the driving transistor T2 and the second power signal terminal.

[0047] Continue to refer to Figures 3-6 In this embodiment, the control terminal of the data writing module 104 receives a first scan signal SP, which controls the opening and closing of the data writing module 104; the control terminal of the compensation module 102 receives a second scan signal S2N, which controls the opening and closing of the compensation module 102; the control terminal of the bias adjustment module 105 receives a bias adjustment control signal SP*, which controls the opening and closing of the bias adjustment module 105; the control terminal of the reset module 103 receives a third scan signal S1N, which controls the opening and closing of the reset module 103; the control terminal of the initialization module 106 receives a fourth scan signal S3N, which controls the opening and closing of the initialization module 106; and the control terminal of the light emission control module 107 receives a light emission control signal EM, which controls the opening and closing of the light emission control module 107.

[0048] Additionally, optional, such as Figures 3-6 As shown, the data writing module 104 includes a data writing transistor T1, and a first scan signal SP controls the turning on and off of the data writing transistor T1; the compensation module 102 includes a compensation transistor T3, and a second scan signal S2N controls the turning on and off of the compensation transistor T3; the bias adjustment module 105 includes a bias adjustment transistor T4, and a bias adjustment control signal SP* controls the turning on and off of the bias adjustment transistor T4; the reset module 103 includes a reset transistor T5, and a third scan signal S1N controls the turning on and off of the reset transistor T5; the initialization module 106 includes an initialization transistor T6, and a fourth scan signal S3N controls the turning on and off of the initialization transistor T6; the first light emission control module 1071 includes a first light emission control transistor T7, and the second light emission control module 1072 includes a second light emission control transistor T8, and a light emission control signal EM controls the turning on and off of the first light emission control transistor T7 and the second light emission control transistor T8.

[0049] It should be noted that at least two of the first scan signal SP, the second scan signal S2N, the third scan signal S1N, the fourth scan signal S3N, the bias adjustment control signal SP*, the light-emitting control signal EM and the like can be the same signal, provided that the conditions are met. For example, when the bias adjustment transistor T4 and the initialization transistor T6 are the same type of transistor, the bias adjustment control signal SP* and the fourth scan signal S3N can be the same signal.

[0050] In addition, as shown in Figure 3 and Figure 4 When the driving transistor T2 is a PMOS type transistor, the pixel circuit 10 can further include a storage capacitor C1, the first electrode of the storage capacitor C1 being connected to the first power signal end, and the second electrode being connected to the gate of the driving transistor T2, for storing the signal transmitted to the gate of the driving transistor T2. As shown in Figure 3 , the bias adjustment module 105 is connected to the first electrode of the driving transistor T2, i.e. the N2 node, as shown in Figure 4 , the bias adjustment module 105 is connected to the second electrode of the driving transistor T2, i.e. the N3 node.

[0051] Continuing to refer to Figure 5 and Figure 6 When the driving transistor T2 is an NMOS type transistor, the pixel circuit 10 can further include a storage capacitor C1, the first electrode of the storage capacitor C1 being connected to the light-emitting element 11, and the second electrode being connected to the gate of the driving transistor T2, for storing the signal transmitted to the gate of the driving transistor T2. As shown in Figure 5 , the bias adjustment module 105 is connected to the first electrode of the driving transistor T2, i.e. the N2 node, as shown in Figure 6 , the bias adjustment module 105 is connected to the second electrode of the driving transistor T2, i.e. the N3 node.

[0052] Continuing to refer to Figure 7 and Figure 8 The working process of the display panel at least includes a reset stage t10, a data writing stage t20 and a bias adjustment stage t30.

[0053] As shown in Figures 3-8 , for example, the reset module 103 is an NMOS type reset transistor T5, the data writing stage t20 is a PMOS type data writing transistor T1, and the compensation module 102 is an NMOS type compensation transistor T3.

[0054] During the reset phase t10, the third scan signal S1N is a high-level effective pulse, which turns on the reset transistor T5. The reset signal Vref is transmitted to the gate of the driving transistor T2 (i.e., node N1) through the turned-on reset transistor T5, thereby resetting the gate of the driving transistor T2. At this time, the potential of the gate of the driving transistor T2 (i.e., node N1) is consistent with the reset signal Vref to avoid the data signal of the previous frame carried on the gate of the driving transistor T2 from affecting the writing of the data signal of the next frame.

[0055] During the data writing phase t20, the first scan signal SP is a low-level valid pulse, and the second scan signal S2N is a high-level valid pulse, causing the data writing transistor T1 and the compensation transistor T3 to conduct. Simultaneously, the gate potential of the driving transistor T2 is aligned with the reset signal Vref, and driving transistor T2 also conducts. The data signal Vdata passes through the data writing transistor T1, driving transistor T2, and compensation transistor T3, and is applied to the gate of driving transistor T2 (i.e., node N1). The potential of node N1 gradually increases until driving transistor T2 is turned off. When driving transistor T2 is turned off, its gate potential is V0. data -|V th |, where V data Let |V_data be the voltage value of the data signal V_data. th | represents the threshold voltage for driving transistor T2.

[0056] Furthermore, after the data writing phase t20 ends, the display panel can enter the light-emitting phase, for example, such as... Figure 3 and Figure 4 As shown, taking the first light-emitting control module 1071 as a PMOS type first light-emitting control transistor T7 and the second light-emitting control module 1072 as a PMOS type second light-emitting control transistor T8 as an example, during the light-emitting stage, the light-emitting control signal EM will jump to a low-level effective pulse, and the first light-emitting control transistor T7 and the second light-emitting control transistor T8 will be turned on. Due to the conduction of the first light-emitting control transistor T7, the first power supply signal PVDD will be transmitted to the first terminal of the driving transistor T2. Therefore, the voltage difference between the first terminal and the gate of the driving transistor T2 is V. PVDD -(V data -|V th |), so that the driving current generated by the driving transistor T2 is K*(V data -V PVDD ) 2 K is a coefficient related to the size and material of the driving transistor T2. Thus, the driving current generated by the driving transistor T2 is related to its own threshold voltage |V thIrrespective of this, the drive current is transmitted to the anode of the light emitting element 11 through the turned-on second light emitting control transistor T8, so that the light emitting element 11 emits light.

[0057] As described above, the voltage value V data The size of the drive current generated by the drive transistor T2 determines the final gray scale presented by the display panel, and thus the voltage value V data The voltage value V

[0058] Since the data signal Vdata written to the gate of the drive transistor T2 varies with the gray scale, the potential difference between the gate and the first electrode or the second electrode of the drive transistor T2 during the light emitting process can cause a bias problem, i.e., when the drive transistor T2 is a PMOS transistor, the bias problem occurs when the drive transistor T2 is turned on but the voltage of the gate is greater than the voltage of the first electrode or the second electrode; i.e., when the drive transistor T2 is an NMOS transistor, the bias problem occurs when the drive transistor T2 is turned on but the voltage of the gate is less than the voltage of the first electrode or the second electrode. The bias problem often causes a reverse electric field to be generated inside the drive transistor T2, resulting in carrier polarization, which causes the threshold voltage of the drive transistor T2 to shift, and the threshold voltage shift of the drive transistor T2 affects the writing of the data signal, causing the drive current generated by the drive transistor T2 to be unstable, especially when the gray scale changes, which can cause flickering.

[0059] Based on the above technical problem, in the embodiment, the working process of the display panel further includes a bias adjustment phase t30, as shown in Figure 3 、 Figure 4 、 Figure 7 and Figure 8 For example, the bias adjustment module 105 is a PMOS bias adjustment transistor T4, in the bias adjustment phase t30, the bias adjustment control signal SP* is a low-level effective pulse, so that the bias adjustment transistor T4 is turned on, and the bias adjustment signal V0 is input to the first electrode or the second electrode of the drive transistor T2 to adjust the voltage difference between the gate and the first electrode or the second electrode of the drive transistor T2, thereby eliminating the reverse electric field generated inside the drive transistor T2, solving the bias problem, avoiding the threshold voltage of the drive transistor T2 from shifting, and thus facilitating the reduction of the flickering phenomenon.

[0060] For example, when the driving transistor T2 is a PMOS transistor, in the bias adjustment stage t30, the potential of the first electrode or the second electrode of the driving transistor T2 can be pulled up by the bias adjustment signal V0 to increase the voltage difference between the first electrode or the second electrode and the gate of the driving transistor T2, to offset the reverse electric field generated inside the driving transistor T2, to solve the bias problem, but the application is not limited thereto.

[0061] With reference to the foregoing Figure 3 , Figure 4 , Figure 7 and Figure 8 , in the bias adjustment stage t30, the second scanning signal S2N is a high-level effective pulse, so that the compensation transistor T3 is turned on, and at this time, the bias adjustment signal V0 can be transmitted to the gate of the driving transistor T2 through the compensation transistor T3, so that the potential of the gate of the driving transistor T2 is consistent with the potential of the first electrode and / or the second electrode, which can further improve the threshold voltage shift of the driving transistor T2, and thus weaken the flicker phenomenon.

[0062] In addition, when the fourth scanning signal S3N controls the initialization transistor T6 to be turned on, the initialization signal Vini can be transmitted to the anode of the light emitting element 11 to initialize the anode of the light emitting element 11, so as to prevent the driving current provided to the anode of the light emitting element 11 in the previous frame from affecting the display luminance of the light emitting element 11 in the next frame.

[0063] In an optional embodiment, the channel type of the initialization transistor T6 can be the same as the channel type of the bias adjustment transistor T4, so that the bias adjustment control signal SP* and the fourth scanning signal S3N can be set as the same signal, so that the initialization transistor T6 and the bias adjustment transistor T4 can be turned on or turned off at the same time.

[0064] It can be understood that the above only exemplarily describes the types of the transistors in the pixel circuit 10 and the corresponding driving process. In the embodiment of the application, when the types of the transistors in the pixel circuit 10 change, the driving process similar to the above can also be achieved by changing the signals received by the gates of the transistors, which will not be described herein again.

[0065] Figure 9 For a driving timing diagram of a pixel circuit in the related art, as shown in Figure 9As shown, in the bias adjustment stage t30, the second scanning signal S2N is a valid pulse, the compensation transistor T3 is turned on once, and a bias adjustment signal V0 is provided for the gate of the driving transistor T2; in the data writing stage t20, the second scanning signal S2N is a valid pulse, the compensation transistor T3 is turned on again, and a data signal Vdata is provided for the gate of the driving transistor T2. It can be seen that in one frame refresh, the compensation transistor T3 needs to be turned on twice, and the second scanning signal S2N needs to provide two valid pulses in one frame refresh, and the driving process is relatively complex. Meanwhile, the driving circuit for providing the second scanning signal S2N needs to output a valid pulse at a higher transition frequency, which puts higher requirements on the processing capacity of the driving circuit, and thus increases the process complexity and manufacturing cost of the driving circuit.

[0066] Based on the above technical problems, with continuous reference to Figure 3 and Figure 7 In the embodiment of the present application, in the bias adjustment stage t30 and the data writing stage t20, and the time period t40 between the bias adjustment stage t30 and the data writing stage t20, the compensation module 102 remains turned on. At this time, after the compensation module 102 is turned on for the first time in the bias adjustment stage t30, it remains turned on until after the data writing stage t20 of the current frame refresh, and then the compensation module 102 is turned off. The compensation module 102 only needs to be turned on once in one frame refresh, and correspondingly, the second scanning signal S2N only needs to provide one valid pulse in one frame refresh. Compared with the related art, in the time period t40 between the bias adjustment stage t30 and the data writing stage t20, the second scanning signal S2N maintains a valid pulse and does not transition, so that the transition frequency of the second scanning signal S2N can be reduced, the driving process can be simplified, the requirement on the processing capacity of the driving circuit for providing the second scanning signal S2N can be reduced, and the process complexity and manufacturing cost of the driving circuit can be reduced.

[0067] With continuous reference to Figure 3 and Figure 8 In another optional embodiment, in the bias adjustment stage t30 and the reset stage t10, the third scanning signal S1 is a valid pulse, the reset module 103 remains turned on, and the reset signal Vref can be written to the gate of the driving transistor T2 (i.e., the N1 node) to reset the driving transistor T2, clear the data signal written to the gate of the driving transistor T2 in the previous frame, and enable the driving transistor T2 to be in a conductive state.

[0068] In the bias adjustment stage t30, the reset module 103 keeps on, the reset signal Vref can adjust the gate potential of the driving transistor T2, at the same time, the bias adjustment control signal SP* is an effective pulse, the bias adjustment module 105 is turned on, the bias adjustment signal V0 is input to the first electrode or the second electrode of the driving transistor T2, so as to adjust the potential of the first electrode or the second electrode of the driving transistor T2, thereby adjusting the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2 through the reset signal Vref and the bias adjustment signal V0 at the same time. In this way, the adjustment range of the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2 can be increased, which is more helpful to eliminate the reverse electric field generated in the driving transistor T2, solve the bias problem, avoid the threshold voltage of the driving transistor T2 from shifting, and weaken the flicker phenomenon.

[0069] As shown in Figure 3 and Figure 8 For example, taking the driving transistor T2 as a PMOS transistor, in the bias adjustment stage t30, the third scan signal S1 is an effective pulse, the reset module 103 keeps on, the reset signal Vref is written to the gate of the driving transistor T2, and the data signal written to the gate of the driving transistor T2 in the last frame is cleared. At the same time, in order to ensure that the driving transistor T2 is in the on state, the reset signal Vref will pull down the gate potential of the driving transistor T2, so that the gate potential of the driving transistor T2 is a lower potential. At the same time, the bias adjustment control signal SP* is an effective pulse, the bias adjustment module 105 is turned on, and the bias adjustment signal V0 is written to the second electrode (i.e. N3 node) of the driving transistor T2, which can pull up the second electrode potential of the driving transistor T2, thereby forming a larger voltage difference between the second electrode and the gate of the driving transistor T2. In this way, the reverse electric field generated in the driving transistor T2 can be offset more quickly, the bias problem can be solved, the threshold voltage of the driving transistor T2 can be more stable, and the flicker phenomenon can be weakened.

[0070] Continuing to refer to Figure 3 and Figure 8In the embodiment, since the reset module 103 is kept on during the bias adjustment stage t30, the gate potential of the driving transistor T2 is adjusted by the reset signal Vref, and the compensation module 102 does not need to be turned on again, i.e., the compensation module 102 is kept off during the bias adjustment stage t30, so that the second scan signal S2N does not need to jump again to provide an effective pulse during the bias adjustment stage t30. Therefore, the compensation module 102 only needs to be turned on once during the data writing stage t20 in one frame of picture refreshing, and accordingly, the second scan signal S2N also only needs to provide an effective pulse once during the data writing stage t20, so that the jump frequency of the second scan signal S2N can be reduced, the driving process is simplified, the processing capacity requirement of the driving circuit for providing the second scan signal S2N is reduced, and the process complexity and manufacturing cost of the driving circuit are reduced.

[0071] Figure 10 For the driving timing diagram of another pixel circuit in the related art, as shown in Figure 3 and Figure 10 The inventors have further found that, after the end of the bias adjustment stage t30, there is a large voltage difference between the second electrode and the gate of the driving transistor T2. Taking the driving transistor T2 as a PMOS transistor as an example, the gate potential of the driving transistor T2 is a low potential, and the second electrode (i.e., the N3 node) of the driving transistor T2 is kept at a high potential, as shown in Figure 10 If the reset stage t10 is located before the compensation module 102 is turned on, i.e., the reset module 103 is turned off before the compensation module 102 is turned on, during the data writing stage t20, the data writing transistor T1 and the compensation transistor T3 are turned on, and the data signal Vdata is written from the first electrode (i.e., the N2 node) of the driving transistor T2 to the gate (i.e., the N1 node) of the driving transistor T2 through the second electrode (i.e., the N3 node), and since the second electrode (i.e., the N3 node) of the driving transistor T2 is at a high potential, the input of the data signal Vdata is affected, which is not conducive to the writing of the data signal Vdata to the gate (i.e., the N1 node) of the driving transistor T2, and affects the accuracy and stability of the data signal Vdata writing.

[0072] Based on the above technical problems, continuing to refer to Figure 3 and Figure 8In the embodiment, the reset module 103 is set to be turned off at least after the compensation module 102 is turned on, that is, there is an overlap between the time period (i.e., the reset stage t10) during which the reset module 103 is turned on and the time period during which the compensation module 102 is turned on, and during the overlap time of the time period during which the reset module 103 is turned on and the time period during which the compensation module 102 is turned on, the reset module 103 and the compensation module 102 are both kept on, and the reset signal Vref is transmitted to the second electrode (i.e., the N3 node) of the driving transistor T2 through the reset module 103 and the compensation module 102, so as to pull down the potential of the second electrode of the driving transistor T2, and make the potential of the second electrode of the driving transistor T2 the same as the potential of the gate electrode of the driving transistor T2. In this way, during the data writing stage t20, when the data signal Vdata is written into the gate electrode (i.e., the N1 node) of the driving transistor T2 from the first electrode (i.e., the N2 node) of the driving transistor T2 through the second electrode (i.e., the N3 node), since the second electrode (i.e., the N3 node) of the driving transistor T2 is at a low potential, the input of the data signal Vdata is more favorable, so that the data signal Vdata is more accurately written into the gate electrode (i.e., the N1 node) of the driving transistor T2.

[0073] It should be noted that the technical solutions shown in the above Figure 3 and Figure 8 are only described by taking the driving transistor T2 as a PMOS type transistor as an example, and in other embodiments, when the type of the driving transistor T2 changes, by changing the high and low potentials of the signals, similar driving processes and beneficial effects as described above can also be achieved, and thus will not be described herein.

[0074] In addition, in one picture refresh frame, a plurality of bias adjustment stages t30 can be included, wherein a part of the bias adjustment stages t30 and the data writing stages t20, and the time period between the part of the bias adjustment stages t30 and the data writing stages t20, the compensation module 102 is kept on; another part of the bias adjustment stages t30 and the reset stages t10, the reset module 103 is kept on, and the reset module 103 is turned off at least after the compensation module 102 is turned on, so as to achieve similar driving processes and beneficial effects as described above, and the embodiments of the present application are not limited thereto.

[0075] In summary, the display panel provided by the embodiments of the present invention, by setting the compensation module to be on during the bias adjustment phase and the data writing phase, and during the time period between the bias adjustment phase and the data writing phase; and / or, by setting the reset module to be on during the bias adjustment phase and the reset phase, and by setting the reset module to be off at least after the compensation module is turned on, so that the compensation module in the pixel circuit is turned on only once in a screen refresh frame, and correspondingly, the scanning signal that controls the on and off of the compensation transistor only needs to provide one effective pulse in a screen refresh frame, thereby reducing the switching frequency of the scanning signal, simplifying the driving process, reducing the processing capability requirements of the driving circuit that provides the scanning signal, and thus reducing the process complexity and manufacturing cost of the driving circuit.

[0076] Figure 11 A driving timing diagram for another pixel circuit provided in an embodiment of the present invention, such as... Figure 3 , Figure 7 and Figure 11 As shown, optionally, the compensation module 102 remains active during the bias adjustment phase t30 and the data writing phase t20, and during the time period t40 between the bias adjustment phase t30 and the data writing phase t20. The duration of the bias adjustment phase t30 is Ws, the duration of the data writing phase t20 is Wd, and the duration of the time period during which the compensation module 102 is active is Wc. Wherein, the bias adjustment phase t30 is before the data writing phase t20, the duration of the time period t41 between the end of the bias adjustment phase t30 and the start of the data writing phase t20 is Wt1, and Wc ≥ (Ws + Wd + Wt1). Alternatively, the bias adjustment phase t30 is after the data writing phase t20, the duration of the time period t42 between the end of the data writing phase t20 and the start of the bias adjustment phase t30 is Wt2, and Wc ≥ (Ws + Wd + Wt2).

[0077] Specifically, such as Figure 3 and Figure 7 As shown, in this embodiment, the bias adjustment stage t30 can be located before the data writing stage t20, so that a bias adjustment signal V0 is provided to the driving transistor T2 before the data signal Vdata is written to the gate of the driving transistor T2. The bias adjustment signal V0 will adjust the voltage difference between the gate of the driving transistor T2 and the first or second electrode to improve the phenomenon of threshold voltage drift caused by the large potential difference between the gate, the first electrode and the second electrode of the driving transistor T2, thereby facilitating the accurate writing of the data signal Vdata in the data writing stage t20.

[0078] Meanwhile, continue to refer to Figure 3 and Figure 7, the time length Wc of the time period during which the compensation module 102 is turned on is at least equal to the sum of the time length Ws of the bias adjustment stage t30, the time length Wd of the data writing stage t20, and the time length Wt1 of the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20, so that the time length Wc of the time period during which the compensation module 102 is turned on can cover the time length Ws of the bias adjustment stage t30, the time length Wd of the data writing stage t20, and the time length Wt1 of the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20, and the compensation module 102 is ensured to be in the turned-on state during the bias adjustment stage t30, the data writing stage t20, and the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20, so that the compensation module 102 only needs to be turned on once in one picture refresh frame while the driving process of the bias adjustment stage t30 and the data writing stage t20 is implemented, and accordingly, the second scanning signal S2N only needs to be provided with one valid pulse in one picture refresh frame, so that the second scanning signal S2N does not need to jump again during the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20, thereby reducing the jump frequency of the second scanning signal S2N, simplifying the driving process, reducing the requirement on the processing capability of the driving circuit for providing the second scanning signal S2N, and helping to reduce the process complexity and the process manufacturing cost of the driving circuit.

[0079] In addition, after the jump frequency of the second scanning signal S2N is reduced, the frequency of the valid pulse output by the driving circuit for providing the second scanning signal S2N is also reduced, which is also helpful to reduce the power consumption of the driving circuit, thereby being beneficial to reducing the power consumption of the display panel.

[0080] Further, as Figure 3 and Figure 7As shown, the time length Wcof the time period during which the compensation module 102 is enabled can be set to be greater than the sum of the time length Wsof the bias adjustment stage t30, the time length Wdof the data writing stage t20, and the time length Wt1of the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20, i.e., Wc>(Ws+Wd+Wt1). In this way, the compensation module 102 is enabled before the bias adjustment stage t30, i.e., before the bias adjustment signal Vo is input to the driving transistor T2, so that the working stability of the compensation module 102 is ensured when the bias adjustment signal Vo is transmitted to the gate of the driving transistor T2 through the compensation module 102. Meanwhile, Wc>(Ws+Wd+Wt1) also ensures that the compensation module 102 is disabled after the data writing stage t20, so that the compensation module 102 is in a stable enabled state during the data writing stage t20, i.e., when the data signal Vdata is written to the gate of the driving transistor T2, and the accuracy and stability of the data signal Vdata are ensured.

[0081] In another alternative embodiment, as shown in Figure 3 and Figure 11 the bias adjustment stage t30 can be located after the data writing stage t20, so that the bias adjustment signal Vo is provided to the driving transistor T2 after the data signal Vdata is written to the gate of the driving transistor T2 and before the light emitting element 11 enters the light emitting stage. The bias adjustment signal Vo adjusts the voltage difference between the gate and the first or second electrode of the driving transistor T2 to improve the threshold voltage drift caused by the large potential difference between the gate, the first electrode and the second electrode of the driving transistor T2, so that the driving transistor T2 can provide accurate driving current to the light emitting element 11 in the subsequent light emitting stage, the light emitting element 11 can emit light accurately, and the display effect of the display panel is improved.

[0082] Meanwhile, continuing to refer to Figure 3 and Figure 11, the time length Wc of the time period during which the compensation module 102 is turned on is at least equal to the sum of the time length Wsof the bias adjustment stage t30, the time length Wdof the data writing stage t20, and the time length Wt2of the time period t42 between the end of the data writing stage t20 and the start of the bias adjustment stage t30, so that the time length Wcof the time period during which the compensation module 102 is turned on can cover the time length Wsof the bias adjustment stage t30, the time length Wdof the data writing stage t20, and the time length Wt2of the time period t42 between the end of the data writing stage t20 and the start of the bias adjustment stage t30, and the compensation module 102 is ensured to be turned on during the bias adjustment stage t30, the data writing stage t20, and the time period t42 between the end of the data writing stage t20 and the start of the bias adjustment stage t30, so that the compensation module 102 only needs to be turned on once in one frame of picture refresh while the driving process of the bias adjustment stage t30 and the data writing stage t20 is implemented, accordingly, the second scanning signal S2N only needs to provide one valid pulse in one frame of picture refresh, so that the second scanning signal S2N does not need to jump again during the time period t42 between the end of the data writing stage t20 and the start of the bias adjustment stage t30, thereby reducing the jump frequency of the second scanning signal S2N, simplifying the driving process, reducing the requirement on the processing capability of the driving circuit for providing the second scanning signal S2N, and helping to reduce the process complexity and the process manufacturing cost of the driving circuit.

[0083] In addition, after reducing the jump frequency of the second scanning signal S2N, the frequency of the valid pulse output by the driving circuit for providing the second scanning signal S2N is also reduced, which is also helpful to reduce the power consumption of the driving circuit, thereby being beneficial to reducing the power consumption of the display panel.

[0084] Further, as Figure 3 and Figure 11As shown, the time length Wcof the time period during which the compensation module 102 is enabled can be set to be greater than the sum of the time length Wsof the bias adjustment stage t30, the time length Wdof the data writing stage t20, and the time length Wt2of the time period t42 between the end of the data writing stage t20 and the start of the bias adjustment stage t30, i.e., Wc>(Ws+Wd+Wt2). In this way, the compensation module 102 is enabled before the data writing stage t20, i.e., before the data signal Vdata is written to the gate of the driving transistor T2, so that the compensation module 102 is in a stable enabled state when the data signal Vdata is written to the gate of the driving transistor T2, thereby ensuring the accuracy and stability of the writing of the data signal Vdata. Meanwhile, setting Wc>(Ws+Wd+Wt2) also enables the compensation module 102 to be disabled after the bias adjustment stage t30, i.e., after the bias adjustment signal V0 is written to the driving transistor T2, so that the compensation module 102 is in a stable enabled state when the bias adjustment signal V0 is transmitted to the gate of the driving transistor T2 via the compensation module 102, thereby ensuring the accuracy and stability of the writing of the bias adjustment signal V0.

[0085] With reference back to Figure 3 and Figure 7 Optionally, the reset stage t10 is located between the bias adjustment stage t30 and the data writing stage t20, and during the reset stage t10, the compensation module 102 remains enabled.

[0086] Specifically, as shown in Figure 3 and Figure 7 , the reset stage t10 is set to be located between the bias adjustment stage t30 and the data writing stage t20, so that the time of the active pulse of the third scan signal S1N does not overlap with the time of the active pulse of the bias adjustment control signal SP*, so that the reset stage t10 and the bias adjustment stage t30 are performed at different times and do not affect each other, thereby ensuring the accuracy of the reset of the driving transistor T2 and the accuracy of the bias adjustment. Meanwhile, the time of the active pulse of the third scan signal S1N does not overlap with the time of the active pulse of the first scan signal SP, so that the reset stage t10 and the data writing stage t20 are performed at different times, thereby avoiding the writing of the data signal Vdata affecting the reset of the gate of the driving transistor T2, and preventing the reset signal Vref from affecting the writing of the data signal Vdata, thereby improving the accuracy of the reset of the gate of the driving transistor T2 while ensuring that the data signal Vdata can be accurately written to the gate of the driving transistor T2.

[0087] With reference to the foregoing Figure 3 and Figure 7 In the reset stage t10, the compensation module 102 keeps on, on the one hand, it can ensure that the compensation module 102 only needs to be turned on once in a frame of picture refreshing, and accordingly, the second scanning signal S2N only needs to provide one valid pulse in a frame of picture refreshing, which reduces the frequency of the second scanning signal S2N, simplifies the driving process, reduces the requirement for the processing capacity of the driving circuit for providing the second scanning signal S2N, and further reduces the process complexity and the process manufacturing cost of the driving circuit. On the other hand, in the reset stage t10, the compensation module 102 keeps on, the reset signal Vref will be transmitted to the second electrode (i.e. the N3 node) of the driving transistor T2 through the reset module 103 and the compensation module 102, so that the potential of the second electrode of the driving transistor T2 is the same as the potential of the gate of the driving transistor T2. Thus, in the data writing stage t20, when the data signal Vdata is written into the gate of the driving transistor T2 from the first electrode (i.e. the N2 node) of the driving transistor T2 through the second electrode (i.e. the N3 node), since the second electrode of the driving transistor T2 is written with the reset signal Vref, it is more conducive to the input of the data signal Vdata, so that the data signal Vdata is more accurately written into the gate of the driving transistor T2.

[0088] With reference to the foregoing Figure 3 and Figure 7 Optionally, the time length of the time period in which the reset module 103 is turned on is Wr, the bias adjustment stage t30 is located before the data writing stage t20, and the time length of the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20 is Wt1; wherein Wr

[0089] The time length of the time period in which the reset module 103 is turned on is Wr, which is the time length of the reset stage t10.

[0090] In this embodiment, as Figure 3 and Figure 7As shown, the time length Wr of the time period during which the reset module 103 is turned on is less than the time length Wt1 of the time period t41 between the end of the bias adjustment stage t30 and the start of the data writing stage t20. In this way, the time interval between the time of the active pulse of the third scan signal S1N and the time of the active pulse of the bias adjustment control signal SP* can exist while ensuring that the reset stage t10 and the bias adjustment stage t30 are performed at different times and that the reset stage t10 and the data writing stage t20 are performed at different times. In this way, the reset module 103 is turned on after the end of the bias adjustment stage t30, so that the reset module 103 is in a stable off state when the bias adjustment signal V0 is transmitted to the gate of the drive transistor T2 via the compensation module 102 in the bias adjustment stage t30, thereby avoiding the influence of the writing of the reset signal Vref on the accuracy of the bias adjustment of the drive transistor T2.

[0091] Meanwhile, the setting of Wr < Wt1 can also cause a time interval to exist between the time of the active pulse of the third scan signal S1N and the time of the active pulse of the first scan signal SP, so that the data writing module 104 is turned on after the reset module 103 is turned off, thereby ensuring that the reset of the gate of the drive transistor T2 is completed before the data writing stage t20, i.e., before the data signal Vdata is written to the gate of the drive transistor T2, and that the drive transistor T2 is in a conductive state. In addition, the reset module 103 is in a stable off state when the data signal Vdata is written to the gate of the drive transistor T2 in the data writing stage t20, thereby preventing the reset signal Vref from affecting the writing of the data signal Vdata, so as to improve the accuracy of the reset of the gate of the drive transistor T2 while ensuring that the data signal Vdata can be accurately written to the gate of the drive transistor T2.

[0092] With reference to the foregoing Figure 3 and Figure 7 Optionally, the bias adjustment stage t30 is located before the data writing stage t20, the time length of the time period during which the compensation module 102 is turned on between the start of the bias adjustment stage t30 and the end of the bias adjustment stage t30 is Wb1, and the time length of the time period between the end of the data writing stage t20 and the turning off of the compensation module 102 is Wa1. In this way, Wb1 ≥ 0, and / or Wa1 ≥ 0.

[0093] Specifically, as Figure 3 and Figure 7As shown, the bias adjustment phase t30 is located before the data writing phase t20, so as to provide the bias adjustment signal Vo to the driving transistor T2 before the data signal Vdata is written into the gate of the driving transistor T2, which adjusts the voltage difference between the gate and the first or second electrode of the driving transistor T2, so as to improve the threshold voltage drift due to the large potential difference between the gate, the first electrode and the second electrode of the driving transistor T2, thereby facilitating the accurate writing of the data signal Vdata in the data writing phase t20.

[0094] Meanwhile, with reference to Figure 3 and Figure 7 , the time length Wb1 of the time period from when the compensation module 102 is turned on to the start of the bias adjustment phase t30 is greater than or equal to 0, so as to ensure that the compensation module 102 is in the on state at the bias adjustment phase t30, so that the bias adjustment signal Vo can be transmitted to the gate of the driving transistor T2 through the compensation transistor T3, so that the potential of the gate of the driving transistor T2 is consistent with that of the first electrode and / or the second electrode, thereby improving the threshold voltage drift of the driving transistor T2 and weakening the flicker phenomenon.

[0095] Further, as shown in Figure 3 and Figure 7 , the time length Wb1 of the time period from when the compensation module 102 is turned on to the start of the bias adjustment phase t30 can be greater than 0, so that the compensation module 102 is turned on before the bias adjustment phase t30, i.e., before the bias adjustment signal Vo is input into the driving transistor T2, so as to ensure that the compensation module 102 is in the on state before the bias adjustment signal Vo is transmitted to the gate of the driving transistor T2 through the compensation module 102, thereby ensuring the stability of the compensation module 102.

[0096] With reference to Figure 3 and Figure 7 , in this embodiment, the time length Wa1 of the time period from the end of the data writing phase t20 to when the compensation module 102 is turned off is greater than or equal to 0, so as to ensure that the compensation module 102 is in the on state during the data writing phase t20, thereby enabling the data signal Vdata to be written into the gate of the driving transistor T2 through the compensation transistor T3.

[0097] Further, as shown in Figure 3 and Figure 7 , the time length Wa1 of the time period from the end of the data writing phase t20 to when the compensation module 102 is turned off can be greater than 0, so that the compensation module 102 is turned off after the data writing phase t20, thereby ensuring that the compensation module 102 is in the stable on state during the data writing phase t20, i.e., when the data signal Vdata is written into the gate of the driving transistor T2, thereby ensuring the accuracy and stability of the writing of the data signal Vdata.

[0098] Continue to refer to Figure 3 and Figure 7 Optional, Wb1≠Wa1.

[0099] Among them, such as Figure 3 and Figure 7 As shown, during the bias adjustment stage t30, the bias adjustment control signal SP* is an effective pulse, the bias adjustment module 105 is turned on, and the bias adjustment signal V0 is input to the first or second terminal of the driving transistor T2 to adjust the voltage difference between the gate of the driving transistor T2 and the first or second terminal, thereby eliminating the reverse electric field generated inside the driving transistor T2 and solving the bias problem. At the same time, the bias adjustment signal V0 can also be transmitted to the gate of the driving transistor T2 through the compensation transistor T3, so that the potential of the gate of the driving transistor T2 is consistent with that of the first and / or second terminal, improving the threshold voltage offset phenomenon of the driving transistor T2 and reducing the flickering phenomenon.

[0100] During the data writing stage t20, the first scan signal SP is a valid pulse, the second scan signal S2N is a valid pulse, the data writing module 104 and the compensation module 102 are turned on, and the data signal Vdata is written to the gate of the driving transistor T2 through the data writing module 104, the driving transistor T2 and the compensation module 10 until the driving transistor T2 is turned off.

[0101] Therefore, it can be seen that the driving process and the signal of the write driving transistor T2 are different in the bias adjustment stage t30 and the data writing stage t20, and the required technical effects are also different. Therefore, setting the time length Wb1 between the start of the compensation module 102 and the start of the bias adjustment stage t30 to be unequal to the time length Wa1 between the end of the data writing stage t20 and the turn-off of the compensation module 102 can make the time length Wb1 between the start of the compensation module 102 and the start of the bias adjustment stage t30 and the time length Wa1 between the end of the data writing stage t20 and the turn-off of the compensation module 102 more in line with the driving requirements of the bias adjustment stage t30 and the data writing stage t20. This makes the driving process of the pixel circuit more conducive to the accurate light emission of the light-emitting element 11 and improves the display effect of the display panel.

[0102] Continue to refer to Figure 3 and Figure 7 Optional, Wb1 < Wa1.

[0103] Wherein, since the voltage value of the data signal Vdata written to the gate of the driving transistor T2 will affect the size of the driving current generated by the driving transistor T2, and the size of the driving current generated by the driving transistor T2 determines the final gray scale presented by the display panel, therefore, accurately writing the data signal Vdata to the gate of the driving transistor T2 in the data writing stage t20 is crucial to the final display effect of the display panel.

[0104] In the embodiment, as shown in Figure 3 and Figure 7 , by setting the time length Wa1 of the time period between the end of the data writing stage t20 and the turning off of the compensation module 102 to be relatively long, the compensation module 102 is kept in the on state for a relatively long time after the end of the data writing stage t20, i.e. after the data signal Vdata is written to the gate of the driving transistor T2, so as to ensure the accuracy and stability of the writing of the data signal Vdata.

[0105] Meanwhile, the time length Wb1 of the time period between the turning on of the compensation module 102 and the start of the bias adjustment stage t30 is set to be relatively short, so as to shorten the time length Wb1 of the time period between the turning on of the compensation module 102 and the start of the bias adjustment stage t30, without affecting the bias adjustment of the driving transistor T2 in the bias adjustment stage t30, thereby helping to prolong the time of the light emitting stage when the time length of one frame of picture refresh is fixed, and being conducive to improving the display light emitting brightness of the display panel and improving the display effect.

[0106] Continuing to refer to Figure 3 and Figure 7 , optionally, the bias adjustment stage t30 is located after the data writing stage t20, the time length of the time period between the turning on of the compensation module 102 and the start of the data writing stage t20 is Wb2, and the time length of the time period between the end of the bias adjustment stage t30 and the turning off of the compensation module 102 is Wa2; wherein, Wb2≥0, and / or, Wa2≥0.

[0107] Specifically, as shown in Figure 3 and Figure 7 , the bias adjustment stage t30 is located after the data writing stage t20, so as to provide the bias adjustment signal V0 to the driving transistor T2 after the data signal Vdata is written to the gate of the driving transistor T2 and before the light emitting element 11 enters the light emitting stage. The bias adjustment signal V0 will adjust the voltage difference between the gate and the first or second electrode of the driving transistor T2, so as to improve the threshold voltage drift phenomenon caused by the large potential difference between the gate, the first electrode and the second electrode of the driving transistor T2, thereby enabling the driving transistor T2 to provide accurate driving current to the light emitting element 11 in the subsequent light emitting stage, enabling the light emitting element 11 to emit light accurately, and improving the display effect of the display panel.

[0108] As shown in Figure 3 and Figure 8 , the time length Wb2 of the time period between the compensation module 102 being turned on and the data writing stage t20 being started is greater than or equal to 0, which ensures that the compensation module 102 is in the on state during the data writing stage t20, so that the data signal Vdata can be written to the gate of the drive transistor T2 through the compensation transistor T3.

[0109] Further, as shown in Figure 3 and Figure 8 , the time length Wb2 of the time period between the compensation module 102 being turned on and the data writing stage t20 being started can be greater than 0, so that the compensation module 102 is turned on before the data writing stage t20, thereby ensuring that the compensation module 102 is in a stable on state during the data writing stage t20, i.e., when the data signal Vdata is written to the gate of the drive transistor T2, to ensure the accuracy and stability of data signal Vdata writing.

[0110] Continuing to refer to Figure 3 and Figure 8 , the time length Wa2 of the time period between the end of the bias adjustment stage t30 and the compensation module 102 being turned off is greater than or equal to 0, which ensures that the compensation module 102 is in the on state during the bias adjustment stage t30, so that the bias adjustment signal V0 can be transmitted to the gate of the drive transistor T2 through the compensation transistor T3, so that the gate of the drive transistor T2 is consistent with the potential of the first electrode and / or the second electrode, improving the threshold voltage shift phenomenon of the drive transistor T2 and weakening the flicker phenomenon.

[0111] Further, as shown in Figure 3 and Figure 8 , the time length Wa2 of the time period between the end of the bias adjustment stage t30 and the compensation module 102 being turned off can be greater than 0, so that the compensation module 102 is turned off after the bias adjustment stage t30 is ended, thereby ensuring that the compensation module 102 is in a stable on state during the bias adjustment stage t30, i.e., when the bias adjustment signal V0 is transmitted to the gate of the drive transistor T2 through the compensation module 102, to ensure the accuracy and stability of bias adjustment.

[0112] Continuing to refer to Figure 3 and Figure 8 , optionally, Wb2≠Wa2.

[0113] Wherein, as described above, the driving process and the signal of the write driving transistor T2 are different in the bias adjustment stage t30 and the data writing stage t20, and the technical effects required to be achieved are also different, therefore, the time length Wb2 of the time period from the compensation module 102 being turned on to the beginning of the data writing stage t20 is set to be different from the time length Wa2 of the time period from the end of the bias adjustment stage t30 to the compensation module 102 being turned off, so that the time length Wb2 of the time period from the compensation module 102 being turned on to the beginning of the data writing stage t20 and the time length Wa2 of the time period from the end of the bias adjustment stage t30 to the compensation module 102 being turned off can be more consistent with the driving requirements of the bias adjustment stage t30 and the data writing stage t20, so that the driving process of the pixel circuit is more conducive to the accurate light emission of the light emitting element 11, and the display effect of the display panel is improved.

[0114] With reference to the foregoing Figure 3 and Figure 8 , optionally, Wb2>Wa2.

[0115] Wherein, since the voltage value of the data signal Vdata at the gate of the write driving transistor T2 will affect the size of the driving current generated by the driving transistor T2, and the size of the driving current generated by the driving transistor T2 determines the final gray scale of the display panel, therefore, accurately writing the data signal Vdata at the gate of the driving transistor T2 in the data writing stage t20 is crucial to the display effect of the final display panel.

[0116] In the embodiment, as shown in Figure 3 and Figure 8 , the time length Wb2 of the time period from the compensation module 102 being turned on to the beginning of the data writing stage t20 is set to be longer, so that the compensation module 102 is kept in the turned-on state for a longer time before the data writing stage t20, i.e., before the data signal Vdata is written at the gate of the driving transistor T2, thereby ensuring that the compensation module 102 is in a stable turned-on state when the data writing stage t20, i.e., when the data signal Vdata is written at the gate of the driving transistor T2, so as to improve the accuracy and stability of the data signal Vdata writing.

[0117] Meanwhile, the time length Wa2 of the time period from the end of the bias adjustment stage t30 to the compensation module 102 being turned off is set to be shorter, so that the time length Wa2 of the time period from the end of the bias adjustment stage t30 to the compensation module 102 being turned off is shortened without affecting the bias adjustment of the driving transistor T2 in the bias adjustment stage t30, thereby helping to prolong the light emitting stage when the time length of a frame of picture refresh is fixed, which is conducive to improving the display light emitting brightness of the display panel and improving the display effect.

[0118] With reference to the foregoingFigure 3 and Figure 8 Optionally, during the bias adjustment stage t30 and the reset stage t10, the reset module 103 keeps on, and the reset module 103 is turned off at least after the compensation module 102 is turned on. The length of the bias adjustment stage t30 is Ws, the time period between the end of the bias adjustment stage t30 and the compensation module 102 is turned on is Wt3, and the length of the reset stage t10 is Wr, wherein Wr≥(Ws+Wt3).

[0119] As shown in Figure 3 and Figure 8 During the bias adjustment stage t30, the third scan signal S1 is a valid pulse, the reset module 103 keeps on, the reset signal Vref can adjust the gate potential of the driving transistor T2, at the same time, the bias adjustment control signal SP* is a valid pulse, the bias adjustment module 105 is turned on, and the bias adjustment signal Vo is input to the first electrode or the second electrode of the driving transistor T2 to adjust the potential of the first electrode or the second electrode of the driving transistor T2, so as to adjust the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2 through the reset signal Vref and the bias adjustment signal Vo at the same time. In this way, the adjustment range of the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2 can be increased, which is more helpful to eliminate the reverse electric field generated inside the driving transistor T2, solve the bias problem, avoid the threshold voltage of the driving transistor T2 from shifting, and weaken the flicker phenomenon.

[0120] At the same time, since the reset module 103 keeps on during the bias adjustment stage t30, the gate potential of the driving transistor T2 is adjusted by the reset signal Vref, so the compensation module 102 does not need to be turned on again, i.e., the compensation module 102 keeps off during the bias adjustment stage t30, so that the second scan signal S2N does not need to jump to provide a valid pulse during the bias adjustment stage t30. Therefore, in one frame of picture refresh, the compensation module 102 only needs to be turned on once during the data writing stage t20, and correspondingly, the second scan signal S2N also only needs to provide a valid pulse once during the data writing stage t20, so as to reduce the jump frequency of the second scan signal S2N, simplify the driving process, reduce the requirement for the processing capability of the driving circuit for providing the second scan signal S2N, and help to reduce the process complexity and process manufacturing cost of the driving circuit.

[0121] Further, as shown in Figure 3 and Figure 8As shown, the time length Wr of the reset stage t10 is set to be at least equal to the sum of the time length Ws of the bias adjustment stage t30 and the time period Wt3 between the end of the bias adjustment stage t30 and the start of the compensation module 102, so that the time length Wr of the reset stage t10 can cover the time length Ws of the bias adjustment stage t30 and the time period Wt3 between the end of the bias adjustment stage t30 and the start of the compensation module 102, ensuring that the reset module 103 is in the state of being turned on during both the bias adjustment stage t30 and the reset stage t10, so that the reset module 103 only needs to be turned on once in a picture refresh frame while the driving process of the bias adjustment stage t30 and the reset stage t10 is implemented, and accordingly, the third scanning signal S1N only needs to provide one valid pulse in a picture refresh frame, thereby avoiding the increase of the jump frequency of the third scanning signal S1N, and making the process complexity and the process manufacturing cost of the driving circuit for providing the third scanning signal S1N lower.

[0122] Further, as shown in Figure 3 and Figure 8 , the time length Wr of the reset stage t10 can be set to be greater than the sum of the time length Ws of the bias adjustment stage t30 and the time period Wt3 between the end of the bias adjustment stage t30 and the start of the compensation module 102, i.e. Wr>(Ws+Wt3), so that, while ensuring that the reset module 103 is in the state of being turned on during both the bias adjustment stage t30 and the reset stage t10, the reset module 103 can also be turned on before the bias adjustment stage t30, i.e. before the bias adjustment signal V0 is input to the driving transistor T2, the reset signal Vref has been written to the gate of the driving transistor T2, so that the driving transistor T2 is in a stable conduction state, thereby ensuring that the potentials of the first electrode and the second electrode of the driving transistor T2 are consistent with the bias adjustment signal V0 when the bias adjustment signal V0 is input to the driving transistor T2, improving the phenomenon of threshold voltage drift due to the large potential difference between the gate, the first electrode and the second electrode of the driving transistor T, solving the bias problem and weakening the flicker phenomenon.

[0123] Meanwhile, as shown in Figure 3 and Figure 8As shown, setting Wr>(Ws+Wt3) can also ensure that the reset module 103 is turned off after the compensation module 102 is turned on, so that there is an overlap between the time period when the reset module 103 is turned on (i.e. the reset stage t10) and the time period when the compensation module 102 is turned on. During the overlap time of the time period when the reset module 103 is turned on and the time period when the compensation module 102 is turned on, the reset module 103 and the compensation module 102 are both kept on, and the reset signal Vref is transmitted to the second electrode (i.e. the N3 node) of the drive transistor T2 through the reset module 103 and the compensation module 102, so as to adjust the potential of the second electrode of the drive transistor T2, so that the potential of the second electrode of the drive transistor T2 is the same as the potential of the gate electrode of the drive transistor T2. In this way, during the data writing stage t20, when the data signal Vdata is written to the gate electrode (i.e. the N1 node) of the drive transistor T2 from the first electrode (i.e. the N2 node) of the drive transistor T2 through the second electrode (i.e. the N3 node) of the drive transistor T2, since the potential of the second electrode (i.e. the N3 node) of the drive transistor T2 is the same as the potential of the gate electrode of the drive transistor T2, it is more conducive to the input of the data signal Vdata, so that the data signal Vdata is more accurately written to the gate electrode of the drive transistor T2.

[0124] With reference to the foregoing Figure 3 and Figure 8 Optionally, the time length of the time period of the overlap between the reset stage t10 and the time period when the compensation module 102 is turned on is Wt4; wherein Wr≥(Ws+Wt3+Wt4).

[0125] Specifically, as shown in FIG. 1, the time length of the time period of the overlap between the reset stage t10 and the time period when the compensation module 102 is turned on is Wt4; wherein Wr≥(Ws+Wt3+Wt4). Figure 3 and Figure 8As shown, the time length Wr of the reset phase t10 is set to be at least equal to the sum of the time length Ws of the bias adjustment phase t30, the time period Wt3 between the end of the bias adjustment phase t30 and the start of the compensation module 102, and the time length Wt4 of the overlapping time period between the reset phase t10 and the start of the compensation module 102. This ensures that the time length Wr of the reset phase t10 covers the time length Ws of the bias adjustment phase t30, the time period Wt3 between the end of the bias adjustment phase t30 and the start of the compensation module 102, and the time length Wt4 of the overlapping time period between the reset phase t10 and the start of the compensation module 102, thus guaranteeing that the reset module 103 operates within the bias adjustment phase t30, the bias adjustment phase t30, the offset ... The time period Wt3 between the end of the bias adjustment phase t30 and the start of the compensation module 102, as well as the overlapping time period between the reset phase t10 and the start of the compensation module 102, are all in an on state. Thus, while realizing the driving process of the bias adjustment phase t30, the reset phase t10, and the overlapping time period between the reset phase t10 and the start of the compensation module 102, the reset module 103 only needs to be turned on once in a screen refresh frame. Correspondingly, the third scan signal S1N only needs to provide one effective pulse in a screen refresh frame, thereby avoiding the increase of the switching frequency of the third scan signal S1N and making the process complexity and manufacturing cost of the driving circuit that provides the third scan signal S1N lower.

[0126] Continue to refer to Figures 3-6 and Figures 3-6 Optionally, the time period between the start of the reset phase t10 and the start of the bias adjustment phase t30 is Wb3, where Wb3≥0.

[0127] Among them, such as Figure 3 and Figure 7 As shown, the time length Wb3 between the start of the reset phase t10 and the start of the bias adjustment phase t30 is greater than or equal to 0, ensuring that the reset module 103 is in the on state during the bias adjustment phase t30. This allows the reset signal Vref to be written to the gate of the drive transistor T2 simultaneously with the bias adjustment signal V0 written to the first or second terminal of the drive transistor T2. This adjusts the voltage difference between the gate and the first or second terminal of the drive transistor T2 by simultaneously adjusting the reset signal Vref and the bias adjustment signal V0, thereby eliminating the reverse electric field generated inside the drive transistor T2, solving the bias problem, reducing the threshold voltage offset of the drive transistor T2, and reducing the flickering phenomenon.

[0128] Furthermore, such as Figure 3 and Figure 7As shown, the time length Wb3 between the start of the reset phase t10 and the start of the bias adjustment phase t30 can be set to be greater than 0, so that the reset module 103 is turned on before the bias adjustment phase t30. Thus, before the bias adjustment signal V0 is input to the driving transistor T2, the driving transistor T2 is in a stable conducting state. When the bias adjustment signal V0 is input to the driving transistor T2, it can be ensured that the potential of the first and second terminals of the driving transistor T2 is consistent with the bias adjustment signal V0. This improves the phenomenon of threshold voltage drift caused by the large potential difference between the gate, first terminal and second terminal of the driving transistor T, solves the bias problem and reduces the flickering phenomenon.

[0129] Continue to refer to Figure 3 and Figure 7 Optional, Wb3≠Wt4.

[0130] Among them, such as Figure 3 and Figure 4 As shown, during the overlapping period between the reset phase t10 and the time period when the compensation module 102 is turned on, the reset signal Vref is transmitted to the second terminal (i.e., node N3) of the driving transistor T2 via the reset module 103 and the compensation module 102, thereby adjusting the potential of the second terminal of the driving transistor T2 so that the potential of the second terminal of the driving transistor T2 is the same as the potential of the gate of the driving transistor T2. Thus, during the data writing phase t20, when the data signal Vdata is written from the first terminal (i.e., node N2) of the driving transistor T2 to the gate (i.e., node N1) of the driving transistor T2 via the second terminal (i.e., node N3), the second terminal (i.e., node N3) of the driving transistor T2 has the same potential as the gate of the driving transistor T2, which is more conducive to the input of the data signal Vdata, thereby making the data signal Vdata more accurately written to the gate of the driving transistor T2.

[0131] During the period between the start of the reset phase t10 and the start of the bias adjustment phase t30, the reset module 103 is turned on before the bias adjustment phase t30. Thus, before the bias adjustment signal V0 is input to the driving transistor T2, the driving transistor T2 is in the on state. When the bias adjustment signal V0 is input to the driving transistor T2, it can ensure that the potential of the first and second terminals of the driving transistor T2 is consistent with the bias adjustment signal V0. This improves the phenomenon of threshold voltage drift caused by the large potential difference between the gate, first terminal and second terminal of the driving transistor T, solves the bias problem and reduces the flickering phenomenon.

[0132] Therefore, the time length Wb3 of the time period between the start of the reset stage t10 and the start of the bias adjustment stage t30 is not equal to the time length Wt4 of the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on, so that the time length Wb3 of the time period between the start of the reset stage t10 and the start of the bias adjustment stage t30 and the time length Wt4 of the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on can be more in line with the driving requirements of the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on and the time period between the start of the reset stage t10 and the start of the bias adjustment stage t30, so that the driving process of the pixel circuit is more conducive to accurate light emission of the light emitting element 11, and the display effect of the display panel is improved.

[0133] With reference to Figure 3 and Figure 4 optionally, Wb3≤Wt4.

[0134] In the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on, the potential of the second electrode of the driving transistor T2 adjusted by the reset signal Vref will affect the accuracy of the data signal Vdata written into the gate electrode of the driving transistor T2 in the data writing stage t20, and the data signal Vdata written into the gate electrode of the driving transistor T2 will affect the size of the driving current generated by the driving transistor T2, and further affect the gray scale finally presented by the display panel, so that the effect of the reset signal Vref written into the second electrode of the driving transistor T2 in the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on will affect the display effect of the final display panel.

[0135] In the embodiment, as shown in Figure 5 and Figure 6 , the time length Wt4 of the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on is set to be at least equal to the time length Wb3 of the time period between the start of the reset stage t10 and the start of the bias adjustment stage t30, so as to ensure that the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on has sufficient time length, and ensure that the potential of the second electrode of the driving transistor T2 is consistent with the reset signal Vref, so that the data signal Vdata is more accurately written into the gate electrode of the driving transistor T2 in the data writing stage t20.

[0136] Further, with reference to Figure 5 and Figure 6The time length Wb3 of the time period between the start of the reset stage t10 and the start of the bias adjustment stage t30 can be set to be less than the time length Wt4 of the time period overlapping between the reset stage t10 and the time period when the compensation module 102 is turned on. In this way, the time length Wb3 of the time period between the start of the reset stage t10 and the start of the bias adjustment stage t30 can be shortened without affecting the bias adjustment of the driving transistor T2 in the bias adjustment stage t30, thereby helping to prolong the light emitting stage when the time length of one frame of picture refresh is fixed, and helping to improve the display light emitting brightness of the display panel and improve the display effect.

[0137] With reference to Figures 3-8 Optionally, the reset module 103 is connected to the gate of the driving transistor T2 (i.e., the N1 node), the data writing module 104 is connected to the first electrode of the driving transistor T2 (i.e., the N2 node), and the bias adjustment module 105 is connected to the first electrode (i.e., the N2 node) or the second electrode (i.e., the N3 node) of the driving transistor T2.

[0138] Specifically, as shown in Figure 3 , the reset module 103 can be connected to the gate of the driving transistor T2 (i.e., the N1 node) to provide a reset signal Vref for the gate of the driving transistor T2.

[0139] For example, as shown in Figure 7 and Figure 3 , in the reset stage t10, the third scan signal S1N is an effective pulse, the reset module 103 is turned on, and the reset signal Vref is transmitted to the gate of the driving transistor T2 (i.e., the N1 node) through the turned-on reset module 103, so as to reset the gate of the driving transistor T2. At this time, the potential of the gate of the driving transistor T2 (i.e., the N1 node) is consistent with the reset signal Vref, so as to avoid the influence of the data signal of the previous frame carried on the gate of the driving transistor T2 on the writing of the data signal of the next frame.

[0140] The data writing module 104 can be connected to the first electrode of the driving transistor T2 (i.e., the N2 node) to provide a data signal Vdata for the driving transistor T2.

[0141] For example, as shown in Figure 8 and Figure 12 , in the data writing stage t20, the first scan signal SP is an effective pulse, the second scan signal S2N is an effective pulse, the data writing module 104 and the compensation module 102 are turned on, and the data signal Vdata passes through the data writing module 104, the driving transistor T2 and the compensation module 102 to be written into the gate of the driving transistor T2 (i.e., the N1 node).

[0142] The bias adjustment module 105 can be connected to the first terminal (i.e. N2 node) or the second terminal (i.e. N3 node) of the driving transistor T2 for providing the bias adjustment signal V0 to the driving transistor T2.

[0143] As shown in Figure 3 and Figure 12 , in the bias adjustment stage t30, the bias adjustment control signal SP* is a valid pulse, the bias adjustment module 105 is turned on, and the bias adjustment signal V0 is input to the first terminal or the second terminal of the driving transistor T2 for adjusting the voltage difference between the gate and the first terminal or the second terminal of the driving transistor T2, thereby eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, avoiding the threshold voltage shift of the driving transistor T2, and facilitating the weakening of the flicker phenomenon.

[0144] As shown in Figure 3 and Figure 12 , when the driving transistor T2 is a PMOS transistor, the first terminal of the storage capacitor C1 in the pixel circuit 10 is connected to the first power signal terminal, and the second terminal is connected to the gate of the driving transistor T2 for storing the signal transmitted to the gate of the driving transistor T2. At this time, as shown in Figure 3 , the bias adjustment module 105 can be connected to the first terminal of the driving transistor T2, i.e. the N2 node. In another possible embodiment, as shown in Figure 12 , the bias adjustment module 105 can also be connected to the second terminal of the driving transistor T2, i.e. the N3 node.

[0145] As shown in Figure 3 and Figure 12 , when the driving transistor T2 is an NMOS transistor, the first terminal of the storage capacitor C1 in the pixel circuit 10 is connected to the light emitting element 11, and the second terminal is connected to the gate of the driving transistor T2 for storing the signal transmitted to the gate of the driving transistor T2. At this time, as shown in Figure 13 , the bias adjustment module 105 can be connected to the first terminal of the driving transistor T2, i.e. the N2 node. In another possible embodiment, as shown in Figure 3 , the bias adjustment module 105 can also be connected to the second terminal of the driving transistor T2, i.e. the N3 node.

[0146] Continuing to refer to Figure 13 , when the compensation module 102 is turned on, the bias adjustment module 105 transmits the bias adjustment signal V0 to the gate of the driving transistor T2 in the bias adjustment stage t30. When the compensation module 102 is turned off, the bias adjustment module 105 transmits the bias adjustment signal V0 to the first terminal and / or the second terminal of the driving transistor T2 in the bias adjustment stage t30.

[0147] As shown in Figure 3 andFigure 13 As shown in FIG. 8, in the bias adjustment stage t30, the compensation module 102 is turned on, and the bias adjustment module 105 can transmit the bias adjustment signal V0 to the gate of the driving transistor T2 through the compensation module 102, so that the potential of the gate of the driving transistor T2 is consistent with that of the first electrode and / or the second electrode, thereby eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, improving the threshold voltage shift phenomenon of the driving transistor T2, and weakening the flicker phenomenon.

[0148] In another possible embodiment, as shown in FIG. 9, in the bias adjustment stage t30, the compensation module 102 is turned off, and the bias adjustment module 105 can transmit the bias adjustment signal V0 to the first electrode and / or the second electrode of the driving transistor T2, so as to adjust the potential of the first electrode and / or the second electrode of the driving transistor T2, thereby adjusting the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2, eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, improving the threshold voltage shift phenomenon of the driving transistor T2, and weakening the flicker phenomenon. Figure 3 Figure 13 As shown in FIG. 8, in the bias adjustment stage t30, the compensation module 102 is turned on, and the bias adjustment module 105 can transmit the bias adjustment signal V0 to the gate of the driving transistor T2 through the compensation module 102, so that the potential of the gate of the driving transistor T2 is consistent with that of the first electrode and / or the second electrode, thereby eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, improving the threshold voltage shift phenomenon of the driving transistor T2, and weakening the flicker phenomenon.

[0149] Figure 3 As shown in FIG. 10, FIG. 11 and FIG. 12, the bias adjustment stage t30 includes a first bias adjustment stage t31 and a second bias adjustment stage t32, the first bias adjustment stage t31 is located before the data writing stage t20, and the second bias adjustment stage t32 is located after the data writing stage t20. In the first bias adjustment stage t31 and the data writing stage t20, and the time period t40 between the first bias adjustment stage t31 and the data writing stage t20, the compensation module 102 is kept on. Figure 13 Figure 14 As shown in FIG. 10, FIG. 11 and FIG. 12, the bias adjustment stage t30 includes a first bias adjustment stage t31 and a second bias adjustment stage t32, the first bias adjustment stage t31 is located before the data writing stage t20, and the second bias adjustment stage t32 is located after the data writing stage t20. In the first bias adjustment stage t31 and the data writing stage t20, and the time period t40 between the first bias adjustment stage t31 and the data writing stage t20, the compensation module 102 is kept on.

[0150] As shown in FIG. 10, FIG. 11 and FIG. 12, the bias adjustment stage t30 includes a first bias adjustment stage t31 and a second bias adjustment stage t32, the first bias adjustment stage t31 is located before the data writing stage t20, and the second bias adjustment stage t32 is located after the data writing stage t20. In the first bias adjustment stage t31 and the data writing stage t20, and the time period t40 between the first bias adjustment stage t31 and the data writing stage t20, the compensation module 102 is kept on. Figure 14 Figure 14 As shown in FIG. 10, FIG. 11 and FIG. 12, the bias adjustment stage t30 includes a first bias adjustment stage t31 and a second bias adjustment stage t32, the first bias adjustment stage t31 is located before the data writing stage t20, and the second bias adjustment stage t32 is located after the data writing stage t20. In the first bias adjustment stage t31 and the data writing stage t20, and the time period t40 between the first bias adjustment stage t31 and the data writing stage t20, the compensation module 102 is kept on.

[0151] ​​​The second bias adjustment stage t32 is located after the data writing stage t20, so as to provide the bias adjustment signal V0 to the driving transistor T2 after the data signal Vdata is written to the gate of the driving transistor T2 and before the light emitting element 11 enters the light emitting stage, which adjusts the voltage difference between the gate and the first or second electrode of the driving transistor T2, so as to improve the threshold voltage drift phenomenon caused by the large potential difference among the gate, the first electrode and the second electrode of the driving transistor T2, so that the driving transistor T2 can provide accurate driving current to the light emitting element 11 in the subsequent light emitting stage, so that the light emitting element 11 accurately emits light, and the display effect of the display panel is improved.

[0152] Further, as shown in ​ and ​ , the compensation module 102 is kept on during the first bias adjustment stage t31 and the data writing stage t20, and the time period t40 between the first bias adjustment stage t31 and the data writing stage t20, that is, the compensation module 102 is kept on after the first time of opening in the first bias adjustment stage t31, and is kept on until the data writing stage t20 of the current frame is finished, and then the compensation module 102 is turned off. The compensation module 102 only needs to be turned on once in one frame, and the second scanning signal S2N only needs to provide one valid pulse in one frame, so as to reduce the frequency of the second scanning signal S2N, simplify the driving process, reduce the processing capacity requirement of the driving circuit for providing the second scanning signal S2N, and help to reduce the process complexity and manufacturing cost of the driving circuit.

[0153] It should be noted that, as shown in ​ and ​ , during the first bias adjustment stage t31, the compensation module 102 is turned on, and the bias adjustment module 105 can transmit the bias adjustment signal V0 to the gate of the driving transistor T2 through the compensation module 102, so that the potential of the gate of the driving transistor T2 is consistent with that of the first electrode and / or the second electrode, thereby eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, improving the threshold voltage shift phenomenon of the driving transistor T2, and weakening the flicker phenomenon.

[0154] During the second bias adjustment stage t32, the compensation module 102 is turned off, and the bias adjustment module 105 can transmit the bias adjustment signal V0 to the first electrode and / or the second electrode of the driving transistor T2, so as to adjust the potential of the first electrode and / or the second electrode of the driving transistor T2, thereby adjusting the voltage difference between the gate and the first or second electrode of the driving transistor T2, eliminating the reverse electric field generated inside the driving transistor T2, solving the bias problem, improving the threshold voltage shift phenomenon of the driving transistor T2, and weakening the flicker phenomenon.

[0155] ​ Figure 6 shows a driving timing diagram of another pixel circuit according to an embodiment of the present application. ​ ​ Optionally, the bias adjustment stage t30 comprises a first bias adjustment stage t31 and a second bias adjustment stage t32. The first bias adjustment stage t31 is located before the data writing stage t20, and the second bias adjustment stage t32 is located after the data writing stage t20. In the first bias adjustment stage t31 and the reset stage t10, the reset module 103 is kept on, and the reset module 103 is turned off at least after the compensation module 102 is turned on.

[0156] In the first bias adjustment stage t31, the reset module 103 is kept on, and the compensation module 102 is turned on. In the second bias adjustment stage t32, the reset module 103 is kept on, and the compensation module 102 is turned off. ​ ​ The first bias adjustment stage t31 is located before the data writing stage t20, so as to provide the bias adjustment signal V0 to the driving transistor T2 before the data signal Vdata is written to the gate of the driving transistor T2. The bias adjustment signal V0 adjusts the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2, so as to improve the threshold voltage drift phenomenon caused by the large potential difference among the gate, the first electrode and the second electrode of the driving transistor T2, thereby facilitating the accurate writing of the data signal Vdata in the data writing stage t20.

[0157] The second bias adjustment stage t32 is located after the data writing stage t20, so as to provide the bias adjustment signal V0 to the driving transistor T2 after the data signal Vdata is written to the gate of the driving transistor T2 and before the light emitting element 11 enters the light emitting stage. The bias adjustment signal V0 adjusts the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2, so as to improve the threshold voltage drift phenomenon caused by the large potential difference among the gate, the first electrode and the second electrode of the driving transistor T2, thereby enabling the driving transistor T2 to provide accurate driving current to the light emitting element 11 in the subsequent light emitting stage, enabling the light emitting element 11 to emit light accurately, and improving the display effect of the display panel.

[0158] Further, as shown in ​ ​ the first bias adjustment stage t31 is located before the data writing stage t20, so as to provide the bias adjustment signal V0 to the driving transistor T2 before the data signal Vdata is written to the gate of the driving transistor T2. The bias adjustment signal V0 adjusts the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2, so as to improve the threshold voltage drift phenomenon caused by the large potential difference among the gate, the first electrode and the second electrode of the driving transistor T2, thereby facilitating the accurate writing of the data signal Vdata in the data writing stage t20.​​As shown in FIG. 1, in the first bias adjustment stage t31 and the reset stage t10, the third scan signal S1 is a valid pulse, the reset module 103 remains open, the reset signal Vref is written to the gate of the driving transistor T2 (i.e. the N1 node), so as to adjust the gate potential of the driving transistor T2, and at the same time, the bias adjustment control signal SP* is a valid pulse, the bias adjustment module 105 is open, and the bias adjustment signal V0 is input to the first electrode or the second electrode of the driving transistor T2, so as to adjust the potential of the first electrode or the second electrode of the driving transistor T2, thereby adjusting the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2 by the reset signal Vref and the bias adjustment signal V0 at the same time. In this way, the adjustment range of the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2 can be increased, which helps to eliminate the reverse electric field generated in the driving transistor T2, solve the bias problem, improve the threshold voltage shift phenomenon of the driving transistor T2, and weaken the flicker phenomenon.

[0159] At the same time, the reset module 103 is at least turned off after the compensation module 102 is turned on, that is, there is an overlap between the time period in which the reset module 103 is open (i.e. the reset stage t10) and the time period in which the compensation module 102 is open. In the overlap time of the time period in which the reset module 103 is open and the time period in which the compensation module 102 is open, the reset module 103 and the compensation module 102 remain open, the reset signal Vref is transmitted to the second electrode (i.e. the N3 node) of the driving transistor T2 through the reset module 103 and the compensation module 102, so that the potential of the second electrode of the driving transistor T2 is consistent with the reset signal Vref. In this way, in the data writing stage t20, when the data signal Vdata is written to the gate (i.e. the N1 node) of the driving transistor T2 from the first electrode (i.e. the N2 node) of the driving transistor T2 through the second electrode (i.e. the N3 node), the potential of the second electrode of the driving transistor T2 is consistent with the reset signal Vref, which is more conducive to the input of the data signal Vdata, so that the data signal Vdata can be more accurately written to the gate of the driving transistor T2.

[0160] It should be noted that, as shown in FIG. 1, ​ and ​ As shown in FIG. 1, in the first bias adjustment stage t31 and the second bias adjustment stage t32, the compensation module 102 is turned off, and the bias adjustment module 105 can transmit the bias adjustment signal V0 to the first electrode and / or the second electrode of the driving transistor T2, so as to adjust the potential of the first electrode and / or the second electrode of the driving transistor T2, thereby adjusting the voltage difference between the gate and the first electrode or the second electrode of the driving transistor T2, eliminating the reverse electric field generated in the driving transistor T2, solving the bias problem, improving the threshold voltage shift phenomenon of the driving transistor T2, and weakening the flicker phenomenon.

[0161] Based on the same inventive concept, the embodiment of the present application also provides a display device,​ This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... ​ As shown, the display device 50 includes the display panel 51 described in any embodiment of the present invention. Therefore, the display device 50 provided by the embodiments of the present invention has the technical effects of the technical solutions in any of the above embodiments. The explanations of the same or corresponding structures and terms as described in the above embodiments will not be repeated here.

[0162] The display device 50 provided in this embodiment of the invention can be ​ The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0163] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0164] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a compensation module, a reset module, a data writing module, and a bias adjustment module; The driving module includes a driving transistor, which includes a gate, a first electrode, and a second electrode. The compensation module is connected between the gate and the second electrode of the driving transistor. The operation of the display panel includes a reset phase, a data writing phase, and a bias adjustment phase. During the reset phase, the reset module provides a reset signal to the driving transistor; During the data writing phase, the data writing module provides data signals to the driving transistor; During the bias adjustment phase, the bias adjustment module is activated, and the bias adjustment module provides a bias adjustment signal to the driving transistor; wherein... The compensation module remains active during the bias adjustment phase and the data writing phase, as well as during the time interval between the bias adjustment phase and the data writing phase. And / or, During the bias adjustment phase and the reset phase, the reset module remains on, and the reset module is turned off at least after the compensation module is turned on. There is an overlap between the time periods during which the reset module is on and the time periods during which the compensation module is on.

2. The display panel according to claim 1, characterized in that, The compensation module remains active during the bias adjustment phase and the data writing phase, as well as during the time interval between the bias adjustment phase and the data writing phase. The duration of the bias adjustment phase is Ws, the duration of the data writing phase is Wd, and the duration of the compensation module's activation period is Wc; wherein... The bias adjustment phase occurs before the data writing phase, and the time interval between the end of the bias adjustment phase and the start of the data writing phase is Wt1, where Wc ≥ (Ws + Wd + Wt1); or... The bias adjustment phase is located after the data writing phase, and the time length between the end of the data writing phase and the start of the bias adjustment phase is Wt2, where Wc≥(Ws+Wd+Wt2).

3. The display panel according to claim 2, characterized in that, The reset phase is located between the bias adjustment phase and the data writing phase, and the compensation module remains on during the reset phase.

4. The display panel according to claim 3, characterized in that, The duration of the time period during which the reset module is activated is Wr; The bias adjustment phase occurs before the data writing phase, and the time interval between the end of the bias adjustment phase and the start of the data writing phase is Wt1; wherein... Wr < Wt1.

5. The display panel according to claim 2, characterized in that, The bias adjustment phase occurs before the data writing phase; The time interval between the activation of the compensation module and the start of the bias adjustment phase is Wb1, and the time interval between the end of the data writing phase and the deactivation of the compensation module is Wa1; wherein... Wb1≥0, and / or Wa1≥0.

6. The display panel according to claim 5, characterized in that, Wb1≠Wa1.

7. The display panel according to claim 6, characterized in that, Wb1 < Wa1.

8. The display panel according to claim 2, characterized in that, The bias adjustment phase occurs after the data writing phase; The time interval from the activation of the compensation module to the start of the data writing phase is Wb2, and the time interval from the end of the bias adjustment phase to the deactivation of the compensation module is Wa2; wherein... Wb2≥0, and / or Wa2≥0.

9. The display panel according to claim 8, characterized in that, Wb2≠Wa2.

10. The display panel according to claim 9, characterized in that, Wb2 > Wa2.

11. The display panel according to claim 1, characterized in that, During the bias adjustment phase and the reset phase, the reset module remains on, and the reset module is turned off at least after the compensation module is turned on; The duration of the bias adjustment phase is Ws, the time interval between the end of the bias adjustment phase and the activation of the compensation module is Wt3, and the duration of the reset phase is Wr; wherein... Wr≥(Ws+Wt3).

12. The display panel according to claim 11, characterized in that, The overlap between the reset phase and the time period during which the compensation module is activated is Wt4; where, Wr≥(Ws+Wt3+Wt4).

13. The display panel according to claim 12, characterized in that, The time interval between the start of the reset phase and the start of the bias adjustment phase is Wb3; where... Wb3≥0.

14. The display panel according to claim 13, characterized in that, Wb3≠Wt4.

15. The display panel according to claim 13, characterized in that, Wb3≤Wt4.

16. The display panel according to claim 1, characterized in that, The reset module is connected to the gate of the driving transistor; The data writing module is connected to the first electrode of the driving transistor; The bias adjustment module is connected to the first or second terminal of the driving transistor.

17. The display panel according to claim 1, characterized in that, When the compensation module is turned on, during the bias adjustment phase, the bias adjustment module transmits the bias adjustment signal to the gate of the driving transistor. When the compensation module is turned off, during the bias adjustment phase, the bias adjustment module transmits the bias adjustment signal to the first and / or second pole of the driving transistor.

18. The display panel according to claim 1, characterized in that, The bias adjustment phase includes a first bias adjustment phase and a second bias adjustment phase, wherein the first bias adjustment phase is located before the data writing phase, and the second bias adjustment phase is located after the data writing phase; wherein, The compensation module remains active during the first bias adjustment phase and the data writing phase, as well as during the time interval between the first bias adjustment phase and the data writing phase.

19. The display panel according to claim 1, characterized in that, The bias adjustment phase includes a first bias adjustment phase and a second bias adjustment phase, wherein the first bias adjustment phase is located before the data writing phase, and the second bias adjustment phase is located after the data writing phase; wherein, During the first bias adjustment phase and the reset phase, the reset module remains on, and the reset module is turned off at least after the compensation module is turned on.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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