Floating field limiting ring power device based on dielectric positioning and preparation method thereof

Abstract

The present invention discloses a floating field-limiting ring power device based on dielectric positioning and a preparation method thereof, which includes a device main body, a high-K dielectric trench region, and a P-type floating field-limiting ring; the device main body includes an N-type doped semiconductor drift region; the high-K dielectric trench regions are arranged equidistantly at the top center of the semiconductor drift region, and each high-K dielectric trench region includes a groove and a high-K dielectric filled in the groove; an active layer located between the high-K dielectric trench regions forms a semiconductor island region; the semiconductor island region is formed into a P-type floating field-limiting ring through P-type doping, and the junction depth of the P-type floating field-limiting ring is greater than the depth of the high-K dielectric trench region. The groove is a strip-shaped groove, a mesh groove, a rectangular groove, or the like. The P-type floating field-limiting ring of the present invention is positioned based on the dielectric groove, which can reduce process steps such as masking. The high-K dielectric deposited in the groove can effectively modulate the surface electric field and avoid the influence of surface charges on the P-type floating field-limiting ring, thereby improving the breakdown voltage. At the same time, the concentration of the drift region is increased, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and particularly to a floating field limiting ring power device based on dielectric positioning and a preparation method thereof. Background Art

[0002] Power devices are the core devices for power control. To increase the breakdown voltage of power devices, a low drift region concentration is often required, while to reduce the specific on-resistance, a high drift region concentration is needed. Therefore, how to obtain a compromise relationship between the breakdown voltage and the on-resistance is one of the goals and difficulties in the design of power devices.

[0003] The field limiting ring terminal technology is a commonly used junction terminal structure in power devices. By deforming the field limiting ring of the terminal structure, a voltage dividing effect can be achieved, thereby achieving the purpose of increasing the breakdown voltage.

[0004] The structure of the traditional floating field limiting ring is in contact with the field oxide SiO2 and is easily affected by surface charges and interface trap charges. Especially for the field limiting ring structure of a shallow planar junction, the breakdown voltage of the device will decrease due to the influence of the surface electric field, and even the device will fail. Moreover, the breakdown voltage performance of the traditional floating field limiting ring junction terminal structure is very sensitive to the spacing of the floating field limiting ring. The change in the spacing of the field limiting ring caused by the process preparation will cause the position of the floating field limiting ring to deviate from the expected position, and a locally high peak electric field will be generated at the edge, causing the device to break down in advance, thereby affecting the improvement of the breakdown voltage performance and reliability of the device. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a floating field limiting ring power device based on dielectric positioning and a preparation method thereof in view of the above-mentioned deficiencies of the prior art. The floating field limiting ring power device based on dielectric positioning and the preparation method thereof use a high dielectric constant medium to position the P-type floating field limiting ring and serve as the gate field medium, realizing a new structure of the floating field limiting ring power device based on dielectric positioning. This floating field limiting ring power device based on dielectric positioning can not only position the size of the floating field limiting ring through the high dielectric constant medium, but also improve the surface charge effect, effectively modulate the electric field distribution and achieve the purpose of increasing the breakdown voltage. In addition, the high dielectric constant and the P-type field limiting ring can jointly modulate and increase the doping concentration of the drift region, achieving the purpose of reducing the on-resistance of the device.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A floating field limiting ring power device based on dielectric positioning includes a device main body, a high-K dielectric trench region, and a P-type floating field limiting ring.

[0008] The device main body includes an N-type doped semiconductor drift region.

[0009] The high-K dielectric trench regions are arranged at equal intervals at the top center of the semiconductor drift region; the high-K dielectric trench regions include grooves and high-K dielectrics filled in the grooves.

[0010] The active layer located between the high-K dielectric trench regions is formed into a semiconductor island region; the semiconductor island region is formed into a P-type floating field limiting ring through P-type doping, and the junction depth of the P-type floating field limiting ring is greater than the depth of the high-K dielectric trench region.

[0011] The grooves are M strip-shaped grooves arranged at equal intervals along the length direction of the semiconductor drift region, and M-1 semiconductor island regions are formed between the M strip-shaped grooves; wherein, M≥3.

[0012] The grooves are mesh grooves, and the number of mesh holes of the mesh grooves is not less than 6, and the semiconductor island regions are located at the mesh hole positions of the mesh grooves.

[0013] The grooves are distributed rectangular grooves, and the number of rectangular grooves is not less than 6, and the length direction of each rectangular groove is along the width direction of the semiconductor drift region.

[0014] The dielectric constant of the high-K dielectric filled in the grooves is greater than 20.

[0015] The depth of the high-K dielectric trench region is 0.5 to 1 micron; the junction depth of the P-type floating field limiting ring is 0.1 to 1 micron deeper than the depth of the high-K dielectric trench region.

[0016] The device body further includes an active layer and a field dielectric layer arranged on the top of the active layer.

[0017] The semiconductor drift region is located in the active layer; the field dielectric layer is a high-K dielectric with the same dielectric as the high-K dielectric trench region.

[0018] The device body further includes a substrate, a buried layer, a gate metal, a source metal, and a drain metal.

[0019] The substrate, the buried layer, and the active layer are all rectangular and are arranged in sequence from bottom to top.

[0020] The active layer includes a semiconductor well region, a semiconductor drain region, and the semiconductor drift region located between the two.

[0021] The semiconductor well region includes a semiconductor source region and a semiconductor contact region, and the semiconductor contact region is located outside the semiconductor source region.

[0022] The source metal is arranged on the tops of the semiconductor source region and the semiconductor contact region, the gate metal is arranged on the top of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the semiconductor drift region; the drain metal is arranged on the top of the semiconductor drain region.

[0023] A preparation method of a floating field limiting ring power device based on dielectric positioning includes the following steps:

[0024] Step 1: Select a substrate, and sequentially arrange a buried layer and an active layer on top of the substrate.

[0025] Step 2: Etch grooves: Etch equally spaced and equally deep grooves at the top center of the active layer. The raised active layer between the grooves forms a semiconductor island region.

[0026] Step 3: Fill the grooves: Adopt a dielectric deposition process to deposit and fill a high-K dielectric in each groove and planarize it to form a high-K dielectric trench region.

[0027] Step 4: Fabricate a floating field limiting ring: Use ion implantation, with photoresist as a mask, to perform P-type doping on top of each semiconductor island region, and perform rapid thermal annealing to repair the damage, thereby forming a P-type floating field limiting ring.

[0028] Step 5: Fabricate a well region, source and drain regions: Adopt an ion implantation process and perform high-temperature drive-in diffusion, thereby forming a semiconductor well region, a semiconductor contact region, a semiconductor source region, and a semiconductor drain region in the active layer; wherein, the semiconductor well region and the semiconductor drain region are located on both sides of the semiconductor drift region; the semiconductor contact region and the semiconductor source region are located on top of the semiconductor well region, and the semiconductor contact region is located outside the semiconductor source region; during the high-temperature drive-in diffusion process, the high-K dielectric filled in Step 3 can prevent the lateral diffusion of the P-type floating field limiting ring caused by the high-temperature process.

[0029] Step 6: Fabricate a field dielectric layer: Adopt a dielectric deposition process to deposit another layer of high-K dielectric homogeneous with the high-K dielectric in Step 3 on top of the active layer as the field dielectric layer and planarize it.

[0030] Step 7: Etch source and drain contact holes: Etch source and drain contact holes in the field dielectric layer. The source and drain contact holes include a source contact hole and a drain contact hole; wherein, the source contact hole is in contact with the semiconductor contact region and the semiconductor source region, and the drain contact hole is in contact with the semiconductor drain region.

[0031] Step 8: Prepare metal electrodes: Deposit source electrode metal in the source contact hole and deposit drain electrode metal in the drain contact hole; deposit gate metal on the top surface of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the semiconductor drift region; wherein, the field dielectric directly below the gate metal forms a gate dielectric layer.

[0032] The grooves in Step 2 are strip-shaped grooves, mesh-shaped grooves or rectangular grooves.

[0033] The present invention has the following beneficial effects:

[0034] 1. By forming a high-K dielectric trench region, the present invention can arbitrarily control the position of the P-type floating field limiting ring, avoiding the position offset of the P-type floating field limiting ring during the process; at the same time, the modulation effect of the high-dielectric constant dielectric can form a specific surface electric field distribution and reduce the adverse effect of the surface charge effect on the field limiting ring, thereby improving the breakdown voltage of the device.

[0035] 2. The high dielectric constant of the high-K dielectric trench and the P-type floating field limiting ring can jointly modulate and increase the doping concentration of the semiconductor drift region to achieve the purpose of reducing the on-resistance of the device.

[0036] 3. The process preparation of the present invention only requires etching and deposition processes to form the positioning dielectric area, and the gate dielectric also uses a homogeneous dielectric, so the process feasibility is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of the structure of a floating field limiting ring power device based on dielectric positioning in Example 1 of the present invention.

[0038] Figure 2 This is a schematic diagram of the structure completed in step 1 of Example 1 of the present invention.

[0039] Figure 3 This is a schematic diagram of the structure after the groove etching is completed in step 2 of Example 1 of the present invention.

[0040] Figure 4 This is a schematic structural diagram of the step 3 of depositing a high-K dielectric in the groove in Example 1 of the present invention.

[0041] Figure 5 This is a schematic diagram of the structure completed in step 5 of Example 1 of the present invention.

[0042] Figure 6 This is a schematic diagram of the structure after the field dielectric layer is manufactured in step 6 of Example 1 of the present invention.

[0043] Figure 7 1 is a comparison chart of the performance of embodiment 1 of the present invention and traditional power devices.

[0044] Figure 8 This is a schematic diagram of the structure after the groove etching is completed in step 2 of Example 2 of the present invention.

[0045] Figure 9 This is a schematic structural diagram of the step 3 of depositing a high-K dielectric in the groove in Example 2 of the present invention.

[0046] Figure 10 This is a schematic diagram of the structure completed in step 5 of Example 2 of the present invention.

[0047] Figure 11 This is a schematic diagram of the structure after the groove etching is completed in step 2 of Example 3 of the present invention.

[0048] Figure 12 This is a schematic structural diagram of the step 3 of Example 3 of the present invention after depositing a high-K dielectric in the groove.

[0049] Figure 13This is the structural schematic diagram completed in step 5 of Embodiment 3 of the present invention.

[0050] Among them are:

[0051] 1. Substrate; 2. Buried layer; 3. Active layer;

[0052] 4. Groove; 4-2. Mesh groove; 4-3. Rectangular groove;

[0053] 5. Semiconductor island region; 5-2. Rectangular semiconductor island region; 5-3. Mesh semiconductor island region;

[0054] 6. High-K dielectric trench region;

[0055] 7. P-type floating field limiting ring; 7-2. Rectangular P-type floating field limiting ring; 7-3. Mesh P-type floating field limiting ring;

[0056] 8. Semiconductor well region; 9. Semiconductor drift region; 10. Semiconductor contact region. 11. Semiconductor source region; 12. Semiconductor drain region; 13. Field dielectric layer; 14. Source metal; 15. Gate metal; 16. Drain metal; 17. Gate dielectric layer. Specific implementation mode

[0057] The present invention will be further described in detail below with reference to the drawings and specific preferred embodiments.

[0058] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "left side", "right side", "upper part", "lower part", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. "First", "second", etc. do not represent the importance of components, so it cannot be understood as a limitation to the present invention. The specific dimensions adopted in this embodiment are only for illustrating the technical solution and do not limit the protection scope of the present invention.

[0059] Embodiment 1

[0060] As Figure 1 and Figure 5 shown, a floating field limiting ring power device based on dielectric positioning includes a device main body, a high-K dielectric trench region 6 and a P-type floating field limiting ring 7.

[0061] The device main body includes a substrate 1, a buried layer 2, an active layer 3, a field dielectric layer 13, a source metal 14, a gate metal 15 and a drain metal 16.

[0062] The substrate, the buried layer and the active layer are all rectangular and are arranged in sequence from bottom to top.

[0063] The active layer 3 is preferably one of silicon, silicon carbide, gallium nitride, and gallium oxide, and the thickness of the active layer is generally greater than 1 micron.

[0064] The active layer includes a semiconductor well region 8, a semiconductor drain region 12, and a semiconductor drift region 9 located therebetween.

[0065] The semiconductor well region includes a semiconductor contact region 10 and a semiconductor source region 11, wherein the semiconductor contact region 10 is located outside the semiconductor source region 11.

[0066] The field dielectric layer is disposed on top of the active layer and is a high-K dielectric with a dielectric constant greater than 20.

[0067] The source metal is disposed on top of the semiconductor source region and the semiconductor contact region, and the cross-sectional shape is preferably T-shaped.

[0068] The gate metal is disposed on top of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the semiconductor drift region.

[0069] The drain metal is disposed on top of the semiconductor drain region, and the cross-sectional shape is preferably inverted L-shaped, which can reduce the peak electric field at the junction.

[0070] The above-mentioned semiconductor drift region is a drift region with low-concentration N-type doping, and the concentration is generally lower than 1×10 17 cm -3 .

[0071] The high-K dielectric trench regions are equidistantly disposed at the top center of the semiconductor drift region. The high-K dielectric trench region includes a groove and a high-K dielectric filled in the groove. Among them, the high-K dielectric filled in each groove region is preferably the same material as the field dielectric layer.

[0072] The grooves are preferably M strip-shaped grooves equidistantly disposed along the length direction of the semiconductor drift region. M-1 semiconductor island regions are formed between the M strip-shaped grooves; among them, M≥3, and in this Embodiment 1, M is preferably 4.

[0073] The active layer located between the high-K dielectric trench regions is formed into a semiconductor island region 5; the semiconductor island region is formed into a P-type floating field limiting ring by P-type doping, and the junction depth of the P-type floating field limiting ring is greater than the depth of the high-K dielectric trench region. In this embodiment, the depth of the high-K dielectric trench region is preferably 0.5 to 1 micron; the junction depth of the P-type floating field limiting ring is preferably 0.1 to 1 micron deeper than the depth of the high-K dielectric trench region.

[0074] The position of the P-type floating field limiting ring 7 is determined by the position of the high-K dielectric trench region 6, and the size of the P-type floating field limiting ring 7 is determined by the spacing of the high-K dielectric trench region 6.

[0075] A preparation method of a floating field limiting ring power device based on dielectric positioning includes the following steps:

[0076] Step 1: Select a substrate, and sequentially arrange a buried layer and an active layer on the top of the substrate. After fabrication, it is as shown in Figure 2 the figure.

[0077] Step 2: Etch grooves: Preferably adopt a dry etching process to etch equally spaced and equally deep grooves 4 at the center of the top of the active layer. The etching depth of the grooves 4 is preferably 1 / 5 - 1 / 2 of the thickness of the active layer, and the interval between each groove is controlled to be the same. The raised active layer between the grooves forms a semiconductor island region 5. Specifically, it is as shown in Figure 3 the figure.

[0078] In this embodiment, the grooves are preferably strip-shaped grooves, preferably 4 in number, and the semiconductor island regions are preferably 3 in number.

[0079] Step 3: Fill the grooves: Adopt a dielectric deposition process (such as physical vapor deposition or chemical vapor deposition) to deposit and fill a high-K dielectric in each groove and planarize it to form a high-K dielectric trench region as shown in Figure 4 the figure.

[0080] Step 4: Fabricate a floating field limiting ring: Adopt ion implantation, using photoresist as a mask, to perform P-type doping on the top of each semiconductor island region, and perform rapid annealing to repair the damage, thereby forming a P-type floating field limiting ring.

[0081] Step 5: Fabricate a well region, source and drain regions: Adopt an ion implantation process and perform high-temperature drive-in diffusion, thereby forming a semiconductor well region, a semiconductor contact region, a semiconductor source region and a semiconductor drain region in the active layer. Specifically, it is as shown in Figure 5 the figure. Among them, the semiconductor well region and the semiconductor drain region are located on both sides of the semiconductor drift region; the semiconductor contact region and the semiconductor source region are located on the top of the semiconductor well region, and the semiconductor contact region is located outside the semiconductor source region; during the high-temperature drive-in diffusion process, the high-K dielectric filled in Step 3 can prevent the lateral diffusion of the P-type floating field limiting ring caused by the high-temperature process.

[0082] Step 6: Fabricate a field dielectric layer: Adopt a dielectric deposition process to deposit another layer of high-K dielectric homogeneous with the high-K dielectric in Step 3 on the top of the active layer as the field dielectric layer and planarize it. Specifically, it is as shown in Figure 6 the figure.

[0083] Step 7: Etch source and drain contact holes: Etch source and drain contact holes in the field dielectric layer. The source and drain contact holes include a source contact hole and a drain contact hole; among them, the source contact hole is in contact with the semiconductor contact region and the semiconductor source region, and the drain contact hole is in contact with the semiconductor drain region.

[0084] Step 8: Prepare metal electrodes: Deposit source electrode metal in the source contact hole, deposit drain electrode metal in the drain contact hole; deposit gate metal on the top surface of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the semiconductor drift region. Specifically, it is as shown inFigure 1 As shown; among them, the field dielectric directly under the gate metal is formed into a gate dielectric layer.

[0085] In this Embodiment 1, the high-K dielectric selected for re-deposition is used as the gate dielectric layer and the field dielectric layer to modulate the surface electric field to solve the adverse effect of the surface charge effect on the field limiting ring. The high-K dielectric as the gate electrode can reduce the device threshold voltage.

[0086] Figure 7 The following gives a comparison chart of the breakdown voltage (BV), specific on-resistance (Ron,sp), and figure of merit (FOM) of the floating field limiting ring power device (new device) based on strip-shaped high-k dielectric positioning, the traditional power device without a field limiting ring (traditional device), and the power device with a field limiting ring structure (conventional field limiting ring device) provided by the present invention in Embodiment 1 as the drift region doping concentration changes. From Figure 7 It can be seen that compared with the traditional device and the conventional field limiting ring device, the breakdown voltage of the new device is significantly improved, and the doping concentration of the drift region corresponding to the maximum breakdown voltage increases significantly, so the corresponding on-resistance is significantly reduced. Correspondingly, the FOM value of the new device is significantly improved, indicating that the floating field limiting ring power device with high-k dielectric positioning provided by the present invention has better device performance.

[0087] Embodiment 2

[0088] Embodiment 2 is basically the same as Embodiment 1, the difference being that: the groove shapes are different, and the groove is a mesh groove 4-2 as Figure 8 shown. The active layer protruding in each mesh hole is formed into a rectangular semiconductor island region 5-2. Therefore, after depositing the high-K dielectric in the groove and planarizing in Step 3, it is formed into a rectangular P-type floating field limiting ring 7-2 as Figure 9 shown; the structure after the well region and the source / drain regions are fabricated in Step 5 is as Figure 10 shown.

[0089] Embodiment 3

[0090] Embodiment 3 is basically the same as Embodiment 1, the difference being that: the groove shapes are different, and the groove is a distributed rectangular groove 4-3 as Figure 11 shown. The active layer protruding in each mesh hole is formed into a mesh semiconductor island region 5-3. Therefore, after depositing the high-K dielectric in the groove and planarizing in Step 3, it is formed into a mesh P-type floating field limiting ring 7-3 as Figure 12 shown; the structure after the well region and the source / drain regions are fabricated in Step 5 is as Figure 13 shown.

[0091] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A preparation method of a floating field limiting ring power device based on dielectric positioning, characterized in that: It includes the following steps: Step 1: Select a substrate, and sequentially arrange a buried layer and an active layer on the top of the substrate; Step 2: Etch grooves: Etch equally spaced and equally deep grooves at the top center of the active layer. The raised active layer between the grooves forms a semiconductor island region; Step 3: Fill the grooves: Adopt a dielectric deposition process to deposit and fill high-K dielectric in each groove and planarize it to form a high-K dielectric trench region; Step 4: Fabricate a floating field limiting ring: Adopt ion implantation, using photoresist as a mask, perform P-type doping on the top of each semiconductor island region, and perform rapid thermal annealing to repair the damage, thereby forming a P-type floating field limiting ring; The junction depth of the P-type floating field limiting ring is greater than the depth of the high-K dielectric trench region; Step 5: Fabricate a well region, source and drain regions: Adopt an ion implantation process and perform high-temperature drive-in diffusion, thereby forming a semiconductor well region, a semiconductor contact region, a semiconductor source region and a semiconductor drain region in the active layer; wherein, the semiconductor well region and the semiconductor drain region are located on both sides of the semiconductor drift region; the semiconductor contact region and the semiconductor source region are located on the top of the semiconductor well region, and the semiconductor contact region is located outside the semiconductor source region; during the high-temperature drive-in diffusion process, the high-K dielectric filled in Step 3 can prevent the lateral diffusion of the P-type floating field limiting ring caused by the high-temperature process; Step 6: Fabricate a field dielectric layer: Adopt a dielectric deposition process to deposit another layer of high-K dielectric homogeneous with the high-K dielectric in Step 3 on the top of the active layer as the field dielectric layer and planarize it; Step 7: Etch source and drain contact holes: Etch source and drain contact holes in the field dielectric layer. The source and drain contact holes include a source contact hole and a drain contact hole; wherein, the source contact hole is in contact with the semiconductor contact region and the semiconductor source region, and the drain contact hole is in contact with the semiconductor drain region; Step 8: Prepare metal electrodes: Deposit source electrode metal in the source contact hole and deposit drain electrode metal in the drain contact hole; deposit gate metal on the top surface of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the semiconductor drift region; wherein, the field dielectric directly below the gate metal forms a gate dielectric layer.

2. A floating field-limiting ring power device based on dielectric positioning, based on the manufacturing method described in claim 1, characterized in that: It includes a device body, a high-K dielectric trench region and a P-type floating field limiting ring; The device body includes an N-type doped semiconductor drift region; The high-K dielectric trench regions are equally spaced and arranged at the top center of the semiconductor drift region; the high-K dielectric trench region includes a groove and the high-K dielectric filled in the groove; The groove is a strip groove, a mesh groove or a rectangular groove; The active layer located between the high-K dielectric trench regions forms a semiconductor island region; the semiconductor island region forms a P-type floating field limiting ring through P-type doping, and the junction depth of the P-type floating field limiting ring is greater than the depth of the high-K dielectric trench region; The high-K dielectric trench region can arbitrarily control the position of the P-type floating field limiting ring and avoid the position offset of the P-type floating field limiting ring during the process; at the same time, the modulation effect of the high dielectric constant dielectric can reduce the adverse effect of the surface charge effect on the field limiting ring, thereby improving the breakdown voltage of the device; The high dielectric constant of the high-K dielectric trench region and the P-type floating field limiting ring can jointly modulate and increase the doping concentration of the semiconductor drift region to 13×10 15 cm -3 .

3. The floating field limiting ring power device based on medium positioning according to claim 2, wherein: The groove is M strip grooves equally spaced along the length direction of the semiconductor drift region, and M-1 semiconductor island regions are formed between the M strip grooves; wherein, M≥3.

4. The floating field limiting ring power device based on medium positioning according to claim 2, characterized in that: The groove is a mesh groove, and the number of mesh holes of the mesh groove is not less than 6, and the semiconductor island region is located at the mesh hole position of the mesh groove.

5. The floating field limiting ring power device based on dielectric positioning according to claim 2, wherein: The grooves are distributed rectangular grooves, and the number of rectangular grooves is not less than 6. The length direction of each rectangular groove is along the width direction of the semiconductor drift region.

6. The floating field limiting ring power device based on dielectric positioning according to claim 2, wherein: The dielectric constant of the high-K dielectric filled in the grooves is greater than 20.

7. The floating field limiting ring power device based on dielectric positioning according to claim 2, characterized in that: The depth of the high-K dielectric trench region is 0.5 - 1 micron; the junction depth of the P-type floating field limiting ring is 0.1 - 1 micron deeper than the depth of the high-K dielectric trench region.

8. The floating field limiting ring power device based on medium positioning according to claim 2, wherein: The device body further includes an active layer and a field dielectric layer disposed on top of the active layer; The semiconductor drift region is located within the active layer; the field dielectric layer is a high-K dielectric with the same dielectric as the high-K dielectric trench region.

9. The floating field limiting ring power device based on medium positioning according to claim 8, characterized in that: The device body further includes a substrate, a buried layer, gate metal, source metal, and drain metal; The substrate, the buried layer, and the active layer are all rectangular and are arranged in sequence from bottom to top; The active layer includes a semiconductor well region, a semiconductor drain region, and the semiconductor drift region located between the two; The semiconductor well region includes a semiconductor source region and a semiconductor contact region, and the semiconductor contact region is located outside the semiconductor source region; The source metal is disposed on top of the semiconductor source region and the semiconductor contact region, and the gate metal is disposed on top of the field dielectric layer directly above the semiconductor well region between the semiconductor source region and the semiconductor drift region; The drain metal is disposed on top of the semiconductor drain region.

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