An on-chip integrated plasmonic photodetector and a preparation method and application thereof

Abstract

The application discloses an on-chip integrated plasmonic photodetector and a preparation method and application thereof, and belongs to the technical field of optical elements.The photodetector comprises a semiconductor structure, an electrode and a plasmonic waveguide; the semiconductor structure comprises silicon, silicon dioxide and a semiconductor photoelectric material from bottom to top, is obtained by etching part of the top silicon of silicon-on-insulator or is obtained by depositing or transferring the required semiconductor photoelectric material after etching the top silicon of silicon-on-insulator completely; the electrode is arranged at two ends of the semiconductor photoelectric material and is in contact with the semiconductor photoelectric material; and the plasmonic waveguide is arranged at the side of the semiconductor photoelectric material, and a gap exists between the end of the plasmonic waveguide and the semiconductor photoelectric material.The application realizes efficient near-field coupling between the plasmonic waveguide and the silicon nanostructure by optimizing the structure parameters, and finally realizes on-chip integrated direct detection of the electrical signal of the plasmon, and has good controllability in processing and preparation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of optical elements, in particular to an on-chip integrated plasmonic photodetector and a preparation method and application thereof. BACKGROUND

[0002] The basis of integrated optoelectronic chips is the on-chip integrated optical information device. Surface plasmon is a localized electromagnetic field propagating at the interface between metal and dielectric. Plasmonic waveguide can break through the optical diffraction limit of dielectric waveguide to confine electromagnetic field energy, and thus is an important component of small-sized on-chip integrated optical information device. Correspondingly, in order to realize the detection of propagating plasmons in plasmonic waveguides and further realize the on-chip integrated plasmonic photodetector for optical-electric signal conversion, it is an urgent problem to be solved.

[0003] The detection methods for propagating plasmons include optical microscope imaging of scattered light at the end of plasmonic waveguide, near-field optical scanning microscope near-field imaging, near-field imaging of quantum dots coated on the surface of plasmonic waveguide by fluorescence, and detection of propagating plasmons by combining plasmonic waveguide with graphene two-dimensional material and germanium semiconductor nanowire. The optical microscope imaging of scattered light at the end of plasmonic waveguide requires a uniform dielectric constant background around the plasmonic waveguide, so the refractive index of oil mirror matching glass and quartz substrate is generally used. The near-field optical scanning microscope realizes detection by converting the near-field light of the plasmonic waveguide into scattered light by using a probe. The near-field imaging of quantum dots coated on the surface of plasmonic waveguide by fluorescence forms a quantum dot coating layer on the surface of the waveguide structure. Therefore, the optical microscope imaging, near-field optical scanning microscope imaging and quantum dot fluorescence imaging are only used as characterization methods for studying the propagation loss of plasmons, and cannot be used for on-chip integrated detection of propagating plasmon signals. Graphene and other two-dimensional materials and germanium semiconductor nanowires can be used as photoelectric conversion materials for propagating plasmons, but these nanomaterials are derived from chemical synthesis, and the published literature mainly uses random combinations of gold and silver nanowires with the above materials to select suitable devices for research, and there are few controllable plasmonic on-chip detection schemes.

[0004] Therefore, an easy-to-process, high-efficiency, integrated small-sized on-chip plasmonic detector has important applications in the field of integrated optoelectronic technology based on plasmons. SUMMARY

[0005] In order to solve the urgent need for efficient plasmon photodetectors in plasmonic integrated optoelectronic technology, on the basis of the previous work (Chinese patent CN112596153A, an on-chip subwavelength bound waveguide and its preparation method), by optimizing the structure design, the efficient coupling of propagating plasmons and photodetection are successfully realized. In addition to improving the plasmon detection performance indicators and the miniaturization of device size, the processing method of the device is also compatible with the current integrated optical microfabrication process.

[0006] In order to achieve the above purpose, the application provides an on-chip integrated plasmonic photodetector, which comprises a semiconductor structure, an electrode and a plasmonic waveguide.

[0007] The semiconductor structure comprises silicon, silicon dioxide and semiconductor photoelectric material from bottom to top, which is obtained by etching part of the top silicon on silicon-on-insulator or by etching the top silicon on silicon-on-insulator and then depositing the corresponding semiconductor photoelectric material. It should be noted that the substrate used in the application is silicon-on-insulator, which comprises bottom silicon, middle silicon dioxide and top silicon from bottom to top. Therefore, the required size of the silicon strip can be obtained by etching the top silicon through electron beam exposure, ultraviolet lithography or chemical reagent etching process to form the required semiconductor structure. When other semiconductor photoelectric materials other than silicon are used, the top silicon is etched completely, and then the semiconductor photoelectric material is deposited or transferred to the middle silicon dioxide to form the required semiconductor structure.

[0008] The electrode is arranged at both ends of the semiconductor photoelectric material and in contact with the semiconductor photoelectric material.

[0009] The plasmonic waveguide is arranged at the side of the semiconductor photoelectric material, and the end of the plasmonic waveguide has a gap with the semiconductor photoelectric material.

[0010] The top silicon of the silicon-on-insulator is P-type or N-type, and the doping concentration is 10 12 ~10 20 / cm 3 , and the top silicon is a high refractive index medium layer.

[0011] Further, the thickness of the semiconductor photoelectric material is 0.1-500nm, and the width is 0.01-10um. The semiconductor photoelectric material is a conventional material, including silicon, germanium, gallium arsenide, cadmium sulfide and other semiconductor materials.

[0012] Further, the thickness of the plasmonic waveguide is 50-500nm, and the width is 50nm-10um.

[0013] Further, the material, structure and size of the semiconductor optoelectronic material need to be designed and optimized to realize efficient near-field coupling with the propagating plasmons, generate electron-hole pairs, and effectively separate the electrons and holes. The thickness of the plasmonic waveguide is less than the thickness of the semiconductor optoelectronic material, and the coupling effect is best when the thickness is about half of the thickness of the semiconductor optoelectronic material.

[0014] The material of the plasmonic waveguide includes metal, such as gold, silver, aluminum, etc. The plasmonic waveguide is a nanostructure such as a gold, silver, or aluminum nanowire or nanobelt, and a small gap is formed between the end of the plasmonic waveguide and the semiconductor optoelectronic material.

[0015] The electrode is composed of metal or other conductive material. As an embodiment, the electrode is composed of two layers of metal, the upper layer of metal includes one of gold, silver, and copper, and the lower layer of metal includes one of chromium, titanium, nickel, and indium, and the lower layer of metal is used to enhance the adhesion of the upper layer of metal to the substrate.

[0016] Further, the gap is 0.1-50 nm.

[0017] The application also provides a preparation method of the above-mentioned on-chip integrated plasmonic photodetector, which comprises,

[0018] After etching part of the top silicon of the silicon-on-insulator or completely etching the top silicon of the silicon-on-insulator, the semiconductor optoelectronic material is deposited to obtain a semiconductor structure, which comprises, from bottom to top, silicon, silicon dioxide, and the semiconductor optoelectronic material.

[0019] The electrode material is deposited at both ends of the semiconductor optoelectronic material to form electrodes in contact with the semiconductor optoelectronic material.

[0020] The plasmonic waveguide is prepared on the side of the semiconductor optoelectronic material by means of micro-nano processing, and a gap exists between the end of the plasmonic waveguide and the optoelectronic material.

[0021] The application also provides the application of the above-mentioned on-chip integrated plasmonic photodetector in photodetection.

[0022] Compared with the prior art, the application has the following beneficial effects:

[0023] The application realizes efficient near-field coupling between the plasmonic waveguide and the semiconductor optoelectronic material by optimizing the structure parameters, and finally realizes on-chip integrated direct detection of plasmonic electrical signals, and has good controllability in processing and preparation. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0025] Figure 1 A flow chart of a preparation method of the on-chip integrated plasmonic photodetector of the embodiment 1 of the present application is shown.

[0026] Figure 2 A structural schematic diagram of a silicon-on-insulator and a semiconductor structure in the embodiment 1 of the present application is shown; wherein, Figure 2 (a) is a silicon-on-insulator; Figure 2 (b) is a silicon strip structure prepared based on the silicon-on-insulator;

[0027] Figure 3 A schematic diagram of a semiconductor structure of the embodiments 4-6 of the present application is shown.

[0028] Figure 4 A scanning electron microscope image of the on-chip integrated plasmonic photodetector prepared in the embodiments 1 and 2 of the present application is shown; wherein, Figure 4 (a) is the embodiment 1; Figure 4 (b) is the embodiment 2;

[0029] Figure 5 An optical microscopic imaging of the on-chip integrated plasmonic photodetector prepared in the embodiments 1 and 2 of the present application is shown; wherein, Figure 5 (a) is the embodiment 1; Figure 5 (b) is the embodiment 2;

[0030] Figure 6 Detailed comparison results of the product plasmon excitation prepared in the embodiments 1 and 3 of the present application are shown.

[0031] Fig. 7(a) is a current response result under different polarization excitation different intensity plasmons; Fig. 7(b) is a photocurrent response under on / off plasmon signals; Fig. 7(c) is a response dependence diagram of plasmons and photocurrent formed by different wavelength lasers; Fig. 7(d) is a response dependence diagram of plasmons and photocurrent formed by different power lasers.

[0032] Figure 8 A schematic diagram of the plasmon detection principle of the embodiments 1-3 of the present application is shown. DETAILED DESCRIPTION

[0033] The endpoints and any values ​​of the ranges disclosed in this invention are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this invention.

[0034] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Example 1

[0036] like Figure 1 As shown, a method for fabricating an on-chip integrated plasmonic photodetector includes the following steps:

[0037] Step 1: Fabrication of the semiconductor structure: Silicon-on-insulator (SOI) is cleaned and dried to serve as the substrate, such as... Figure 2 As shown in (a), the silicon-on-insulator structure consists of a bottom silicon layer, a middle silicon dioxide layer, and a top silicon layer from bottom to top. The bottom silicon layer has a thickness of 500 μm, the middle silicon dioxide layer has a thickness of 3 μm, and the top silicon layer has a thickness of 220 nm and a boron doping concentration of 10. 12 / cm 3 P-type silicon; a 450 nm electron beam photoresist PMMA is spin-coated onto the top silicon layer, followed by electron beam exposure and development, and then reactive ion etching is used to remove part of the top silicon layer to obtain the semiconductor structure, such as... Figure 2 As shown in (b), the semiconductor structure includes, from bottom to top, a bottom silicon layer, a middle silicon dioxide layer, and a silicon strip. The silicon strip is T-shaped, with a thickness of 220 nm, a width of 3 μm, and a length of 12 μm in the horizontal portion, and a thickness of 220 nm, a width of 3 μm, and a length of 6.5 μm in the vertical portion.

[0038] Step 2, Electrode fabrication: Electrode patterns with a length of 40 μm and a width of 4 μm are obtained at both ends of the silicon strip using electron beam lithography. Then, indium with a thickness of 20 nm and gold with a thickness of 150 nm are deposited sequentially using thermal evaporation deposition. After immersion in acetone to remove the adhesive, indium / gold electrodes in contact with the transverse portion of the silicon strip are obtained. Preferably, in order to facilitate the connection of electrical test probes to the constructed photodetector, an additional indium / gold thin film is deposited on the electrode end. Its structure is a cube electrode with a size of more than 50 μm to facilitate probe contact or lead bonding.

[0039] Step 3, preparation of plasmonic waveguide: the longitudinal part of the silicon strip in step 1 is thinned to 50 nm by electron beam exposure over-etching and plasma etching process, at this time the longitudinal part and the transverse part of the silicon strip form a "step" due to the difference in thickness, and then the plasmonic waveguide pattern is prepared at the side edge of the transverse part of the silicon strip by electron beam exposure over-etching process, a thin silicon layer is reserved below the plasmonic waveguide, which can form a hybrid plasmonic waveguide to enhance the transmission performance of the waveguide. The plasmonic waveguide is obtained by thermal evaporation of gold with a thickness of 110 nm, a width of 3 μm and a length of 6.5 μm.

[0040] The on-chip integrated plasmonic photoelectric detector is prepared through steps 1-3.

[0041] Embodiment 2

[0042] A preparation method of an on-chip integrated plasmonic photoelectric detector, the steps are as follows:

[0043] Step 1, the preparation method is basically the same as that of embodiment 1, the difference is that the thickness of the transverse part of the silicon strip is 220 nm, the width is 600 nm, and the length is 12 μm, the thickness of the longitudinal part is 220 nm, the width is 600 nm, and the length is 6.5 μm;

[0044] Step 2, preparation of electrode: electrode patterns are obtained at both ends of the silicon strip by electron beam exposure technology, the length is 40 μm, and the width is 4 μm, then indium with a thickness of 20 nm and gold with a thickness of 150 nm are deposited in turn by thermal evaporation film plating technology, and after acetone soaking and degumming, the indium / gold electrode in contact with the silicon strip is obtained;

[0045] Step 3, preparation of plasmonic waveguide: the plasmonic waveguide pattern is prepared at the side edge of the transverse part of the silicon strip by electron beam exposure over-etching process, and the plasmonic waveguide is obtained by thermal evaporation of gold with a thickness of 110 nm, a width of 280 nm and a length of 6 μm.

[0046] The on-chip integrated plasmonic photoelectric detector is prepared through steps 1-3.

[0047] Embodiment 3

[0048] A preparation method of an on-chip integrated plasmonic photoelectric detector, which is basically the same as that of embodiment 1, the only difference is that the thickness of the silicon strip is 110 nm.

[0049] Embodiments 4-6

[0050] The same as embodiment 2, the only difference is that in the preparation of the semiconductor structure in step 1, the top layer of silicon on the insulator is completely etched off, and then germanium, gallium arsenide and cadmium sulfide with the same structure as the silicon strip are deposited or transferred on the surface of the middle layer of silicon dioxide, respectively, to formFigure 3 The semiconductor structure shown.

[0051] Test Example

[0052] The topography of the on-chip integrated plasmonic photodetectors prepared in Example 1 and Example 2 was observed using a scanning electron microscope, and the results are shown in Figure 4 (a) and Figure 4 (b), respectively.

[0053] The on-chip integrated plasmonic photodetectors prepared in Example 1, Example 2 and Example 3 were placed on a photodetection platform, the electrodes were connected to a source table, a bias was applied across the electrodes, and a laser with a wavelength of 710 nm was used to excite plasmons at the incident end of the plasmonic waveguide through a 50x objective lens. The on-chip integrated plasmonic photodetectors prepared in Example 1 and Example 2 could be seen on the microscope CCD to have a small amount of scattered light spots at the other end of the silicon strip after the plasmons were coupled into the silicon nanomaterial, and the results are shown in Figure 5 (a) and Figure 5 (b), respectively. Figure 6 Detailed comparative results of the products prepared in Example 1 (right) and Example 3 (left) are shown to have excited plasmons, wherein the lower inset in the figure represents the relative thickness of the plasmonic waveguide and the silicon strip. The results show that when the thickness of the silicon strip and the thickness of the plasmonic waveguide are comparable (110 nm), there is a clear light spot at the junction of the plasmonic waveguide and the silicon strip, which indicates that most of the energy is scattered before entering the silicon strip. When the thickness of the silicon strip is about twice the thickness of the plasmonic waveguide (220 nm), the light spot on the other side of the silicon strip is relatively bright, which indicates that most of the energy is in-coupled into the silicon strip and scattered out at the other end. More plasmonic energy is in-coupled into the silicon strip, which improves the absorption efficiency of the silicon and in turn improves the detection efficiency.

[0054] The electrodes of the on-chip integrated plasmonic photodetector prepared in Example 2 are connected to electrical test probes, and a bias voltage of 20 mV is applied. The current response of the silicon strip under different polarized excitation of different intensity plasmons with a laser of wavelength 685 nm and power 0.36 μW is shown in Figure 7(a); it can be seen that the current of the silicon strip exhibits different photocurrent responses to polarized light with different polarization angles, so that linearly polarized light with different polarization angles can be identified. The photocurrent response under the on / off plasmon signal of a laser of wavelength 685 nm and power 0.36 μW is shown in Figure 7(b); it can be seen that the on / off ratio of the photocurrent can reach 3.5, and the responsivity is 0.14 mA / W. The plasmon formation and photocurrent response dependence with different wavelengths (wavelength range 700-800 nm) of a laser with power 0.36 μW is shown in Figure 7(c); it can be seen that the on-chip integrated plasmonic photodetector prepared can detect plasmons of different wavelengths, and exhibits typical Fabry-Perot cavity interference behavior. The plasmon formation and photocurrent response dependence with a laser of wavelength 685 nm and different powers (0.15, 0.30, 0.45, 0.60 μW) is shown in Figure 7(d); it can be seen that the on-chip integrated plasmonic photodetector prepared has good linear response to different powers of laser. Figure 8 The schematic diagram of the principle of the plasmonic photodetector is shown; the plasmons excited by the laser are transmitted along the plasmon waveguide, and are absorbed by the silicon strip near the field on one side of the silicon strip. The conductivity of the silicon strip increases, so that under an applied bias voltage, the photocurrent changes.

[0055] Finally, it should be noted that: the above only for the preferred embodiments of the present application, and not for limiting the present application, although the foregoing detailed description of the present application is made with reference to the foregoing embodiments, for those skilled in the art, it still can be modified to the technical solutions recorded in the foregoing embodiments, or equivalent replacement of some of the technical features, within the spirit and principles of the present application, any modification, equivalent replacement, improvement, etc. made, should be included in the scope of protection of the present application.

Claims

1. An on-chip integrated plasmonic photodetector, characterized in that, Including semiconductor structures, electrodes, and plasmonic waveguides; The semiconductor structure, from bottom to top, includes silicon, silicon dioxide, and semiconductor optoelectronic materials. It is obtained by etching part of the top silicon layer on silicon-on-insulator or by depositing or transferring the required semiconductor optoelectronic materials after completely etching the top silicon layer on silicon-on-insulator. The electrodes are disposed at both ends of the semiconductor optoelectronic material and are in contact with the semiconductor optoelectronic material; The plasmonic waveguide is disposed on the side of the semiconductor optoelectronic material, and there is a gap between the end of the plasmonic waveguide and the semiconductor optoelectronic material.

2. The on-chip integrated plasmonic photodetector according to claim 1, characterized in that, The semiconductor optoelectronic material has a thickness of 0.1~500nm and a width of 0.01~10μm.

3. The on-chip integrated plasmonic photodetector according to claim 1, characterized in that, The thickness of the plasmonic waveguide is 50~500nm and the width is 50nm~10μm; The material of the plasmonic waveguide includes metals.

4. The on-chip integrated plasmonic photodetector according to claim 1, characterized in that, The thickness of the plasmonic waveguide is less than the thickness of the semiconductor optoelectronic material.

5. The on-chip integrated plasmonic photodetector according to claim 1, characterized in that, The electrode is composed of metal or other conductive materials.

6. The on-chip integrated plasmonic photodetector according to claim 1, characterized in that, The gap is 0.1~50nm.

7. The on-chip integrated plasmonic photodetector according to any one of claims 1 to 6, characterized in that, The top silicon layer of the silicon-on-insulator is P-type or N-type, with a doping concentration of 10⁻⁶. 12 ~10 20 / cm 3 .

8. A method for fabricating an on-chip integrated plasmonic photodetector, characterized in that, include, A semiconductor structure is obtained by etching part or all of the top silicon layer of silicon on insulator and then depositing or transferring the desired semiconductor optoelectronic material. The semiconductor structure comprises silicon, silicon dioxide and semiconductor optoelectronic material from bottom to top. Electrode material is deposited at both ends of the semiconductor optoelectronic material to form electrodes in contact with the semiconductor optoelectronic material; A plasmonic waveguide is fabricated on the side of the semiconductor optoelectronic material using micro-nano fabrication techniques, with a gap between the plasmonic waveguide end and the optoelectronic material.

9. The application of the on-chip integrated plasmonic photodetector according to any one of claims 1 to 7 in photoelectric detection.

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