Vertical cavity surface emitting laser chip and method for manufacturing the same

Abstract

The application discloses a vertical cavity surface emitting laser chip and a preparation method thereof. The vertical cavity surface emitting laser chip comprises a substrate, an epitaxial column, an annular groove, a filling layer, a passivation layer, an oxidation hole and an electrode. The epitaxial column is arranged on the substrate. The annular groove is arranged above the epitaxial column to form an "island" waveguide area surrounded by the annular groove. The filling layer is filled in the annular groove. The electrode comprises a P-surface electrode, an N-surface electrode and a connecting electrode. The P-surface electrode is arranged above the "island" waveguide area and is in a concentric circle with the annular groove and the filling layer filled in the annular groove. The N-surface electrode is arranged above the substrate and is adjacent to the epitaxial column. The connecting electrode is isolated from the epitaxial column through the passivation layer and is electrically connected with the P-surface electrode at a window of the passivation layer. The P-surface electrode is coincident with the center of the annular groove and the oxidation hole. The laser chip can be prepared through a simple process and has high reliability, low parasitic capacitance and high transmission rate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor laser technology, specifically relating to a vertical cavity surface-emitting laser chip and its fabrication method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) offer advantages over edge-emitting lasers, including lower threshold voltage, lower power consumption, single longitudinal mode, circular spot size, high modulation bandwidth, ease of on-chip testing, and ease of large-scale array integration, making them a core light source for short-range optical communication. Currently, VCSEL epitaxial structures primarily employ alternating high-aluminum and low-aluminum layers, forming a double-truncated cone structure through etching, and then oxidizing the oxide confinement layer to Al2O3 to confine the electric and optical fields. However, due to the stress mismatch between Al2O3 and the surrounding AlGaAs material, defects can easily arise during fabrication or operation, potentially causing complete chip failure. Therefore, this traditional VCSEL structure suffers from poor reliability, hindering its high-speed transmission performance. Existing technology (Patent Application No.: CN113809636A "Preparation Method and Vertical Cavity Surface Emitting Laser") (Authorization Publication No.: CN113013725 B "Vertical Cavity Surface Emitting Laser") discloses a method of setting a non-closed trench on the top of the epitaxial structure, that is, the waveguide region is connected to the outside of the trench by one or more bridges. Due to the bridges as a supporting structure, this type of VCSEL with a non-closed trench has high reliability. However, this type of laser requires the combined use of proton injection technology and wet oxidation technology to completely confine the electric field and optical field to the waveguide region, thus increasing the fabrication complexity and production cost of the laser. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a vertical cavity surface-emitting laser chip and its fabrication method, aiming to omit proton injection technology and improve the reliability and high-speed transmission characteristics of the laser chip device with a simpler process and lower cost.

[0004] To achieve the above objectives, the technical solution of the present invention is as follows:

[0005] A laser chip is disclosed, comprising a substrate, an epitaxial pillar, an annular trench, a filling layer, a passivation layer, oxide holes, and electrodes. The epitaxial pillar is disposed on the substrate, and an annular trench is formed above the epitaxial pillar to create an "island" waveguide region surrounded by the annular trench. The annular trench is filled with a filling layer. The electrodes include a P-side electrode, an N-side electrode, and a connecting electrode. The P-side electrode is disposed above the "island" waveguide region and forms a concentric ring with the annular trench and the filling layer inside it. The N-side electrode is disposed above the substrate and adjacent to the epitaxial pillar. The connecting electrode is isolated from the epitaxial pillar by the passivation layer and forms an electrical connection with the P-side electrode at a window in the passivation layer. The center of the P-side electrode coincides with the center of the annular trench and the oxide holes.

[0006] According to an embodiment of the present invention, the substrate material is, for example, N-type doped GaAs, or an undoped or half-doped GaAs with an N-GaAs buffer layer grown on top.

[0007] According to an embodiment of the present invention, the epitaxial structure of the epitaxial pillar is provided with an N-type ohmic contact layer, an N-DBR layer, an active region, an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer from bottom to top.

[0008] According to an embodiment of the present invention, the epitaxial structure of the epitaxial pillar is formed by stacking an N-type ohmic contact layer, an N-DBR layer, an active region, an oxide confinement layer, a P-DBR layer and a P-type ohmic contact layer from above the substrate using MOCVD, and then etched by an inductively coupled plasma etching (ICP) device.

[0009] According to an embodiment of the present invention, the N-type ohmic contact layer and the P-type ohmic contact layer are made of N-type doped GaAs and P-type doped GaAs, respectively.

[0010] According to an embodiment of the present invention, the N-DBR layer is made of alternating N-type doped Al. x Ga 1-x As and Al y Ga 1-y As; the P-DBR layer is made of alternating P-type doped Al. x Ga 1-x As and Al y Ga 1-y As, where: x = 0.1-0.15, exemplarily 0.12; y = 0.85-0.9, exemplarily 0.88.

[0011] According to an embodiment of the present invention, the optical thickness of each pair of DBRs (N-DBR layer, P-DBR layer) is 1 / 2 times the center wavelength of the laser.

[0012] According to an embodiment of the present invention, in the P-DBR layer, Al x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 20-30 times, exemplarily 25 times; in the N-DBR layer, Al x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 30-40 times, with 36 times being an example.

[0013] According to an embodiment of the present invention, the material of the oxide confinement layer is Al. x Ga 1-x As, x = 0.96 - 1.0, for example 0.98.

[0014] According to an embodiment of the present invention, the thickness of the oxide confinement layer is 10-20 nm, exemplarily 10 nm, 15 nm, or 20 nm.

[0015] According to an embodiment of the present invention, the oxide confinement layer is formed with oxide pores by an oxidation process; preferably, a wet oxidation technique is used to oxidize the oxide confinement layer to form oxide pores, so as to further confine the light field and electric field.

[0016] According to an embodiment of the present invention, the diameter of the oxide pore is 5-7 μm, exemplarily 5 μm, 6 μm, or 7 μm.

[0017] According to an embodiment of the present invention, the active region is composed of a quantum well (MQW) and a resonant cavity, wherein: the quantum well is composed of In x Ga 1-x As and Al y Ga 1-y As grows alternately, where x = 0.1 - 0.2, y = 0.2 - 0.4, In x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 3-5 times; the material of the resonant cavity is GaAs.

[0018] According to an embodiment of the present invention, the sum of the optical thicknesses of the quantum well and the resonant cavity is an integer multiple of half the laser lasing wavelength, such as 1 or 2 times.

[0019] According to an embodiment of the present invention, the laser chip has an annular trench etched on the surface of the epitaxial pillar to form an "island" waveguide region surrounded by the annular trench, and then the annular trench is filled by a filling layer.

[0020] According to an embodiment of the present invention, the annular trench is formed by an ICP etching process, and its etching depth is controlled by an atomic emission spectrometer or a photoelectric value monitor. The etching depth is from the P-type ohmic contact layer to the point where it passes through the active region and then stops.

[0021] According to an embodiment of the present invention, the inner diameter of the annular groove is 20-25 μm (e.g., 22 μm), and the width of the annular groove is 15-20 μm (e.g., 20 μm).

[0022] According to an embodiment of the present invention, the filling layer is used to protect the oxide confinement layer and the "island" waveguide region, and its material is, for example, SiO2 or SiN. x One, two, or more of SiON, polyimide, photoresist, and styrene-cyclobutene (BCB), preferably SiO2-BCB-SiN. x The combined structure.

[0023] According to an embodiment of the present invention, the thickness of the filling layer is 1-3.5 μm; exemplary values ​​are 1 μm, 2 μm, 3 μm, and 3.5 μm.

[0024] According to an exemplary embodiment of the present invention, when the filling layer material is SiO2 or SiN... x When the material is SiON, the thickness of the filling layer is preferably 1 μm; when the material of the filling layer is polyimide, photoresist, or styrene-cyclobutene (BCB), the thickness of the filling layer is preferably 3.5 μm.

[0025] According to an embodiment of the present invention, the P-side electrode is a ring structure, located above the "island" waveguide region and coinciding with the center of the ring trench and the oxide hole.

[0026] According to an embodiment of the present invention, the inner diameter of the P-side electrode is 10 μm and the outer diameter is 18-20 μm.

[0027] According to an embodiment of the present invention, the material of the P-side electrode is Ti / Pt / Au, the thickness is 250-300nm, and the deposition method is thermal evaporation or magnetron sputtering.

[0028] According to an embodiment of the present invention, the material of the N-side electrode is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, the thickness is 300-400nm, and the deposition method is thermal evaporation or magnetron sputtering.

[0029] According to an embodiment of the present invention, the connected electrode is connected to the P-side electrode and extends across the annular trench to the top of the epitaxial pillar. Preferably, the material of the connected electrode is Ti / Au or Cr / Au, the thickness is 0.5 to 2 μm (exemplarily 1 μm), and the plating method is thermal evaporation, magnetron sputtering, electroplating, or electroless plating.

[0030] According to an embodiment of the present invention, the passivation layer is made of SiNx with a refractive index N = 1.917.

[0031] According to an embodiment of the present invention, the optical thickness of the passivation layer is 3 / 4 or 5 / 4 times the laser lasing wavelength.

[0032] According to an embodiment of the present invention, the projected area of ​​the connected electrodes on the substrate should include the projected area of ​​the annular trench on the substrate, so as to increase the heat dissipation characteristics of the laser chip.

[0033] According to an embodiment of the present invention, the laser chip is a vertical cavity surface-emitting laser chip.

[0034] The present invention also provides a method for fabricating the above-mentioned laser chip, comprising the following steps:

[0035] S1: An N-type ohmic contact layer, an N-DBR layer, an active region (composed of MQWs and a resonant cavity), an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer are sequentially grown on the substrate to form a vertical cavity surface-emitting laser epitaxial wafer.

[0036] S2: Perform the first ICP etching on the epitaxial wafer to form an annular trench and a cylindrical "island" waveguide region surrounded by it to confine the optical and electric fields.

[0037] S3: Oxidize the oxide confinement layer to form oxide holes to further confine the light and electric fields;

[0038] S4: Use a filler layer to fill the annular trench to form a protective layer, which isolates the oxide confinement layer and supports the "island" structure;

[0039] S5: Deposit a P-side electrode on top of the "island" and anneal it to form an ohmic contact;

[0040] S6: Perform a second ICP etching on the epitaxial wafer to form irregular epitaxial pillars and expose the N-type buffer layer of the substrate;

[0041] S7: Deposit an N-face electrode adjacent to the epitaxial pillar on the N-type buffer layer of the substrate and anneal it to form an ohmic contact.

[0042] S8: Deposit a passivation layer on the epitaxial pillar and perform RIE etching to open windows above the P-side electrode and N-side electrode;

[0043] S9: Deposit an interconnected electrode on top of the epitaxial pillar so that it forms an electrical connection with the P-side electrode through the opening of the passivation layer.

[0044] According to an embodiment of the present invention, in step S1, an N-type ohmic contact layer, an N-DBR layer, an active region (including MQWs and a confinement layer), an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer are sequentially grown on the substrate using MOCVD.

[0045] According to an embodiment of the present invention, the substrate material is, for example, N-type doped GaAs, or it may be undoped or half-doped GaAs with an N-GaAs buffer layer grown on top. For example, the substrate is selected from GaAs substrates.

[0046] According to an embodiment of the present invention, in step S2, the inner diameter of the annular trench is 20-25 μm, the trench width is 15-20 μm, and the etching depth is from the P-type ohmic contact layer to the point where the etching stops after passing through the active region.

[0047] According to an embodiment of the present invention, in step S3, the diameter of the unoxidized area (i.e., the oxide pore) in the middle of the oxide confinement layer, viewed from a top angle, is 5-7 μm.

[0048] According to an embodiment of the present invention, in step S4, the material of the filling layer is an insulator such as SiO2 or SiN. x One, two, or more of SiON, photoresist, styrene-cyclobutene, and polyimide, preferably SiO2-BCB-SiN. x The combined structure has a filler layer thickness of 1-3.5μm.

[0049] According to an embodiment of the present invention, in step S5, the P-side electrode is a ring structure with an inner diameter of 10 μm and an outer diameter of 18-20 μm. From a top-down perspective, the P-side electrode coincides with the center of the ring groove and the oxide hole.

[0050] According to an embodiment of the present invention, in step S5, the material of the P-side electrode is Ti / Pt / Au, the thickness is 250-300nm, and the deposition method is thermal evaporation or magnetron sputtering.

[0051] According to an embodiment of the present invention, in step S6, the epitaxial pillar is formed by an etching process, and the etching depth starts from the P-type ohmic contact layer and stops at the N-type ohmic contact layer.

[0052] According to an embodiment of the present invention, in step S7, the material of the N-side electrode is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, the thickness is 300-400nm, and the deposition method is thermal evaporation or magnetron sputtering;

[0053] According to an embodiment of the present invention, in step S8, the material of the passivation layer is SiN. x With a refractive index of N = 1.917, its optical thickness is 3 / 4 or 5 / 4 times the laser lasing wavelength.

[0054] According to an embodiment of the present invention, in step S9, the material of the connected electrode is Ti / Au or Cr / Au, the thickness is 1μm, and the plating method is thermal evaporation, magnetron sputtering, electroplating or chemical plating.

[0055] According to an embodiment of the present invention, after step S9, the wafer can be thinned to 100-150μm and on-chip performance testing can be performed, followed by chip cleaving and packaging.

[0056] The beneficial effects of this invention:

[0057] This invention creates annular trenches on the surface of the epitaxial pillars of a laser chip, forming an "island" waveguide region surrounded by these trenches. This completely confines the electric and optical fields within the "island" waveguide region. An insulating filling layer then fills the annular trenches to protect the oxide confinement layer and the "island" waveguide region structure. The laser chip structure design and fabrication method of this invention can omit proton injection technology, improving device reliability and high-speed transmission characteristics with a simpler process and lower cost, while also reducing the parasitic capacitance of the laser chip. Attached Figure Description

[0058] Figure 1 This is a top view of the vertical cavity surface-emitting laser chip of the present invention.

[0059] Figure 2 This is a schematic diagram of a longitudinal cross-section of the vertical cavity surface-emitting laser chip of the present invention;

[0060] In the figure: 1-substrate; 2-epipolar pillar; 3-P-side electrode; 4-connected electrode; 5-annular trench; 6-filling layer; 7-passivation layer; 8-N-side electrode; 9-oxidation hole.

[0061] Figure 3 This is a schematic diagram of the epitaxial structure of the vertical cavity surface-emitting laser chip of the present invention;

[0062] In the figure: 1-substrate; 10-N-type ohmic contact layer; 11-N-DBR layer; 12-active region; 13-oxidation confinement layer; 14-P-DBR layer; 15-P-type ohmic contact layer.

[0063] Figure 4 This is a flowchart illustrating the fabrication method of the vertical cavity surface-emitting laser chip of the present invention.

[0064] Figure 5 This is a graph showing the optical power, voltage, and current of the vertical cavity surface-emitting laser chip of the present invention.

[0065] Figure 6 The results are the high-speed transmission eye diagram test results of the vertical cavity surface-emitting laser chip of this invention. Detailed Implementation

[0066] The technical solution of the present invention will be further described in detail below with reference to specific embodiments. It should be understood that the following embodiments are merely illustrative and explanatory of the present invention, and should not be construed as limiting the scope of protection of the present invention. All technologies implemented based on the above content of the present invention are covered within the scope of protection intended by the present invention.

[0067] Unless otherwise stated, the raw materials and reagents used in the following examples are commercially available products or can be prepared by known methods.

[0068] Example 1

[0069] Figure 1 This is a top view of the vertical-cavity surface-emitting laser chip provided in this embodiment. Figure 2 This is a schematic diagram of a longitudinal cross-section of a vertical-cavity surface-emitting laser chip provided in an embodiment of the present invention, as shown below. Figure 1 and Figure 2 As shown, the vertical cavity surface-emitting laser chip provided in this embodiment includes a substrate 1, an epitaxial pillar 2, a P-side electrode 3, a connecting electrode 4, an annular trench 5, a filling layer 6, a passivation layer 7, an N-side electrode 8, and an oxide hole 9. The epitaxial pillar 2 is disposed on the substrate 1, and an annular trench 5 is disposed above the epitaxial pillar 2 to form an "island" waveguide region surrounded by the annular trench. The annular trench 5 is filled with a filling layer 6. The P-side electrode 3 is disposed above the "island" waveguide region and forms a concentric ring with the annular trench 5 and the filling layer 6 inside it. The N-side electrode 8 is disposed above the substrate 1 and adjacent to the epitaxial pillar 2. The connecting electrode 4 is isolated from the epitaxial pillar 2 by the passivation layer 7 and forms an electrical connection with the P-side electrode 3 at the opening of the passivation layer 7. The center of the P-side electrode 3 coincides with the center of the annular trench 5 and the oxide hole 9.

[0070] [Base]

[0071] The substrate 1 is used to support the epitaxial pillar 2. The material of the substrate 1 is, for example, N-type doped GaAs, or it can be undoped or half-doped GaAs with an N-GaAs buffer layer grown on top.

[0072] [Extensional Column]

[0073] The epitaxial structure of the epitaxial pillar 2 is provided with an N-type ohmic contact layer 10, an N-DBR layer 11, an active region 12, an oxide confinement layer 13, a P-DBR layer 14 and a P-type ohmic contact layer 15 from bottom to top.

[0074] The epitaxial structure of the epitaxial pillar 2 is first formed by stacking an N-type ohmic contact layer 10, an N-DBR layer 11, an active region 12, an oxide confinement layer 13, a P-DBR layer 14 and a P-type ohmic contact layer 15 from above the substrate 1 by MOCVD, and then etched by an inductively coupled plasma etching (ICP) device.

[0075] in:

[0076] The N-type ohmic contact layer 10 and the P-type ohmic contact layer 15 are made of N-type doped GaAs and P-type doped GaAs, respectively.

[0077] The N-DBR layer 11 and the P-DBR layer 14 are made of alternating N-type doped Al, respectively. x Ga 1-x As and Al y Ga 1- y Al grown with alternating As and P-type doping x Ga 1-x As and Al y Ga 1-y As, where: x = 0.1-0.15, x is 0.12 for example; y = 0.85-0.9, y is 0.88 for example.

[0078] The optical thickness of each DBR pair is half the center wavelength of the laser. In P-DBR layer 14, Al x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 20-30 times, with an example of 25 times; in the N-DBR layer 11, the alternating growth cycle of AlxGa1-xAs and AlyGa1-yAs is 30-40 times, with an example of 36 times.

[0079] The material of the oxide confinement layer 13 is Al x Ga 1-x As, x = 0.96-1.0, with examples of 0.96, 0.98, and 1.0; the thickness of the oxide confinement layer 13 is 10-20 nm, with examples of 10 nm, 12 nm, 15 nm, and 20 nm.

[0080] Wet oxidation technology is used to oxidize the oxide confinement layer to form oxide holes 9, in order to further confine the light field and electric field.

[0081] The diameter of the oxide pore 9 is 5-7 μm, with examples being 5 μm, 6 μm, and 7 μm.

[0082] The active region consists of quantum wells (MQWs) and a resonant cavity, wherein: the quantum well is composed of In x Ga1-x As and Al y Ga 1-y As grows alternately, where x = 0.1 - 0.2, y = 0.2 - 0.4, In x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 3-5 times; the material of the resonant cavity is GaAs, and the sum of the optical thicknesses of the quantum well and the resonant cavity is an integer multiple of half the laser lasing wavelength.

[0083] [Annular trench]

[0084] The annular trench 5 is used to provide space for the process of oxidizing the oxide confinement layer to Al2O3, and to confine the electric and optical fields to the "island" waveguide region instead of the ion implantation process.

[0085] The annular trench 5 is formed by ICP etching process, and its etching depth is controlled by atomic emission spectrometer or photoelectric value monitor. The etching depth is from the P-type ohmic contact layer to the active region and then stops.

[0086] The inner diameter of the annular groove 5 is 20-25 μm (e.g., 22 μm), and the width of the annular groove 5 is 15-20 μm (e.g., 20 μm).

[0087]

Fill Layer

[0088] Filler layer 6 is used to protect the oxide confinement layer and the "island" waveguide region; its material is, for example, SiO2 or SiN. x One, two, or more of SiON, polyimide, photoresist, and styrene-cyclobutene (BCB), preferably SiO2-BCB-SiN. x The combined structure.

[0089] The thickness of the filler layer 6 is 1-3.5 μm; examples are 1 μm, 2 μm, 3 μm, and 3.5 μm.

[0090] For example, when the filling layer material 6 is SiO2 or SiN x When the material of the filling layer 6 is SiON, the thickness of the filling layer 6 is preferably 1 μm; when the material of the filling layer 6 is polyimide, photoresist, or styrene-cyclobutene (BCB), the thickness of the filling layer 6 is preferably 3.5 μm.

[0091]

P-side electrode

[0092] The P-side electrode 3 is annular with an inner diameter of 10 μm and an outer diameter of 18-20 μm. From a top-down perspective, the center of the P-side electrode 3 coincides with the center of the annular groove 5 and the oxide hole 9.

[0093] The material of the P-side electrode 3 is Ti / Pt / Au, with a thickness of 250-300nm, and it is deposited by thermal evaporation or magnetron sputtering.

[0094]

N-face electrode

[0095] The N-side electrode is made of Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, with a thickness of 300-400nm, and is deposited by thermal evaporation or magnetron sputtering.

[0096] [Connected Electrodes]

[0097] The material of the connected electrode 4 is Ti / Au or Cr / Au, with a thickness of 1μm, and the plating method is thermal evaporation, magnetron sputtering, electroplating or chemical plating.

[0098] Passivation layer

[0099] The material of the passivation layer 7 is SiNx, with a refractive index N = 1.917, and the optical thickness of the passivation layer 7 is 3 / 4 or 5 / 4 times the laser lasing wavelength.

[0100] As a preferred embodiment, the projected area of ​​the connected electrode 4 on the substrate 1 should include the projected area of ​​the annular trench 5 on the substrate 1 to increase the heat dissipation characteristics of the laser chip.

[0101] The vertical-cavity surface-emitting laser chip of the present invention, by etching annular trenches 5 on the surface of the laser epitaxial pillar 2 and forming an "island" waveguide region surrounded by the annular trenches 5, completely confines the electric and optical fields within the "island" waveguide region. An insulating filling layer 6 fills the annular trenches 5 to protect the oxide confinement layer and the "island" waveguide region structure. The laser chip structure design of the present invention can omit proton injection technology, improving device reliability and high-speed transmission characteristics with a simpler process and lower cost.

[0102] Example 2

[0103] like Figure 4 As shown, a method for fabricating a vertical-cavity surface-emitting laser chip includes the following steps:

[0104] S1: Select a GaAs substrate as substrate 1. On substrate 1, use MOCVD (trimethylgallium (TMGa), trimethylaluminum (TMA1), and trimethylindium (TMIn) as group III sources, arsine (AsH3) as group V sources, silane (SiH4) as N-type dopant source, and carbon tetrasulfide (CBr4) as P-type dopant source) to sequentially grow an epitaxial pillar 2 with an N-type ohmic contact layer 10 (material: N-GaAs, physical thickness: 1500nm) and an N-DBR layer 11 (material: Al). 0.9 Ga 0.1 As / Al0.1 Ga 0.9 As, 36 pairs, each pair with an optical thickness of 425nm), active region 12 (made of MQWs (material is In) 0.3 Ga 0.7 As / GaAs (3 pairs, each pair with a physical thickness of 15nm) and a resonant cavity (the resonant cavity material is GaAs) are combined, and an oxide confinement layer (the material is Al) is formed. 0.98 Ga 0.02 As, with a physical thickness of 20nm), P-DBR layer 14 (Al) 0.9 Ga 0.1 As / Al 0.1 Ga 0.9 As, 36 pairs, each with an optical thickness of 425nm) and a P-type ohmic contact layer 15 (made of P-GaAs with a physical thickness of 150nm) to form a vertical cavity surface-emitting laser epitaxial wafer;

[0105] S2: Perform the first ICP etching on the epitaxial wafer (process parameters: Cl2 flow rate 2sccm, Ar2 flow rate 40sccm, ICP-RF power 300W, Table RF power 75W, temperature 250℃) to form an annular trench 5 and a cylindrical "island" waveguide region surrounded by it to limit the optical field and electric field.

[0106] S3: Wet oxidation technology is used to oxidize the oxide confinement layer to form oxide holes 9, so as to further confine the light field and electric field. (The oxidation temperature will affect the oxidation rate and the control accuracy of the oxide holes. It is adjusted according to the aluminum composition content in the oxide confinement layer, generally 350-420℃ (exemplary is 400℃)).

[0107] S4: Use filler layer 6 (material is SiO2-BCB-SiN) x The combined structure (with a filling layer thickness of 3.5 μm) is used to fill the annular trench 5 to form a protective layer, thereby isolating the oxide confinement layer and supporting the "island" waveguide region structure;

[0108] S5: Deposit P-surface electrode 3 on top of the "island" waveguide region and anneal to form an ohmic contact;

[0109] S6: Perform a second ICP etching on the epitaxial wafer (process parameters: Cl2 flow rate 6 sccm, Ar2 flow rate 40 sccm, ICP-RF power 300W, Table RF power 120W, temperature 25℃) to form irregular epitaxial pillars 2 and expose the N-GaAs buffer layer of the substrate 1.

[0110] S7: An N-face electrode 8 is deposited adjacent to the epitaxial pillar 2 on the N-GaAs buffer layer of the substrate 1 and annealed to form an ohmic contact.

[0111] S8: SiN was deposited on epitaxial pillar 2 using PECVD. x Passivation layer 7 (material is SiN) x (with a thickness of 4000A), and RIE etching is performed above the P-side electrode 3 and the N-side electrode 8 to create windows;

[0112] S9: Deposit an interconnected electrode 4 above the epitaxial pillar 2, so that it forms an electrical connection with the P-side electrode 3 through the opening of the passivation layer 7.

[0113] The high-speed VCSEL chip obtained in this embodiment was subjected to LIV photoelectric performance testing using an automatic testing machine. The results are as follows: Figure 5 As shown. Eye diagram performance was tested using a large-signal high-speed test platform, and the results are as follows. Figure 6 As shown. From Figure 5 As can be seen, the high-speed VCSEL chip obtained in this embodiment has higher output optical power, lower impedance, and a smoother LIV curve. The maximum output optical power can reach 10mW, the differential resistance is 60Ω, the slope efficiency Se = 0.98W / A, and the photoelectric conversion efficiency PCE = 36%. Figure 6 It can be seen that the high-speed VCSEL chip obtained in this embodiment has excellent high-speed transmission characteristics, with a margin of 30.5% under a template of 10.3125Gbps.

[0114] The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A laser chip, characterized in that, The laser chip includes a substrate, an epitaxial pillar, an annular trench, a filling layer, a passivation layer, oxide holes, and electrodes. The epitaxial pillar is disposed on the substrate, and an annular trench is disposed above the epitaxial pillar to form an "island" waveguide region surrounded by the annular trench. The annular trench is filled with a filling layer. The electrode includes a P-side electrode, an N-side electrode, and a connecting electrode. The P-side electrode is disposed above the "island" waveguide region and forms a concentric ring with the annular trench and the filling layer inside it. The N-side electrode is disposed above the substrate and adjacent to the epitaxial pillar. The connecting electrode is isolated from the epitaxial pillar by a passivation layer and forms an electrical connection with the P-side electrode at the passivation layer opening. The P-side electrode coincides with the center of the annular trench and the oxide hole. The epitaxial structure of the epitaxial pillar is formed by stacking an N-type ohmic contact layer, an N-DBR layer, an active region, an oxide confinement layer, a P-DBR layer and a P-type ohmic contact layer from above the substrate using MOCVD to form an epitaxial wafer, which is then etched by an inductively coupled plasma etching (ICP) device. The laser chip has annular trenches etched on the surface of the epitaxial pillar to form an "island" waveguide region surrounded by the annular trenches, and then the annular trenches are filled by a filling layer. The annular trench is formed by ICP etching process, and its etching depth is controlled by atomic emission spectrometer or photoelectric value monitor. The etching depth is from the P-type ohmic contact layer to the active region and then stops. The inner diameter of the annular groove is 20-25 μm, and the width of the annular groove is 15-20 μm; The filling layer is used to protect the oxide confinement layer and the "island" waveguide region, and its material is SiO2 or SiN. x One, two, or more of the following: SiON, polyimide, photoresist, and styrene-cyclobutene; The connected electrode is connected to the P-face electrode and extends across the annular groove to the top of the epitaxial column.

2. The laser chip as described in claim 1, characterized in that, The substrate material is N-type doped GaAs, or it can be undoped or half-doped GaAs with an N-GaAs buffer layer grown on top.

3. The laser chip as described in claim 1, characterized in that, The N-type ohmic contact layer and the P-type ohmic contact layer are made of N-type doped GaAs and P-type doped GaAs, respectively. And / or, the N-DBR layer is made of alternating layers of N-type doped Al. x Ga 1-x As and Al y Ga 1-y As; the P-DBR layer is made of alternating P-type doped Al. x Ga 1-x As and Al y Ga 1-y As, where: x = 0.1 - 0.15; y = 0.85 - 0.9; And / or, the optical thickness of each pair of N-DBR layers and P-DBR layers is 1 / 2 times the center wavelength of the laser; And / or, in the P-DBR layer, Al x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 20-30 times; in the N-DBR layer, Al x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 30-40 times.

4. The laser chip as described in claim 1, characterized in that, The material of the oxidation confinement layer is Al. x Ga 1-x As, x = 0.96 - 1.0; And / or, the thickness of the oxide confinement layer is 10-20 nm; And / or, the oxide confinement layer is formed with oxide pores through an oxidation process; the oxide confinement layer is oxidized with wet oxidation technology to form oxide pores, so as to further confine the light field and electric field; And / or, the diameter of the oxide pores is 5-7 μm.

5. The laser chip as described in claim 1, characterized in that, The active region consists of a quantum well and a resonant cavity, wherein: the quantum well is composed of In x Ga 1-x As and Al y Ga 1-y As grows alternately, where x = 0.1 - 0.2, y = 0.2 - 0.4, In x Ga 1-x As and Al y Ga 1-y The alternating growth cycle of As is 3-5 times; the material of the resonant cavity is GaAs; And / or, the sum of the optical thicknesses of the quantum well and the resonant cavity is an integer multiple of half the laser lasing wavelength.

6. The laser chip according to any one of claims 1-5, characterized in that, The filler layer material is SiO2-BCB-SiN x Combinatorial structure; And / or, the thickness of the filling layer is 1-3.5 μm.

7. The laser chip according to any one of claims 1-4, characterized in that, The P-side electrode has a ring structure, located above the "island" waveguide region and coinciding with the center of the ring trench and oxide hole; And / or, the inner diameter of the P-side electrode is 10 μm and the outer diameter is 18-20 μm; And / or, the material of the P-side electrode is Ti / Pt / Au, the thickness is 250-300nm, and the deposition method is thermal evaporation or magnetron sputtering; And / or, the material of the N-side electrode is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, with a thickness of 300-400nm, and the deposition method is thermal evaporation or magnetron sputtering.

8. The laser chip according to any one of claims 1-5, characterized in that, The passivation layer is made of SiNx with a refractive index of N=1.917; And / or, the optical thickness of the passivation layer is 3 / 4 or 5 / 4 times the laser lasing wavelength; And / or, the projected area of ​​the connected electrodes on the substrate should include the projected area of ​​the annular trench on the substrate to increase the heat dissipation characteristics of the laser chip.

9. A method for fabricating a laser chip according to any one of claims 1-8, comprising the following steps: S1: An N-type ohmic contact layer, an N-DBR layer, an active region, an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer are sequentially grown on the substrate to form a vertical cavity surface-emitting laser epitaxial wafer. S2: Perform the first ICP etching on the epitaxial wafer to form an annular trench and a cylindrical "island" waveguide region surrounded by it to confine the optical and electric fields. S3: Oxidize the oxide confinement layer to form oxide holes to further confine the light and electric fields; S4: Use a filling layer to fill the annular trench to form a protective layer, which isolates the oxide confinement layer and supports the "island" structure; S5: Deposit a P-side electrode on top of the "island" and anneal it to form an ohmic contact; S6: Perform a second ICP etching on the epitaxial wafer to form irregular epitaxial pillars and expose the N-type buffer layer of the substrate; S7: Deposit an N-face electrode adjacent to the epitaxial pillar on the N-type buffer layer of the substrate and anneal it to form an ohmic contact. S8: Deposit a passivation layer on the epitaxial pillar and perform RIE etching to open windows above the P-side electrode and N-side electrode; S9: Deposit an interconnected electrode on top of the epitaxial pillar so that it forms an electrical connection with the P-side electrode through the opening of the passivation layer.

10. The preparation method according to claim 9, characterized in that, In step S1, an N-type ohmic contact layer, an N-DBR layer, an active region, an oxide confinement layer, a P-DBR layer, and a P-type ohmic contact layer are sequentially grown on the substrate using the MOCVD method. And / or, the substrate material is N-type doped GaAs, or it may be undoped or half-doped GaAs with an N-GaAs buffer layer grown on top; And / or, in step S2, the inner diameter of the annular trench is 20-25 μm, the trench width is 15-20 μm, and the etching depth is from the P-type ohmic contact layer to the point where it stops after passing through the active region; And / or, in step S3, the diameter of the unoxidized area in the middle of the oxide confinement layer, i.e., the oxide pore, is 5-7 μm when viewed from above; And / or, in step S4, the filling layer material is an insulator SiO2 or SiN. x One, two, or more of the following: SiON, photoresist, styrene, and polyimide; And / or, the thickness of the filling layer is 1-3.5 μm.

11. The preparation method according to claim 9, characterized in that, In step S5, the P-side electrode has a ring structure with an inner diameter of 10 μm and an outer diameter of 18-20 μm. From a top-down perspective, the P-side electrode coincides with the center of the ring groove and the oxide hole. And / or, in step S5, the material of the P-side electrode is Ti / Pt / Au, the thickness is 250-300nm, and the deposition method is thermal evaporation or magnetron sputtering.

12. The preparation method according to claim 9, characterized in that, In step S6, the epitaxial pillar is formed by an etching process, with the etching depth starting from the P-type ohmic contact layer and ending at the N-type ohmic contact layer.

13. The preparation method according to claim 9, characterized in that, In step S7, the material of the N-side electrode is Ni / Ge / Au / Ni / Au or GeAu / Ni / Au, with a thickness of 300-400 nm, and the deposition method is thermal evaporation or magnetron sputtering. And / or, in step S8, the material of the passivation layer is SiNx, the refractive index N=1.917, and its optical thickness is 3 / 4 times or 5 / 4 times the laser lasing wavelength; And / or, in step S9, the material of the connected electrode is Ti / Au or Cr / Au, the thickness is 1μm, and the plating method is thermal evaporation, magnetron sputtering, electroplating or chemical plating.

14. The preparation method according to claim 9, characterized in that, After step S9, the wafer can be thinned to 100-150μm and on-chip performance testing can be performed before chip cleaving and packaging.

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