Memory and method of forming the same
By constructing a first isolation structure during the etching of the semiconductor layer and forming a barrier layer through self-alignment, the problem of poor gate layer thickness uniformity in three-dimensional memory is solved, thereby improving memory performance and reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-03-21
- Publication Date
- 2026-07-24
AI Technical Summary
In three-dimensional memory, the thickness uniformity between adjacent gate layers is poor, and the selectivity of barrier layer materials is limited, leading to decreased memory performance and increased manufacturing costs.
By constructing the first isolation structure while etching the semiconductor layer, and forming the barrier layer by self-aligned exposure etching before forming the gate layer, the range of barrier layer materials is expanded, the manufacturing process is simplified, the isolation effect is improved, and the capacitive coupling effect is reduced.
It improves the uniformity of gate layer thickness in memory, simplifies the manufacturing process, reduces the capacitive coupling effect between adjacent gate layers, improves memory performance, and reduces costs.
Smart Images
Figure CN116828842B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a memory and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] As the size of memory devices such as DRAM continues to shrink, the gate structure in memory has evolved to the smaller-sized gate all-around (GAA) structure, and memory has also evolved from two-dimensional to three-dimensional structures. However, in three-dimensional memory, the thickness uniformity between adjacent gate layers is poor, and due to limitations in fabrication processes, the material selection for the barrier layer used to isolate adjacent gate layers is relatively limited. For example, the material of the barrier layer is generally silicon oxide, which reduces the performance of the memory and is not conducive to simplifying the memory manufacturing process or reducing the cost of memory manufacturing.
[0004] Therefore, how to reduce the thickness difference between different gate layers in memory, improve the flexibility of barrier layer material selection, enhance the isolation effect between adjacent gate layers, and reduce the capacitive coupling effect between adjacent gate layers, thereby improving memory performance, is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides a memory and a method for forming the same, which are used to solve the problem of large thickness differences between different gate layers in the memory. This improves the uniformity of the thickness of multiple gate layers in the memory, increases the flexibility in selecting barrier layer materials between adjacent gate layers, improves the isolation effect between adjacent gate layers, and reduces the capacitive coupling effect between adjacent gate layers, thereby improving the performance of the memory and reducing the manufacturing cost of the memory.
[0006] According to some embodiments, this disclosure provides a method for forming a memory, including the following steps:
[0007] Forming a substrate and a semiconductor layer on the substrate;
[0008] The semiconductor layer is patterned to form a plurality of first isolation structures. The portion of the semiconductor layer remaining between two adjacent first isolation structures forms a channel region. The first isolation structure includes a first via and a second via that penetrate the semiconductor layer in a direction perpendicular to the top surface of the substrate, and a first isolation pillar formed by the semiconductor layer remaining between the first via and the second via.
[0009] A first filling layer is formed that fills the first through hole and the second through hole;
[0010] Remove the first isolation pillar to form a third through-hole located in the first filler layer;
[0011] A barrier layer is formed that fills the third through-hole;
[0012] Remove the first filler layer to expose the channel region;
[0013] A gate layer is formed covering the surface of the channel region.
[0014] In some embodiments, the specific steps of forming a substrate and a semiconductor layer on the substrate include:
[0015] Provide substrate;
[0016] The semiconductor layer is formed by alternately depositing a first sub-semiconductor layer and a second sub-semiconductor layer on the top surface of the substrate in a direction perpendicular to the top surface of the substrate.
[0017] In some embodiments, the specific steps of patterning the semiconductor layer include:
[0018] The semiconductor layer is etched to form a plurality of first isolation structures that extend parallel to each other along a first direction. Each first isolation structure includes a first isolation pillar and a first via and a second via distributed on opposite sides of the first isolation pillar along a second direction. The first sub-semiconductor layer remaining between two adjacent first isolation structures forms a channel region. The first direction is a direction parallel to the top surface of the substrate, and the second direction is a direction parallel to the top surface of the substrate and intersecting the first direction.
[0019] In some embodiments, the width of the first through hole is equal to the width of the second through hole along the second direction.
[0020] In some embodiments, the semiconductor layer includes a first region and a second region distributed outside the first region along the first direction; the specific steps of etching the semiconductor layer include:
[0021] The first region and the second region of the semiconductor layer are etched to form a plurality of first isolation structures and a plurality of channel regions in the first region, and a plurality of second isolation structures are formed in the second region. The semiconductor layer remaining between two adjacent second isolation structures forms a virtual channel region. The second isolation structure includes a fourth via and a fifth via that penetrate the semiconductor layer in a direction perpendicular to the top surface of the substrate, and a second isolation pillar formed by the semiconductor layer remaining between the fourth via and the fifth via.
[0022] In some embodiments, along the second direction, the width of the first isolation post is smaller than the width of the trench area.
[0023] In some embodiments, the specific steps for forming a third through-hole located in the first filling layer include:
[0024] The first filling layer located on the top surface of the first region of the semiconductor layer is etched to form a first opening that exposes the first isolation pillar;
[0025] The first isolation post is removed along the first opening, forming the third through hole in the first region.
[0026] In some embodiments, along the second direction, the width of the first opening is greater than or equal to the width of the first isolation post.
[0027] In some embodiments, the specific steps of forming a barrier layer that fills the third through-hole include:
[0028] An insulating material is deposited along the first opening into the third through-hole to form a barrier layer in the first region.
[0029] In some embodiments, before exposing the channel region, the following steps are further included:
[0030] A support layer is formed in the second region of the semiconductor layer.
[0031] In some embodiments, the specific steps of forming a support layer in the second region of the semiconductor layer include:
[0032] A second filling layer is formed, which fills the top surface of the second region of the semiconductor layer and covers the fourth and fifth through holes.
[0033] Remove the second isolation column to form a sixth through hole in the second filling layer;
[0034] A first sacrificial layer is formed within the sixth through hole;
[0035] Remove the second filling layer inside the fourth through hole and the fifth through hole to expose the fourth through hole and the fifth through hole;
[0036] A portion of the second sub-semiconductor layer located in the second region is removed along the fourth and fifth vias to form a first void region located between adjacent first sub-semiconductor layers;
[0037] A supporting layer is formed by filling the fourth through hole, the fifth through hole, and the first void region with a medium material.
[0038] In some embodiments, the specific steps for exposing the trench region include:
[0039] Remove the first filler layer located in the first through hole and the second through hole to expose the first through hole and the second through hole;
[0040] The second sub-semiconductor layer located in the first region is removed along the first via and the second via to form a second void region located between two adjacent first sub-semiconductor layers.
[0041] A second sacrificial layer is formed that fills the first through-hole, the second through-hole, and the second void region;
[0042] Remove the second sacrificial layer to expose the channel region, the first via, the second via, and the second void region.
[0043] In some embodiments, the specific steps of forming a gate layer covering the surface of the channel region include:
[0044] The gate layer is formed to fill the first via, the second via, and the second void region.
[0045] In some embodiments, the specific steps of forming the gate layer that fills the first via, the second via, and the second void region include:
[0046] A gate dielectric layer is formed covering the surface of the channel region;
[0047] The gate layer is formed to fill the first via, the second via, and the second void region, and to cover the surface of the gate dielectric layer.
[0048] In some embodiments, the material of the first sub-semiconductor layer is silicon; the specific steps of forming the gate dielectric layer covering the surface of the channel region include:
[0049] The surface of the channel region is oxidized in situ to form the gate dielectric layer.
[0050] In some embodiments, the step of forming a barrier layer that fills the third through-hole specifically includes:
[0051] A first sub-barrier layer is formed, filling the third through-hole;
[0052] The first sub-barrier layer is etched to form an etched hole extending in a direction perpendicular to the top surface of the substrate;
[0053] A second sub-barrier layer is formed within the etched hole.
[0054] In some embodiments, the material of the second sub-barrier layer is a nitride material, and the material of the first sub-barrier layer is an oxide material.
[0055] In some embodiments, the second sub-barrier layer is located within the first sub-barrier layer.
[0056] According to other embodiments, this disclosure also provides a memory, including:
[0057] Substrate;
[0058] Multiple channel regions are located above the substrate and are arranged in parallel along a direction parallel to the top surface of the substrate. Each channel region includes multiple channel regions arranged in parallel along a direction perpendicular to the top surface of the substrate.
[0059] Multiple barrier layers, the barrier layers being located above the substrate and between two adjacent groups of the channel regions;
[0060] A plurality of gate layers are located above the substrate, each gate layer being located between at least one barrier layer and one group of channel regions and covering the surface of all the channel regions in one group of channel regions, wherein the gate layers on opposite sides of one barrier layer have equal thickness.
[0061] In some embodiments, the barrier layer is a single-layer structure; or,
[0062] The barrier layer has a multi-layer structure.
[0063] In some embodiments, the barrier layer includes:
[0064] The first sub-blocking layer extends in a direction perpendicular to the top surface of the substrate and covers the surface of the gate layer;
[0065] The second sub-barrier layer extends in a direction perpendicular to the top surface of the substrate and is sandwiched inside the first sub-barrier layer.
[0066] In some embodiments, the first sub-barrier layer is made of an oxide material, and the second sub-barrier layer is made of a nitride material.
[0067] In some embodiments, the gate layer includes:
[0068] The first portion extends in a direction perpendicular to the top surface of the substrate and continuously covers the sidewalls of all the channel regions in the same group of channel regions. The first portions of the two gate layers located on opposite sides of a barrier layer have equal thickness.
[0069] The second part connects to the first part and is located between two adjacent channel areas within the same channel area group.
[0070] In some embodiments, it also includes:
[0071] A gate dielectric layer covers the surface of the channel region, and a gate layer covers the surface of the gate dielectric.
[0072] In some embodiments, it also includes:
[0073] The source and drain regions are distributed on opposite sides of the channel region;
[0074] A capacitor is connected to the drain region;
[0075] Bit lines connect the source region.
[0076] The memory and its formation method provided in some embodiments of this disclosure form a first isolation structure between adjacent active pillars while etching an active pillar in a semiconductor layer. The first isolation structure includes a first via, a second via, and a first isolation pillar located between the first and second vias. Then, before forming the gate layer, a barrier layer is formed by self-aligned exposure etching of the first isolation structure. This expands the material selection range for the barrier layer, simplifies the memory manufacturing process, and helps improve the isolation effect between adjacent gate layers, reducing the capacitive coupling effect between adjacent gate layers. Furthermore, some embodiments of this disclosure form the first isolation structure including the first isolation pillar simultaneously with the etching of the active pillars, and subsequently form the barrier layer using a self-aligned process. This avoids errors caused by photolithographic alignment, thereby reducing the thickness difference between adjacent gate layers and improving the thickness uniformity among the multiple gate layers within the memory. Attached Figure Description
[0077] Appendix Figure 1 This is a flowchart of a method for forming a memory according to a specific embodiment of this disclosure;
[0078] Appendix Figure 2 This is a top view schematic diagram of a memory formed according to a specific embodiment of the present disclosure;
[0079] Appendix Figure 3A-3K This is a schematic diagram of the main process cross-sections during the formation of the memory according to a specific embodiment of this disclosure;
[0080] Appendix Figure 4 This is a cross-sectional schematic diagram of the memory in a specific embodiment of this disclosure;
[0081] Appendix Figure 5 This is another cross-sectional schematic diagram of the memory in a specific embodiment of this disclosure. Detailed Implementation
[0082] The specific embodiments of the memory and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0083] This disclosure provides a memory, with appended... Figure 1 This is a flowchart illustrating the method for forming a memory according to a specific embodiment of this disclosure, with appended... Figure 2 This is a top view schematic diagram of a memory formed according to a specific embodiment of the present disclosure, with attached... Figure 3A-3K This is a schematic diagram of the main process cross-sections during the formation of the memory according to a specific embodiment of this disclosure. Figures 3A-3K from Figure 2 The five directions shown in the diagram—a-a', b-b', c-c', d-d', and e-e'—illustrate the main process cross-sections during the fabrication of the semiconductor device, clearly illustrating the fabrication process. The semiconductor device described in this specific embodiment may be, but is not limited to, DRAM. For example... Figure 1 , Figure 2 , Figures 3A-3K As shown, the method for forming the memory includes the following steps:
[0084] Step S11: Forming a substrate 30 and a semiconductor layer on the substrate 30.
[0085] In some embodiments, the specific steps of forming the substrate 30 and the semiconductor layer located on the substrate 30 include:
[0086] Substrate 30 is provided;
[0087] A first sub-semiconductor layer 31 and a second sub-semiconductor layer 32 are alternately deposited on the top surface of the substrate 30 along a direction perpendicular to the top surface of the substrate 30 to form the semiconductor layer, as follows: Figure 3A As shown.
[0088] The substrate 30 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 30 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. Subsequently, the first sub-semiconductor layer 31 and the second sub-semiconductor layer 32 are alternately deposited on the top surface of the substrate 30 along a direction perpendicular to the top surface of the substrate 30 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form the semiconductor layer with a superlattice stack structure, thereby further improving the storage density of the memory.
[0089] In one embodiment, the material of the first sub-semiconductor layer 31 may be Si, and the material of the second sub-semiconductor layer 32 may be SiGe.
[0090] Step S12: Pattern the semiconductor layer to form a plurality of first isolation structures. The portion of the semiconductor layer remaining between two adjacent first isolation structures forms a channel region. The first isolation structure includes a first via 34 and a second via 35 that penetrate the semiconductor layer in a direction perpendicular to the top surface of the substrate 30, and a first isolation pillar 37 formed by the semiconductor layer remaining between the first via 34 and the second via 35. Figure 3B As shown.
[0091] In some embodiments, the specific steps of patterning the semiconductor layer include:
[0092] The semiconductor layer is etched to form a plurality of first isolation structures extending along a first direction and parallel to each other. Each first isolation structure includes a first isolation pillar 37 and a first via 34 and a second via 35 distributed on opposite sides of the first isolation pillar 37 along a second direction. The first sub-semiconductor layer 31 remaining between two adjacent first isolation structures forms a channel region. The first direction is parallel to the top surface of the substrate 30, and the second direction is parallel to the top surface of the substrate 30 and intersects with the first direction.
[0093] Specifically, SADP (Self-aligned Double Patterning) or SAQP (Self-aligned Quardruple Patterning) processes can be used, combined with dry etching, to etch the semiconductor layer along a direction perpendicular to the top surface of the substrate 30, forming along the first direction (e.g. Figure 2 , Figures 3A-3KWhile multiple active pillars 36 (the multiple active pillars 36 are parallel to each other and spaced apart) extending from e-e' in the second direction are formed, a first isolation structure for separating adjacent active pillars 36 is formed. The first isolation structure includes, for example, along the second direction. Figure 2 , Figures 3A-3K The first via 34, the first isolation pillar 37, and the second via 35 are arranged sequentially (b-b'). The active pillar 36 includes a first sub-semiconductor layer 31 and a second sub-semiconductor layer 32 alternately stacked along a direction perpendicular to the top surface of the substrate 30, wherein the first sub-semiconductor layer 31 in the active pillar 36 forms the channel region. A plurality of first isolation structures are parallel to each other and spaced apart along the second direction. Both the first via 34 and the second via 35 are used for subsequent formation of gate layers, and the first isolation pillar 37 located between the first via 34 and the second via 35 is used for subsequent formation of a barrier layer isolating two adjacent gate layers.
[0094] In some embodiments, along the second direction (e.g.) Figure 2 , Figures 3A-3K On b-b'), the inner diameter of the first through hole 34 is equal to the inner diameter of the second through hole 35.
[0095] Specifically, both the first via 34 and the second via 35 are used to subsequently form gate layers, and the first isolation pillar 37 located between the first via 34 and the second via 35 is used to subsequently form a barrier layer that isolates the two adjacent gate layers. By controlling the inner diameter of the first via 34 and the inner diameter of the second via 35 to be equal during the etching of the semiconductor layer to form the active pillar 36, the thickness difference between the gate layer subsequently formed in the first via 34 and the gate layer subsequently formed in the second via 35 can be reduced. For example, the thickness of the gate layer subsequently formed in the first via 34 can be made equal to the thickness of the gate layer formed in the second via 35, avoiding thickness drift caused by etching differences in the gate metal layer formed by the etching process, thereby further improving the uniformity of the gate layer thickness in the memory and improving the electrical performance of the memory.
[0096] In order to increase the space for subsequent formation of the all-around gate structure and thus further simplify the memory manufacturing process, in some embodiments, the width of the first isolation pillar 37 is smaller than the width of the channel region along the second direction.
[0097] In some embodiments, the semiconductor layer includes a first region 21 and a second region 22 distributed along a first direction outside the first region 21; the specific steps of etching the semiconductor layer include:
[0098] The first and second regions of the semiconductor layer are etched to form a plurality of first isolation structures and a plurality of channel regions in the first region, and simultaneously to form a plurality of second isolation structures in the second region. The semiconductor layer remaining between two adjacent second isolation structures forms a virtual channel region. The second isolation structure includes a fourth via 38 and a fifth via 39 that penetrate the semiconductor layer in a direction perpendicular to the top surface of the substrate 30, and a second isolation pillar 40 formed by the semiconductor layer remaining between the fourth via 38 and the fifth via 39. Figure 3B As shown.
[0099] Specifically, such as Figure 2 As shown, the semiconductor layer includes a first region 21, along the first direction (e.g., Figure 2 , Figures 3A-3K The e-e') are distributed in the second region 22 outside the first region 21, and along the first direction (e.g. Figure 2 , Figures 3A-3K The e-e') in the first region 21 are distributed in the third region 20 outside the first region 21, and the first region 21 is located between the second region 22 and the third region 20. For example, the first region 21 can be a transistor region, the second region 22 can be a capacitor region, and the third region 20 can be a bit line region (e.g., a stepped bit line structure region). The first region 21 is electrically connected to both the second region 22 and the third region 20.
[0100] While etching the first region 21 of the semiconductor layer to form the active pillar 36, the second region 22 of the semiconductor layer is etched to form an extension along the first direction (e.g., while the active pillar 36 and the first isolation structure are formed in the first region 21). Figure 2 , Figures 3A-3K Multiple virtual active pillars 41 (e-e' in the text), wherein the multiple virtual active pillars 41 are parallel to each other and along a third direction (e.g., Figure 2 , Figures 3A-3K The virtual active pillars 41 are arranged at d-d' intervals, and a second isolation structure is formed between adjacent virtual active pillars 41. The second isolation structure includes the fourth via 38, the second isolation pillar 40, and the fifth via 39 arranged sequentially along the third direction. The virtual active pillar 41 includes a first sub-semiconductor layer 31 and a second sub-semiconductor layer 32 alternately stacked along a direction perpendicular to the top surface of the substrate 30, wherein the first sub-semiconductor layer 31 in the virtual active pillar 41 forms the virtual channel region.
[0101] Step S13, forming a first filling layer 42 that fills the first through hole 34 and the second through hole 35, such as Figure 3C As shown.
[0102] Specifically, an oxide material (e.g., silicon dioxide) can be deposited within the first via 34 and the second via 35, as well as on the top surface of the semiconductor layer, using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The first filling layer 42 is then formed after CMP (chemical mechanical polishing). The material of the first filling layer 42 should have a high etch selectivity ratio with the material of the semiconductor layer to allow for selective removal of portions of the semiconductor layer. In one embodiment, the etch selectivity ratio between the first filling layer 42 and the first sub-semiconductor layer 31, and the etch selectivity ratio between the first filling layer 42 and the second sub-semiconductor layer 32, are both greater than 3.
[0103] Step S14: Remove the first isolation pillar 37 to form a third through hole 43 located in the first filling layer 42, such as... Figure 3E As shown.
[0104] In some embodiments, the specific steps for forming the third through-hole 43 located in the first filling layer 42 include:
[0105] The first filling layer 42 located on the top surface of the first region 21 of the semiconductor layer is etched to form a first opening 421 exposing the first isolation pillar 37, such as... Figure 3D As shown;
[0106] The first isolation post 37 is removed along the first opening 421, forming the third through hole 43 in the first region 21, as follows. Figure 3E As shown.
[0107] Specifically, after the first filling layer 42 is formed, a photolithography process can be used to pattern the first filling layer 42 to form the first opening 421 that exposes the top surface of the first isolation pillar 37, such as... Figure 3D As shown. Then, the first isolation pillar 37 is self-aligned and etched along the first opening 421. After completely removing the first isolation pillar 37, the third through hole 43 is formed, as shown. Figure 3EAs shown. In this specific embodiment, by controlling the etching selectivity ratio between the first filling layer 42 and the first sub-semiconductor layer 31, and the etching selectivity ratio between the first filling layer 42 and the second sub-semiconductor layer 32, both are greater than 3, the first filling layer 42 is not damaged when the first isolation pillar 37 is removed, thereby further improving the thickness uniformity of the gate layer subsequently formed in the first via 34 and the second via 35.
[0108] To ensure that the first isolation post 37 is completely removed, in some embodiments, the width of the first opening 421 along the second direction is greater than or equal to the width of the first isolation post 37.
[0109] Step S15, forming a barrier layer 44 that fills the third through-hole 43, such as Figure 3F As shown.
[0110] In some embodiments, the specific steps for forming the barrier layer 44 that fills the third through-hole 43 include:
[0111] An insulating material is deposited along the first opening 421 into the third through-hole 43, forming a barrier layer 44 in the first region 21.
[0112] Specifically, insulating materials such as nitrides (e.g., silicon nitride) can be deposited along the first opening 421 into the third via 43 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form the barrier layer 44 for electrically isolating adjacent gate layers. Then, a chemical mechanical polishing (CMP) process is used to remove all remaining first filler layers 42 and the remaining barrier layer 44 from the top surface of the semiconductor layer, exposing the top surface of the semiconductor layer. Next, an insulating material such as oxide (e.g., silicon dioxide) is deposited again on the top surface of the first region 21 of the semiconductor layer and the top surface of the barrier layer 44 to form a first capping layer 45 covering the top surface of the first region 21 of the semiconductor layer and the top surface of the barrier layer 44, such as... Figure 3F As shown.
[0113] Step S16: Remove the first filling layer 42 to expose the channel region 23, as shown. Figure 3I As shown.
[0114] In some embodiments, before exposing the channel region 23, the following steps are further included:
[0115] A support layer 56 is formed in the second region 22 of the semiconductor layer, such as Figure 3G As shown.
[0116] Specifically, in order to prevent tilting or collapse during the exposure of the trench area 23, the support layer 56 is formed in the second area 22 connected to the first area 21 before the trench area 23 is exposed, so as to support the first area 21 and improve the structural stability of the first area 21.
[0117] In some embodiments, the specific steps of forming a support layer 56 in the second region 22 of the semiconductor layer include:
[0118] A second filling layer 52 is formed, filling the top surface of the second region 22 of the semiconductor layer and covering the fourth through-hole 38 and the fifth through-hole 39, as shown below. Figure 3C As shown;
[0119] Remove the second isolation pillar 40 and form a sixth through hole 53 in the second filling layer 52, such as Figure 3E As shown;
[0120] A first sacrificial layer 54 is formed within the sixth through hole 53, such as Figure 3F As shown;
[0121] Remove the second filling layer 52 inside the fourth through hole 38 and the fifth through hole 39 to expose the fourth through hole 38 and the fifth through hole 39;
[0122] A portion of the second sub-semiconductor layer 32 located in the second region 22 is removed along the fourth through-hole 38 and the fifth through-hole 39 to form a first void region located between adjacent first sub-semiconductor layers 31;
[0123] A supporting layer 56 is formed by filling the fourth through hole 38, the fifth through hole 39, and the first void region with a medium material, such as Figure 3G As shown.
[0124] Specifically, an oxide material (e.g., silicon dioxide) can be deposited in the fourth via 38 and the fifth via 39 using atomic layer deposition (ALD) technology, covering the top surface of the second region 22 of the semiconductor layer, to form the second filling layer 52. Figure 3C As shown. In one embodiment, the filling steps of the fourth through-hole 38 and the fifth through-hole 39 can be performed simultaneously with the filling steps of the first through-hole 34 and the second through-hole 35, that is, the first filling layer 42 and the second filling layer 52 are formed synchronously. After the second filling layer 52 is formed, the second filling layer 52 is patterned to form a second opening 521 in the second filling layer 52 that exposes the top surface of the second isolation post 40, as shown. Figure 3DAs shown. Then, the second isolation post 40 is removed by self-alignment along the second opening 521, in the sixth through hole 53 of the second filling layer 52, as shown. Figure 3E As shown. Next, an insulating dielectric material such as a nitride (e.g., silicon nitride) is deposited into the sixth via 53 along the second opening 521 to form a first sacrificial layer 54. After removing the second filler layer and the remaining first sacrificial layer 54 on the top surface of the second region of the semiconductor layer by a chemical mechanical polishing process, an insulating material such as an oxide (e.g., silicon dioxide) is deposited again on the top surface of the second region 22 of the semiconductor layer and the top surface of the first sacrificial layer 54 to form a second capping layer 55 covering the top surface of the second region 22 of the semiconductor layer and the top surface of the first sacrificial layer 54, as shown. Figure 3F As shown. Then, the second filling layer 52 is removed by etching, exposing the fourth via 38 and the fifth via 39. A portion of the second sub-semiconductor layer 32 located in the second region 22 is removed along the fourth via 38 and the fifth via 39, forming a first void region located between adjacent first sub-semiconductor layers 31. Subsequently, a dielectric material such as a nitride (e.g., silicon nitride) is filled in the fourth via 38, the fifth via 39, and the first void region to form a support layer 56, such as... Figure 3G As shown.
[0125] In some embodiments, the specific steps for exposing the channel region 23 include:
[0126] Remove the first filling layer 42 located in the first through hole 34 and the second through hole 35 to expose the first through hole 34 and the second through hole 35;
[0127] The second sub-semiconductor layer 32 located in the first region 21 is removed along the first through hole 34 and the second through hole 35 to form a second void region 47 located between two adjacent first sub-semiconductor layers 31;
[0128] A second sacrificial layer 46 is formed, filling the first through-hole 34, the second through-hole 35, and the second void region 47, as shown below. Figure 3H As shown;
[0129] Remove the second sacrificial layer 46 to expose the channel region 23, the first through-hole 34, the second through-hole 35, and the second void region 47, as shown. Figure 3I As shown.
[0130] Specifically, the first filling layer 42, located within the first via 34 and the second via 35, and covering the top surface of the first region of the semiconductor layer, is first removed by an etching process, exposing the first via 34 and the second via 35. Next, a wet etching process is used to remove the second sub-semiconductor layer 32 located in the first region 21 along the first via 34 and the second via 35, forming a second gap region 47 between two adjacent first sub-semiconductor layers 31. To simultaneously form an isolation layer (e.g., a bit line isolation layer for electrically isolating adjacent bit lines) in the third region 20, after forming the second gap region 47, the gate layer is not formed directly. Instead, a second sacrificial layer 46 is first formed, filling the first via 34, the second via 35, and the second gap region 47, and covering the semiconductor layer in the third region 20. Figure 3H As shown. The second sacrificial layer 46 is used to form an isolation layer in the third region 20. Then, the second sacrificial layer 46 located in the first region 21 is removed again, exposing the channel region 23, the first via 34, the second via 35, and the second void region 47, as shown. Figure 3I As shown.
[0131] Step S17, forming a gate layer 48 covering the surface of the channel region 23, such as Figure 3J As shown.
[0132] In some embodiments, the specific steps of forming the gate layer 48 covering the surface of the channel region 23 include:
[0133] The gate layer 48 is formed to fill the first via 34, the second via 35 and the second void region 47.
[0134] In some embodiments, the specific steps of forming the gate layer 48 that fills the first via 34, the second via 35, and the second void region 47 include:
[0135] A gate dielectric layer 49 is formed covering the surface of the channel region 23;
[0136] The gate layer 48 is formed to fill the first via 34, the second via 35, and the second void region 47, and to cover the surface of the gate dielectric layer 49, as follows: Figure 3J As shown.
[0137] In some embodiments, the material of the first sub-semiconductor layer 31 is silicon; the specific steps for forming the gate dielectric layer 49 covering the surface of the channel region 23 include:
[0138] The surface of the channel region 23 is oxidized in situ to form the gate dielectric layer 49.
[0139] The following explanation uses silicon as an example of the material of the first sub-semiconductor layer 31. For example, in the formation of such... Figure 3I Following the structure shown, the surface of the channel region 23 is oxidized using an in-situ oxidation process (e.g., an in-situ water vapor generation process) to form the gate dielectric layer 49. Then, an atomic layer deposition process is used to deposit conductive materials such as tungsten along the first via 34 and the second via 35 to form the gate layer 48, which fills the first via 34, the second via 35, and the second void region 47, and covers the surface of the gate dielectric layer 49. Figure 3J As shown.
[0140] In some embodiments, the barrier layer 44 is a single-layer structure. In other embodiments, the step of forming the barrier layer 44 that fills the third through-hole 43 specifically includes:
[0141] A first sub-barrier layer 441 is formed, filling the third through-hole 43;
[0142] The first sub-barrier layer 441 is etched to form an etched hole extending in a direction perpendicular to the top surface of the substrate 30;
[0143] A second sub-barrier layer 442 is formed within the etched hole.
[0144] In some embodiments, the material of the second sub-barrier layer 442 is a nitride material, and the material of the first sub-barrier layer 441 is an oxide material.
[0145] In some embodiments, the second sub-blocking layer 442 is located within the first sub-blocking layer 441.
[0146] Specifically, since the third via 43 is formed by a self-aligned etching process before the gate layer 48 is formed, and the barrier layer 44 is formed by filling the third via 43, the range of materials that can be selected for the barrier layer 44 is expanded, and a multilayer barrier layer structure can be formed. This improves the electrical isolation performance of the barrier layer while reducing the parasitic capacitance inside the barrier layer. The material of the first sub-barrier layer 441 can be, but is not limited to, a nitride (e.g., silicon nitride) material, and the material of the second sub-barrier layer 442 can be, but is not limited to, an oxide (e.g., silicon dioxide) material. Figure 3K A schematic diagram of the structure of a memory including the first sub-blocking layer 441 and the second sub-blocking layer 442 is shown.
[0147] In another embodiment, the barrier layer may further include a first sub-barrier layer and a second sub-barrier layer located between two adjacent gate layers 48 and arranged along the second direction b-b', wherein the material of the first sub-barrier layer is different from the material of the second sub-barrier layer.
[0148] This specific embodiment also provides a memory. (See attached image) Figure 4 This is a cross-sectional schematic diagram of the memory in a specific embodiment of this disclosure, attached. Figure 5 This is another cross-sectional schematic diagram of the memory in a specific embodiment of this disclosure. The memory provided in this specific embodiment can be adopted as follows: Figures 1-2 , Figures 3A-3K The memory is formed using the method shown. For example... Figure 2 , Figures 3A-3K , Figure 4 and Figure 5 As shown, the memory includes:
[0149] Substrate 30;
[0150] Multiple channel regions 60 are located above the substrate 30. The multiple channel regions 60 are arranged in parallel along a direction parallel to the top surface of the substrate 30. Each channel region 60 includes multiple channel regions 23 arranged in parallel along a direction perpendicular to the top surface of the substrate 30.
[0151] Multiple barrier layers 44 are located above the substrate 30 and between two adjacent groups of the channel regions 60;
[0152] A plurality of gate layers 48 are located above the substrate 30, each gate layer 48 being located between at least one barrier layer 44 and one channel region group 60 and covering the surface of all the channel regions 23 in one channel region group 60, and the gate layers 48 located on opposite sides of one barrier layer 44 having equal thickness.
[0153] In some embodiments, the barrier layer 44 is a single-layer structure, such as... Figure 4 As shown; or,
[0154] The barrier layer 44 has a multi-layer structure.
[0155] In some embodiments, the barrier layer 44 includes:
[0156] The first sub-blocking layer 441 extends in a direction perpendicular to the top surface of the substrate 30 and covers the surface of the gate layer 48;
[0157] The second sub-barrier layer 442 extends in a direction perpendicular to the top surface of the substrate 30 and is sandwiched inside the first sub-barrier layer 441, such as... Figure 5 As shown.
[0158] In some embodiments, the first sub-barrier layer 441 is made of an oxide material, and the second sub-barrier layer is made of a nitride material.
[0159] In some embodiments, the gate layer 48 includes:
[0160] The first portion 481 extends in a direction perpendicular to the top surface of the substrate 30 and continuously covers the sidewalls of all the channel regions 23 in the same channel region group 60. The first portion 481 of the two gate layers 48 located on opposite sides of a barrier layer 44 has the same thickness.
[0161] The second part 482 connects to the first part 481 and is located between two adjacent channel areas 23 within the same channel area group 60.
[0162] In some embodiments, the memory further includes:
[0163] A gate dielectric layer 49 covers the surface of the channel region 23, and a gate layer 48 covers the surface of the gate dielectric layer 49.
[0164] In some embodiments, the memory further includes:
[0165] The source and drain regions are distributed on opposite sides of the channel region 23;
[0166] A capacitor is connected to the drain region;
[0167] Bit lines connect the source region.
[0168] The memory and its formation method provided in some embodiments of this disclosure form a first isolation structure between adjacent active pillars while etching an active pillar in a semiconductor layer. The first isolation structure includes a first via, a second via, and a first isolation pillar located between the first and second vias. Then, before forming the gate layer, a barrier layer is formed by self-aligned exposure etching of the first isolation structure. This expands the material selection range for the barrier layer, simplifies the memory manufacturing process, and helps improve the isolation effect between adjacent gate layers, reducing the capacitive coupling effect between adjacent gate layers. Furthermore, some embodiments of this disclosure form the first isolation structure including the first isolation pillar simultaneously with the etching of the active pillars, and subsequently form the barrier layer using a self-aligned process. This avoids errors caused by photolithographic alignment, thereby reducing the thickness difference between adjacent gate layers and improving the thickness uniformity among the multiple gate layers within the memory.
[0169] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a memory, characterized in that, Includes the following steps: Forming a substrate and a semiconductor layer on the substrate; The semiconductor layer is patterned to form a plurality of first isolation structures. The portion of the semiconductor layer remaining between two adjacent first isolation structures forms a channel region. The first isolation structure includes a first via and a second via that penetrate the semiconductor layer in a direction perpendicular to the top surface of the substrate, and a first isolation pillar formed by the semiconductor layer remaining between the first via and the second via. A first filling layer is formed that fills the first through hole and the second through hole; Remove the first isolation pillar to form a third through-hole located in the first filler layer; A barrier layer is formed that fills the third through-hole; Remove the first filler layer to expose the channel region; A gate layer is formed covering the surface of the channel region; The gate layers located on opposite sides of the barrier layer have equal thickness.
2. The method for forming a memory according to claim 1, characterized in that, The specific steps for forming the substrate and the semiconductor layer on the substrate include: Provide substrate; The semiconductor layer is formed by alternately depositing a first sub-semiconductor layer and a second sub-semiconductor layer on the top surface of the substrate in a direction perpendicular to the top surface of the substrate.
3. The method for forming a memory according to claim 2, characterized in that, The specific steps for patterning the semiconductor layer include: The semiconductor layer is etched to form a plurality of first isolation structures that extend along a first direction and are parallel to each other. Each first isolation structure includes a first isolation pillar and a first via and a second via distributed on opposite sides of the first isolation pillar along a second direction. The first sub-semiconductor layer remaining between two adjacent first isolation structures forms a channel region. The first direction is a direction parallel to the top surface of the substrate, and the second direction is a direction parallel to the top surface of the substrate and intersecting the first direction.
4. The method for forming a memory according to claim 3, characterized in that, Along the second direction, the width of the first through hole is equal to the width of the second through hole.
5. The method for forming a memory according to claim 3, characterized in that, The semiconductor layer includes a first region and a second region distributed outside the first region along the first direction; The specific steps for etching the semiconductor layer include: The first region and the second region of the semiconductor layer are etched to form a plurality of first isolation structures and a plurality of channel regions in the first region, and a plurality of second isolation structures are formed in the second region. The semiconductor layer remaining between two adjacent second isolation structures forms a virtual channel region. The second isolation structure includes a fourth via and a fifth via that penetrate the semiconductor layer in a direction perpendicular to the top surface of the substrate, and a second isolation pillar formed by the semiconductor layer remaining between the fourth via and the fifth via.
6. The method for forming a memory according to claim 5, characterized in that, Along the second direction, the width of the first isolation post is smaller than the width of the trench area.
7. The method for forming a memory according to claim 5, characterized in that, The specific steps for forming the third through-hole located in the first filling layer include: The first filling layer located on the top surface of the first region of the semiconductor layer is etched to form a first opening that exposes the first isolation pillar; The first isolation post is removed along the first opening, forming the third through hole in the first region.
8. The method for forming a memory according to claim 7, characterized in that, Along the second direction, the width of the first opening is greater than or equal to the width of the first isolation post.
9. The method for forming a memory according to claim 7, characterized in that, The specific steps for forming the barrier layer that fills the third through-hole include: An insulating material is deposited along the first opening into the third through-hole to form a barrier layer in the first region.
10. The method for forming a memory according to claim 5, characterized in that, Before exposing the trench area, the following steps are also included: A support layer is formed in the second region of the semiconductor layer.
11. The method for forming a memory according to claim 10, characterized in that, The specific steps for forming a support layer in the second region of the semiconductor layer include: A second filling layer is formed, which fills the top surface of the second region of the semiconductor layer and covers the fourth and fifth through holes. Remove the second isolation column to form a sixth through hole in the second filling layer; A first sacrificial layer is formed within the sixth through hole; Remove the second filling layer inside the fourth through hole and the fifth through hole to expose the fourth through hole and the fifth through hole; A portion of the second sub-semiconductor layer located in the second region is removed along the fourth and fifth vias to form a first void region located between adjacent first sub-semiconductor layers; A supporting layer is formed by filling the fourth through hole, the fifth through hole, and the first void region with a medium material.
12. The method for forming a memory according to claim 5, characterized in that, The specific steps for exposing the trench area include: Remove the first filler layer located in the first through hole and the second through hole to expose the first through hole and the second through hole; The second sub-semiconductor layer located in the first region is removed along the first via and the second via to form a second void region located between two adjacent first sub-semiconductor layers. A second sacrificial layer is formed that fills the first through-hole, the second through-hole, and the second void region; Remove the second sacrificial layer to expose the channel region, the first via, the second via, and the second void region.
13. The method for forming a memory according to claim 12, characterized in that, The specific steps for forming a gate layer covering the surface of the channel region include: The gate layer is formed to fill the first via, the second via, and the second void region.
14. The method for forming a memory according to claim 13, characterized in that, The specific steps for forming the gate layer that fills the first via, the second via, and the second void region include: A gate dielectric layer is formed covering the surface of the channel region; The gate layer is formed to fill the first via, the second via, and the second void region, and to cover the surface of the gate dielectric layer.
15. The method for forming a memory according to claim 14, characterized in that, The material of the first sub-semiconductor layer is silicon; The specific steps for forming the gate dielectric layer covering the surface of the channel region include: The surface of the channel region is oxidized in situ to form the gate dielectric layer.
16. The method for forming a memory according to claim 1, characterized in that, The steps for forming a barrier layer that fills the third through-hole specifically include: A first sub-barrier layer is formed, filling the third through-hole; The first sub-barrier layer is etched to form an etched hole extending in a direction perpendicular to the top surface of the substrate; A second sub-barrier layer is formed within the etched hole.
17. The method for forming a memory according to claim 16, characterized in that, The material of the second sub-barrier layer is a nitride material, and the material of the first sub-barrier layer is an oxide material.
18. The method for forming a memory according to claim 16, characterized in that, The second sub-barrier layer is located within the first sub-barrier layer.
19. A memory formed using the method for forming a memory according to any one of claims 1-18, characterized in that, include: Substrate; Multiple channel regions are located above the substrate and are arranged in parallel along a direction parallel to the top surface of the substrate. Each channel region includes multiple channel regions arranged in parallel along a direction perpendicular to the top surface of the substrate. Multiple barrier layers, the barrier layers being located above the substrate and between two adjacent groups of the channel regions; A plurality of gate layers are located above the substrate, each gate layer being located between at least one barrier layer and one group of channel regions and covering the surface of all the channel regions in one group of channel regions, wherein the gate layers on opposite sides of one barrier layer have equal thickness.
20. The memory according to claim 19, characterized in that, The barrier layer is a single-layer structure; or... The barrier layer has a multi-layer structure.
21. The memory according to claim 19, characterized in that, The barrier layer includes: The first sub-blocking layer extends in a direction perpendicular to the top surface of the substrate and covers the surface of the gate layer; The second sub-barrier layer extends in a direction perpendicular to the top surface of the substrate and is sandwiched inside the first sub-barrier layer.
22. The memory according to claim 21, characterized in that, The first sub-barrier layer is made of an oxide material, and the second sub-barrier layer is made of a nitride material.
23. The memory according to claim 19, characterized in that, The gate layer includes: The first portion extends in a direction perpendicular to the top surface of the substrate and continuously covers the sidewalls of all the channel regions in the same group of channel regions. The first portions of the two gate layers located on opposite sides of a barrier layer have equal thickness. The second part connects to the first part and is located between two adjacent channel areas within the same channel area group.
24. The memory according to claim 19, characterized in that, Also includes: A gate dielectric layer covers the surface of the channel region, and a gate layer covers the surface of the gate dielectric.
25. The memory according to claim 19, characterized in that, Also includes: The source and drain regions are distributed on opposite sides of the channel region; A capacitor is connected to the drain region; Bit lines connect the source region.