Pixel unit, display panel and display device

Abstract

The application provides a pixel unit, which comprises a plurality of sub-pixel units, each of which comprises a liquid crystal capacitor and a potential adjusting unit, a second end of a switch unit is electrically connected with a first end of the liquid crystal capacitor and a first end of the potential adjusting unit, a second end of the liquid crystal capacitor is electrically connected with a first common voltage terminal, and a second end and a control terminal of the potential adjusting unit are electrically connected with a second common voltage terminal. The control terminal of the potential adjusting unit receives an electrical signal output by the second common voltage terminal to make the first end of the liquid crystal capacitor conduct with the second common voltage terminal, so as to adjust the potential of the first end of the liquid crystal capacitor. Therefore, in a frame time, with the increase of time, the potential of the first end of the liquid crystal capacitor dynamically changes, so that the deflection angle of the liquid crystal molecules in the liquid crystal capacitor also dynamically changes, so that the color difference under different viewing angles is smaller, thereby improving the viewing angle deviation. The application further provides a display panel and a display device.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a pixel unit, a display panel having the pixel unit, and a display device having the display panel. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in the display industry due to their advantages such as thinness, energy efficiency, no radiation, and soft image quality. However, with the development of LCD technology, the size of LCD devices is increasing, making the problem of color shift during viewing more prominent.

[0003] Currently, the solution to viewing angle color shift (GAS) involves dividing subpixels into main pixel regions and subpixel regions. The driving voltages of the main pixel regions and subpixel regions are different, resulting in different deflection angles of the liquid crystal molecules in the main pixel regions and the subpixel regions. This reduces color differences at different viewing angles, thus improving GAS. However, the current solution of improving GAS by adjusting the driving voltages of the main pixel regions and subpixel regions is not ideal.

[0004] Therefore, how to further improve the viewing angle bias of liquid crystal display devices is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a pixel unit, a display panel having the pixel unit, and a display device having the display panel, which aims to solve the problem of viewing angle distortion in liquid crystal display devices.

[0006] To address the aforementioned technical problems, this application provides a pixel unit comprising multiple sub-pixel units. Each sub-pixel unit includes a switching unit, a liquid crystal capacitor, and a potential adjustment unit. The control terminal of the switching unit receives a scanning signal, and the first terminal of the switching unit receives a data signal. The second terminal of the switching unit is electrically connected to the first terminal of the liquid crystal capacitor and the first terminal of the potential adjustment unit. The second terminal of the liquid crystal capacitor is electrically connected to a first common voltage terminal. The second terminal and the control terminal of the potential adjustment unit are both electrically connected to a second common voltage terminal. The control terminal of the potential adjustment unit receives an electrical signal output from the second common voltage terminal to connect the first terminal of the liquid crystal capacitor to the second common voltage terminal, thereby adjusting the potential of the first terminal of the liquid crystal capacitor.

[0007] In summary, the pixel unit provided in this application includes multiple sub-pixel units. Each sub-pixel unit includes a switching unit, a liquid crystal capacitor, and a potential adjustment unit. The control terminal of the potential adjustment unit receives an electrical signal output from the second common voltage terminal, causing the first terminal of the liquid crystal capacitor to conduct with the second common voltage terminal, thereby adjusting the potential of the first terminal of the liquid crystal capacitor. Therefore, within one frame, the potential of the first terminal of the liquid crystal capacitor is a dynamically changing value as time increases, causing the deflection angle of the multiple liquid crystal molecules within the liquid crystal capacitor to also change dynamically. This results in smaller color differences under different viewing angles, thereby improving viewpoint color shift.

[0008] In an exemplary embodiment, the electrical signal output from the second common voltage terminal is a DC electrical signal.

[0009] In an exemplary embodiment, the potential adjustment unit includes a first adjustment transistor, which includes a first source, a first drain, and a first gate. The first drain is electrically connected to a first terminal of the liquid crystal capacitor, and both the first source and the first gate are electrically connected to a second common voltage terminal.

[0010] In an exemplary embodiment, the potential adjustment unit includes a first adjustment transistor, which includes a first source, a first drain, and a first gate. The first source is electrically connected to a first terminal of the liquid crystal capacitor, and both the first drain and the first gate are electrically connected to a second common voltage terminal.

[0011] In an exemplary embodiment, the channel length of the first regulating transistor is 0.5µm to 1µm, and the channel width of the first regulating transistor is 7.5µm to 15µm.

[0012] In an exemplary embodiment, the potential adjustment unit includes a first adjustment transistor and a second adjustment transistor. The first adjustment transistor includes a first source, a first drain, and a first gate. The second adjustment transistor includes a second source, a second drain, and a second gate. The first source and the first gate are both electrically connected to the second common voltage terminal. The first drain and the second drain are electrically connected. The second source and the second gate are both electrically connected to the first terminal of the liquid crystal capacitor.

[0013] In an exemplary embodiment, the potential adjustment unit includes a first adjustment transistor and a second adjustment transistor. The first adjustment transistor includes a first source, a first drain, and a first gate. The second adjustment transistor includes a second source, a second drain, and a second gate. The first drain and the first gate are both electrically connected to the second common voltage terminal. The first source and the second source are electrically connected. The second drain and the second gate are both electrically connected to the first terminal of the liquid crystal capacitor.

[0014] In an exemplary embodiment, the channel length of the first regulating transistor is 0.5 μm to 1 μm, and the channel width of the first regulating transistor is 7.5 μm to 15 μm. The channel length of the second regulating transistor is 0.5 μm to 1 μm, and the channel width of the second regulating transistor F2 is 6 μm to 12 μm.

[0015] Based on the same inventive concept, this application also provides a display panel, which includes a plurality of scan lines, a plurality of data lines and a plurality of the above-mentioned pixel units, each pixel unit including a plurality of sub-pixel units, the sub-pixel units being electrically connected to the scan lines and the data lines respectively.

[0016] In summary, the display panel provided in this application includes multiple scan lines, multiple data lines, and multiple pixel units. Each pixel unit includes multiple sub-pixel units, each sub-pixel unit comprising a switching unit, a liquid crystal capacitor, and a potential adjustment unit. The control terminal of the potential adjustment unit receives an electrical signal output from the second common voltage terminal, causing the first terminal of the liquid crystal capacitor to conduct with the second common voltage terminal, thereby adjusting the potential of the first terminal of the liquid crystal capacitor. Therefore, within one frame, the potential of the first terminal of the liquid crystal capacitor is a dynamically changing value as time increases, causing the deflection angle of the multiple liquid crystal molecules within the liquid crystal capacitor to also change dynamically, resulting in smaller color differences at different viewing angles and thus improving viewing angle distortion.

[0017] Based on the same inventive concept, this application also provides a display device, which includes a scanning driving circuit, a data driving circuit, and the aforementioned display panel, wherein the display panel is electrically connected to the scanning driving circuit and the data driving circuit respectively.

[0018] In summary, the display device provided in this application includes a scan driving circuit, a data driving circuit, and the aforementioned display panel. The display panel includes multiple scan lines, multiple data lines, and multiple pixel units. Each pixel unit includes multiple sub-pixel units, and each sub-pixel unit includes a switching unit, a liquid crystal capacitor, and a potential adjustment unit. The control terminal of the potential adjustment unit receives an electrical signal output from the second common voltage terminal, causing the first terminal of the liquid crystal capacitor to conduct with the second common voltage terminal, thereby adjusting the potential of the first terminal of the liquid crystal capacitor. Therefore, within one frame, as time increases, the potential of the first terminal of the liquid crystal capacitor is a dynamically changing value, causing the deflection angle of the multiple liquid crystal molecules within the liquid crystal capacitor to also change dynamically, resulting in smaller color differences at different viewing angles, thereby improving viewing angle color shift. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the display device disclosed in the first embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the circuit structure of the display panel disclosed in the second embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the first circuit structure of the sub-pixel unit disclosed in the third embodiment of this application;

[0023] Figure 4 This is a schematic diagram showing the change of the potential at the first end of the liquid crystal capacitor of the sub-pixel unit in one frame for the first circuit structure disclosed in the third embodiment of this application.

[0024] Figure 5 This is a schematic diagram of the second circuit structure of the sub-pixel unit disclosed in the third embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of the sub-pixel unit disclosed in the third embodiment of this application;

[0026] Figure 7 for Figure 6 An enlarged schematic diagram of structure VI in the sub-pixel unit shown;

[0027] Figure 8 for Figure 7 A schematic cross-sectional view of the first via of the sub-pixel unit shown;

[0028] Figure 9 for Figure 7 A schematic cross-sectional view of the second via of the sub-pixel unit shown;

[0029] Figure 10 for Figure 7 A schematic diagram of the layer structure of a switching transistor;

[0030] Figure 11 for Figure 7 A schematic diagram of the layer structure of the first regulating transistor;

[0031] Figure 12 This is a schematic diagram of the first circuit structure of the sub-pixel unit disclosed in the fourth embodiment of this application;

[0032] Figure 13 This is a schematic diagram showing the change of the potential at the first end of the liquid crystal capacitor of the sub-pixel unit in the first circuit structure disclosed in the fourth embodiment of this application within one frame.

[0033] Figure 14 This is a schematic diagram of the second circuit structure of the sub-pixel unit disclosed in the fourth embodiment of this application;

[0034] Figure 15 This is a schematic diagram of the structure of the sub-pixel unit disclosed in the fourth embodiment of this application;

[0035] Figure 16 for Figure 15 An enlarged schematic diagram of structure XII in the sub-pixel unit shown;

[0036] Figure 17 for Figure 16 A schematic diagram of the layer structure of the second regulating transistor.

[0037] Explanation of reference numerals in the attached figures:

[0038] 001 - First direction; 002 - Second direction; 100 - Display device; 110 - Display panel; 110a - Display area; 110b - Non-display area; 111 - Potential adjustment unit; 111a - First active layer; 111b - First source; 111c - First drain; 111d - First gate; 112a - Second active layer; 112b - Second source; 112c - Second drain; 112d - Second gate; 113 - Switching unit; 113a - Third active layer; 113b - Third source; 113c - Third drain; 113d - Third gate; 115 - Pixel electrode; 116 - Array substrate Common electrode; 117-First connecting electrode; 118-Second connecting electrode; 130-Scan driving circuit; 140-Data driving circuit; 160-Timing control circuit; 210-Array substrate; 211-Substrate; 212-Gate insulating layer; 213-Insulating protective layer; DL-Scan line; GL-Data line; SP-Sub-pixel unit; Clc-Liquid crystal capacitor; Cst-Storage capacitor; Ccom-First common voltage terminal; Acom-Second common voltage terminal; F1-First regulating transistor; F2-Second regulating transistor; T-Switch transistor; H1-First via; H2-Second via; H3-Third via. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0040] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.

[0041] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joint" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding disclosed function, operation, element, etc., and do not limit one or more other functions, operations, elements, etc. Moreover, the terms "comprising" or "include" indicate the presence of the corresponding features, number, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, number, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. It is also important to understand that “at least one” as described in this article means one or more, such as one, two or three, while “multiple” means at least two, such as two or three, unless otherwise explicitly specified.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the display device disclosed in the first embodiment of this application. The display device 100 provided in this embodiment may include a display panel 110, a scan driving circuit 130, a data driving circuit 140, and a timing control circuit 160, wherein the display panel 110 is electrically connected to the scan driving circuit 130 and the data driving circuit 140 respectively, and the timing control circuit 160 is electrically connected to the scan driving circuit 130 and the data driving circuit 140 respectively.

[0044] Specifically, the scan driving circuit 130 is used to output a scan signal to the display panel 110, and the data driving circuit 140 is used to output a data signal to the display panel 110. The timing control circuit 160 is used to output a timing control signal to the scan driving circuit 130 to control when the scan driving circuit 130 outputs the scan signal to the display panel 110. The timing control circuit 160 is also used to output a timing control signal to the data driving circuit 140 to control when the data driving circuit 140 outputs the data signal to the display panel 110.

[0045] Understandably, the display device 100 can be used in electronic devices including but not limited to televisions, tablets, laptops, desktop computers, mobile phones, in-vehicle displays, smartwatches, smart bracelets, and smart glasses. According to embodiments of this application, the specific type of the display device 100 is not particularly limited, and those skilled in the art can design it accordingly based on the specific usage requirements of the display device 100; further details will not be elaborated here.

[0046] In an exemplary embodiment, the display device 100 may also include other necessary components and parts such as a power board, a high voltage board, and a button control board. Those skilled in the art can make corresponding additions according to the specific type and actual function of the display device 100, which will not be elaborated here.

[0047] In this embodiment of the application, the display panel 110 may be a Twisted Nematic (TN) display panel, a Vertical Alignment (VA) display panel, an In-Plane Switching (IPS) display panel, or a Fringe Field Switching (FFS) display panel. This application does not impose any specific limitations on this.

[0048] In an exemplary embodiment, the display panel 110 may further include a display area 110a and a non-display area 110b disposed around or partially around the display area 110a. The display area 110a is used to display an image, and the non-display area 110b is configured with corresponding driving circuitry to control the display area 110a to display the image.

[0049] Please see Figure 2 , Figure 2This is a schematic diagram of the circuit structure of the display panel disclosed in the second embodiment of this application. In this embodiment, the display panel 110 includes multiple scan lines GL, multiple data lines DL, and multiple sub-pixel units SP. The multiple scan lines GL extend along a first direction 001 and are arranged in parallel intervals along a second direction 002. The multiple data lines DL extend along the second direction 002 and are arranged in parallel intervals along the first direction 001. The sub-pixel units SP are disposed between two adjacent scan lines GL and two adjacent data lines DL. The sub-pixel units SP are electrically connected to the scan lines GL and the data lines DL, respectively. The scan lines GL are also electrically connected to the scan driving circuit 130, and the data lines DL are also electrically connected to the data driving circuit 140. The scan signal output by the scan driving circuit 130 is transmitted to the sub-pixel unit SP through the scan lines GL, and the data signal output by the data driving circuit 140 is transmitted to the sub-pixel unit SP through the data lines DL.

[0050] It is understood that one scan line GL intersects with and is insulated from multiple data lines DL, and one data line DL intersects with and is insulated from multiple scan lines GL, i.e., the multiple scan lines GL and multiple data lines DL are arranged in a grid pattern. One sub-pixel unit SP is electrically connected to one scan line GL and one data line DL. Specifically, a sub-pixel unit SP is disposed between any two adjacent scan lines GL and any two adjacent data lines DL; sub-pixel units SP located in the same column are all electrically connected to the same data line DL; and sub-pixel units SP located in the same row are all electrically connected to the same scan line GL. In this embodiment, the multiple sub-pixel units SP are arranged in an array.

[0051] In an exemplary embodiment, the first direction 001 is perpendicular to the second direction 002, the plurality of scan lines GL are arranged at intervals and are insulated from each other, and the plurality of data lines DL are arranged at intervals and are insulated from each other.

[0052] In this embodiment, three sub-pixel units SP arranged sequentially along the first direction 001 constitute a pixel unit, and the three sub-pixel units SP can emit red light, green light, and blue light respectively, enabling the pixel unit to display color. That is, the display panel 110 includes multiple pixel units, and each pixel unit includes three sub-pixel units SP. In other embodiments, each pixel unit may include multiple sub-pixel units SP.

[0053] Please see Figure 3 , Figure 3This is a schematic diagram of the first circuit structure of the sub-pixel unit disclosed in the third embodiment of this application. In this embodiment, the sub-pixel unit SP includes a liquid crystal capacitor Clc and a potential adjustment unit 111. The first terminal of the liquid crystal capacitor Clc is electrically connected to the first terminal of the potential adjustment unit 111, and the second terminal of the liquid crystal capacitor Clc is electrically connected to a first common voltage terminal Ccom. The second terminal and the control terminal of the potential adjustment unit 111 are both electrically connected to a second common voltage terminal Acom. The control terminal of the potential adjustment unit 111 receives an electrical signal output from the second common voltage terminal Acom, thereby turning on the potential adjustment unit 111, which in turn connects the first terminal of the liquid crystal capacitor Clc to the second common voltage terminal Acom, thereby adjusting the potential of the first terminal of the liquid crystal capacitor Clc. Adjusting the potential of the first terminal of the liquid crystal capacitor Clc means pulling up or down the potential of the first terminal of the liquid crystal capacitor Clc.

[0054] It is understood that the liquid crystal capacitor Clc is an equivalent capacitance, and the liquid crystal capacitor Clc contains multiple liquid crystal molecules. Within one frame, as time increases, the potential at the first end of the liquid crystal capacitor Clc decreases or increases, causing the deflection angle of the multiple liquid crystal molecules within the liquid crystal capacitor Clc to decrease or increase, thereby reducing color differences at different viewing angles and improving viewing angle color shift. In other words, the technical solution of this application achieves that the sub-pixel SP has N domains (temporal domain) within one frame. Increasing the number of domains is beneficial to improving the viewing angle color shift of the display panel.

[0055] In an exemplary embodiment, the electrical signal output from the second common voltage terminal Acom can be a DC signal. It is understood that having a DC signal output from the second common voltage terminal Acom allows the potential of the first terminal of the liquid crystal capacitor Clc to gradually decrease or gradually increase. This gradual decrease or increase means that the potential change curve of the first terminal of the liquid crystal capacitor Clc is relatively smooth, avoiding flickering on the display panel 110 caused by large potential changes at the first terminal of the liquid crystal capacitor Clc, thus improving the display quality of the display panel 110.

[0056] In this embodiment, the sub-pixel unit SP further includes a switching unit 113. The control terminal of the switching unit 113 is electrically connected to the scan line GL, the first terminal of the switching unit 113 is electrically connected to the data line GL, and the second terminal of the switching unit 113 is electrically connected to the first terminal of the liquid crystal capacitor Clc and the first terminal of the potential adjustment unit 111. Specifically, the control terminal of the switching unit 113 receives the scan signal through the scan line GL, thereby turning on the switching unit 113, which in turn turns on the first terminal of the liquid crystal capacitor Clc and the data line DL. The potential of the data signal on the data line DL is applied to the first terminal of the liquid crystal capacitor Clc. That is, the control terminal of the switching unit 113 receives the scan signal, and the first terminal of the switching unit 113 receives the data signal.

[0057] like Figure 3 As shown in this embodiment, the sub-pixel unit SP further includes a storage capacitor Cst. The first terminal of the storage capacitor Cst is electrically connected to the second terminal of the switching unit 113, the first terminal of the liquid crystal capacitor Clc, and the first terminal of the potential adjustment unit 111. The second terminal of the storage capacitor Cst is electrically connected to the second common voltage terminal Acom. The control terminal of the switching unit 113 receives the scan signal through the scan line GL, thereby turning on the switching unit 113, which in turn connects the first terminal of the storage capacitor Cst to the data line DL. The potential of the data signal on the data line DL is applied to the first terminal of the storage capacitor Cst. When the switching unit 113 is turned off, the storage capacitor Cst discharges to maintain the potential of the first terminal of the liquid crystal capacitor Clc.

[0058] In summary, the pixel unit provided in this application includes multiple sub-pixel units SP, each of which includes a liquid crystal capacitor Clc and a potential adjustment unit 111. The first terminal of the liquid crystal capacitor Clc is electrically connected to the first terminal of the potential adjustment unit 111, and the second terminal of the liquid crystal capacitor Clc is electrically connected to the first common voltage terminal Ccom. The second terminal and control terminal of the potential adjustment unit 111 are both electrically connected to the second common voltage terminal Acom. The control terminal of the potential adjustment unit 111 receives an electrical signal output from the second common voltage terminal Acom and connects the first terminal of the liquid crystal capacitor Clc to the second terminal of the second common voltage terminal Acom to adjust the potential of the first terminal of the liquid crystal capacitor Clc. Therefore, within one frame, the potential of the first terminal of the liquid crystal capacitor Clc is a dynamically changing value as time increases, causing the deflection angle of the multiple liquid crystal molecules within the liquid crystal capacitor Clc to also change dynamically, resulting in smaller color differences at different viewing angles and thus improving viewing angle color shift.

[0059] like Figure 3 As shown in the embodiment of this application, the potential adjustment unit 111 includes a first adjustment transistor F1. The first adjustment transistor F1 includes a first source 111b, a first drain 111c, and a first gate 111d. The first drain 111c can be the first terminal of the potential adjustment unit 111, the first source 111b can be the second terminal of the potential adjustment unit 111, and the first gate 111d is the control terminal of the potential adjustment unit 111. That is, the first drain 111c is electrically connected to the first terminal of the liquid crystal capacitor Clc, and the first source 111b and the first gate 111d are both electrically connected to the second common voltage terminal Acom. The first adjustment transistor F1 can be an N-type MOS transistor. It can be understood that the first adjustment transistor F1 receives the electrical signal transmitted from the second common voltage terminal Acom and conducts.

[0060] In an exemplary embodiment, the channel length of the first regulating transistor F1 can be from 0.5µm to 1µm, for example, 0.5µm, 0.55µm, 0.6µm, 0.72µm, 0.8µm, 0.9µm, 1µm, or other values, and this application does not impose specific limitations on it. The channel width of the first regulating transistor F1 can be from 7.5µm to 15µm, for example, 7.5µm, 9.5µm, 10µm, 12.6µm, 14µm, 15µm, or other values, and this application does not impose specific limitations on it.

[0061] like Figure 3 As shown in the embodiment of this application, the switching unit 113 includes a switching transistor T, which includes a third source 113b, a third drain 113c, and a third gate 113d. The third drain 113c can be the second terminal of the switching unit 113, the third source 113b can be the first terminal of the switching unit 113, and the third gate 113d is the control terminal of the switching unit 113. That is, the third source 113b is connected to the data line DL to achieve electrical connection, the third drain 113c is connected to the first terminal of the liquid crystal capacitor Clc to achieve electrical connection, and the third gate 113d is connected to the scan line GL to achieve electrical connection.

[0062] To verify the feasibility of the technical solution of this application, the simulation settings are as follows: the VGH of the switching transistor T is 30V, the VGL of the switching transistor T is -7V, the channel length of the switching transistor T is 31µm, the channel width of the switching transistor T is 5µm, the potential of the first common voltage terminal Ccom and the potential of the second common voltage terminal Acom are both 7.2V, the channel length of the first regulating transistor F1 is 0.5µm, and the channel width of the first regulating transistor F1 is 10µm. Please refer to [link / reference]. Figure 4 , Figure 4 This diagram illustrates the potential change of the first terminal of the liquid crystal capacitor in the sub-pixel unit of the first circuit structure disclosed in the third embodiment of this application within one frame. Here, Vhold_s(+) refers to the positive frame start potential, Vhold_e(+) refers to the positive frame end potential, Vhold_s(-) refers to the negative frame start potential, and Vhold_e(-) refers to the negative frame end potential. Simulation results show that the positive potential residual rate Ratio(+) is 76.22%, and the negative potential residual rate Ratio(-) is 13.82%. Where Ratio(+) = (Vhold_e(+) - Vcom) / (Vhold_s(+) - Vcom), Ratio(-) = (Vhold_e(-) - Vcom) / (Vhold_s(-) - Vcom), and Vcom = (Vhold_s(+) + Vhold_s(-)) / 2. Figure 4 It can be concluded that when the potential of the first terminal of the liquid crystal capacitor Clc is positive, its potential decreases; when the potential of the first terminal of the liquid crystal capacitor Clc is negative, its potential increases. Therefore, the potential of the first terminal of the liquid crystal capacitor Clc can be adjusted by the potential adjustment unit 111.

[0063] It is understandable that when the potential of the first terminal of the liquid crystal capacitor Clc is positive, the first terminal of the liquid crystal capacitor Clc discharges to the second common voltage terminal Acom, thereby reducing the degree of forward bias of the first regulating transistor F1; when the potential of the first terminal of the liquid crystal capacitor Clc is negative, the discharge of the second common voltage terminal Acom to the first terminal of the liquid crystal capacitor Clc increases the degree of forward bias of the first regulating transistor F1. That is, the resistance of the potential regulating unit 111 in the positive polarity is greater than the resistance of the potential regulating unit 111 in the negative polarity, and thus the positive polarity potential residual rate Ratio(+) is greater than the negative polarity potential residual rate Ratio(-).

[0064] For other embodiments of this application, please refer to Figure 5 , Figure 5This is a schematic diagram of a second circuit structure for a sub-pixel unit disclosed in the third embodiment of this application. The first source 111b can be the first terminal of the potential adjustment unit 111, the first drain 111c can be the second terminal of the potential adjustment unit 111, and the first gate 111d is the control terminal of the potential adjustment unit 111. That is, the first source 111b is electrically connected to the first terminal of the liquid crystal capacitor Clc, and both the first drain 111c and the first gate 111d are electrically connected to the second common voltage terminal Acom. It is understood that when the potential of the first terminal of the liquid crystal capacitor Clc is positive, the first terminal of the liquid crystal capacitor Clc discharges to the second common voltage terminal Acom, thereby increasing the degree of forward bias of the first regulating transistor F1; when the potential of the first terminal of the liquid crystal capacitor Clc is negative, the discharge of the second common voltage terminal Acom to the first terminal of the liquid crystal capacitor Clc reduces the degree of forward bias of the first regulating transistor F1. That is, the resistance of the potential regulating unit 111 when the potential is positive is less than the resistance of the potential regulating unit 111 when the potential is negative, and thus the potential residual rate Ratio(+) of the negative potential is greater than the potential residual rate Ratio(+) of the positive potential.

[0065] In the embodiments of this application, please refer to Figure 6 , Figure 6 This is a schematic diagram of the sub-pixel unit disclosed in the third embodiment of this application. The sub-pixel unit SP includes a pixel electrode 115 and a common electrode (not shown). The pixel electrode 115 and the common electrode constitute the liquid crystal capacitor Clc, that is, the pixel electrode 115 is the first end of the liquid crystal capacitor Clc, and the common electrode is the second end of the liquid crystal capacitor Clc. The sub-pixel unit SP also includes an array substrate common electrode 116, which surrounds the periphery of the pixel electrode 115. The pixel electrode 115 and the array substrate common electrode 116 constitute the storage capacitor Cst, that is, the pixel electrode 115 is the first end of the storage capacitor Cst, and the array substrate common electrode 116 is the second end of the storage capacitor Cst.

[0066] In an exemplary embodiment, the array substrate common electrode 116 of the plurality of sub-pixel units SP is electrically connected so that the electrical signal potential received by the array substrate common electrode 116 is the same.

[0067] Please see Figure 7 , Figure 7 for Figure 6The diagram shows an enlarged view of structure VI in the sub-pixel unit. In this embodiment, the switching transistor T includes a third active layer 113a, a third source 113b, a third drain 113c, and a third gate. The third gate is disposed on the scan line GL, the third active layer 113a is disposed on the third gate, and the third source 113b and the third drain 113c are disposed on the side of the third active layer 113a opposite to the third gate. The third source 113b is connected to the data line DL to achieve electrical connection.

[0068] In an exemplary embodiment, the sub-pixel unit SP further includes a first connection electrode 117, a portion of which is located within a first via H1 and connected to the third drain 113c for electrical connection. The first connection electrode 117 is also connected to the pixel electrode 115 for electrical connection.

[0069] In the embodiments of this application, please refer to Figure 7 The first regulating transistor F1 includes a first active layer 111a, a first source 111b, a first drain 111c, and a first gate. The first gate is disposed on a portion of the array substrate common electrode 116. The first active layer 111a is disposed on the first gate. The first source 111b and the first drain 111c are disposed on the side of the first active layer 111a opposite to the first gate.

[0070] In an exemplary embodiment, the sub-pixel unit SP further includes a second connection electrode 118, a portion of which is located within the second via H2 and connected to the first source electrode 111b for electrical connection. The second connection electrode 118 is also connected to the array substrate common electrode 116 for electrical connection. The first drain electrode 111c is connected to the third drain electrode 113c for electrical connection.

[0071] In the embodiments of this application, please refer to Figure 8 , Figure 8 for Figure 7The diagram shows a cross-sectional view of the first via of the sub-pixel unit. The display panel 110 includes an array substrate 210, which includes a substrate 211, a gate insulating layer 212, and an insulating protective layer 213. The gate insulating layer 212 is disposed on one side of the substrate 211, and the third drain 113c is disposed on the side of the gate insulating layer 212 opposite to the substrate 211. The insulating protective layer 213 covers the third drain 113c on the gate insulating layer 212. A first via H1 is formed in the insulating protective layer 213, through which a portion of the third drain 113c is exposed in the insulating protective layer 213. A first connecting electrode 117 is disposed on the insulating protective layer 213, and a portion of the first connecting electrode 117 is located within the first via H1 and connected to the third drain 113c to achieve electrical connection.

[0072] In the embodiments of this application, please refer to Figure 9 , Figure 9 for Figure 7 The diagram shows a cross-sectional view of the second via of the sub-pixel unit. The array substrate common electrode 116 is disposed on one side of the substrate 211, and the gate insulating layer 212 covers the array substrate common electrode 116 on the substrate 211. The first source electrode 111b is disposed on the side of the gate insulating layer 212 opposite to the array substrate common electrode 116, and the insulating protective layer 213 covers the first source electrode 111b on the gate insulating layer 212. The gate insulating layer 212 has a second via H2 penetrating through it, with a portion of the array substrate common electrode 116 exposed in the second via H2. The insulating protective layer 213 has a third via H3 penetrating through it, and the third via H3 communicates with the second via H2. A portion of the first source electrode 111b is exposed in the third via H3, meaning that a portion of the first source electrode 111b and the insulating protective layer 213 constitute the wall of the third via H3. The second connection electrode 118 is disposed on the insulating protective layer 213, and a portion of the second connection electrode 118 is located within the second via H2 and the third via H3, and is connected to the array substrate common electrode 116 and the first source electrode 111b, so as to electrically connect the array substrate common electrode 116 and the first source electrode 111b.

[0073] In the embodiments of this application, please refer to Figure 10 , Figure 10 for Figure 7A schematic diagram of the layer structure of a switching transistor. The scan line GL is disposed on one side of the substrate 211, the third gate 113d is disposed on the scan line GL, the gate insulating layer 212 covers the scan line GL and the third gate 113d on the substrate 211, the third active layer 113a is disposed on the side of the gate insulating layer 212 opposite to the third gate 113d, the third source 113b and the third drain 113c are disposed on the side of the third active layer 113a opposite to the gate insulating layer 212, and the third source 113b and the third drain 113c are spaced apart, and the insulating protective layer 213 covers the third source 113b, the third drain 113c and the third active layer 113a on the gate insulating layer 212.

[0074] In the embodiments of this application, please refer to Figure 11 , Figure 11 for Figure 7 A schematic diagram of the layer structure of the first regulating transistor is shown. The array substrate common electrode 116 is disposed on one side of the substrate 211. The first gate 111d is disposed on the side of the array substrate common electrode 116 facing away from the substrate 211. The gate insulating layer 212 covers the first gate 111d and the array substrate common electrode 116 on the substrate 211. The first active layer 111a is disposed on the side of the gate insulating layer 212 facing away from the first gate 111d. The first source 111b and the first drain 111c are disposed on the side of the first active layer 111a facing away from the gate insulating layer 212, and the first source 111b and the first drain 111c are spaced apart. The insulating protective layer 213 covers the first source 111b, the first drain 111c and the first active layer 111a on the gate insulating layer 212.

[0075] Please see Figure 12 , Figure 12 This is a schematic diagram of the first circuit structure of the sub-pixel unit disclosed in the fourth embodiment of this application. The difference between the second circuit structure sub-pixel unit and the first circuit structure sub-pixel unit is that the potential adjustment unit 111 of the second circuit structure sub-pixel unit further includes a second adjustment transistor F2. For a description of the similarities between the second circuit structure sub-pixel unit and the first circuit structure sub-pixel unit, please refer to the relevant description of the first circuit structure sub-pixel unit, which will not be repeated here.

[0076] In this embodiment, the potential adjustment unit 111 includes a first adjustment transistor F1 and a second adjustment transistor F2. The first adjustment transistor F1 includes a first source, a first drain, and a first gate; the second adjustment transistor F2 includes a second source, a second drain, and a second gate. Both the first source and the first gate are electrically connected to the second common voltage terminal Acom. The first drain and the second drain are electrically connected. Both the second source and the second gate are electrically connected to the first terminal of the liquid crystal capacitor Clc. That is, the second gate and the second source can be the first terminal of the potential adjustment unit 111, the first source can be the second terminal of the potential adjustment unit 111, and the first gate can be the control terminal of the potential adjustment unit 111.

[0077] In the embodiments of this application, the first regulating transistor F1 may be an N-type MOS transistor, and the second regulating transistor F2 may be an N-type MOS transistor.

[0078] It is understood that the first regulating transistor F1 receives the electrical signal transmitted from the second common voltage terminal Acom and turns on, and the second regulating transistor F2 receives the data signal and turns on.

[0079] In an exemplary embodiment, the second gate and the second source of the second regulating transistor F2 are both electrically connected to the second terminal of the switching unit 113 and the first terminal of the storage capacitor Cst.

[0080] In an exemplary embodiment, the channel length of the second regulating transistor F2 can be from 0.5µm to 1µm, for example, 0.5µm, 0.55µm, 0.67µm, 0.7µm, 0.8µm, 0.88µm, 1µm, or other values, and this application does not impose specific limitations on it. The channel width of the second regulating transistor F2 can be from 6µm to 12µm, for example, 6µm, 7µm, 7.5µm, 8.5µm, 9.4µm, 10µm, 11µm, 12µm, or other values, and this application does not impose specific limitations on it.

[0081] To verify the feasibility of the technical solution of this application, the simulation settings are as follows: the VGH of the switching transistor T is 30V, the VGL of the switching transistor T is -7V, the channel length of the switching transistor T is 31µm, the channel width of the switching transistor T is 5µm, the potential of the first common voltage terminal Ccom and the potential of the second common voltage terminal Acom are both 7.2V, the channel length of the first regulating transistor F1 is 0.5µm, the channel width of the first regulating transistor F1 is 7.5µm, the channel length of the second regulating transistor F2 is 0.5µm, and the channel width of the second regulating transistor F2 is 6µm. Please refer to [link / reference]. Figure 13 , Figure 13 This diagram illustrates the potential change of the first terminal of the liquid crystal capacitor in the sub-pixel unit of the first circuit structure disclosed in the fourth embodiment of this application within one frame. Simulation results show that the positive polarity potential residual ratio Ratio(+) is 69.54%, and the negative polarity potential residual ratio Ratio(-) is 72.32%. Figure 13 It can be concluded that the difference between Ratio(+) and Ratio(-) is small.

[0082] It is understood that when the potential of the first terminal of the liquid crystal capacitor Clc is positive, the first terminal of the liquid crystal capacitor Clc discharges to the second common voltage terminal Acom, thereby reducing the forward bias of the first regulating transistor F1 and increasing the forward bias of the second regulating transistor F2; when the potential of the first terminal of the liquid crystal capacitor Clc is negative, the discharge from the second common voltage terminal Acom to the first terminal of the liquid crystal capacitor Clc increases the forward bias of the first regulating transistor F1 and decreases the forward bias of the second regulating transistor F2; thus, regardless of whether the potential of the first terminal of the liquid crystal capacitor Clc is positive or negative, the resistance of the potential adjustment unit 111 is approximately the same, and the positive potential residual rate Ratio(+) and the negative potential residual rate Ratio(-) are relatively close.

[0083] For other embodiments of this application, please refer to Figure 14 , Figure 14This is a schematic diagram of a second circuit structure of the sub-pixel unit disclosed in the fourth embodiment of this application. The potential adjustment unit 111 includes a first adjustment transistor F1 and a second adjustment transistor F2. The first adjustment transistor F1 includes a first source, a first drain, and a first gate. The second adjustment transistor F2 includes a second source, a second drain, and a second gate. The first drain and the first gate are both electrically connected to the second common voltage terminal Acom. The first source and the second source are electrically connected. The second drain and the second gate are both electrically connected to the first terminal of the liquid crystal capacitor Clc. That is, the second drain and the second gate can be the first terminal of the potential adjustment unit 111, the first drain can be the second terminal of the potential adjustment unit 111, and the first gate can be the control terminal of the potential adjustment unit 111. Through the above technical solution, the positive polarity potential residual rate Ratio(+) and the negative polarity potential residual rate Ratio(-) can be made closer.

[0084] In the embodiments of this application, please refer to Figure 15 and Figure 16 , Figure 15 This is a schematic diagram of the structure of the sub-pixel unit disclosed in the fourth embodiment of this application. Figure 16 for Figure 15 The diagram shows an enlarged view of structure XII in the sub-pixel unit. In this embodiment, the second regulating transistor F2 includes a second active layer 112a, a second source 112b, a second drain 112c, and a second gate. The second active layer 112a is disposed on the second gate, and the second source 112b and the second drain 112c are disposed on the side of the second active layer 112a opposite to the second gate. The second gate and the second source 112b are both connected to the third drain 113c for electrical connection, and the second drain 112c is connected to the first drain 111c for electrical connection.

[0085] In the embodiments of this application, please refer to Figure 17 , Figure 17 for Figure 16 A schematic diagram of the layer structure of the second regulating transistor is shown. The gate insulating layer 212 covers the second gate 112d on the substrate 211. The second active layer 112a is disposed on the side of the gate insulating layer 212 opposite to the second gate 112d. The second source 112b and the second drain 112c are disposed on the side of the second active layer 112a opposite to the gate insulating layer 212, and the second source 112b and the second drain 112c are spaced apart. The insulating protective layer 213 covers the second source 112b, the second drain 112c and the second active layer 112a on the gate insulating layer 212.

[0086] In summary, the pixel unit provided in this application includes multiple sub-pixel units SP, each of which includes a liquid crystal capacitor Clc and a potential adjustment unit 111. The first terminal of the liquid crystal capacitor Clc is electrically connected to the first terminal of the potential adjustment unit 111, and the second terminal of the liquid crystal capacitor Clc is electrically connected to the first common voltage terminal Ccom. The second terminal and control terminal of the potential adjustment unit 111 are both electrically connected to the second common voltage terminal Acom. The control terminal of the potential adjustment unit 111 receives an electrical signal output from the second common voltage terminal Acom to connect the first terminal of the liquid crystal capacitor Clc to the second terminal of the second common voltage terminal Acom, thereby adjusting the potential of the first terminal of the liquid crystal capacitor Clc. Therefore, within one frame, the potential of the first terminal of the liquid crystal capacitor Clc is a dynamically changing value as time increases, causing the deflection angle of the multiple liquid crystal molecules within the liquid crystal capacitor Clc to also change dynamically, resulting in smaller color differences at different viewing angles and thus improving viewpoint color shift.

[0087] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0088] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims. Those skilled in the art will understand that implementing all or part of the processes of the above embodiments, and making equivalent changes according to the claims of this application, still falls within the scope of this application.

Claims

1. A pixel unit comprising a plurality of sub-pixel units, characterized in that, Each of the sub-pixel units comprises a switching unit, a liquid crystal capacitor and a potential adjusting unit, a control end of the switching unit receives a scanning signal, a first end of the switching unit receives a data signal, a second end of the switching unit is electrically connected with a first end of the liquid crystal capacitor and a first end of the potential adjusting unit, a second end of the liquid crystal capacitor is electrically connected with a first common voltage end, the control end and the second end of the potential adjusting unit are electrically connected with a second common voltage end, wherein the control end of the potential adjusting unit receives an electrical signal output by the second common voltage end to make the first end of the liquid crystal capacitor conduct with the second common voltage end, so as to dynamically adjust the potential of the first end of the liquid crystal capacitor within a frame time. The potential adjusting unit comprises a first adjusting transistor and a second adjusting transistor, wherein the first adjusting transistor comprises a first source, a first drain and a first gate, and the second adjusting transistor comprises a second source, a second drain and a second gate. The first source and the first gate are electrically connected with the second common voltage end, the first drain and the second drain are electrically connected, and the second source and the second gate are electrically connected with the first end of the liquid crystal capacitor; or the first drain and the first gate are electrically connected with the second common voltage end, the first source and the second source are electrically connected, and the second drain and the second gate are electrically connected with the first end of the liquid crystal capacitor, wherein the positive polarity potential residual rate of the first end of the liquid crystal capacitor is close to the negative polarity potential residual rate of the first end of the liquid crystal capacitor, the positive polarity potential residual rate is equal to (Vhold_e(+)-Vcom) / (Vhold_s(+)-Vcom), and the negative polarity potential residual rate is equal to (Vhold_e(-)-Vcom) / (Vhold_s(-)-Vcom), wherein Vhold_s(+) refers to a frame start potential of positive polarity, Vhold_e(+) refers to a frame end potential of positive polarity, Vhold_s(-) refers to a frame start potential of negative polarity, and Vhold_e(-) refers to a frame end potential of negative polarity, and Vcom=(Vhold_s(+)+Vhold_s(-)) / 2. The channel length of the first adjusting transistor is 0.5um to 1um, and the channel width of the first adjusting transistor is 7.5um to 15um; the channel length of the second adjusting transistor is 0.5um to 1um, and the channel width of the second adjusting transistor is 6um to 12um.

2. The pixel cell of claim 1, wherein, The electrical signal output by the second common voltage end is a direct current signal.

3. A display panel, characterized by, The display panel comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel units as claimed in claim 1 or 2, each of the pixel units comprises a plurality of sub-pixel units, and the sub-pixel units are electrically connected with the scanning lines and the data lines respectively.

4. A display device, characterized by comprising: The display panel comprises a scanning driving circuit, a data driving circuit and a display panel as claimed in claim 3, and the display panel is electrically connected with the scanning driving circuit and the data driving circuit respectively.

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