Semiconductor processing device, semiconductor processing system and semiconductor edge positioning method

Abstract

The present invention provides a semiconductor processing device, which includes: a lower chamber having a first support area for supporting a wafer; an upper chamber having a second support area, wherein when the upper chamber and the lower chamber are closed, the wafer is placed between the first support area and the second support area; a temperature control component arranged adjacent to the upper chamber and / or the lower chamber, which adjusts the temperature of the upper chamber and / or the lower chamber by adjusting its own temperature. A first channel is formed in the edge area of ​​the first support area or the second support area, and the first channel provides a first space for circulating one or more chemical fluids that corrode the edge area of ​​the wafer. The upper chamber and / or the lower chamber includes a positioning structure, which is used to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The present invention adjusts the positioning function of the positioning structure on the wafer by adjusting the temperature of the temperature control component.

Description

Technical field

[0001] The present invention relates to the field of surface processing of semiconductor wafers or similar workpieces, and in particular to a semiconductor processing device, a semiconductor processing system and a semiconductor edge positioning method. [Background Technology]

[0002] During the semiconductor manufacturing process, semiconductor wafers undergo numerous steps to meet the industry's high standards. Advanced semiconductor wafer processing requires uniform, flat, damage-free, and smooth edges. The stringent requirements for uniform and precise etching of the wafer edge surface pose significant challenges to semiconductor wafer processing.

[0003] Figure 1a FIG1 is a top view of the structure of a semiconductor wafer 100. The semiconductor wafer 100 includes a substrate layer 101 and a thin film layer 102 deposited on the substrate layer 101. Figure 1b for Figure 1a The AA cross-sectional view of FIG. Measurement points 1-8 are the locations where the relevant data of the semiconductor wafer is measured during operation. Figure 1b As shown, the etch width is the difference between the radii of substrate layer 101 and thin film layer 102. The etch width should be essentially the same at each measurement point 1-8. The smaller the difference between the maximum and minimum etch widths, the higher the uniformity. For example, when the edge width is designed to be 0.7mm, many high-end process technologies require that the difference between the maximum and minimum etch widths must not exceed 0.1mm, otherwise uneven etch width will result. If the difference between the maximum and minimum etch widths exceeds 0.1mm, it will directly affect the results of subsequent processing operations, ultimately leading to poor performance of the integrated circuit chip and affecting chip manufacturing yield.

[0004] Semiconductor wafer wet processing offers advantages such as simple principles, flexible processes, and low costs. Several traditional wet etching methods exist for semiconductor wafer edge etching. For example, polishing the edge of a semiconductor wafer involves rotating the wafer and removing a thin film layer from the substrate using a combination of physical friction and chemical etching. Because polishing can easily damage both the remaining film layer and the substrate, it is primarily used in semiconductor wafer manufacturing with lower precision requirements. Edge damage can cause the wafer edge to shift during thermal processing, ultimately rendering the wafer scrapped. Another common method involves vacuum suctioning semiconductor wafers. This method uses a vacuum head to hold the wafer, protecting the film to be retained while leaving the film to be removed exposed. The head and wafer are then immersed in a chemical etching solution to etch away the exposed film. However, vacuum suction can result in uneven film removal and uneven etching widths. Another common method is the film lamination method, which uses a pure, corrosion-resistant plastic film such as PTFE or PE to protect the portion of the film that needs to be retained. The entire film is then exposed to a chemically corrosive atmosphere or immersed in a chemically corrosive solution to etch the exposed portion. The film lamination method often results in uneven etching widths because the center of the pre-cut film may not align with the center of the wafer substrate. The process also involves multiple steps and requires the use of various equipment, including film lamination, wet etching, cleaning, and film removal equipment. Another newer method is the spray method, which uses a specialized nozzle to precisely spray the etching fluid onto the edge of the rotating wafer in the desired area, achieving precise, uniform, smooth, and damage-free etching. While the spray method can achieve high etching results, it requires extremely high equipment design and component processing precision, resulting in high equipment costs and demanding process conditions.

[0005] Furthermore, since most materials have a certain temperature expansion coefficient, semiconductor wafer edge processing devices made of materials with a high temperature expansion coefficient may fail to perform uniform and precise etching of wafers at a manufacturing site due to the difference between the manufacturing temperature and the operating temperature, temperature variations during transportation, or other unknown factors. This may necessitate complex and high-precision re-modification of the device, posing a significant challenge to the widespread application of the device.

[0006] In view of this, it is necessary to develop a new type of semiconductor wafer edge processing device that can solve the above problems. [Summary of the invention]

[0007] The purpose of the present invention is to provide a new semiconductor processing device, semiconductor processing system and semiconductor edge positioning method, which can solve the problems existing in the prior art, realize the precise positioning of semiconductor wafers and complete corrosion of designated wafer edge areas, and accurately control the thermal expansion and contraction of the device components or other factors affecting wafer positioning and process processing effects.

[0008] To achieve the above-mentioned objectives, according to one aspect of the present invention, there is provided a semiconductor processing device, comprising: a lower chamber having a first supporting area for supporting a wafer; an upper chamber having a second supporting area, wherein when the upper chamber and the lower chamber are closed, the wafer is placed between the first supporting area and the second supporting area; a temperature control component arranged adjacent to the upper chamber and / or the lower chamber, which adjusts the temperature of the upper chamber and / or the lower chamber by adjusting its own temperature; a first channel formed in the edge area of ​​the first supporting area or the second supporting area, the first channel providing a first space for circulating one or more chemical fluids for corroding the edge area of ​​the wafer.

[0009] According to another aspect of the present invention, the present invention provides a semiconductor processing system, comprising: the above-mentioned semiconductor processing device; and a material storage device connected to the semiconductor processing device, wherein the material storage device is used to store and exchange and transfer one or more chemical fluids with the semiconductor processing device.

[0010] According to another aspect of the present invention, the present invention provides a semiconductor edge positioning method, comprising: placing a wafer in a first support area of ​​a lower chamber of a semiconductor processing device; closing the upper chamber and the lower chamber of the semiconductor processing device between the first support area and the second support area, so that the positioning structure of the upper chamber and / or the lower chamber abuts against the edge outer end of the wafer and aligns the central axis of the wafer with the central axis of the second support area, wherein a temperature control component arranged adjacent to the upper chamber and / or the lower chamber in the semiconductor processing device can adjust its own temperature and be set to a predetermined temperature value; forming a first channel in the edge area of ​​the first support area or the second support area, wherein the first channel provides a first space, and one or more chemical fluids are injected into the first space to corrode the edge area of ​​the wafer; measuring the edge corrosion effect of the wafer to determine whether the measured edge corrosion effect meets the requirements, and if not, increasing or decreasing the temperature value of the temperature control component, continuing to corrode the edge of the wafer and measuring the edge corrosion effect of the wafer until the measured edge corrosion effect meets the requirements.

[0011] The embodiments of the present invention can be used in processing operations involving semiconductor wafers to uniformly and accurately etch edge surfaces, while also reducing the impact of temperature changes on edge etch effects.

[0012] Embodiments of the present invention may provide several advantages over existing solutions.

[0013] By setting up the temperature control component, the present invention can adjust the temperature of the upper chamber and / or the lower chamber as needed, thereby reducing the slight changes in the size of the upper chamber and / or the lower chamber caused by temperature changes or other factors (such as vibration during transportation), and further reducing the impact of temperature changes or other factors on the edge corrosion effect of the corrosion edge of the wafer.

[0014] The features, features, and advantages of the present invention will become apparent upon reading the following detailed description and accompanying drawings. The present invention includes any combination of one or more features or elements, regardless of whether these combinations of features or elements have been explicitly described or otherwise described in the embodiments. The present invention is intended to be read as a whole, such that any separable features or elements of the present invention, in any aspect and embodiment thereof, should be considered combinable unless the context of the present invention clearly dictates otherwise.

[0015] It should be understood that this summary is provided only for the purpose of summarizing some embodiments in order to provide a basic understanding of some aspects of the present invention. Therefore, the above-mentioned embodiments are merely examples and should not be interpreted as narrowing the scope or concept of the present invention in any way. The features, aspects, and advantages of the various embodiments will become apparent upon reading the following detailed description and the accompanying drawings, which illustrate the principles of some embodiments by way of example.

Brief Description of the Drawings

[0016] The present invention will be more readily understood with reference to the accompanying drawings and the following detailed description, wherein like reference numerals correspond to like structural components, and wherein:

[0017] Figure 1a This is a top view of the structure of a semiconductor wafer.

[0018] Figure 1b for Figure 1a AA cross-sectional view.

[0019] Figure 2a FIG. 2 is a schematic cross-sectional view of a semiconductor processing device 200 according to an embodiment of the present invention.

[0020] Figure 2b for Figure 2a An enlarged schematic diagram of circle A in FIG.

[0021] Figure 2c for Figure 2b Enlarged schematic diagram of circle B.

[0022] Figure 2d for Figure 2c Enlarged schematic diagram of circle C in the middle.

[0023] Figure 2e for Figure 2a A bottom view of the upper chamber 220 of the semiconductor processing apparatus 200 is shown.

[0024] Figure 2f for Figure 2a A top view of the lower chamber 210 of the semiconductor processing apparatus 200 .

[0025] Figure 3a FIG. 1 is a schematic cross-sectional view of a semiconductor processing device 300 according to an embodiment of the present invention.

[0026] Figure 3b for Figure 3a Enlarged schematic diagram of circle D.

[0027] Figure 3c for Figure 3a An enlarged schematic view of circle D with protrusion 342 is shown in FIG.

[0028] Figure 3d for Figure 3a A bottom view of the upper chamber 320 of the semiconductor processing apparatus 300 is shown.

[0029] Figure 3e for Figure 3a A top view of the lower chamber 320 of the semiconductor processing apparatus 300 .

[0030] Figure 4a FIG. 4 is a schematic cross-sectional view of a semiconductor processing device 400 according to an embodiment of the present invention.

[0031] Figure 4b for Figure 4a Enlarged schematic diagram of circle E.

[0032] Figure 4c for Figure 4b Enlarged schematic diagram of the middle circle F.

[0033] Figure 4d for Figure 4a A top view of the lower chamber 420 of the semiconductor processing apparatus 400.

[0034] Figure 4e for Figure 4a A bottom view of an upper chamber 410 of a semiconductor processing apparatus 400 is shown.

[0035] Figure 5 The exemplary system 500 of the present invention includes a semiconductor processing apparatus and a material storage apparatus.

[0036] Figure 6 An exemplary method for processing an edge region of a semiconductor wafer using an apparatus according to an embodiment of the present invention is shown.

[0037] Figure 7 This is a schematic diagram of the temperature expansion coefficient curve of PTFE material;

[0038] Figure 8 FIG1 is a schematic structural diagram of a semiconductor processing device capable of fine-tuning wafer positioning accuracy in one embodiment of the present invention. [Specific implementation method]

[0039] Some embodiments of the present invention will be described more fully below with reference to the accompanying drawings, some, but not all, of which are listed. Indeed, various embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this disclosure thorough and complete and will fully convey the scope of the invention to those skilled in the art. For example, unless otherwise stated, referring to something as first, second, etc. should not be construed as implying a particular order. Furthermore, something may be described as being higher than something (unless otherwise stated) when it is actually lower than something, and vice versa; similarly, something described as being on the left may be on the right, and vice versa. The same reference figure number always represents the same element.

[0040] Figures 1a to 1b 1 is a schematic structural diagram of a semiconductor wafer 100 . Figure 1a FIG. 1 is a top view of the structure of the semiconductor wafer 100 . Figure 1b for Figure 1a The sectional view of the AA section. Figure 1a-1b As shown, semiconductor wafer 100 includes a substrate layer 101 and a thin film layer 102 deposited on the upper surface of substrate layer 101, and substrate layer 101 may be partially covered by thin film layer 102. In another embodiment, substrate layer 101 may be completely covered by thin film layer 102. In another embodiment, both sides of the surface of substrate layer 101 may be covered by thin film layer 102 respectively.

[0041] In this embodiment, the thin film layer 102 should be removed from the substrate layer 101 by processing the semiconductor wafer. Figure 1a-1b As shown in FIG, the radius of the thin film layer 102 is smaller than that of the substrate layer 101, and the etching width refers to the difference between the two radii. Figure 1a Measurement points 1-8 in the diagram are test locations for measuring semiconductor wafer-related data. The etch width at measurement points 1-8 should be essentially the same. The smaller the difference between the maximum and minimum values, the better the etch uniformity. For example, when the edge width is designed to be 0.7 mm, advanced processes require that the difference between the maximum and minimum etch widths must not exceed 0.1 mm. In some embodiments, the thin layer covering both sides of the substrate layer 101 surface should be partially or completely removed. The etch width on each side of the substrate layer 101 surface can be the same or different.

[0042] refer to Figures 2a to 2f , this embodiment shows a structural schematic diagram of a semiconductor processing device 200. Figure 2a FIG. 2 is a schematic cross-sectional view of a semiconductor processing device 200 . Figure 2b for Figure 2a An enlarged schematic diagram of circle A in FIG. Figure 2c for Figure 2b (Through hole omitted) Enlarged schematic diagram of circle B. Figure 2d for Figure 2c Enlarged schematic diagram of circle C in the middle. Figure 2e for Figure 2a A bottom view of the upper chamber 220 of the semiconductor processing apparatus 200 is shown. Figure 2f for Figure 2a A top view of the lower chamber 210 of the semiconductor processing apparatus 200 .

[0043] In an embodiment, as shown in Figures 1 and 2, the semiconductor device 200 includes a lower chamber 210 having a first supporting area 212. The first supporting area 212 can support the wafer 100. Figure 2a As shown, the first support area 212 has an upper surface facing the wafer 100. The wafer 100 can be placed on the upper surface of the first support area 212. In some embodiments, the apparatus 200 includes an upper chamber 220 having a second support area 222. Figure 2a As shown, the second support area 222 has a lower surface facing the wafer 100. The upper chamber 220 is closed to the lower chamber 210, and the wafer 100 is placed between the first support area 212 and the second support area 222. With the lower chamber as the origin, the upper chamber 220 can move between two relative positions. In the first position, the wafer 100 can be loaded and / or unloaded to the first support area 212. Figure 2a As shown, in the second position, the upper chamber 220 and the lower chamber 210 are closed, so that the wafer 100 is fixed by the upper surface of the first supporting area 212 and the lower surface of the second supporting area 222 and processed.

[0044] In some embodiments or any combination of the foregoing embodiments, reference Figures 2a to 2c The apparatus 200 includes a first channel 230 formed by the edge region of the first support area 212 or the second support area 222. The first channel 230 provides a first space 232 for one or more chemical fluids to etch the edge region of the wafer 100. Figures 2a to 2c The first channel 230 is formed by the edge area of ​​the second support area 222 in the upper chamber 220. The first channel 230 is formed on the lower surface of the upper chamber 220, and one side of the first channel 230 is open to the wafer 100. In this embodiment, the first channel 230 provides a first space 232, allowing one or more chemical fluids to flow therein to etch the edge area of ​​the wafer 100. Figures 2a to 2c The first space 232 can be formed by the first channel 230 and the inner surface of the wafer 100. In this embodiment, the first channel 230 is annular and surrounds the edge region of the wafer 100. The entire edge region of the wafer 100 is accommodated in the first space 232. In another embodiment, the first channel 230 can be designed as an arc less than 360 degrees, and the edge region of the wafer 100 can be accommodated in a specific area of ​​the first space 232. Then, one or more chemical fluids can etch the wafer edge region along the arc of the first channel 230.

[0045] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, reference Figures 2a to 2c , the upper chamber 220 includes a protruding portion 240 that abuts against the edge of the wafer 100. The protruding portion can directly contact and abut against the edge of the wafer 100. Figure 2a The central axis XX of wafer 100 is perpendicular to the upper surface of wafer 100. The central axis X'-X' of second support area 222 is perpendicular to the lower surface of second support area 222. The raised portion 240 aligns the central axis XX of wafer 100 with the central axis X'-X' of second support area 222. When upper chamber 220 is in the first position, wafer 100 is loaded onto first support area 212. The central axis XX of wafer 100 may not be aligned with the central axis X'-X' of second support area 222. During movement of upper chamber 220 from the first position to the second position, raised portion 240 contacts the edge of wafer 100 and then abuts against the edge, pushing wafer 100 to move across the upper surface of first support area 212. When upper chamber 220 is in the second position, the wafer 100 is secured to the upper surface of first support area 212, and the central axis XX of wafer 100 is parallel to the central axis X'-X' of second support area 222. Alternatively, the central axis XX of the wafer 100 may overlap with the central axis X′-X′ of the second supporting area 222 .

[0046] In some embodiments of the device 200 or any combination of the foregoing embodiments, the raised portion 240 is adjacent to the second support area 222 and extends toward the lower chamber 210. Figure 2a and 2b , the raised portion 240 is connected to the second supporting area 222. When the upper chamber 220 is in the second position, the raised portion 240 extends to the lower chamber 210. Figure 2a and 2b As shown, in this embodiment, the raised portion 240 is located beside the first channel 230. Figure 2a, the central axis XX of wafer 100 is perpendicular to the upper surface of wafer 100, and the central axis X′-X′ of second supporting area 222 is perpendicular to the lower surface of upper chamber 220. The upper surface 100 of wafer is parallel to the lower surface of second supporting area 222. In one embodiment, when upper chamber 220 is in the second position, a portion of the upper surface of wafer 100 overlaps with the lower surface of second supporting area 222, and the central axis XX of wafer 100 overlaps with the central axis X′-X′ of second supporting area 222.

[0047] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, the raised portion 240 can be designed to be a closed loop around the wafer 100. Figure 2a , the raised portion 240 comprises a closed loop. The closed loop can surround the entire edge area of ​​the wafer 100. Therefore, the raised portion 240 can completely abut the edge area of ​​the wafer 100, causing the central axis XX of the wafer 100 to overlap with the central axis X'-X' of the second support area 222. In some embodiments, the closed loop can be an arc with an arc less than 360 degrees, and a specific portion abuts the edge area of ​​the wafer 100, so that the central axis XX of the wafer 100 is aligned and / or overlaps with the central axis X'-X' of the second support area 222 through the raised portion 240. In some embodiments, the raised portion 240 may be an open loop.

[0048] In some embodiments of the device 200 or any combination of the foregoing embodiments, the raised portion 240 includes an inner corner facing the central axis X'-X' of the second support area 222. Figure 2c The raised portion 240 includes an inner surface 242 that is inclined at an angle α to the first reference direction YY. The first reference direction YY is parallel to the lower surface of the second support area 222. The angle α is in the range of 20°-90°. Figure 2b and 2c As shown, the inner corner is formed by the connection between the inner surface 242 and the inner surface of the first channel 230 and faces the central axis X'-X' of the second support area 222. In some embodiments, the inner corner abuts against the edge area of ​​the wafer 100. Figure 2b As shown, during the movement of upper chamber 220 from the first position to the second position, the inner corner of protrusion 240 contacts the edge area of ​​wafer 100 and then rests against the edge of wafer 100, pushing wafer 100. When upper chamber 220 is in the second position, the wafer is secured and the central axis XX of wafer 100 is parallel to the central axis X'-X' of second support area 222. Alternatively, the central axis XX of wafer 100 overlaps the central axis X'-X' of second support area 222.

[0049] In some embodiments of the device 200 or any combination of the foregoing embodiments, the first channel 250 is formed by the edge region 214 of the lower chamber 210, and the first channel 250 provides a first channel space 252 for the flow of one or more chemical fluids. Figure 2a 、 2b 2f, the first channel 250 is formed by the edge region 214 of the lower chamber 210 and is adjacent to the first support region 212 of the lower chamber 210. The first channel 250 forms a first channel space 252, into which one or more chemical fluids can flow from the first space 232 of the first channel 230.

[0050] In some embodiments of the device 200 or any combination of the foregoing embodiments, the passage 260 is located between the upper chamber 220 and the lower chamber 210. Figure 2b and 2f , the lower chamber 210 has a first upper surface 262 between the first support area 212 and the first channel 250. The passage 260 is located between the first upper surface 262 of the lower chamber 210 and the inner surface 242 of the raised portion 240. The passage 260 connects the first space 232 with the first channel space 252, allowing one or more chemical fluids to flow from the first space 232 to the first channel space 252 through the passage 260. In one embodiment, the passage 260 can be blocked by the raised portion 240 to prevent the one or more chemical fluids from flowing from the first space 232 to the first channel space 252. In another embodiment, the passage 260 is blocked by the first support area 210 to prevent the one or more chemical fluids from flowing from the first space 232 to the first channel space 252.

[0051] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, such as Figures 2a to 2c As shown, the first channel 230 is located at the edge area of ​​the second support area 222. The upper chamber 220 includes a first through hole 270, and one or more chemical fluids flow between the first space 232 and the outside of the device 200 via the first through hole 270. The first through hole 270 can pass through the upper chamber 220 from the outside of the device 200 to communicate with the first space 232. In one embodiment, the one or more chemical fluids can flow between the first space 232 and the outside of the device 200 through the first through hole 270. In another embodiment, the upper chamber 220 may include two or more through holes that are substantially the same as the first through hole 270 (e.g., Figure 2a and 2eIn this embodiment, at least one first through hole (e.g., first through hole 270) can be used as an inlet, and the remaining first through holes (e.g., sub-first through holes 272) can be used as outlets. First space 232 can be connected to the outside via first through hole 270 and sub-first through hole 272. In this embodiment, one or more chemical fluids can flow from the outside of device 200 into first space 232 of first channel 230 via first through hole 270, and flow out of first space 232 to the outside of device 200 via sub-first through hole 272.

[0052] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, the second channel 280 is formed by the edge region of the first support area 212 and provides a second space 282 for etching the edge region of the wafer 100 using one or more chemical fluids. Figures 2a to 2c , the second channel 280 is formed by the edge area of ​​the first supporting area 212 in the lower chamber 210. Figures 2a to 2c The second channel 280 is located on the upper surface of the lower chamber 210, and one side of the second channel 280 is open to the wafer. In this embodiment, the second channel 280 provides a first space 232 for one or more chemical fluids to etch the edge area of ​​the wafer 100. Figures 2a to 2c The second space 282 can be formed by the inner surface of the second channel 280 and the wafer 100. In one embodiment, the second channel 280 is annular and surrounds the edge region of the wafer 100. In another embodiment, the second channel 280 can be designed in an arc shape with an arc less than 360 degrees, and the edge region of the wafer 100 is exposed at a specific location in the second space 282. Then, one or more chemical fluids are used to etch the specific edge region of the wafer along the arc of the second channel 280. In some embodiments, the second channel 280 is designed to have the same shape as the first channel 230. The second channel 280 is located between the first support area 212 and the first channel 250 near the first upper surface 262. The passage 260 is located between the first upper surface 262 of the lower chamber 210 and the inner surface 242 of the upper chamber. The passage 260 allows one or more chemical fluids to flow from the second space 282 to the first channel space 252 through the passage 260. In one embodiment, the passage 260 can be blocked by the raised portion 240 to prevent one or more chemical fluids from flowing from the second space 282 to the first channel space 252. In another embodiment, the passage 260 can be blocked by the first support area 210 to prevent one or more chemical fluids from flowing from the second space 282 to the first channel space 252.

[0053] In some embodiments of the apparatus 200 or any combination of the foregoing embodiments, the lower chamber 210 has a second through hole 290 for one or more chemical fluids to flow between the second space 282 and the exterior of the apparatus 200. Figure 2a and 2b , the second through hole 290 can pass through the lower chamber 210 from the outside of the device 200 and communicate with the second space 282 of the second channel 280. In one embodiment, one or more chemical fluids can flow between the second space 282 and the outside of the device 200 via the second through hole 290. In another embodiment, one or more chemical fluids can flow from the outside of the device 200 to the second space 282 of the second channel 280 via the second through hole 290, and then flow from the second space 282 of the second channel 280 to the first channel space 252 of the first channel 250 via the passage 260. In some embodiments, the lower chamber 210 may further include one or more second through holes (such as Figure 2a The second through hole 292 is shown as the second through hole 290. In one embodiment, at least one second through hole (e.g., the second through hole 290) is used as an inlet, and the remaining second through holes (e.g., the second through hole 292) are used as outlets. The second space 282 is connected to the outside of the device 200 through the second through hole 290 and the second through hole 292. In one embodiment, one or more chemical fluids can flow from the outside of the device 200 into the second space 282 of the second channel 280 via the second through hole 290, and flow out of the device 200 from the second space 282 via the second through hole 292. In another embodiment, one or more chemical fluids can flow from the outside of the device 200 into the second space 282 of the second channel 280 via the second through hole 290 and the second through hole 292, and then flow from the second space 282 of the second channel 280 into the first channel space 252 of the first channel 250 via the passage 260.

[0054] refer to Figures 3a to 3e , which shows a schematic structural diagram of a semiconductor processing device 300 provided by an embodiment of the present invention. Figure 3a FIG. 1 is a schematic cross-sectional view of a semiconductor processing device 300 according to an embodiment of the present invention. Figure 3b for Figure 3a Enlarged schematic diagram of circle D. Figure 3c for Figure 3a An enlarged schematic diagram of circle D with raised portion 342 is shown in FIG. Figure 3d for Figure 3a A bottom view of the upper chamber 320 of the semiconductor processing apparatus 300 is shown. Figure 3e for Figure 3a A top view of the lower chamber 320 of the semiconductor processing apparatus 300 .

[0055] In this embodiment, reference Figures 3a to 3e , the device 300 includes a lower chamber 310 having a first support area 312. The lower chamber 310 and the first support area 312 can be referred to as Figures 2a to 2fThe lower chamber 210 and the first support area 212 are shown. The device 300 includes an upper chamber 320 with a second support area 322. The upper chamber 320 and the second support area 322 can be referred to above. Figures 2a to 2f The upper chamber 220 and the second supporting area 222 are shown. As described above, the upper chamber 320 is closed with the lower chamber 310 to fix the wafer 100 between the first supporting area 312 and the second supporting area 322. The apparatus 300 includes a first channel 330 formed by the edge area of ​​the first supporting area 312 or the second supporting area 322. The first channel 330 can be referred to above. Figures 2a to 2f The first channel 230 is formed by the edge area of ​​the second support area 322 in the upper chamber 320 and provides a first space 332 for the circulation of one or more chemical fluids for etching the edge area of ​​the wafer 100. The first space 332 can refer to the above Figures 2a to 2f The first space 232 described above. In some embodiments, the first space 332 of the first channel 330 may also be formed by the inner surface of the first channel 330, the lower chamber 310, and the wafer 100. The entire or partial edge region of the wafer 100 is exposed in the first space 332 of the first channel 330 and is contacted and corroded by one or more chemical fluids.

[0056] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, such as Figures 3a to 3d As shown, the upper chamber 320 includes a raised portion 340 for abutting against the edge of the wafer 100 and aligning the central axis XX of the wafer 100 with the central axis X'-X' of the second supporting area 322. Figures 2a to 2e The raised portion 240 described above. In some embodiments, the raised portion 340 includes a plurality of protrusions 342 that uniformly surround and abut against the edge region of the wafer 100. Each protrusion 342 extends from the raised portion 340 into the first space 332 of the first channel 330. Figure 3c and 3d , the raised portion 340 includes four protrusions (such as protrusions 342a to 342d). Each protrusion 342 includes an inner surface 344 inclined at an angle β to the reference direction YY. The range of angle β is within 20°-90°. The inner surface faces the edge of the wafer 100. The reference direction YY is parallel to the upper surface of the wafer 100, or perpendicular to the central axis X'-X' of the second support area 322. For example, Figure 3c, protrusion 342a includes an inner surface 344a inclined at an angle β relative to reference direction YY. Inner surface 344a can abut against the edge of wafer 100 and push wafer 100 so that central axis XX of wafer 100 is aligned with central axis X'-X' of second support area 322. Raised portion 340 includes a plurality of protrusions 342. In some embodiments, raised portion 340 may include six protrusions 342. In some embodiments, raised portion 340 may include eight protrusions 342. In some embodiments, raised portion 340 may include twelve protrusions 342.

[0057] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, reference Figures 3a to 3c The first channel 350 is formed at the edge region 314 of the lower chamber 310 and provides a first channel space 352 for flowing one or more chemical fluids. The first channel 350, the edge region 314 of the lower chamber 310, and the first channel space 352 of the first channel 350 can be respectively referred to above. Figures 2a to 2f The first channel 250, the edge area 214 of the lower chamber 220 and the first channel space 252 of the first channel 250 are described. In some embodiments, a passage 360 ​​is formed between the upper chamber 320 and the lower chamber 310 to connect the first space 332 with the first channel space 352, and one or more chemical fluids flow from the first space 332 to the first channel space 352 through the passage 360. The passage 360 ​​can be referred to above. Figures 2a to 2f In some embodiments, the passage 360 ​​is formed between the raised portion 340 and the first upper surface 362 of the lower chamber 310. Figures 3a to 3c As shown in FIG3 e , the first upper surface 362 is adjacent to the first supporting area 312 and is located between the first supporting area 312 and the first groove 350 .

[0058] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, such as Figure 3a 、 3b As shown in FIG3d, the upper chamber 320 may include a first through hole 370, so that one or more chemical fluids flow between the first space 332 and the outside of the device 300. The first through hole 370 may refer to the above Figures 2a to 2e In some embodiments, the upper chamber 320 may further include one or more first through holes (e.g., Figure 3a and 3d The arrangement of one or more first through holes can refer to the above Figure 2a and 2e The arrangement of one or more first through holes is described.

[0059] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, reference Figure 3a 、 3b 3e, the lower chamber 310 includes a second through hole 380. Figure 3a and 3b As shown, the second through-hole 380 is used for one or more chemical fluids to flow between the first space 332 and the outside of the device 300. The second through-hole 380 is connected to the first space 332 of the first channel 330 from the outside of the device 300 through the lower chamber 310. In some embodiments, the one or more chemical fluids can flow from the outside of the device 300 to the first space 332 via the second through-hole 380, and then flow from the first space 332 to the first channel space 352 of the first channel 350 through the passage 360. In some embodiments, the one or more chemical fluids can flow from the outside of the device 300 to the first space 332 of the first channel 330 through the first through-hole 370, and then flow from the first space 332 to the first channel space 352 through the passage 360 ​​and then flow to the outside of the device 300 through the second through-hole 380.

[0060] In some embodiments of the device 300 or any combination of the foregoing embodiments, the second channel 390 is formed by the edge region 324 of the upper chamber 320 and is located above the first channel 350. Figures 3a to 3d Second channel 390 is formed by edge region 324 of upper chamber 320 and is adjacent to raised portion 340. Second channel 390 provides a second channel space for chemical circulation. The opening of second channel 390 faces lower chamber 310. Second channel 390 is located above first channel 350, allowing first channel space 352 of first channel 350 to communicate with second channel space of second channel 390. Second channel 390 has the same design as first channel 350. Figure 3d and 3e As shown, the first groove 350 and the second groove 390 are annular. In addition, the first groove 350 and the second groove 390 can also be designed as an arc less than 360 degrees.

[0061] In some embodiments of the apparatus 300 or any combination of the foregoing embodiments, such as Figures 3a to 3c As shown, the elastic member 392 can be placed between the first channel 350 and the second channel 390. In some embodiments, the elastic member 392 is placed in the first channel space 352 or the second channel space. In some embodiments, the elastic member 392 is placed in the first channel space 352 and the second channel space. In some embodiments, the elastic member 392 can be used to prevent one or more chemical fluids from flowing from the first space 332 to the first channel space 352. For example Figures 3a to 3cAs shown, the width of the elastic member 392 is wider than the width of the first channel 350 and the second channel 390. The inner surface of the first channel 350 and / or the inner surface of the second channel 390 abuts against the elastic member 392, preventing the one or more chemical fluids from flowing from the first space 332 to the first channel space 352.

[0062] In some embodiments of the device 300 or any combination of the foregoing embodiments, the resilient member 392 can be an O-ring.

[0063] refer to Figures 4a to 4e , which shows a schematic structural diagram of a semiconductor processing device 400 provided by an embodiment of the present invention. Figure 4b for Figure 4a Enlarged schematic diagram of circle E. Figure 4c for Figure 4b Enlarged schematic diagram of the middle circle F. Figure 4d for Figure 4a A top view of the lower chamber 420 of the semiconductor processing apparatus 400. Figure 4e for Figure 4a A bottom view of an upper chamber 410 of a semiconductor processing apparatus 400 is shown.

[0064] In one embodiment, reference Figures 4a to 4e , the device 400 includes a lower chamber 410 having a first support area 412. The lower chamber 410 and the first support area 412 can refer to Figures 2a to 2f The lower chamber 210 and the first support area 212 are shown. The device 400 includes an upper chamber 420 with a second support area 422. The upper chamber 420 and the second support area 422 can be referred to above. Figures 2a to 2f The upper chamber 220 and the second support area 222 are shown. The device 400 includes a first channel 430 formed by the edge area of ​​the first support area 412. The first channel 430 can be referred to above Figures 2a to 2f The first channel 230. Figures 4a to 4c 4e, a first channel 430 is formed at an edge region of the first support area 412 in the lower chamber 420 and provides a first space 432 for flowing one or more chemical fluids to etch the edge region of the wafer 100. The first space 432 of the first channel 430 may also be formed by the inner surface of the first channel 430 and the wafer 100. The entire or a portion of the edge region of the wafer 100 is accommodated in the first space 432 of the first channel 430, and one or more chemical fluids may be used to contact and etch the edge region of the wafer 100.

[0065] In some embodiments of the apparatus 400 or any combination of the foregoing embodiments, such as Figures 4a to 4dAs shown, the upper chamber 420 includes a raised portion 440 that abuts against the edge of the wafer 100 and aligns the central axis XX of the wafer 100 with the central axis X'-X' of the second supporting area 422. The raised portion 440 can be referred to above. Figures 2a to 2e The raised portion 240 described above. In some embodiments, the raised portion 440 faces the lower chamber 410 and is located near the lower surface 424 of the second support area 422. In some embodiments, the raised portion 440 includes a plurality of protrusions evenly distributed around the wafer 100 and abutting against the edge area of ​​the wafer 100. The protrusions can be referred to above. Figures 3a to 3d The protrusion 342 is described.

[0066] In some embodiments of the apparatus 400 or any combination of the foregoing embodiments, the raised portion 440 includes an inner surface 442 inclined relative to the central axis X'-X' of the second support area 442, and the inner surface 442 abuts against the edge region of the wafer 100. Figures 4a to 4d , the inner surface 442 faces the wafer 100 and contacts the edge of the wafer 100. The inner surface 442 is inclined at an angle γ relative to the reference axis ZZ. The angle γ can range from 20° to 90°. The reference axis ZZ is parallel to the center axis X'-X' of the second support area 442. In some embodiments, the inner surface 442 of the raised portion 440 contacts the edge of the wafer 100 and rests against the edge of the wafer 100, thereby aligning the center axis XX of the wafer 100 with the center axis X'-X' of the second support area 422. In some embodiments, the inner surface 442 of the raised portion 440 can push the wafer 100 so that the center axis XX of the wafer 100 overlaps with the center axis X'-X' of the second support area 422.

[0067] In some embodiments of the apparatus 400 or any combination of the foregoing embodiments, reference is made to Figure 4a 、 4c 4e, the first channel 450 is formed by the edge region 414 of the lower chamber 410 and provides a first channel space 452 that can be used for the circulation of one or more chemical fluids. The first channel 450, the edge region 414 of the lower chamber 410, and the first channel space 452 of the first channel 450 can be respectively referred to above. Figures 2a to 2f The first channel 250, the edge area 214 of the lower chamber 220, and the first channel space 252 of the first channel 250 are described. In some embodiments, the passage 460 is located between the upper chamber 420 and the lower chamber 410, connecting the first space 432 with the first channel space 452, for one or more chemical fluids to flow from the first space 432 to the first channel space 452 through the passage 460. The passage 460 can be referred to above. Figures 2a to 2f The described aisle 260. In some embodiments, as Figure 4cAs shown, the passage 460 is located between the wafer 100 and the first upper surface 462 of the lower chamber 410. Figure 4c and 4e As shown, the first upper surface 462 is located between the first passage 430 and the first slot 450 .

[0068] In some embodiments of the apparatus 400 or any combination of the foregoing embodiments, reference is made to Figures 4a to 4c 4e, the lower chamber 420 includes a first through hole 470, so that one or more chemical fluids flow between the first space 432 and the outside of the device 400. The first through hole 470 can refer to the above Figures 2a to 2e In some embodiments, the lower chamber 420 further includes one or more first through holes (e.g., Figure 4a and 4e The arrangement of one or more first through holes can refer to Figure 2a and 2e described.

[0069] In some embodiments of the apparatus 400 or any combination of the foregoing embodiments, reference is made to Figure 4a 、 4b 4e, the second channel 480 is located at the edge of the first support area 412 and provides a second space 482 for etching the edge of the wafer 100 using one or more chemical fluids. Figure 2b 、 2c and the second channel 280 described in 2f. In some embodiments, the first channel 430 and the second channel 480 can be connected by a passage 484 so that one or more chemical fluids flow between the first space 432 of the first channel 430 and the second space 482 of the second channel 480. Figure 4b and 4c A passage 484 connecting the first channel 430 and the second channel 480 is formed by the wafer 100 and the first support area 412 of the lower chamber 410. One or more chemical fluids can flow between the first space 432 and the second space 482 through the passage 484. In some embodiments, the one or more chemical fluids can flow from the second space 482 through the passage 484, the first space 432, and the passage 460 to the first channel space 452.

[0070] In some embodiments of the apparatus 400 or any combination of the foregoing embodiments, reference is made to Figure 4a 、 4b 4e, the lower chamber 410 includes a second through hole 490, so that one or more chemical fluids flow between the second space 482 and the outside of the device 400. The second through hole 490 can refer to Figures 2a-2cIn some embodiments, the lower chamber 410 further includes one or more second through holes (e.g., Figure 4a and 4e The arrangement of one or more first through holes can refer to the above Figure 2a The arrangement of one or more first through holes is described.

[0071] The present invention utilizes raised portions to accurately and uniformly locate wafer edge etching. Furthermore, by scientifically selecting the chemical fluid composition for etching and controlling the flow rate and contact time of the chemical fluid with the wafer edge, a clear and complete etching edge can be achieved, facilitating subsequent wafer processing operations. Furthermore, processing costs can be reduced. Within a certain range, the invention utilizes the thermal expansion and contraction characteristics of the chamber component materials and adjusts the chamber temperature to select the wafer edge surface to be processed, particularly enabling precise control of the wafer edge etching area.

[0072] In the above embodiments, the raised portion is provided on the upper chamber as an example. In other embodiments, the raised portion may also be provided on the lower chamber. Of course, in some embodiments, other positioning structures may also be provided to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area.

[0073] Figure 5 The system 500 of the present invention includes a semiconductor processing device 510 and a material storage device 520. The device 510 can refer to the above Figures 2a-2f , 3a-3e, and 4a-4e. Apparatus 510 comprises any of apparatus 200, apparatus 300, and apparatus 400 described in

[15] . Apparatus 510 includes a lower chamber having a first support area for supporting a wafer and an upper chamber having a second support area; the upper chamber and the lower chamber are closed to secure the wafer between the first support area and the second support area; a first channel is located at an edge of the first support area or the second support area, the first channel providing a first space for etching the edge area of ​​the wafer with one or more chemical fluids. In some embodiments, the upper chamber includes a raised portion that abuts against the edge of the wafer to align the central axis of the wafer with the central axis of the second support area. Material storage device 520 is connected to apparatus 510 and is a device for storing one or more chemical fluids and transferring the one or more chemical fluids between apparatus 510 and material storage device 520. In some embodiments, the one or more chemical fluids can be selected from H3PO4, HF, HCl, HNO3, H2O2, or any combination thereof.

[0074] In some embodiments of system 500 or any combination of the foregoing embodiments, the raised portion is adjacent to the second support area and extends toward the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support area. In some embodiments, the raised portion comprises a closed loop around the wafer, and the raised portion is evenly positioned against the edge of the wafer, such that the central axis of the wafer overlaps the central axis of the second support area.

[0075] In some embodiments of system 500 or any combination of the foregoing embodiments, the raised portion is adjacent to the second support area and extends toward the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support area. In some embodiments, the raised portion includes a plurality of protrusions distributed in a ring around the wafer to uniformly abut against the edge region of the wafer.

[0076] In some embodiments of system 500 or any combination of the foregoing embodiments, a first channel is present in an edge region of the lower chamber and provides a first channel space for the circulation of one or more chemical fluids. In some embodiments, a channel is formed between the upper chamber and the lower chamber, connecting the first space with the first channel space, allowing the one or more chemical fluids to flow from the first space to the first channel space through the channel. In some embodiments, a second channel is present in an edge region of the upper chamber and is located above the first channel space. In some embodiments, an elastic member may be added between the first channel and the second channel to prevent the one or more chemical fluids from flowing from the first space to the first channel space.

[0077] In some embodiments of the system 500 or any combination of the foregoing embodiments, the system 500 includes a control device 530. The control device 530 can communicate with and control the device 510 and the material storage device 520. For example, the control device 530 can control the movement of the upper chamber between a first position for loading / unloading wafers and a second position for closing the upper chamber and the lower chamber to process wafers; and can control the flow rate and flow direction of one or more chemical fluids. The control device 530 can detect the flow rate, flow direction, state of one or more chemical fluids and a fault of the device 510. In some embodiments, the control device may include a PLC, a controller, a sensor, a storage device (e.g., a memory, a hard drive, an SSD, etc.).

[0078] Figure 6 An exemplary method 600 for processing the edge region of a semiconductor wafer 100 using an apparatus according to an embodiment of the present invention may be employed. Figures 2a-2f, 3a-3e, 4a-4e and 5 described in any of the devices 200, 300, 400 or 500.

[0079] In an embodiment, Figure 6 In step 602, the device 200 (or the device 300, the device 400, or the device 500) receives a wafer and places it on the first support area of ​​the lower chamber. In step 604, the device closes its upper chamber with its lower chamber to fix the wafer between the first support area and the second support area of ​​the upper chamber. In step 606, the edge area of ​​the first support area or the second support area forms a first channel, and the first channel provides a first space. In step 608, the device uses a raised portion to abut the edge of the wafer and align the central axis of the wafer with the central axis of the second support area. In step 610, the equipment injects one or more chemical fluids into the first space to etch the edge area of ​​the wafer.

[0080] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 602, a wafer is placed by a wafer transfer device onto a first support area of ​​a lower chamber of apparatus 200 (or apparatus 300, apparatus 400, or apparatus 500). The upper surface of the first support area faces the wafer. The wafer transfer device may place the wafer on the upper surface of the first support area so that a portion of the lower surface of the wafer is covered by the upper surface of the first support area. In some embodiments, when the upper chamber of apparatus 200 (or apparatus 300, apparatus 400, or apparatus 500) is in a first position, the wafer may be loaded or unloaded into the first support area. That is, the wafer may be transferred from the wafer transfer device to the upper surface of the first support area.

[0081] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 604, the apparatus 200 (or apparatus 300, apparatus 400, or apparatus 500) may close the upper chamber with the lower chamber to secure the wafer between the first support area and the second support area of ​​the upper chamber. When the upper chamber is in the second position, the lower chamber may be closed with the upper chamber and the wafer may be secured between the lower chamber and the upper chamber to process the wafer edge area. The upper chamber includes a second support area facing the lower surface of the wafer. The upper chamber is closed with the lower chamber to place the wafer between the first support area and the second support area. At this point, the wafer may be secured between the lower surface of the second support area and the upper surface of the first support area.

[0082] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 606, a first channel is formed in the edge area of ​​the first support area or the second support area. The first channel may also be formed on the lower surface of the upper chamber, with the opening of the first channel facing the wafer. In some embodiments, the first channel provides a first space for processing the edge area of ​​the wafer. For example, one or more chemical fluids flow in the first channel and corrode the edge area of ​​the wafer. In some embodiments, the first channel may be designed as a closed loop. In some embodiments, the first channel may be designed as a circle. The device 200 (or device 300, device 400 or device 500) or the wafer conveying equipment places the entire or partial edge area of ​​the wafer in the first space for processing. In some embodiments, the first channel may be designed as an arc with an arc less than 360 degrees. The device 200 (or device 300, device 400 or device 500) or the wafer conveying equipment places the partial edge area of ​​the wafer in the first space for processing.

[0083] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 608, the upper chamber or the lower chamber of the device 200 (or the device 300, 400 or 500) has a raised portion. The device can use the raised portion to abut the edge of the wafer. When the upper chamber moves from the first position to the second position, the raised portion contacts the edge of the wafer. Then, the raised portion abuts the edge of the wafer and pushes the wafer to move on the upper surface of the first support area of ​​the lower chamber. When the upper chamber is closed to the lower chamber, the wafer is fixed on the upper surface of the first support area, and the central axis XX of the wafer is parallel to the central axis X'-X' of the second support area. The distance between the central axis XX of the wafer and the central axis X'-X' of the second support area can be in the range of 0mm-0.1mm. In some embodiments, the raised portion can be adjacent to the second support area and extend toward the lower chamber. In one embodiment, the raised portion is adjacent to the first channel.

[0084] In some embodiments, the raised portion includes an inner angle facing the central axis X'-X' of the second support area. The inner angle is formed by the intersection of the inner surface of the raised portion and the inner surface of the first channel and faces the central axis X'-X' of the second support area. In one embodiment, the inner angle abuts against the edge area of ​​the wafer. When the upper chamber moves from the first position to the second position, the inner angle of the raised portion contacts the edge of the wafer, then abuts against the edge of the wafer, and pushes the wafer. In other embodiments, the inner surface of the raised portion contacts the edge of the wafer, then abuts against the edge of the wafer, and pushes the wafer.

[0085] In some embodiments of method 600 or any combination of the foregoing embodiments, in step 610, the device 200 (or the device 300, the device 400, or the device 500) may inject one or more chemical fluids into the first space for etching the edge area of ​​the wafer. The one or more chemical fluids flow around the edge of the wafer in the first space and etching the edge area of ​​the wafer exposed in the first space. In some embodiments, the device includes a through hole connecting the first space with the outside of the device. The one or more chemical fluids may flow into the first space through the through hole. In some embodiments, the one or more chemical fluids may flow from the first space to the outside of the device through the through hole. In other embodiments, the device includes two through holes, each of which connects the first space with the outside of the device. The two through holes are a certain distance apart. The one or more chemical fluids flow into the first space through one through hole and flow out of the device from the first space through the other through hole.

[0086] As mentioned in the background technology, since most materials have a certain temperature expansion coefficient. A semiconductor wafer edge processing device (also referred to as a semiconductor processing device) made of a material with a higher temperature expansion coefficient may change the corrosion conditions during use of the semiconductor wafer edge processing device that can meet the wafer edge corrosion accuracy requirements during manufacturing due to the gap between the manufacturing temperature and the use temperature and the temperature difference changes during transportation, or changes in other factors, resulting in the corrosion effect, accuracy and uniformity failing to meet the process requirements. In order to solve this problem, it is necessary to ensure that the environmental factors during manufacturing are consistent with the environmental factors during use, and temperature control is also required during the transportation process. If it is found that the corrosion effect changes during use and cannot meet the process requirements, a very complicated modification and adjustment process is required, which brings very big problems to the promotion and application of the semiconductor wafer edge processing device.

[0087] The semiconductor wafer edge processing device of the present invention can be manufactured from polytetrafluoroethylene (PTFE). PTFE is highly resistant to acids, alkalis, and various organic solvents, making it compatible with virtually any chemical solvent. Furthermore, PTFE panels are exceptionally pure, with minimal metal contamination, making them the preferred material for chemical reaction tanks and reaction chambers used in wet process equipment for semiconductor manufacturing.

[0088] The basic structure of polytetrafluoroethylene is: -CF2-CF2-CF2-CF2-CF2-CF2-CF2-, where the -CF2- units are arranged in a zigzag shape. Since the radius of the fluorine atom is slightly larger than that of the hydrogen atom, the adjacent CF2 units cannot be completely oriented in a trans-cross orientation, but instead form a spiral twisted chain, with the fluorine atoms almost covering the entire surface of the polymer chain. This molecular structure explains the various properties of polytetrafluoroethylene. When the temperature is below 19°C, a 13 / 6 helix is ​​formed; at 19°C, a phase transition occurs, and the molecules slightly untwist to form a 15 / 7 helix. Figure 7 As shown, the linear expansion coefficient of polytetrafluoroethylene is different in different temperature ranges. It is larger than most plastics and 10 to 20 times that of steel. The linear expansion coefficient of polytetrafluoroethylene changes very irregularly with changes in temperature, especially around 19°C, where its linear expansion coefficient changes greatly. Therefore, if insufficient attention is paid to this aspect of performance during application, unexpected problems may easily occur, affecting the application effect and causing losses. The semiconductor processing device made of polytetrafluoroethylene in the present invention will cause changes in the wafer positioning accuracy (the accuracy of the corrosion edge of the wafer) and the corrosion area of ​​the semiconductor processing device due to changes in the manufacturing temperature and the operating temperature. Of course, in addition to the impact of temperature changes on the accuracy of the corrosion edge of the wafer, there are various other complex factors that may affect the accuracy of the corrosion edge of the wafer, such as vibration during transportation, changes in humidity, and some unknown factors.

[0089] In order to reduce the influence of temperature changes or other factors on the edge corrosion of the wafer, the present invention provides a semiconductor processing device with fine-tunable wafer positioning accuracy. Figure 8 , which is a schematic structural diagram of a semiconductor processing device with fine-tunable wafer positioning accuracy in one embodiment of the present invention.

[0090] Figure 8 Semiconductor processing equipment in Figure 3a The semiconductor processing equipment in the Figure 8 The semiconductor processing device further includes: a temperature control component 810 disposed adjacent to the upper chamber. The temperature control component 810 can adjust the temperature of the upper chamber 320 by adjusting its own temperature. By adjusting the temperature of the upper chamber 320 using the temperature control component 810, the position of the positioning structure is fine-tuned using the thermal expansion and contraction characteristics of the upper chamber 320, thereby adjusting the alignment accuracy between the central axis of the wafer and the central axis of the second support area (i.e., wafer positioning accuracy), ultimately ensuring that the edge corrosion effect on the wafer meets the requirements. The edge corrosion effect includes one or more of edge corrosion completeness, edge corrosion uniformity, and edge corrosion width.

[0091] The edge corrosion completeness reflects whether the portions of the wafer edge that need to be corroded have been completely corroded. For example, if some portions that need to be corroded have not been corroded, the edge corrosion completeness is low. If all portions that need to be corroded have been corroded, the edge corrosion completeness is high. In one embodiment, the edge corrosion completeness needs to be completely corroded. If some portions that need to be corroded have not been corroded, the edge corrosion completeness is considered to be unsatisfactory. If all portions that need to be corroded have been corroded, the edge corrosion completeness is considered to be satisfied.

[0092] Edge corrosion uniformity reflects the consistency of the corrosion width along the wafer edge. For example, if some edge portions have wide corrosion widths and others have narrow corrosion widths, the edge corrosion uniformity will be poor. Alternatively, if the corrosion widths of all portions of the edge are similar, the edge corrosion uniformity will be good. Edge corrosion uniformity can typically be expressed as the difference between the minimum and maximum corrosion widths along the wafer edge. Edge corrosion uniformity is directly related to the alignment accuracy between the wafer's central axis and the second support area's central axis. The higher the alignment accuracy between the wafer's central axis and the second support area's central axis, the higher the wafer's edge corrosion uniformity. Conversely, the lower the alignment accuracy between the wafer's central axis and the second support area's central axis, the lower the wafer's edge corrosion uniformity. The wafer's edge corrosion uniformity can be used to determine the alignment accuracy between the wafer's central axis and the second support area's central axis. In one embodiment, a predetermined uniformity threshold range is provided. If the measured edge corrosion uniformity falls below the uniformity threshold range, it is considered unsatisfactory; if it falls within the uniformity threshold range, it is considered satisfactory.

[0093] The positioning structure can be made to rest tightly against the edge of the wafer to improve the uniformity of edge corrosion, but if it rests too tightly, the positioning structure will be in close contact with the edge of the wafer, so that the portion of the edge in contact will not be corroded, resulting in reduced edge corrosion integrity. Therefore, the position of the positioning structure can be fine-tuned by the temperature control component 810 to adjust the positioning structure and the edge of the wafer to a suitable tightness, so that the precise positioning of the wafer can be achieved without affecting the edge corrosion integrity of the wafer. The edge corrosion width reflects the corrosion width of the edge of the wafer, as shown in Figure 1. By using the temperature control component to adjust the temperature of the upper chamber and / or the lower chamber, the position of the edge of the first support area and / or the second support area can be fine-tuned by utilizing the thermal expansion and contraction of the upper chamber and / or the lower chamber, thereby adjusting the width of the edge area of ​​the wafer extending into the first space, and finally adjusting the corrosion width of the edge of the wafer. In one embodiment, a predetermined edge corrosion width threshold range is set. If the measured edge corrosion width is lower or higher than the edge corrosion width threshold range, it is considered that the requirement is not met; if it is equal to the edge corrosion width threshold range, it is considered that the requirement is met.

[0094] In one embodiment, the temperature control assembly 810 is set to a preset temperature value. The temperature control assembly 810 is first set to the preset temperature value. After the temperature of the upper chamber 320 stabilizes, the wafer is placed in the working area of ​​the lower chamber. The upper chamber 320 and the lower chamber 310 are then closed and the edge of the wafer is etched. The edge etch effect of the wafer is then measured, such as measuring the alignment accuracy of the central axis of the wafer and the central axis of the second support area. It is determined whether the measured edge etch effect of the wafer edge meets the requirements. If it does not meet the requirements, the temperature value of the temperature control assembly 810 can be increased or decreased according to the temperature expansion curve of the upper chamber 320. The edge of the wafer is continuously etched and the edge etch effect of the wafer is measured until the measured edge etch effect meets the requirements. For example, the alignment accuracy of the central axis of the wafer and the central axis of the second support area meets the requirements, that is, the edge etch uniformity meets the requirements. For example, the alignment accuracy requirement can be that the error between the central axis of the wafer and the central axis of the second support area does not exceed 0.1 mm.

[0095] Due to the provision of the temperature control assembly 810, the temperature of the upper chamber can be adjusted as needed. By adjusting the temperature of the temperature control assembly 810, not only can minor changes in the size of the upper chamber caused by temperature changes be reduced, but also minor changes in the size of the upper chamber caused by other factors can be reduced, thereby reducing the impact of temperature changes or other factors on the edge corrosion of the wafer.

[0096] In one embodiment, the temperature control assembly 810 includes a temperature control component 811 and a diffusion component 812. The diffusion component 812 is disposed between the temperature control component 811 and the upper chamber 320. The temperature control component 811 includes multiple electric heating units. The temperature of the temperature control component 811 is controlled by controlling the electric heating units. The diffusion component 812 transfers heat to the upper chamber 320, thereby adjusting the temperature of the upper chamber 320. Specifically, the electric heating units may be electric heating resistors.

[0097] The temperature control component 810 and the upper chamber 320 can be designed as separate bodies and assembled together through connecting components, or they can be set as an integral whole.

[0098] In other embodiments, as needed, the temperature control component 810 may also be disposed on the lower side of the lower chamber 310 to adjust the temperature of the lower chamber 310. Of course, as needed, a corresponding temperature control component 810 may also be disposed on the upper side of the upper chamber 320 and the lower side of the lower chamber 310 to adjust the temperature of both the lower chamber 310 and the upper chamber 320.

[0099] According to another aspect of the present invention, the present invention provides a semiconductor edge positioning method, which includes the following steps.

[0100] S1, placing a wafer in a first supporting area of ​​a lower chamber of a semiconductor processing device;

[0101] S2. Closing the upper chamber and the lower chamber of the semiconductor processing apparatus, fixing the wafer between the first supporting area and the second supporting area, causing the positioning structure of the upper chamber and / or the lower chamber to abut against the outer edge of the wafer and aligning the central axis of the wafer with the central axis of the second supporting area, wherein a temperature control component disposed adjacent to the upper chamber and / or the lower chamber in the semiconductor processing apparatus is capable of adjusting its own temperature and being set to a predetermined temperature value;

[0102] S3, forming a first channel in an edge region of the first supporting area or the second supporting area, wherein the first channel provides a first space, and injecting one or more chemical fluids into the first space to etch the edge region of the wafer;

[0103] S4. Measure the edge corrosion effect of the wafer to determine whether the measured edge corrosion effect meets the requirements. If not, increase or decrease the temperature value of the temperature control component, continue to corrode the edge of the wafer and measure the edge corrosion effect of the wafer until the measured edge corrosion effect meets the requirements.

[0104] By setting up the temperature control component 810, the processing, transportation and installation requirements of the semiconductor processing device can be greatly reduced, the related processing, transportation, installation and calibration costs of the semiconductor processing device can be greatly reduced, and the application of the semiconductor processing device can be promoted.

[0105] Certain embodiments may be viewed as computer program products comprising instructions stored on a non-transitory machine-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the described operations. A machine-readable medium includes any mechanism for storing or transmitting information in a machine (e.g., computer) readable form (e.g., software, processing applications). A machine-readable medium may include, but is not limited to, magnetic storage media (e.g., floppy disks), optical storage media (e.g., CD-ROMs), magneto-optical storage media, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or other types of media suitable for storing electronic instructions. A machine-readable medium may be referred to as a non-transitory machine-readable medium.

[0106] The above description is intended to be illustrative rather than restrictive. Although the present invention has been described with reference to specific illustrative examples, it should be understood that the present invention is not limited to the described embodiments. The scope of the present invention should be determined with reference to the claims and the full scope of equivalents of the claims.

[0107] The "one example (embodiment)" or "example (embodiment)" referred to herein means that the specific features, structures or characteristics associated with the embodiment may be included in at least one implementation of the present invention. The "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it necessarily a separate or selected embodiment that is mutually exclusive with other embodiments. "Multiple" and "several" in the present invention mean two or more. "And / or" in the present invention means "and" or "or". In addition, the terms "first", "second", "third", "fourth" and the like used herein are intended to be used as labels to distinguish different elements, and may not necessarily have sequential meanings according to their numerical designations. Therefore, the terms used herein are only for the purpose of describing specific implementations and are not intended to be limiting.

[0108] It should also be noted that in some alternative embodiments, the functions / actions noted may not occur in the order noted in the figures. For example, two figures shown in succession may actually be performed substantially simultaneously or may sometimes be performed in reverse order, depending on the functions / actions involved.

[0109] Although the method operations are described in a particular order, it should be understood that other operations can be performed between the described operations. The described operations can be adjusted so that they occur at slightly different times, or the described operations can be distributed throughout the system. The system allows multiple unrelated programs to be processed simultaneously.

[0110] Many modifications and other implementations of the present invention involve those skilled in the art who have relevant industry knowledge and some original data. Therefore, it should be understood that the present invention is not limited to the specific embodiments disclosed, but also includes other embodiments modified within the scope of the appended claims. In addition, although the foregoing description and related drawings describe the implementation of specific embodiment combinations of elements and functions, within the scope of the appended claims, elements and functions that are implemented in different combinations by substitution are also included. The appended claims also include combinations of elements and functions that are different from the elements and functions explicitly described above. Although specific terms are used herein, they are intended to be generally descriptive only and not for limiting purposes.

Claims

1. A semiconductor processing device, characterized in that: It includes: a lower chamber having a first supporting area for supporting a wafer; an upper chamber having a second support area, wherein when the upper chamber is closed to the lower chamber, the wafer is positioned between the first support area and the second support area; a temperature control component disposed adjacent to the upper chamber and / or the lower chamber, which adjusts the temperature of the upper chamber and / or the lower chamber by adjusting its own temperature; A first channel is formed in the edge area of ​​the first supporting area or the second supporting area, and the first channel provides a first space for circulating one or more chemical fluids that erode the edge area of ​​the wafer. The upper chamber and / or the lower chamber includes a positioning structure, wherein the positioning structure is used to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second supporting area. The temperature of the upper chamber and / or the lower chamber is adjusted by using the temperature control component, thereby utilizing the thermal expansion and contraction characteristics of the upper chamber and / or the lower chamber to fine-tune the position of the positioning structure, thereby adjusting the alignment accuracy between the center axis of the wafer and the center axis of the second support area.

2. The semiconductor processing device according to claim 1, wherein The positioning structure is arranged on the upper chamber. The positioning mechanism is a raised portion. The raised portion is used to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second supporting area.

3. The semiconductor processing device according to claim 2, wherein: The raised portion of the upper chamber is adjacent to the second supporting area and extends toward the lower chamber, the central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second supporting area is perpendicular to the lower surface of the upper chamber, the upper surface of the wafer is parallel to the lower surface of the second supporting area, and the raised portion includes a curved portion designed in a ring shape around the outer end of the wafer, and the raised portion is evenly abutted against the edge outer end area of ​​the wafer, so that the central axis of the wafer overlaps with the central axis of the second supporting area.

4. The semiconductor processing device according to claim 2, wherein: The raised portion includes a plurality of protrusions that are evenly distributed around the outer end of the wafer in a ring shape and are used to evenly abut against the outer end area of ​​the edge of the wafer.

5. The semiconductor processing apparatus according to claim 3, wherein: The protruding portion includes an inner surface inclined at a certain angle to the central axis of the second supporting area, and the inner surface abuts against an outer end region of an edge of the wafer.

6. The semiconductor processing apparatus according to claim 3, wherein: The raised portion includes an inner corner facing the central axis of the second supporting area, and the inner corner abuts against an outer end region of the edge of the wafer.

7. The semiconductor processing apparatus according to claim 1, wherein: The first channel is located in the edge area of ​​the lower chamber and provides a first channel space for the flow of one or more chemical fluids. At the same time, a channel is formed between the upper chamber and the lower chamber, which connects the first space and the first channel space, so that one or more chemical fluids flow from the first space into the first channel space through the channel.

8. The semiconductor processing apparatus according to claim 7, wherein: The second channel is formed in the edge area of ​​the upper chamber and is located above the first channel. An elastic component is provided between the first channel and the second channel, and the elastic component is used to prevent one or more chemical fluids from flowing from the first space to the first channel space. The edge area of ​​the second supporting area forms a first channel, and one or more chemical fluids flow between the first space and the outside of the device through the first through hole located in the upper chamber. The edge area of ​​the first supporting area forms a second channel, providing a second space for circulating one or more chemical fluids used to etch the edge area of ​​the wafer. The lower cavity provides a second through hole for enabling one or more chemical fluids to flow between the second space of the lower cavity and the outside of the device. The edge area of ​​the first supporting area forms a first channel, the lower chamber includes a first through hole, and one or more chemical fluids flow through the first space and the outside of the device through the first through hole located in the lower chamber.

9. The semiconductor processing apparatus according to claim 1, wherein: The temperature control component is set with a preset temperature value, so that the upper chamber and the lower chamber are closed, and the edge of the wafer is corroded; The edge corrosion effect of the wafer is measured to determine whether the measured edge corrosion effect meets the requirements. If it does not meet the requirements, the temperature value of the temperature control component is increased or decreased, and the edge of the wafer is continuously corroded and the edge corrosion effect of the wafer is measured until the measured edge corrosion effect meets the requirements.

10. The semiconductor processing apparatus according to claim 1, wherein The temperature control component includes a temperature regulating component and a diffusion component. The diffusion component is arranged between the temperature regulating component and the upper chamber and / or the lower chamber. The temperature regulating component includes a plurality of electric heating units.

11. A semiconductor processing system comprising: A semiconductor processing device according to any one of claims 1 to 10; A material storage device connected to the semiconductor processing device is used to store and exchange one or more chemical fluids with the semiconductor processing device.

12. The semiconductor processing system of claim 11, wherein: The positioning structure is arranged on the upper chamber, and the positioning mechanism is a raised portion, which is used to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The raised portion is adjacent to the second support area and extends toward the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support area. The raised portion includes a closed loop portion designed around the outer edge of the wafer. The raised portion evenly abuts against the outer edge area of ​​the wafer, so that the central axis of the wafer overlaps with the central axis of the second support area.

13. The semiconductor processing system of claim 11 , wherein: The positioning structure is arranged on the upper chamber, and the positioning mechanism is a raised portion, which is used to abut against the outer edge of the wafer and align the central axis of the wafer with the central axis of the second support area. The raised portion is adjacent to the second support area and extends toward the lower chamber. The central axis of the wafer is perpendicular to the upper surface of the wafer, the central axis of the second support area is perpendicular to the lower surface of the upper chamber, and the upper surface of the wafer is parallel to the lower surface of the second support area; the raised portion includes a plurality of protrusions, which are evenly distributed in a ring around the outer edge of the wafer, and are used to evenly abut against the outer edge area of ​​the wafer.

14. The semiconductor processing system of claim 11 , wherein: The first channel is located in the edge area of ​​the lower chamber and provides a first channel space for passing one or more chemical fluids. At the same time, a channel is formed between the upper chamber and the lower chamber, which connects the first space and the first channel space, so that one or more chemical fluids flow from the first space into the first channel space through the channel. The second channel is formed in the edge area of ​​the upper chamber and is located above the first channel. An elastic component is designed and placed between the first channel and the second channel. The elastic component is used to prevent one or more chemical fluids from flowing from the first space to the first channel space.

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