Nonvolatile memory cell and method of manufacturing, controlling and nonvolatile memory system
By introducing a surface-pretreated dielectric layer and a chalcogenide semiconductor alloy threshold switching layer into the OTS non-volatile memory cell, the problem of insufficient threshold window in large-scale memory arrays of OTS non-volatile memory cells is solved, achieving more significant threshold state differences and lower leakage current, making it suitable for large-scale memory arrays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2023-06-28
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies make it difficult to achieve OTS non-volatile memory cells with large threshold windows, which limits their application in large-scale memory arrays.
The first metal electrode layer, the first dielectric layer with surface pretreatment, the threshold switch layer and the second metal electrode layer are stacked sequentially from bottom to top. The threshold switch layer material is a chalcogenide semiconductor alloy. The surface pretreatment introduces interface state differences at the interface and introduces significant threshold state differences during positive and negative electrical operation.
The threshold increment has been increased, making it suitable for large-scale OTS-only memory arrays. This alleviates the problem of increased leakage current and ensures the reliability and speed of the memory cells.
Smart Images
Figure CN116847723B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of storage technology, and more specifically, relates to a non-volatile storage cell, its preparation and control method, and a non-volatile storage system. Background Technology
[0002] Dynamic Random Access Memory (DRAM) has been the main memory in computer storage architectures for decades due to its advantages in both speed and storage density. However, as the technology node has entered the 20nm stage, DRAM is limited by the reduction in capacitance and the increase in transistor leakage current caused by size reduction. It has approached the physical limit of size reduction, and the complex process and high cost required for further DRAM miniaturization have also led to the gradual saturation of the cost benefits brought by its miniaturization. This has created a barrier in terms of physical size and cost, resulting in the "miniaturization wall".
[0003] Therefore, new types of memory are needed that can achieve smaller process dimensions while matching the access speed of DRAM. Among the current mainstream novel memories based on resistance switching mechanisms, resistive random access memory (RRAM) and phase-change memory (PCM) have read / write speeds that are difficult to match with DRAM because the memory cells must undergo non-volatile structural transitions during erase and write operations. While spin-transfer torque-transfer magnetic random access memory (STT-MRAM) has advantages in read / write speed, it has disadvantages in scalability, storage density, and cost, and is considered more suitable for applications of static random access memory (SRAM). Ferroelectric RAM (FeRAM) also faces serious miniaturization challenges.
[0004] Ovonic threshold switches (OTSs) offer advantages such as high switching speed, low manufacturing cost, and ease of 3D stacking, making them suitable for DRAM applications in terms of speed and density. Currently, there are solutions for information storage based on controllable threshold voltage changes using OVonic threshold switches. However, existing solutions suffer from threshold voltage increments primarily due to the characteristics of the threshold switch layer material, making optimization difficult and limiting the potential for large-scale OTS-only memory arrays. Summary of the Invention
[0005] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a non-volatile memory cell and its preparation and control method, as well as a non-volatile memory system, with the aim of providing an OTS non-volatile memory cell with a large threshold window.
[0006] To achieve the above objectives, in a first aspect, the present invention provides a non-volatile memory cell, comprising: a first metal electrode layer, a first dielectric layer, a threshold switch layer, and a second metal electrode layer stacked sequentially from bottom to top;
[0007] The threshold switching layer material is a chalcogenide semiconductor alloy;
[0008] The first dielectric layer is a dielectric layer whose upper surface has undergone surface pretreatment. It is used to introduce interface defects to the lower surface of the threshold switch layer, thereby increasing the interface state difference between the upper and lower surfaces of the threshold switch layer.
[0009] More preferably, the surface pretreatment includes: plasma cleaning, argon ion surface bombardment, surface smoothing etching, or chemical mechanical polishing.
[0010] More preferably, the threshold switching layer material includes one or more of Ge, Se, Te, S, and As.
[0011] More preferably, the threshold switching layer material further includes: a doping element; wherein the doping element includes one or more of C, Si, N, Sb, B, O, Al, Ga, In, and Sn.
[0012] More preferably, the thickness of the first dielectric layer is 0.5-5 nm.
[0013] More preferably, the above-mentioned non-volatile memory cell further includes a second dielectric layer disposed between the threshold switch layer and the second metal electrode layer.
[0014] More preferably, the thickness of the second dielectric layer is 0.5-5 nm.
[0015] Secondly, the present invention provides a method for fabricating the above-mentioned non-volatile memory cell, comprising:
[0016] A first dielectric layer is deposited on the first metal electrode layer, and the upper surface of the first dielectric layer is pretreated.
[0017] A threshold switching layer is deposited on the upper surface of the first dielectric layer; wherein the threshold switching layer material is a chalcogenide semiconductor alloy.
[0018] A second metal electrode layer is deposited on the threshold switching layer to obtain a non-volatile memory cell.
[0019] Thirdly, the present invention provides a control method for the above-mentioned non-volatile memory cell, comprising:
[0020] Upon receiving the write first data instruction, a first voltage is applied to the non-volatile memory cell to turn it on; at this time, the non-volatile memory cell has a first threshold voltage.
[0021] Upon receiving a write second data instruction, a second voltage opposite to the direction of the first voltage is applied to the non-volatile memory cell, causing the non-volatile memory cell to conduct; at this time, the non-volatile memory cell has a second threshold voltage.
[0022] Upon receiving a read command, a read voltage in the same direction as the first voltage is applied to the non-volatile memory cell, and it is determined whether the non-volatile memory cell is turned on. If it is turned on, the read result is the first data; otherwise, the read result is the second data.
[0023] Among them, one of the first data and the other of the second data is a logic "1" and the other is a logic "0"; the amplitude of the read voltage is between the first threshold voltage and the second threshold voltage.
[0024] Fourthly, the present invention provides a non-volatile memory system, comprising: a control unit and a non-volatile memory unit provided in the first aspect of the present invention;
[0025] The control unit is used to execute the control method provided in the second aspect of the present invention.
[0026] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:
[0027] 1. This invention provides a non-volatile memory cell, comprising a first metal electrode layer, a first dielectric layer, a threshold switch layer, and a second metal electrode layer stacked sequentially from bottom to top; wherein, the first dielectric layer is a dielectric layer whose upper surface has undergone surface pretreatment. By performing surface pretreatment on the upper surface of the first dielectric, the surface of the threshold switch layer in contact with the dielectric surface has more interface states, thereby introducing polar interface influence into the initial deposition state of the threshold switch layer due to the large difference in interface states between the upper and lower surfaces. This makes the threshold state difference of the threshold switch layer during positive and negative electrical operations more significant, greatly improving the threshold increment and making it more suitable for large-scale OTS-only memory arrays.
[0028] 2. Furthermore, the first and second dielectric layers in the non-volatile memory cells provided by this invention can further alleviate the problem of significantly increased leakage current caused by surface pretreatment, ensuring that OTS can still be used in large-scale OTS-only memory arrays. Specifically, after introducing surface pretreatment technology, the threshold switching layer generates more interface states and introduces more interband states, making it easier for electrons to transition from the valence band to the conduction band, resulting in greater leakage current under the same external field. After introducing the dielectric layer, due to the electrical insulation properties of the dielectric layer, electrons still need to tunnel through the dielectric layer after transition to form leakage current, so only fewer electrons can generate leakage current. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of the structure of the non-volatile memory cell provided in Embodiment 1 of the present invention;
[0030] Figure 2 A flowchart illustrating the fabrication method of the non-volatile memory cell provided in Embodiment 2 of the present invention;
[0031] Figure 3 This is a schematic diagram of the structure of the non-volatile memory system provided in Embodiment 4 of the present invention;
[0032] Figure 4 This is a schematic diagram illustrating the storage function implemented based on the electrical characteristics of the non-volatile memory cell, as provided in Embodiment 4 of the present invention. Detailed Implementation
[0033] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0034] Example 1
[0035] A non-volatile memory cell 100, such as Figure 1 As shown, it includes: a first metal electrode layer 110, a first dielectric layer 120, a threshold switch layer 140, and a second metal electrode layer 150 stacked sequentially from bottom to top;
[0036] The threshold switching layer material is a chalcogenide semiconductor alloy;
[0037] The first dielectric layer is a dielectric layer whose upper surface has undergone surface pretreatment (where 130 is the upper surface of the dielectric layer after surface pretreatment), which is used to introduce interface defects to the lower surface of the threshold switch layer, thereby increasing the interface state difference between the upper and lower surfaces of the threshold switch layer.
[0038] Surface pretreatment can include plasma cleaning, argon ion surface bombardment, surface smoothing etching, and chemical mechanical polishing. Threshold switching layer materials include one or more of Ge, Se, Te, S, and As. Threshold switching layer materials also include doping elements; these doping elements include one or more of C, Si, N, Sb, B, O, Al, Ga, In, and Sn. It should be noted that in some devices, doping with C and N can improve the thermal stability of the device, enabling it to meet the requirements of CMOS back-end processes; doping with In can reduce threshold drift; and doping with B can reduce leakage current and improve the cycling characteristics of the device.
[0039] It should be noted that directly treating the electrode material using surface pretreatment technology significantly increases the leakage current of the threshold switch layer, and the polarity interface effect generated by the pretreatment of the electrode surface is not significant. Therefore, a first dielectric layer after surface pretreatment is needed to concentrate the effect of surface pretreatment on the threshold switch layer surface in contact with the first dielectric layer. In addition, the first dielectric layer can alleviate the problem of significantly increased leakage current caused by surface pretreatment, ensuring that the OTS can still be used in large-scale OTS-only memory arrays. This invention, by pretreating the upper surface of the first dielectric, creates more interface states on the threshold switch layer surface in contact with the dielectric surface. Therefore, the significant difference in interface states between the upper and lower surfaces introduces a polarity interface effect in the initial deposition state, making the threshold state difference of the OTS during positive and negative electrical operation more significant, thus making it more suitable for large-scale OTS-only memory arrays.
[0040] Preferably, the thickness of the first dielectric layer is 0.5-5 nm.
[0041] It should be noted that the non-volatile memory cell has a first threshold voltage after being turned on by applying a first voltage; the non-volatile memory cell has a second threshold voltage after being turned on by applying a second voltage opposite to the first voltage; the absolute value of the difference between the first threshold voltage and the second threshold voltage is relatively large, greater than or equal to 0.5V. Specifically, the first voltage can be a positive voltage or a negative voltage, and correspondingly, the second voltage can be a negative voltage or a positive voltage. In one optional embodiment, the first voltage is a positive voltage, that is, after applying this voltage across the non-volatile memory cell, the current flows from the second metal electrode layer to the first metal electrode layer; the second voltage is a negative voltage, that is, after applying this voltage across the non-volatile memory cell, the current flows from the first metal electrode layer to the second metal electrode layer; in this case, the first threshold voltage is significantly smaller than the second threshold voltage.
[0042] Furthermore, to further mitigate the problem of increased leakage current caused by surface pretreatment and ensure that OTS can still be used in large-scale OTS-only memory arrays, preferably, in an optional embodiment, the above-mentioned non-volatile memory cell further includes: a second dielectric layer disposed between the threshold switch layer and the second metal electrode layer. The surface of the second dielectric layer has not undergone surface pretreatment. Preferably, the thickness of the second dielectric layer is 0.5-5 nm.
[0043] To further illustrate the non-volatile memory unit provided by the present invention, the following detailed description is provided in conjunction with several specific embodiments:
[0044] In Implementation Method 1, the surface pretreatment used is plasma cleaning, the first dielectric layer material is HfO2 with a thickness of 2 nm, and the threshold switching layer material is Ge. a Se b In c B d With a thickness of 30 nm and a plasma cleaning time of 5 minutes, the resulting device achieves a threshold voltage increment of 1.5 V and a leakage current of less than 100 nA. In contrast, directly using Ge as the threshold switching layer material... a Se b In c B d The threshold increment of the device is between 0.2 and 0.5V.
[0045] In embodiment two, the surface pretreatment used is argon ion surface bombardment, the first dielectric layer material is HfO2 with a thickness of 2 nm, and the threshold switching layer material is Ge. a Se b In c B d With a thickness of 30 nm and an argon ion surface bombardment time of 2 minutes, the resulting device achieved a threshold voltage increment of 1.8 V and a leakage current of less than 100 nA. In contrast, directly using Ge as the threshold switching layer material... a Se b In c B d The threshold increment of the device is between 0.2 and 0.5V.
[0046] In embodiment three, the surface pretreatment used is surface smoothing etching, the first dielectric layer material is HfO2 with a thickness of 5 nm, and the threshold switching layer material is Ge. a Se b In c B d With a thickness of 30nm, the surface was smoothly etched using CF4 and O2 gases for 20s. The resulting device achieved a threshold voltage increment of 2V and a leakage current of less than 20nA. In contrast, directly using Ge as the threshold switching layer material...a Se b In c B d The threshold increment of the device is between 0.2 and 0.5V.
[0047] Example 2
[0048] The method for fabricating a non-volatile memory cell provided in Embodiment 1 of the present invention includes:
[0049] A first dielectric layer is deposited on the first metal electrode layer, and the upper surface of the first dielectric layer is pretreated.
[0050] A threshold switching layer is deposited on the upper surface of the first dielectric layer; wherein the threshold switching layer material is a chalcogenide semiconductor alloy.
[0051] A second metal electrode layer is deposited on the threshold switching layer to obtain a non-volatile memory cell.
[0052] Specifically, such as Figure 2 As shown, in one optional embodiment, after depositing the first metal electrode layer (lower electrode), a dielectric material is first deposited to obtain the first dielectric layer. Then, the upper surface of the first dielectric layer is treated with a surface pretreatment technique (argon plasma cleaning). Next, a threshold switch layer is deposited on the surface-pretreated first dielectric layer. Finally, a second metal electrode layer is deposited on the threshold switch layer to obtain a non-volatile memory cell.
[0053] Preferably, in an optional embodiment, the above preparation method further includes: after obtaining the threshold switch layer, before depositing the second metal electrode layer, depositing a second dielectric layer on the upper surface of the threshold switch layer, so as to further alleviate the problem of increased leakage current caused by surface pretreatment and ensure that the OTS can still be used in large-scale OTS-only memory arrays.
[0054] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.
[0055] Example 3
[0056] The control method for non-volatile memory cells provided in Embodiment 1 of the present invention includes:
[0057] Upon receiving the write first data instruction, a first voltage is applied to the non-volatile memory cell to turn it on; at this time, the non-volatile memory cell has a first threshold voltage.
[0058] Upon receiving a write second data instruction, a second voltage opposite to the direction of the first voltage is applied to the non-volatile memory cell, causing the non-volatile memory cell to conduct; at this time, the non-volatile memory cell has a second threshold voltage.
[0059] Upon receiving a read command, a read voltage in the same direction as the first voltage is applied to the non-volatile memory cell, and it is determined whether the non-volatile memory cell is turned on. If it is turned on, the read result is the first data; otherwise, the read result is the second data.
[0060] Among them, one of the first data and the other of the second data is a logic "1" and the other is a logic "0"; the amplitude of the read voltage is between the first threshold voltage and the second threshold voltage.
[0061] Specifically, in one optional implementation, the first data is logic "1", the second data is logic "0", the first voltage is a positive voltage, the second voltage is a negative voltage, and the read voltage is a positive voltage.
[0062] In one optional implementation, the first data is logic "0", the second data is logic "1", the first voltage is a positive voltage, the second voltage is a negative voltage, and the read voltage is a positive voltage.
[0063] In one optional implementation, the first data is logic "1", the second data is logic "0", the first voltage is a negative voltage, the second voltage is a positive voltage, and the read voltage is a negative voltage.
[0064] In one optional implementation, the first data is logic "0", the second data is logic "1", the first voltage is a negative voltage, the second voltage is a positive voltage, and the read voltage is a negative voltage.
[0065] It should be noted that it is only necessary to ensure that the first voltage is in the opposite direction to the first voltage, the reading voltage is in the same direction as the first voltage, and the amplitude of the reading voltage is between the first threshold voltage and the second threshold voltage.
[0066] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.
[0067] Example 4
[0068] A non-volatile memory system includes: a control unit and a non-volatile memory unit provided in Embodiment 1 of the present invention;
[0069] The control unit is used to execute the control method provided in Embodiment 2 of the present invention.
[0070] Specifically, such as Figure 3As shown, in one optional implementation, the above-described non-volatile memory system includes a plurality of non-volatile memory cells 310 that can be operated in different logical states. The word line 315 and bit line 320 of a specific memory cell can be selected. The word line 315 and bit line 320 are spatially perpendicular (including approximately perpendicular). All non-volatile memory cells in the non-volatile memory system can be distinguished and selected through the intersection of the word line 315 and the bit line 320. The non-volatile memory system 300 also includes a control unit for implementing operations on the memory cells, including a row decoder 325, a column decoder 330, a read component 335, a memory controller 340, and an input / output interface 345. When the non-volatile memory system 300 receives a write command, it sends the address information corresponding to the write command to the row decoder 325 and the column decoder 330 through the memory controller 340. The row decoder 325 activates the corresponding word line 315 according to the received row address, and the column decoder 330 activates the corresponding bit line 320 according to the received column address. Through the activated word line 315 and bit line 320, a write command is applied to the selected memory cell. When the memory array 300 receives a read instruction, similar to a write instruction, the memory controller 340 sends the address information of the read instruction to the row decoder 325 and column decoder 330 and activates the corresponding word line 315 and bit line 320. The read instruction is applied to the selected memory cell, and the voltage / current of the output is monitored by the read component. The logic state of the memory cell is read by the voltage / current amplifier in the read component and fed back to the memory controller 340 for output.
[0071] Furthermore, examples of implementing storage functions based on the electrical characteristics of this non-volatile memory cell include... Figure 4 As shown.
[0072] The relevant technical solutions are the same as those in Embodiments 1 and 2, and will not be repeated here.
[0073] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A non-volatile memory cell, characterized in that, include: The first metal electrode layer, the first dielectric layer, the threshold switch layer, and the second metal electrode layer are stacked sequentially from bottom to top. The threshold switching layer material is a chalcogenide semiconductor alloy; The first dielectric layer is a dielectric layer whose upper surface has undergone surface pretreatment, which is used to introduce interface defects to the lower surface of the threshold switch layer, thereby increasing the interface state difference between the upper and lower surfaces of the threshold switch layer.
2. The non-volatile memory cell according to claim 1, characterized in that, The surface pretreatment includes: plasma cleaning, argon ion surface bombardment, surface smoothing etching, or chemical mechanical polishing.
3. The non-volatile memory cell according to claim 1, characterized in that, The material of the threshold switching layer includes one or more of Ge, Se, Te, S, and As.
4. The non-volatile memory cell according to claim 1, characterized in that, The material of the threshold switching layer further includes: doping elements; wherein the doping elements include one or more of C, Si, N, Sb, B, O, Al, Ga, In, and Sn.
5. The non-volatile memory cell according to claim 1, characterized in that, The thickness of the first dielectric layer is 0.5-5 nm.
6. The non-volatile memory cell according to any one of claims 1-5, characterized in that, Also includes: A second dielectric layer is disposed between the threshold switch layer and the second metal electrode layer.
7. The non-volatile memory cell according to claim 6, characterized in that, The thickness of the second dielectric layer is 0.5-5 nm.
8. The method for fabricating the non-volatile memory cell according to claim 1, characterized in that, include: A first dielectric layer is deposited on the first metal electrode layer, and the upper surface of the first dielectric layer is pretreated. A threshold switching layer is deposited on the upper surface of the first dielectric layer; wherein the threshold switching layer material is a chalcogenide semiconductor alloy. A second metal electrode layer is deposited on the threshold switching layer to obtain a non-volatile memory cell.
9. The control method for the non-volatile memory cell according to any one of claims 1-7, characterized in that, include: Upon receiving a write first data instruction, a first voltage is applied to the non-volatile memory cell to turn it on. At this time, the non-volatile memory cell has a first threshold voltage; Upon receiving a write second data instruction, a second voltage opposite in direction to the first voltage is applied to the non-volatile memory cell, causing the non-volatile memory cell to conduct; at this time, the non-volatile memory cell has a second threshold voltage. Upon receiving a read command, a read voltage in the same direction as the first voltage is applied to the non-volatile memory cell, and it is determined whether the non-volatile memory cell is turned on. If it is turned on, the read result is the first data; otherwise, the read result is the second data. In this data, one of the first data and the second data is a logic "1" and the other is a logic "0"; the amplitude of the read voltage is between the first threshold voltage and the second threshold voltage.
10. A non-volatile storage system, characterized in that, include: The control unit and the non-volatile memory unit according to any one of claims 1-7; The control unit is used to execute the control method according to claim 9.