An extended dlp structured light display method and system

Abstract

The application relates to an extended DLP structured light display method and system, which comprises the following steps: dividing a high-resolution or high-bit-depth original pattern into multiple parts, multiplexing the same time sequence configuration for the divided patterns, and burning the multiple patterns and the time sequence configuration into corresponding numbers of DLP memories; a main controller receives an external trigger instruction, and after triggering multiple DLP modules corresponding to the DLP memories to synchronously output one pattern, each DLP module waits for a front dark field; exposure is started, and a camera is synchronously collected; after the exposure is finished, the collected image is output to an external AOI detection system, and after waiting for a rear dark field to finish one pattern period; through the division of the high-resolution or high-bit-depth original pattern and the accurate control trigger of the main controller on each DLP module, the delay control of the exposure time of each corresponding pattern of different DLP modules is within 20-40 ns, which is much smaller than 1us, the high-precision extended DLP structured light display function is realized, and the industrial AOI detection requirement can be met.

Description

Technical Field

[0001] This invention relates to the field of industrial AOI inspection technology, and more specifically, to an extended DLP structured light display method and system. Background Technology

[0002] In recent years, with the development of machine vision and artificial intelligence technologies, optical products using TI's DLP light control technology as the core of industrial 3D structured light displays have become increasingly popular. DLP technology has provided mature and stable 1-bit and 8-bit DMD display products, which can be used for relatively precise light control. For example, DLP3010LC or DLP4710LC display chips, combined with corresponding control chips such as DLPC3478 and DLPC3479, can precisely control the projection output of 720P (1280*720) or 1080P (1920*1080P) resolution 1D raster patterns. This light control technology is used in AOI, SPI, machine scanning, and other fields.

[0003] As application scenarios evolve, market demands for output resolution and optical power are gradually increasing. Improving resolution primarily addresses two needs: increasing the measured area while maintaining the same measurement accuracy, or improving measurement accuracy within the same measured area. Increasing optical power mainly aims to achieve higher light intensity or a higher bit depth grating within the same projected area.

[0004] However, TI is not releasing DMD products for optical control with higher physical resolution or higher bit depth very frequently, or their costs are relatively high. Therefore, a more cost-effective approach would be to combine multiple DMDs and drivers to enhance synchronous optical control and achieve higher resolution based on existing optical control DMDs.

[0005] Traditional methods of using multiple DMDs to enhance DLP display functionality are mainly based on RGB display or 3D printing applications, suitable for displays around 60Hz, with low synchronization accuracy requirements and relatively simple implementation. However, industrial AOI inspection requires inspection speeds of 180Hz, 240Hz, or even 360Hz. When using multiple DLP enhanced displays, the synchronization accuracy requirements are much higher. Traditional methods are difficult to meet the requirements for multi-module synchronous inspection. Therefore, an extended DLP structured light display method that can solve this industry problem is needed. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide an extended DLP structured light display method and an extended DLP structured light display system, in view of the above-mentioned defects of the prior art.

[0007] The technical solution adopted by this invention to solve its technical problem is:

[0008] An extended DLP structured light display method is constructed, comprising the following steps:

[0009] Step 1: Divide the high-resolution or high-bit-depth original pattern into multiple blocks and burn them into the corresponding DLP memory. Reuse the same timing configuration for the divided patterns and burn multiple patterns and timing configurations into each DLP memory.

[0010] Step 2: The main controller receives an external trigger command and simultaneously triggers multiple DLP modules, each corresponding to a DLP memory, to synchronously output a pattern. After waiting for the dark field to appear, exposure begins.

[0011] Step 3: Simultaneously with exposure, the camera acquires images and outputs them to an external AOI detection system. Wait for the dark field to end one frame pattern cycle.

[0012] Step 4: Determine whether the process is complete based on the number of patterns configured in the timing sequence. If yes, end the process; otherwise, return to Step 2 and simultaneously trigger multiple DLP modules to output the next pattern.

[0013] The extended DLP structured light display method of the present invention, wherein, in step one, the programming is performed using the following method:

[0014] A USB hub chip is used to connect multiple USB-to-SPI chips, and each USB-to-SPI chip is connected to one of the DLP memories. The multiple DLP memories are programmed in parallel.

[0015] The extended DLP structured light display method of the present invention further includes, in step two, a method:

[0016] When the main controller receives a projection timing switching command, the corresponding multiple DLP memories synchronously load the new timing and its corresponding pattern set.

[0017] The extended DLP structured light display method of the present invention further includes, in step three, a method:

[0018] The projection pattern is counted after the post-dark field ends.

[0019] The extended DLP structured light display method of the present invention, wherein in step one:

[0020] Each 4K-8BIT pattern is split into four 1080P-8BIT patterns or each 1080P-10BIT pattern is split into four 1080P-8BIT patterns; the timing configuration and the number of DLP memories are both 4;

[0021] In step two:

[0022] The number of DLP modules is 4.

[0023] An extended DLP structured light display system, wherein the system includes a host computer, a main controller, multiple DLP memories, multiple DLP modules, and a camera;

[0024] The host computer includes a pattern processing unit and a burning unit;

[0025] The pattern processing unit is used to divide the high-resolution or high-bit-depth original pattern into multiple segments and reuse the same timing configuration for the segmented patterns; the programming unit is used to program the multiple timing configurations into a corresponding number of DLP memories.

[0026] The main controller is used to precisely synchronize and trigger multiple DLP modules respectively.

[0027] The camera is used to capture images of the output patterns of multiple DLP modules each time they are triggered and output them to an external AOI detection system.

[0028] The extended DLP structured light display system of the present invention includes a programming unit comprising a USB hub chip and a plurality of USB-to-SPI chips electrically connected to the USB hub chip, wherein each USB-to-SPI chip is electrically connected to one DLP memory; the plurality of DLP memories are programmed in parallel.

[0029] In the extended DLP structured light display system of the present invention, the main controller is further configured to receive an external projection timing switching command, and upon receiving the projection timing switching command, control multiple DLP memories to synchronously load the new timing sequence and its corresponding pattern set.

[0030] The extended DLP structured light display system of the present invention further includes a counting unit;

[0031] The counting unit is used to count after multiple DLP modules output a pattern once.

[0032] The extended DLP structured light display system of the present invention includes a pattern processing unit for splitting each 4K-8BIT pattern into four 1080P-8BIT patterns or splitting each 1080P-10BIT pattern into four 1080P-8BIT patterns; the number of timing configurations and the number of DLP memories are both four; and the number of DLP modules is four.

[0033] The beneficial effects of this invention are as follows: By applying the method of this application, high-resolution or high-depth original patterns are segmented, and the main controller precisely controls and triggers each DLP module. The delay of the exposure time of each corresponding pattern in different DLP modules is controlled within 20-40ns, which is much less than 1us. The impact on camera acquisition or display is negligible, thus realizing high-precision extended DLP structured light display function, enabling it to meet the requirements of industrial AOI inspection and solving this industry problem. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:

[0035] Figure 1 This is a flowchart of the extended DLP structured light display method according to a preferred embodiment of the present invention;

[0036] Figure 2 This is a flowchart illustrating the programming process of the extended DLP structured light display method according to a preferred embodiment of the present invention.

[0037] Figure 3 This is a flowchart of the control projection process for the extended DLP structured light display method according to a preferred embodiment of the present invention;

[0038] Figure 4 This is a timing diagram of the extended DLP structured light display method according to a preferred embodiment of the present invention;

[0039] Figure 5 This is a block diagram illustrating the principle of an extended DLP structured light display system according to a preferred embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of the programming principle of the extended DLP structured light display system according to a preferred embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the control projection principle of an extended DLP structured light display system according to a preferred embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, a clear and complete description will be provided below in conjunction with the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0043] The extended DLP structured light display method of the preferred embodiment of the present invention, such as... Figure 1 As shown, see also Figures 2-4 This includes the following steps:

[0044] S01: Divide the high-resolution or high-bit-depth original pattern into multiple blocks and burn them into the corresponding DLP memory. Reuse the same timing configuration for the divided patterns and burn multiple patterns and timing configurations into each DLP memory.

[0045] S02: The main controller receives an external trigger command and simultaneously triggers multiple DLP modules corresponding to the DLP memory to output a pattern synchronously. After waiting for the dark field, exposure begins.

[0046] S03: Simultaneous exposure with camera acquisition, outputting the acquired image to an external AOI detection system, and waiting for the dark field to end one frame pattern cycle;

[0047] S04: Determine whether the process is complete based on the number of patterns corresponding to the timing configuration. If yes, end the process; otherwise, return and simultaneously trigger multiple DLP modules to output the next pattern synchronously.

[0048] By applying the method of this application, high-resolution or high-depth original patterns are segmented, and the main controller precisely controls and triggers each DLP module. The delay of the exposure time of each corresponding pattern in different DLP modules (DLPC+DMD) is controlled within 20-40ns, which is far less than 1us. The impact on camera acquisition or display is negligible, thus realizing high-precision extended DLP structured light display function, which can meet the requirements of industrial AOI inspection and solve this industry problem.

[0049] Using the DLP4710LC display chip and its supporting DLPC3479 control chip as the core technology, and integrating multiple DLP and DLPC technologies as an example (the same principle can be applied to DLP2010 and DLP3010 technologies to achieve enhanced display), the host computer can reasonably split pixel positions or pixel bit depths, and add precise pattern trigger control to achieve extended resolution or extended bit depth functions, as explained below:

[0050] Taking the DLP4710 as an example, a single DMD can output a physical resolution of 1920*1080, two DMDs can achieve 1920*2160, or four DMDs can achieve 4K (3840*2160). When achieving higher bit depths, a single DMD can output an 8-bit depth, two DMDs can achieve approximately 9-bit depth, and four DMDs can achieve approximately 10-bit depth.

[0051] Each pixel of a single DMD represents 8 bits of grayscale (0-255), two DMDs represent approximately 9 bits (0-510), three DMDs represent approximately 9.5 bits (0-765), and four DMDs represent approximately 10 bits (0-1020); the limited projection method cannot fully realize 10 bits (0-1023).

[0052] Taking a single DLP controller with a DLP4710+DLPC3479 as an example, the DLPC's internal mode can support 1-bit or 8-bit 1D pattern projection, and can support a maximum of one row of 1920-pixel vertical raster or one column of 1080-pixel horizontal raster pattern. In trigger mode, the DLPC can project a single 1080P-8-bit pattern in one trigger. By having the main controller trigger the DLPC multiple times in an orderly manner, multiple patterns can be projected in one round.

[0053] The entire invention includes the image slicing process, the burning process, and the triggering process.

[0054] There are two physical ways to make the grayscale brightness of a pixel's projection vary: one is to control the current of that pixel individually; the other is to control the cumulative time of light output at that pixel. Here, multiple DMDs are used to concurrently control the grayscale projected onto the pixel. When the grayscale of pixels at the same location on different DMDs is projected onto the same physical point on the plane, the brightness intensity or grayscale level can be increased. When the grayscale of pixels at the same location on different DMDs is projected onto different points on the physical plane, the projection area can be increased or the projection accuracy can be improved.

[0055] Image slicing process:

[0056] For products requiring increased projection area or precision, the original 4K-8BIT pattern can be split into four 1080P-8BIT patterns. As shown in the table below, each DLP module retains its basic functionality, only the pattern content is displayed in different positions during projection.

[0057] When used for extended resolution, the pixel position corresponding to each DMD is:

[0058] Pixel 0-1919 1920-3839 0-1079 DMD1 DMD3 1080-2159 DMD2 DMD4

[0059] For products requiring increased projection light intensity or bit depth, the original 1080P-10BIT pattern can be split into four 1080P-8BIT patterns. As shown in the table below, each DLP module retains its basic functionality; only the content of different bits is used when projecting the same pattern at the same location. Due to representational limitations, it can represent 0–1020 gray levels, slightly less than 10 bits (0–1023). Therefore, the last few gray levels can be omitted from the original raster pattern design.

[0060] When used to enhance light intensity or bit depth, the grayscale bit depth corresponding to each DMD is as follows:

[0061] BIT 8 9 9.5 10 DMD DMD1 DMD2 DMD3 DMD4 pixel value 0-255 +255 +255 +255

[0062] Circuit programming and process

[0063] For the programming process of a single DLP system, refer to... Figure 6 A high-speed USB hub chip CH335 is used to connect four CypressUSB to SPI chips, and the four CypressUSB chips are connected to the FLASH memory of each master controller. The reason for using a hub to connect four CypressUSB chips is to parallelize the firmware burning process of the four DLP chips, making the burning speed close to that of a single DLP chip.

[0064] Preprocessing

[0065] After 2 to 4 DLP modules start up, they enter the internal pattern mode, each loading the previously segmented 1D pattern and waiting for the trigger command. If a projection timing switch command is received in the middle, each module should also load the new timing and its corresponding pattern set synchronously.

[0066] Triggering circuit and process

[0067] The triggering process of a single DLP structured light only requires an external trigger signal. The main controller drives the DLP to project each pattern in sequence. However, if multiple DLP modules are used to extend synchronous projection, and each module projects each pattern independently through an external signal, the first pattern is basically synchronized. But due to the possible cumulative errors between different modules, the projection errors of subsequent patterns may gradually increase, making synchronization impossible. This results in inconsistent display of the final enhanced patterns, which may compromise the camera's acquisition effect.

[0068] Therefore, refer to Figure 7 The main controller is designed to provide two external IO connections: trigger input and trigger output. Internally, one trigger IO is connected to the trigger input ports of four DLP modules to control the synchronous output of each pattern.

[0069] Since each pattern set may be different in size, and the exposure timing of different pattern sets may also be different, a fixed PWM pulse signal cannot be used to control each DLP module. It is necessary to dynamically calculate the exposure timing and loading time of each pattern and make precise control triggers to ensure accurate pattern projection and maintain the synchronization of multiple DLP modules.

[0070] For example Figure 4As shown, it contains 11 patterns in 3 groups (5+1+5). After each pattern is triggered, the synchronization error of the two DLP projection output signals is controlled within 50ns. Since the number of images or the exposure sequence of the pattern set may be set differently, the trigger interval also needs to be changed. This is to ensure no frame drops and to ensure the frame rate is as fast as possible.

[0071] In summary, by segmenting the high-resolution or high-bit-depth original pattern and precisely controlling the triggering of each DLP module by the main controller, instead of using uniform batch triggering, the exposure time delay of each corresponding pattern in different DLP modules is controlled within 20-40ns, far less than 1us. The impact on camera acquisition or display is negligible. This achieves high-precision extended DLP structured light display functionality. The maximum frame rate of 8-bit patterns can also maintain the same consistency as the frame rate of a single DLP (close to a constant 360 frames per second, or a maximum of 427 frames per second).

[0072] An extended DLP structured light display system, such as Figure 5 As shown, see also Figure 6 and Figure 7 The system includes a host computer 100, a main controller 101, multiple DLP memory units 102, multiple DLP modules 103, and a camera 104.

[0073] The host computer 100 includes a pattern processing unit 1000 and a programming unit 1001;

[0074] The pattern processing unit 1000 is used to divide the high-resolution or high-bit-depth original pattern into multiple parts and reuse the same timing configuration for the divided patterns; the programming unit 1001 is used to program multiple timing configurations into a corresponding number of DLP memories.

[0075] The main controller 101 is used to precisely synchronize and trigger multiple DLP modules.

[0076] Camera 104 is used to capture images of the output patterns of multiple DLP modules each time they are triggered and output them to an external AOI detection system;

[0077] The system applying this application segments high-resolution or high-depth original patterns, and the main controller precisely controls and triggers each DLP module. The delay of the exposure time of each corresponding pattern in different DLP modules is controlled within 20-40ns, which is far less than 1us. The impact on camera acquisition or display is negligible, realizing high-precision extended DLP structured light display function, enabling it to meet the requirements of industrial AOI inspection and solving this industry problem.

[0078] The main controller can precisely control each DLP module by triggering multiple DLP modules corresponding one-to-one with the DLP memory to synchronously output a pattern, waiting for the front dark field, exposing the camera, outputting the acquired image to the external AOI detection system, and waiting for the back dark field. Of course, other existing precise control methods can also be used, and there is no limitation on this.

[0079] Preferably, the programming unit includes a USB hub chip and multiple USB-to-SPI chips electrically connected to the USB hub chip, each USB-to-SPI chip being electrically connected to a DLP memory; multiple DLP memories are programmed in parallel; this method can effectively improve the programming speed.

[0080] Preferably, the main controller is also used to receive external projection timing switching commands, and upon receiving the projection timing switching command, to control multiple DLP memories to synchronously load the initial pattern set of the new timing, so as to facilitate temporary timing control of multiple DLP modules.

[0081] Preferably, the system also includes a counting unit; the counting unit is used to count after multiple DLP modules output a pattern once; the counting unit can be a separate chip or a counter function built into the main controller; the counting function is used to determine the number of currently output patterns;

[0082] Preferably, the pattern processing unit is used to split a 4K-8BIT pattern into four 1080P-8BIT patterns or to split a 1080P-10BIT pattern into four 1080P-8BIT patterns; the number of timing configurations and DLP memories are both 4; the number of DLP modules is 4; this embodiment is a preferred embodiment, but of course, the embodiment described here is only for illustrative purposes and is not intended to limit the quantity. The actual quantity can be increased or decreased according to actual needs.

[0083] Examples of chip models involved in the system of this application are as follows:

[0084] type Example Model Other optional models USB HUB CH335 CH334 USB controller CY7C65215 CH347H DLP controller DLPC3479 DLPC3470, DLPC3478 DLP display chip DLP4710 DLP2010, DLP3010 DLP power driver DLPA3005 DLPA3000 Pattern processing unit MSP430 C2000, GD32... DLP memory GD25Q64EWIGR W25Q64FVZPIG

[0085] The above model numbers are for illustrative purposes only and are not intended to limit the number of models.

[0086] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. An extended DLP structured light display method, characterized in that, The method comprises the following steps: Step 1: high-resolution or high-bit-depth original patterns are divided into multiple blocks and burned into corresponding DLP memories, the same timing configuration is reused for the divided patterns, and the multiple patterns and the timing configuration are burned into the DLP memories; Step 2: the main controller receives an external trigger instruction, and after triggering the multiple DLP modules corresponding to the DLP memories to synchronously output a pattern, the main controller waits for the start of the exposure after the dark field; Step 3: the camera synchronously collects the exposure, outputs the collected image to an external AOI detection system, and waits for the end of a period of a pattern after the dark field; Step 4: whether the pattern is completed is determined according to the number of patterns corresponding to the timing configuration, and if yes, the process is ended, otherwise, the process returns to Step 2. In Step 1, the burning is performed in the following manner: A USB hub chip is connected to multiple USB-to-SPI chips, each USB-to-SPI chip is connected to one DLP memory, and the host computer burns in parallel by opening the SPI channels connected to the multiple DLP memories.

2. The extended DLP structured light display method of claim 1, wherein, In Step 2, the method further comprises the following steps: When the main controller receives a projection timing switching command, the corresponding multiple DLP memories synchronously clear the old timing and load the new timing and the corresponding pattern set.

3. The extended DLP structured light display method of claim 1, wherein, In Step 3, the method further comprises the following steps: After the end of the dark field, the camera counts the actual output pattern.

4. The extended DLP structured light display method of any of claims 1-3, wherein, In Step 1: Each 4K-8BIT pattern is divided into four 1080P-8BIT patterns, or each 1080P-10BIT pattern is divided into four 1080P-8BIT patterns; the number of timing configurations and DLP memories is four; In Step 2: The number of DLP modules is four.

5. An extended DLP structured light display system for implementing the extended DLP structured light display method of any one of claims 1-4, wherein, The system comprises a host computer, a main controller, multiple DLP memories, multiple DLP modules and a camera. The host computer comprises a pattern processing unit and a burning unit. The pattern processing unit is configured to divide high-resolution or high-bit-depth original patterns into multiple patterns and reuse the same timing configuration for the divided patterns; and the burning unit is configured to burn multiple timing configurations into corresponding DLP memories. The main controller is configured to accurately control and trigger the multiple DLP modules respectively. The camera is configured to take a photo of the output pattern of the multiple DLP modules triggered each time and output the photo to an external AOI detection system. The burning unit comprises a USB hub chip and multiple USB-to-SPI chips electrically connected to the USB hub chip, each USB-to-SPI chip is electrically connected to one DLP memory, and the multiple DLP memories are burned in parallel.

6. The extended DLP structured light display system of claim 5, wherein, The main controller is further configured to receive an external projection timing switching command, and control the multiple DLP memories to synchronously load a new timing and a corresponding pattern set when the projection timing switching command is received.

7. The extended DLP structured light display system of claim 5, wherein, The system further comprises a counting unit. The counting unit is configured to count after the multiple DLP modules output a pattern.

8. The extended DLP structured light display system of any of claims 5-7, wherein, The pattern processing unit is configured to split a 4K-8BIT pattern into four 1080P-8BIT patterns or split a 1080P-10BIT pattern into four 1080P-8BIT patterns; the number of the timing configurations and the number of the DLP memories are both 4; and the number of the DLP modules is 4.

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