A method, system, electronic device and storage medium for generating a quantum linear reversible circuit based on BDD

Abstract

The present invention discloses a method, system, electronic device and storage medium for generating a quantum linear reversible circuit based on BDD. The method comprises the following steps: obtaining a quantum linear reversible circuit to be processed and converting it into a reversible matrix; establishing an identity matrix V0 with the same dimension as the reversible matrix V1; performing a state conversion operation on the reversible matrix V1 and the identity matrix V0 to obtain a target state BDD set and an initial state BDD set respectively; and determining whether the target state BDD set and the initial state BDD set have an intersection v. t :If there is an intersection v t Then, the sequence of row transformation relations CNOT obtained by arranging the two paths in order is represented by a linear reversible circuit. The present invention uses reachability analysis to study the generation of linear reversible circuits and uses a bidirectional BDD search method to reduce the time and space complexity of BDD calculation for large functions.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum circuit design, and in particular to a method, system, electronic device and storage medium for generating a quantum linear reversible circuit based on BDD. Background Art

[0002] Quantum circuits are composed of a cascade of quantum logic gates. They implement circuit functions by performing a series of unitary transformations on quantum information. As the quantum information passes through each quantum logic gate, it undergoes transformations based on the gate's function. The operation of a quantum logic gate on quantum information is essentially a unitary transformation. A key characteristic of unitary transformations is that they are reversible, meaning that each quantum logic gate is also reversible. Therefore, reversibility is an important consideration when designing electronic circuits and algorithms.

[0003] In quantum computing, a key issue is how to generate linear reversible circuits using the fewest quantum resources possible. Reversible matrices can be used to represent linear reversible circuits. Therefore, efficiently generating linear reversible circuits while minimizing the number of CNOT gates used has become a pressing challenge in quantum circuit design. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a method, system, electronic device and storage medium for generating a quantum linear reversible circuit based on BDD.

[0005] The object of the present invention is achieved through the following technical solutions:

[0006] A first aspect of the present invention provides a method for generating a quantum linear reversible circuit based on BDD, comprising the following steps:

[0007] Obtain the quantum linear reversible circuit to be processed and convert it into an n×n reversible matrix V1;

[0008] Establish the identity matrix V0 with the same dimension as the reversible matrix V1 and define all row transformation relations CNOT i，j As a state transition operation and expressed as an operation set Op = {CNOT i，j |1≤i, j≤n, i≠j}, where the operation set is represented as Op={op i |1≤i≤n(n-1)};

[0009] Perform state conversion operations on the reversible matrix V1 and the identity matrix V0 to obtain the target state BDD set and the initial state BDD set respectively;

[0010] Determine whether there is an intersection v between the target state BDD set and the initial state BDD set t :

[0011] If there is an intersection v t Then get the matrix from the identity matrix V0 to the intersection v t The transfer path from the reversible matrix V1 to the intersection v t The reverse path of the transfer path, the sequence of row transformation relations CNOT obtained by arranging the two paths in sequence is represented by a linear reversible circuit;

[0012] If there is no intersection v t , then continue to perform state conversion operations and intersection judgment operations on the reversible matrix V1 and the identity matrix V0 respectively, until the target state BDD set and the initial state BDD set no longer grow, and there is no intersection v between the target state BDD set and the initial state BDD set t , it is determined that there is no reachable path.

[0013] Furthermore, the reversible matrix V1 and the identity matrix V0 are respectively converted into column vectors or row vectors, and then a state conversion operation is performed.

[0014] Furthermore, the state conversion operation and intersection judgment operation are sequentially performed on the reversible matrix V1 and the identity matrix V0, specifically:

[0015] First, perform state conversion and intersection judgment operations on the identity matrix V0, and then perform state conversion and intersection judgment operations on the reversible matrix V1; or:

[0016] First, the state conversion operation and intersection judgment operation are performed on the reversible matrix V1, and then the state conversion operation and intersection judgment operation are performed on the unit matrix V0.

[0017] Furthermore, the target state BDD set and the initial state BDD set no longer grow, specifically:

[0018] Determine whether the number of states of the two target state BDD sets before and after the state conversion operation on the reversible matrix V1 increases, and if not, the target state BDD set no longer increases;

[0019] It is determined whether the state quantity of the two initial state BDD sets before and after the state conversion operation is performed on the identity matrix V0 increases. If not, the initial state BDD set no longer increases.

[0020] A second aspect of the present invention provides a system for generating a quantum linear reversible circuit based on BDD, comprising:

[0021] Circuit acquisition and conversion module: used to obtain the quantum linear reversible circuit to be processed and convert it into an n×n reversible matrix V1;

[0022] Initial state establishment module: used to establish the identity matrix V0 with the same dimension as the reversible matrix V1 and define all row transformation relations CNOT i，j As a state transition operation and expressed as an operation set Op = {CNOT i，j |1≤i, j≤n, i≠j}, where the operation set is represented as Op={op i |1≤i≤n(n-1)};

[0023] Linear reversible circuit generation module, including:

[0024] BDD set building unit: used to perform state conversion operations on the reversible matrix V1 and the identity matrix V0 to obtain the target state BDD set and the initial state BDD set respectively;

[0025] Intersection judgment unit: used to judge whether there is an intersection between the target state BDD collection and the initial state BDD collection t :

[0026] If there is an intersection v t Then get the matrix from the identity matrix V0 to the intersection v t The transfer path from the reversible matrix V1 to the intersection v t The reverse path of the transfer path, the sequence of row transformation relations CNOT obtained by arranging the two paths in sequence is represented by a linear reversible circuit;

[0027] If there is no intersection v t , then continue to perform state conversion operations and intersection judgment operations on the reversible matrix V1 and the identity matrix V0 respectively, until the target state BDD set and the initial state BDD set no longer grow, and there is no intersection v between the target state BDD set and the initial state BDD set t , it is determined that there is no reachable path.

[0028] Furthermore, the reversible matrix V1 and the identity matrix V0 are respectively converted into column vectors or row vectors, and then a state conversion operation is performed.

[0029] Furthermore, the state conversion operation and intersection judgment operation are sequentially performed on the reversible matrix V1 and the identity matrix V0, specifically:

[0030] First, perform state conversion and intersection judgment operations on the identity matrix V0, and then perform state conversion and intersection judgment operations on the reversible matrix V1; or:

[0031] First, the state conversion operation and intersection judgment operation are performed on the reversible matrix V1, and then the state conversion operation and intersection judgment operation are performed on the unit matrix V0.

[0032] Furthermore, the target state BDD set and the initial state BDD set no longer grow, specifically:

[0033] Determine whether the number of states of the two target state BDD sets before and after the state conversion operation on the reversible matrix V1 increases, and if not, the target state BDD set no longer increases;

[0034] It is determined whether the state quantity of the two initial state BDD sets before and after the state conversion operation is performed on the identity matrix V0 increases. If not, the initial state BDD set no longer increases.

[0035] According to a third aspect of the present invention, an electronic device is provided, comprising a storage unit and a processing unit, wherein the storage unit stores computer instructions that can be run on the processing unit, and when the processing unit runs the computer instructions, the processing unit executes the steps of the method for generating a quantum linear reversible circuit based on BDD.

[0036] According to a fourth aspect of the present invention, a storage medium is provided, on which computer instructions are stored. When the computer instructions are executed, the steps of the method for generating a quantum linear reversible circuit based on BDD are executed.

[0037] The beneficial effects of the present invention are:

[0038] This exemplary embodiment converts the problem into generating linear reversible circuits using CNOT gates based on a bidirectional search of BDD by representing the linear reversible circuit in the form of a reversible matrix. By converting the matrix representation into a state representation and the CNOT gates corresponding to the state transition relationship, reachability analysis is used to study the generation of linear reversible circuits. A binary decision diagram (BDD) is used for bidirectional search reachability analysis. In the reachability analysis, the shortest path that intersects the system from the initial state and the target state can be determined by performing state transitions on each state in the state space. Compared to the unidirectional BDD search method that only involves traversal in one direction, this exemplary embodiment uses a bidirectional BDD search method, which can reduce the time and space complexity of large-scale function calculation BDDs. The method is more efficient and can provide a CNOT gate sequence with the minimum number of state transitions. The generated CNOT gate sequence is finally represented using a linear reversible circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of a method for generating a linear reversible circuit based on BDD provided in an exemplary embodiment of the present invention.

[0040] Figure 2 is a state set provided in an exemplary embodiment of the present invention BDD representation schematic.

[0041] Figure 3 is a state set provided in an exemplary embodiment of the present invention BDD representation schematic.

[0042] Figure 4 is a state set provided in an exemplary embodiment of the present invention BDD representation schematic.

[0043] Figure 5 A linear reversible circuit diagram generated by the method provided in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0044] The technical solution of the present invention is described clearly and completely below with reference to the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention.

[0045] In the description of the present invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "up," "down," "left," "right," "vertical," "horizontal," "inside," and "outside" are based on the directions or positional relationships described in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention.

[0047] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] See also Figure 1 , Figure 1 A flowchart of a method for generating a quantum linear reversible circuit based on BDD provided in an exemplary embodiment of the present invention is shown, comprising the following steps:

[0049] Obtain the quantum linear reversible circuit to be processed and convert it into an n×n reversible matrix V1;

[0050] Establish the identity matrix V0 with the same dimension as the reversible matrix V1 and define all row transformation relations CNOT i，j As a state transition operation and expressed as an operation set Op = {CNOT i，j |1≤i, j≤n, i≠j}, where the operation set is represented as Op={op i |1≤i≤n(n-1)};

[0051] Perform state conversion operations on the reversible matrix V1 and the identity matrix V0 to obtain the target state BDD set and the initial state BDD set, which are expressed as At the same time, the operations of each state in the BDD are recorded. The operations in the two different BDD sets are represented as follows:

[0052] Determine whether there is an intersection v between the target state BDD set and the initial state BDD set t :

[0053] If there is an intersection v t Then get the matrix from the identity matrix V0 to the intersection v t The transfer path from the reversible matrix V1 to the intersection v t The reverse path of the transfer path, that is, record the transition from the initial state v0 to v t The transfer path is From the target state v1 to v t The transfer path is Arrange the inversion paths of P0 and P1 to obtain the minimum CNOT gate sequence from the identity matrix V0 to the target reversible matrix V1: Finally, the sequence of row transformation relations CNOT obtained by arranging the two paths in order is represented by a linear reversible circuit;

[0054] If there is no intersection v t , then continue to perform state conversion operations and intersection judgment operations on the reversible matrix V1 and the identity matrix V0 respectively, until the target state BDD set and the initial state BDD set no longer grow, and there is no intersection v between the target state BDD set and the initial state BDD set t , it is determined that there is no reachable path.

[0055] A quantum linear reversible circuit consists of several input and output lines and CNOT gates. The states of the input and output lines can be represented as vectors, and the operation of the CNOT gates as matrices. This allows the entire linear circuit to be represented as a matrix multiplication. Therefore, a sequence of CNOT gates is required to generate a linear reversible circuit.

[0056] Given an n×n reversible matrix V1, use as few CNOT gates as possible to convert the n×n identity matrix V0 into a reversible matrix V1. Specifically, the n×n matrix V1 can be converted into an n×n matrix V1 in row-first order. 2 The column vector of dimension v1 (preferred solution) is represented as follows:

[0057]

[0058] This converts the matrix into a vector, where each element is either 0 or 1, creating a 0 / 1 matrix or a binary matrix. The converted vector v1 can be considered a state vector, with each element representing a state variable in the system. Therefore, the state vector v1 can be represented as a point in a state space, representing the combination of values of the system's state variables at a given moment.

[0059] The CNOT gate is a commonly used quantum gate, short for controlled flip gate. The CNOT gate acts on two qubits, one of which is called the control bit and the other is called the target bit. Its function is to flip the state of the target bit according to the state of the control bit. That is, if the control bit is 1, the state of the target bit is negated. Using elementary matrix row transformations, the n×n identity matrix can be converted into a reversible matrix, expressed as the matrix product V1=P1P2...P n-1 P n V0, using Gaussian elimination, we can find the matrix product that transforms the n×n identity matrix into a reversible matrix V1. However, this method is generally not optimal. Finding the minimum number of elementary matrices is the advantage of our method. We consider the elementary transformation of the rows of the matrix, and the CNOT gate can be used to represent this row transformation relationship. i，j Expressed as Among them, ~ represents the control bit, x i Represents the target bit. Given the state vector u1, the transition relation CNOT i，j It can be defined as:

[0060]

[0061] The set of all CNOT gates is represented as:

[0062] {CNOT i，j|1≤i,j≤n,i≠j}

[0063] Therefore, there are n×(n-1) operations for controlling the conversion of state variables using CNOT gates, namely: We use CNOT gate to realize the state transition relationship. In this state transition relationship, if the control variable x j When it is 1, the target variable x i In reachability analysis, we can determine which states the system can reach from the initial state and the properties it may have when it reaches a certain state by performing state transitions on each state in the state space.

[0064] A method for determining the minimum number of CNOT gate sequences is used to intersect state sets using a bidirectional BDD search. By converting matrices into state representations and mapping CNOT gates to state transitions, reachability analysis is used to study the generation of linear reversible circuits. The method uses a binary decision diagram (BDD) for reachability analysis, representing all possible state transitions. The BDD is then iteratively expanded and updated to search for the shortest path from the initial state to the target state. Each BDD node records all state transitions along the path from the initial state to that node, and the resulting path represents the minimum number of CNOT gate sequences required. The bidirectional BDD search method involves searching in two directions: from root to leaf and from leaf to root, i.e., from the initial state to the target state and from the target state to the initial state. It can reduce the time and space complexity of computing the BDD for large functions and is more efficient than unidirectional BDD methods. It can also provide the minimum number of CNOT gate sequences required for state transitions.

[0065] Therefore, in this exemplary embodiment, by representing the linear reversible circuit in the form of a reversible matrix, the problem is converted into the generation of linear reversible circuits using CNOT gates based on a BDD bidirectional search. By converting the matrix representation into a state representation and the CNOT gates corresponding to the state transition relationship, the generation of linear reversible circuits is studied using reachability analysis. A binary decision diagram BDD is used for bidirectional search reachability analysis. In the reachability analysis, the shortest path that produces an intersection between the system starting from the initial state and the target state can be determined by performing state transitions on each state in the state space. Compared to the unidirectional BDD search method that only involves traversal in one direction, this exemplary embodiment uses a bidirectional BDD search method, which can reduce the time and space complexity of large function calculation BDDs. The method is more efficient and can provide a CNOT gate sequence with the minimum number of state transitions. The generated CNOT gate sequence is finally represented using a linear reversible circuit.

[0066] More preferably, in an exemplary embodiment, the reversible matrix V1 and the identity matrix V0 are respectively converted into column vectors or row vectors before performing a state conversion operation.

[0067] Specifically, in this exemplary embodiment, this method is used for processing to facilitate subsequent processing by a computer.

[0068] More preferably, in an exemplary embodiment, the state conversion operation and the intersection determination operation are sequentially performed on the reversible matrix V1 and the identity matrix V0, specifically:

[0069] First perform state conversion operation on the identity matrix V0 And intersection judgment operation, then perform state conversion operation on the reversible matrix V1 and intersection operation; or:

[0070] First perform state conversion operation on the reversible matrix V1 And the intersection judgment operation, and then the state conversion operation of the unit matrix V0 and intersection operations.

[0071] Specifically, in this exemplary embodiment, except for the initial establishment of the target state BDD collection and the initial state BDD collection, the newly generated target state BDD collection and the initial state BDD collection in subsequent steps are all established in sequence.

[0072] More preferably, in an exemplary embodiment, the target state BDD collection and the initial state BDD collection no longer grow, specifically:

[0073] Determine whether the number of states of the two target state BDD sets before and after the state conversion operation on the reversible matrix V1 increases, and if not, the target state BDD set no longer increases;

[0074] It is determined whether the state quantity of the two initial state BDD sets before and after the state conversion operation is performed on the identity matrix V0 increases. If not, the initial state BDD set no longer increases.

[0075] The following content uses the 3×3 reversible matrix V1 as an example for explanation:

[0076] Convert the 3×3 identity matrix V0 to a column vector v0 (preferred solution for easy subsequent processing) as the initial state. Given a 3×3 reversible matrix V1, convert it to a column vector v1 as the target state. Operation set Op = {CNOT i，j |1≤i, j≤3, i≠j}={CNOT 1，2 , CNOT 1，3 , CNOT2，1 , CNOT 2，3 , CNOT 3，1 , CNOT 3，2 ,}, for convenience, the operation set is recorded as Op = {op1, ..., op6}, the number of operation sets is 3 × (3-1) = 6, and the size of the system state space is 2 3×3 =2 9 For example, given state x = (x1, x2, x3, x4, x5, x6, x7, x8, x9) T , transfer relation CNOT 1，2 Can be defined as

[0077]

[0078]

[0079] Define the variable t0=1 for the number of initial state transitions and the variable t1=1 for the number of target state transitions. Use the state transition operation to operate on the initial state and the target state respectively, and obtain the state represented by the BDD set of the first step operation, which is expressed as They are:

[0080]

[0081] At the same time, the operations of each state in the BDD are recorded. The operations in the two different BDD sets are represented as follows: For example, given the initial state v0, in CNOT 1，3 Under the effect of the transfer relationship, the state is (1, 0, 1, 0, 1, 0, 0, 1) T The generation process is: (1, 0, 1, 0, 1, 0, 0, 1) T =CNOT 1，3 (v0). Figure 2 、 Figure 3 They are Schematic diagram of BDD representation, the number of representatives in its state set are 7 and 7 respectively.

[0082] Judgment and Discovery and There is no intersection, and the state set sizes of both are increasing, so we proceed to the next step. We use the state transition relationship to continue operating on the BDD set of the initial state direction calculated in the previous step. The state set represented by Figure 4 yes The BDD representation diagram of , the number of representatives in its state set is 31 (the same state will be merged after the increase).

[0083]

[0084] Record the operation of each state in the BDD. The state operation in the BDD set is represented as Judgment and Discovery and There is an intersection v t , Take out a representative element v from the intersection t =(1,0,1,0,1,0,0,1,1) T , record from initial state v0 to v t The transfer path is From the target state v1 to v t The transfer path is Arrange the path of P0 and the inverse path of P1 to obtain the minimum number of CNOT gate sequences from the identity matrix V0 to the target reversible matrix V1: Then we have:

[0085]

[0086] Figure 5 The generated CNOT gate sequence is represented by a linear reversible circuit, in which the number of CNOT gates is the least.

[0087] Having the same inventive concept as the above exemplary embodiment, another exemplary embodiment of the present invention provides a system for generating a quantum linear reversible circuit based on BDD, comprising:

[0088] Circuit acquisition and conversion module: used to obtain the quantum linear reversible circuit to be processed and convert it into an n×n reversible matrix V1;

[0089] Initial state establishment module: used to establish the identity matrix V0 with the same dimension as the reversible matrix V1 and define all row transformation relations CNOT i，j As a state transition operation and expressed as an operation set Op = {CNOT i，j |1≤i, j≤n, i≠j}, where the operation set is represented as Op={op i |1≤i≤n(n-1)};

[0090] Linear reversible circuit generation module, including:

[0091] BDD set building unit: used to perform state conversion operations on the reversible matrix V1 and the identity matrix V0 to obtain the target state BDD set and the initial state BDD set respectively;

[0092] Intersection judgment unit: used to judge whether there is an intersection between the target state BDD collection and the initial state BDD collection t :

[0093] If there is an intersection v t Then get the matrix from the identity matrix V0 to the intersection v t The transfer path from the reversible matrix V1 to the intersection v t The reverse path of the transfer path, the sequence of row transformation relations CNOT obtained by arranging the two paths in sequence is represented by a linear reversible circuit;

[0094] If there is no intersection v t , then continue to perform state conversion operations and intersection judgment operations on the reversible matrix V1 and the identity matrix V0 respectively, until the target state BDD set and the initial state BDD set no longer grow, and there is no intersection v between the target state BDD set and the initial state BDD set t , it is determined that there is no reachable path.

[0095] Correspondingly, the reversible matrix V1 and the identity matrix V0 are respectively converted into column vectors or row vectors, and then a state conversion operation is performed.

[0096] Correspondingly, the state conversion operation and intersection judgment operation are sequentially performed on the reversible matrix V1 and the identity matrix V0, specifically:

[0097] First, perform state conversion and intersection judgment operations on the identity matrix V0, and then perform state conversion and intersection judgment operations on the reversible matrix V1; or:

[0098] First, the state conversion operation and intersection judgment operation are performed on the reversible matrix V1, and then the state conversion operation and intersection judgment operation are performed on the unit matrix V0.

[0099] Correspondingly, the target state BDD collection and the initial state BDD collection no longer grow, specifically:

[0100] Determine whether the number of states of the two target state BDD sets before and after the state conversion operation on the reversible matrix V1 increases, and if not, the target state BDD set no longer increases;

[0101] It is determined whether the state quantity of the two initial state BDD sets before and after the state conversion operation is performed on the identity matrix V0 increases. If not, the initial state BDD set no longer increases.

[0102] Having the same inventive concept as the above exemplary embodiment, another exemplary embodiment of the present invention provides an electronic device, including a storage unit and a processing unit, wherein the storage unit stores computer instructions that can be run on the processing unit, and when the processing unit runs the computer instructions, it executes the steps of the method for generating a quantum linear reversible circuit based on BDD.

[0103] The electronic device is implemented as a general-purpose computing device. Components of the electronic device may include, but are not limited to, the at least one processing unit, the at least one storage unit, and a bus connecting different system components (including the storage unit and the processing unit).

[0104] The storage unit stores program codes that can be executed by the processing unit, so that the processing unit performs the steps according to various exemplary embodiments of the present invention described in the "Exemplary Method" section above. For example, the processing unit can perform the following steps: Figure 1 The method shown in .

[0105] The storage unit may include a readable medium in the form of a volatile memory unit, such as a random access memory unit (RAM) 3201 and / or a cache memory unit, and may further include a read-only memory unit (ROM).

[0106] The storage unit may also include a program / utility having a set (at least one) of program modules, such program modules including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0107] The bus can represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0108] The electronic device may also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device, and / or any device that enables the electronic device to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface. Furthermore, the electronic device may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter. The network adapter communicates with other modules of the electronic device via a bus. It should be understood that other hardware and / or software modules may be used in conjunction with the electronic device, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0109] Through the above description, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented through software or through a combination of software and necessary hardware. Therefore, the technical solution according to this exemplary embodiment can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, a USB flash drive, a mobile hard drive, etc.) or on a network, and includes several instructions to enable a computing device (such as a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to this exemplary embodiment.

[0110] Another exemplary embodiment of the present invention shares the same inventive concept as the aforementioned exemplary embodiment. A storage medium is provided, on which computer instructions are stored. When executed, the computer instructions execute the steps of the method for generating a quantum linear reversible circuit based on a BDD.

[0111] Based on this understanding, the technical solution of this embodiment, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product (program product). The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention.

[0112] The program product may be implemented in any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0113] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0114] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0115] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, and the like, as well as conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0116] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications can be made based on the above descriptions. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications derived therefrom remain within the scope of protection of the present invention.

Claims

1. A method for generating a quantum linear reversible circuit based on BDD, characterized by: The following steps are involved: Obtain the quantum linear reversible circuit to be processed and convert it into an n×n reversible matrix V1; the quantum linear reversible circuit includes several input lines, output lines, and CNOT gates. The states of the input and output lines are represented as a vector, and the operation of the CNOT gate is represented as a matrix. In this way, the entire quantum linear reversible circuit is represented as a matrix multiplication. Therefore, a CNOT gate sequence is required to generate the linear reversible circuit; Establish the identity matrix V0 with the same dimension as the reversible matrix V1 and define all row transformation relations CNOT i，j As a state transition operation and expressed as an operation set Op = {CNOT i，j |1≤i, j≤n, i≠j}, where the operation set is represented as Op={op i |1≤i≤n(n-1)}; Perform state conversion operations on the reversible matrix V1 and the identity matrix V0 to obtain the target state BDD set and the initial state BDD set respectively; Determine whether there is an intersection v between the target state BDD set and the initial state BDD set t : If there is an intersection v t Then get the matrix from the identity matrix V0 to the intersection v t The transfer path from the reversible matrix V1 to the intersection v t The reverse path of the transfer path, the sequence of row transformation relations CNOT obtained by arranging the two paths in sequence is represented by a linear reversible circuit; If there is no intersection v t , then continue to perform state conversion operations and intersection judgment operations on the reversible matrix V1 and the identity matrix V0 respectively, until the target state BDD set and the initial state BDD set no longer grow, and there is no intersection v between the target state BDD set and the initial state BDD set t , it is determined that there is no reachable path.

2. The method for generating a quantum linear reversible circuit based on BDD according to claim 1, characterized in that: After the reversible matrix V1 and the identity matrix V0 are converted into column vectors or row vectors respectively, a state conversion operation is performed.

3. The method for generating a quantum linear reversible circuit based on BDD according to claim 1, characterized in that: The state conversion operation and intersection judgment operation are performed on the reversible matrix V1 and the identity matrix V0 in sequence, specifically: First, perform state conversion and intersection judgment operations on the identity matrix V0, and then perform state conversion and intersection judgment operations on the reversible matrix V1; or: First, the state conversion operation and intersection judgment operation are performed on the reversible matrix V1, and then the state conversion operation and intersection judgment operation are performed on the unit matrix V0.

4. The method for generating a quantum linear reversible circuit based on BDD according to claim 1, characterized in that: The target state BDD collection and the initial state BDD collection no longer grow, specifically: Determine whether the number of states of the two target state BDD sets before and after the state conversion operation on the reversible matrix V1 increases, and if not, the target state BDD set no longer increases; It is determined whether the state quantity of the two initial state BDD sets before and after the state conversion operation is performed on the identity matrix V0 increases. If not, the initial state BDD set no longer increases.

5. A BDD-based quantum linear reversible circuit generation system, characterized by: include: Circuit acquisition and conversion module: used to obtain the quantum linear reversible circuit to be processed and convert it into an n×n reversible matrix V1. The quantum linear reversible circuit includes several input lines, output lines, and CNOT gates. The states of the input and output lines are represented as a vector, and the operation of the CNOT gate is represented as a matrix. In this way, the entire quantum linear reversible circuit is represented as a matrix multiplication. Therefore, a CNOT gate sequence is required to generate the linear reversible circuit. Initial state establishment module: used to establish the identity matrix V0 with the same dimension as the reversible matrix V1 and define all row transformation relationships CNOT i，j As a state transition operation and expressed as an operation set Op = {CNOT i，j |1≤i, j≤n, i≠j}, where the operation set is represented as Op={op i |1≤i≤n(n-1)}; Linear reversible circuit generation module, including: BDD set building unit: used to perform state conversion operations on the reversible matrix V1 and the identity matrix V0 to obtain the target state BDD set and the initial state BDD set respectively; Intersection judgment unit: used to judge whether there is an intersection between the target state BDD collection and the initial state BDD collection t : If there is an intersection v t Then get the matrix from the identity matrix V0 to the intersection v t The transfer path from the reversible matrix V1 to the intersection v t The reverse path of the transfer path, the sequence of row transformation relations CNOT obtained by arranging the two paths in sequence is represented by a linear reversible circuit; If there is no intersection v t , then continue to perform state conversion operations and intersection judgment operations on the reversible matrix V1 and the identity matrix V0 respectively, until the target state BDD set and the initial state BDD set no longer grow, and there is no intersection v between the target state BDD set and the initial state BDD set t , it is determined that there is no reachable path.

6. The BDD-based quantum linear reversible circuit generation system according to claim 5, characterized in that: After the reversible matrix V1 and the identity matrix V0 are converted into column vectors or row vectors respectively, a state conversion operation is performed.

7. The BDD-based quantum linear reversible circuit generation system according to claim 5, characterized in that: The state conversion operation and intersection judgment operation are performed on the reversible matrix V1 and the identity matrix V0 in sequence, specifically: First, perform state conversion and intersection judgment operations on the identity matrix V0, and then perform state conversion and intersection judgment operations on the reversible matrix V1; or: First, the state conversion operation and intersection judgment operation are performed on the reversible matrix V1, and then the state conversion operation and intersection judgment operation are performed on the unit matrix V0.

8. The BDD-based quantum linear reversible circuit generation system according to claim 5, characterized in that: The target state BDD collection and the initial state BDD collection no longer grow, specifically: Determine whether the number of states of the two target state BDD sets before and after the state conversion operation on the reversible matrix V1 increases, and if not, the target state BDD set no longer increases; It is determined whether the state quantity of the two initial state BDD sets before and after the state conversion operation is performed on the identity matrix V0 increases. If not, the initial state BDD set no longer increases.

9. An electronic device comprising a storage unit and a processing unit, wherein the storage unit stores computer instructions that can be executed on the processing unit, wherein: When the processing unit runs the computer instructions, the processing unit performs the steps of the method for generating a quantum linear reversible circuit based on BDD according to any one of claims 1 to 4.

10. A storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed, the steps of the method for generating a quantum linear reversible circuit based on BDD as claimed in any one of claims 1 to 4 are executed.

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