Linearization calibration circuit and calibration method applied to a pipeline ADC without sample-and-hold structure

Abstract

The application discloses a linearization calibration circuit and method applied to a pipeline ADC without a sampling and holding structure, and the circuit comprises a signal generation module, a pipeline ADC quantization module and a linear calibration module. The signal generation module is used for generating a pseudo-random signal, and the pseudo-random signal is converted into a dithering signal and then input into the pipeline ADC quantization module. The dithering signal comprises a first dithering signal and a second dithering signal. The pipeline ADC quantization module is used for superimposing the first dithering signal and the second dithering signal on an input signal respectively after the first dithering signal and the second dithering signal are processed through different paths, generating a to-be-calibrated signal, and quantizing the to-be-calibrated signal to obtain an output digital code. The linear calibration module is used for calibrating the to-be-calibrated signal based on a preset weight coefficient, the output digital code and the pseudo-random signal, and obtaining a calibrated signal. The application does not affect the main function of the circuit during calibration, is suitable for the pipeline ADC without the sampling and holding structure, can be operated in the background, has low circuit complexity, and has important significance for improving the linearity of the ADC applied to various communication systems.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design technology, specifically relating to a linearization calibration circuit and calibration method for pipelined ADCs without sampling and protection structures. Background Technology

[0002] With the development of radio frequency communication, signal frequencies are getting higher and higher, and bandwidths are getting wider and wider. Therefore, there are higher linearity requirements for high-speed radio frequency ADCs (analog to digital converters) in radio frequency communication.

[0003] In related technologies, while advancements in process nodes have increased transistor speed, they have also reduced power supply voltage and intrinsic gain, leading to a deterioration in the linearity of operational amplifiers in pipelined ADCs. This has become a bottleneck for improving the linearity of pipelined ADCs. Therefore, those skilled in the art urgently need to find methods to overcome this bottleneck. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a linearization calibration circuit and method for a pipelined ADC without a sampling and protection structure. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides a linearization calibration circuit for a pipelined ADC without a sample-and-protection structure, comprising: a signal generation module, a pipelined ADC quantization module, and a linear calibration module; wherein...

[0006] The signal generation module is used to generate a pseudo-random signal D. PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D The jitter signal V is then input to the pipeline ADC quantization module. D Includes the first jitter signal and the second jitter signal;

[0007] The pipelined ADC quantization module is used to process the first jitter signal and the second jitter signal through different paths and then respectively compare them with the input signal V. IN The signals are superimposed, and after generating the signal to be calibrated, the signal to be calibrated is quantized to obtain the output digital code;

[0008] The linear calibration module is used to perform calibration based on preset weighting coefficients, the output digital code, and the pseudo-random signal D. PRBS The signal to be calibrated is then calibrated to obtain a calibration signal.

[0009] In one embodiment of the present invention, the pipelined ADC quantization module includes an N-stage pipeline;

[0010] The pipelined ADC quantization module is specifically used to process the first jitter signal and the second jitter signal through different paths, and then respectively compare them with the input signal V. IN After superimposing to generate the signal to be calibrated, the N-stage pipeline is used to quantize the signal to be calibrated to obtain N output digital codes.

[0011] In one embodiment of the present invention, the preset weighting coefficients include N first preset weighting coefficients corresponding to the N output digital codes and the pseudo-random signal D. PRBS The corresponding second preset weighting coefficient;

[0012] The linear calibration module is specifically used to calibrate the signal to be calibrated according to the following formula:

[0013] D OUT_CALI =D1×α1+D2×α2+……+D N ×α N -D PRBS ×α PRBS

[0014] Where α1, α2, ..., α N α represents the N first preset weight coefficients corresponding to the N output digital codes. PRBS The pseudo-random signal D represents PRBS The corresponding second preset weighting coefficient, D OUT_CALI This refers to the calibration signal.

[0015] In one embodiment of the present invention, the signal generation module includes a PRBS generation unit, a first injection dithering unit, and a second injection dithering unit; wherein,

[0016] The PRBS generation unit is used to generate a pseudo-random binary sequence and use the pseudo-random binary sequence as a pseudo-random signal D. PRBS The first injection jitter module is used to inject jitter based on the pseudo-random signal D. PRBS A reference voltage is generated, the reference voltage carrying a first jitter signal, and the second jitter module is used to generate a reference voltage based on the pseudo-random signal D. PRBS A second jitter signal is generated.

[0017] In one embodiment of the present invention, it further includes an inverting reference voltage signal terminal VREFN and a non-inverting reference voltage signal terminal VREFP. The first injection jitter unit includes a series of multi-stage sub-units. The first terminal of the first stage sub-unit is connected to the non-inverting reference voltage signal terminal VREFP, and the second terminal of the last stage sub-unit is connected to the inverting reference voltage signal terminal VREFN.

[0018] The subunit includes a first jitter signal output terminal, resistors R1, R2, R3, and R4, and switches K1, K2, and K3. R1, R2, R3, and R4 are connected in series. R1 and R2 are connected to a first node N1, R2 and R3 are connected to a second node N2, and R3 and R4 are connected to a third node N3. The first terminals of K1, K2, and K3 are connected to the first node N1, the second node N2, and the third node N3, respectively, and the second terminals are all connected to the reference voltage output terminal.

[0019] In one embodiment of the present invention, switches K1 and K3 are controlled by differential signals generated by the PRBS generation unit.

[0020] In one embodiment of the present invention, the second injected jitter unit includes: a digital-to-analog converter (DAC) and a calibration capacitor C. D The input terminal of the DAC is connected to the output terminal of the PRBS generation unit, and the output terminal is connected to the calibration capacitor C. D Connect to the first stage pipeline in the N-stage pipeline.

[0021] Secondly, the present invention provides a linearization calibration method for an ADC in a pipeline without a sampling and protection structure, characterized in that it is applied to the above-mentioned linearization calibration circuit, comprising:

[0022] Generate pseudo-random signal D PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D The jitter signal V D Includes the first jitter signal and the second jitter signal;

[0023] After the first jitter signal and the second jitter signal are processed through different paths, they are respectively compared with the input signal V. IN Superimposed to generate the signal to be calibrated;

[0024] After quantizing the signal to be calibrated into N output digital codes using an N-stage pipeline, the N output digital codes are then used as the basis for the calibration. PRBS The signal to be calibrated is then calibrated to obtain a calibration signal.

[0025] In one embodiment of the present invention, the preset weighting coefficients include N first preset weighting coefficients corresponding to the N output digital codes and the pseudo-random signal D. PRBS The corresponding second preset weighting coefficient;

[0026] After quantizing the signal to be calibrated into N output digital codes using an N-stage pipeline, the N output digital codes are then used as the basis for the calibration. PRBSThe signal to be calibrated is calibrated according to the following formula:

[0027] D OUT_CALI =D1×α1+D2×α2+……+D N ×α N -D PRBS ×α PRBS

[0028] Where α1, α2, ..., α N α represents the N first preset weight coefficients corresponding to the N output digital codes. PRBS The pseudo-random signal D represents PRBS The corresponding second preset weighting coefficient, D OUT_CALI This refers to the calibration signal.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] This invention provides a linearization calibration circuit and calibration method for a pipelined ADC without a sampling and protection structure. Since the first jitter signal and the second jitter signal have different processing paths and opposite polarities, the injected first jitter signal and second jitter signal can cancel each other out after entering the first stage pipeline of the pipelined ADC quantization module, thus avoiding the jitter signal occupying the redundant range and ensuring the normal operation of the circuit.

[0031] Furthermore, in this invention, the pseudo-random signal can be regarded as a known signal, and the linear calibration module achieves calibration by subtracting the total digital code from the known pseudo-random code, without affecting the signal-to-noise ratio of the ADC in each stage of the pipeline.

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0033] Figure 1 This is a block diagram of a linearization calibration circuit for a pipelined ADC without a sampling and protection structure, provided in an embodiment of the present invention.

[0034] Figure 2 This is a partial schematic diagram of a linearization calibration circuit applied to a pipeline ADC without a sampling and protection structure, provided in an embodiment of the present invention.

[0035] Figure 3a This is a schematic diagram of the circuit structure of the first injection jitter unit provided in an embodiment of the present invention;

[0036] Figure 3b This is a schematic diagram of the circuit structure of the first injection jitter unit in the related technology;

[0037] Figure 4This is a 2.5-bit transmission curve diagram of the first stage pipeline in the pipelined ADC quantization module provided in this embodiment of the invention;

[0038] Figure 5 This is a transmission curve of 2.5-bit superimposed jitter in the first stage pipeline of the pipelined ADC quantization module provided in this embodiment of the invention;

[0039] Figure 6a This is an uncalibrated ADC spectrum diagram provided in an embodiment of the present invention;

[0040] Figure 6b This is the ADC spectrum after linearization calibration provided in this embodiment;

[0041] Figure 7 This is a flowchart of a linearization calibration method for a pipelined ADC without a sampling and protection structure, provided by an embodiment of the present invention. Detailed Implementation

[0042] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0043] Figure 1 This is a block diagram of a linearization calibration circuit for a pipelined ADC without a sampling and protection structure, provided in an embodiment of the present invention. Please refer to... Figure 1 This invention provides a linearization calibration circuit for a pipelined ADC without a sampling and protection structure, comprising: a signal generation module 10, a pipelined ADC quantization module 20, and a linear calibration module 30; wherein,

[0044] Signal generation module 10 is used to generate pseudo-random signal D. PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D The jitter signal V is then input to the pipeline ADC quantization module 20. D Includes the first jitter signal and the second jitter signal;

[0045] The pipelined ADC quantization module 20 is used to process the first jitter signal and the second jitter signal through different paths and then respectively compare them with the input signal V. IN The signals are superimposed, and after generating the signal to be calibrated, the signal to be calibrated is quantized to obtain the output digital code;

[0046] Linear calibration module 30 is used to perform calibration based on preset weighting coefficients, output digital code, and pseudo-random signal D. PRBS The signal to be calibrated is calibrated to obtain the calibration signal.

[0047] In this embodiment, after calibration is enabled, the signal generation module 10 first generates a PRBS (Pseudo-Random Binary Sequence) as a pseudo-random signal D. PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D Then, the input signal V IN With jitter signal V D The superimposed signals are sent to the pipelined ADC quantization module 20, which can quantize the signals to be calibrated into output digital codes.

[0048] Optionally, the pipelined ADC quantization module 20 includes an N-stage pipeline;

[0049] The pipelined ADC quantization module 20 is specifically used to process the first jitter signal and the second jitter signal through different paths and then respectively compare them with the input signal V. IN After superimposing the signals to be calibrated, the signals are quantized using an N-stage pipeline to obtain N output digital codes.

[0050] Furthermore, the preset weighting coefficients include N first preset weighting coefficients corresponding to the N output digital codes and the pseudo-random signal D. PRBS The corresponding second preset weighting coefficient;

[0051] Linear calibration module 30 is specifically used to calibrate the signal to be calibrated according to the following formula:

[0052] D OUT_CALI =D1×α1+D2×α2+……+D N ×α N -D PRBS ×α PRBS

[0053] Where α1, α2, ..., α N α represents the N first preset weight coefficients corresponding to the N output numeric codes. PRBS Represents the pseudo-random signal D PRBS The corresponding second preset weighting coefficient, D OUT_CALI This indicates the calibration signal.

[0054] It should be understood that, without calibration, the output signal D OUT_UNCAL =D1×α1+D2×α2+……+D N ×α N After calibration is enabled, the jitter signal V in the signal to be calibrated needs to be removed. D Among them, the jitter signal V D For pseudo-random signal D PRBSThe product of its corresponding second preset weight coefficient, i.e.: V D =D PRBS ×α PRBS Therefore, the calibration signal is: D OUT_CALI =D1×α1+D2×α2+……+D N ×α N -D PRBS ×α PRBS This removes jitter from the signal to be calibrated without affecting the circuit function.

[0055] In addition, in practical applications, the LMS (Least Mean Square) algorithm can be used to extract the pseudo-random signal D from the signal to be calibrated. PRBS .

[0056] Figure 2 This is a partial schematic diagram of a linearization calibration circuit applied to a pipelined ADC without a sampling and protection structure, provided in an embodiment of the present invention. Figure 2 As shown, in this embodiment, the signal generation module 10 includes a PRBS generation unit 101, a first injection jitter unit 102, and a second injection jitter unit 103; wherein,

[0057] PRBS generation unit 101 is used to generate a pseudo-random binary sequence and use the pseudo-random binary sequence as a pseudo-random signal D. PRBS The first injection jitter module is used to inject jitter based on the pseudo-random signal D. PRBS A reference voltage is generated, carrying a first jitter signal. The second jitter module is used to generate a reference voltage based on a pseudo-random signal D. PRBS A second jitter signal is generated.

[0058] Specifically, the above includes an inverted reference voltage signal terminal VREFN and a non-inverted reference voltage signal terminal VREFP. The first injection jitter unit 102 includes multiple sub-units connected in series. The first terminal of the first-level sub-unit is connected to the non-inverted reference voltage signal terminal VREFP, and the second terminal of the last-level sub-unit is connected to the inverted reference voltage signal terminal VREFN.

[0059] Figure 3a This is a schematic diagram of the circuit structure of the first injection jitter unit 102 provided in an embodiment of the present invention. Figure 3aAs shown, the sub-unit includes a first jitter signal output terminal, resistors R1, R2, R3, and R4, and switches K1, K2, and K3. R1, R2, R3, and R4 are connected in series. There is a first node N1 between R1 and R2, a second node N2 between R2 and R3, and a third node N3 between R3 and R4. The first terminals of K1, K2, and K3 are connected to the first node N1, the second node N2, and the third node N3, respectively, and the second terminals are all connected to the reference voltage output terminal.

[0060] Optionally, switches K1 and K3 are controlled by differential signals generated by PRBS generation unit 101.

[0061] Figure 3b This is a schematic diagram of the circuit structure of the first injection dithering unit 102 in the related technology. As shown in Figure 3, in the related technology, eight reference voltages are generated through resistor voltage division and provided to the sub-ADC of the first stage pipeline in the pipelined ADC quantization module 20. Figure 3b Compared to the circuit structures shown, the difference between the two is that in this embodiment, each reference voltage output is connected through three switches (K1, K2, K3). In normal operation mode, the reference voltage is connected to the intermediate voltage value. In calibration mode, the reference voltage is randomly connected to switches K1 and K3. When the reference voltage is connected to switch K1, the reference voltage will increase by a certain voltage value. When the reference voltage is connected to switch K3, the reference voltage will decrease by the same amount. In this embodiment, the first jitter signal is superimposed on the reference voltage in this way, thereby adding the pseudo-random code to the sub-ADC.

[0062] Furthermore, the second injection jitter unit 103 includes: a digital-to-analog converter (DAC) and a calibration capacitor C. D The input terminal of the DAC is connected to the output terminal of the PRBS generation unit 101, and the output terminal is connected to the calibration capacitor C. D Connect to the first stage pipeline in the N-stage pipeline.

[0063] Please continue reading Figure 2 The sampling capacitor C in the pipelined ADC quantization module 20 s Responsible for sampling input signal V IN And maintain the sampled value, calibrating capacitor C D The lower plate of the ADC is connected to the inverting input of the op-amp, and the upper plate is connected to a voltage selected by a digital-to-analog converter (DAC). Controlled by a pseudo-random code generated by PRBS, this voltage value generates a random signal, also known as the second jitter signal. This second jitter signal is superimposed on the sampled signal and injected into the op-amp. Due to the random nature of the jitter signal, it affects the nonlinearity generated in the op-amp. The C of the sub-ADC... REF The capacitor will receive an input signal V. INThe superposition of the reference voltage and the second jitter signal is achieved at the reference voltage output terminal of the resistor string through switches K1, K2, and K3 of the PRBS generation unit 101, thereby affecting the nonlinearity of the sub-ADC. These effects uniformly convert harmonics in the frequency spectrum into noise in the frequency band through randomization, so that high-power harmonics are attenuated, thereby improving linearity and total harmonic distortion.

[0064] As the above analysis shows, in this invention, after the pseudo-random signal is converted into a first jitter signal and a second jitter signal, the first jitter signal and the second jitter signal are injected into the first stage pipeline of the pipelined ADC quantization module through two paths. Since the processing paths of the first jitter signal and the second jitter signal are different and their polarities are opposite, the first jitter signal and the second jitter signal injected at the operational amplifier output cancel each other out, which can prevent the jitter signal from occupying the redundant range, thereby ensuring the normal operation of the circuit. At the same time, the linear calibration module completes the calibration based on the first preset weight coefficient, the second preset weight coefficient, the pseudo-random signal, and the output digital code. This method is applicable to pipelined ADCs without a sampling and protection structure, can run in the background, has low circuit complexity, and will not affect the main function. This is of great significance for improving the linearity of ADCs applied in various communication systems.

[0065] Figure 4 This is a 2.5-bit transmission curve diagram of the first stage pipeline in the pipelined ADC quantization module 20 provided in this embodiment of the invention. Figure 4 As shown, in the calibration method provided by this invention, in addition to the sub-ADC, an extra comparator is added to each pipeline stage, which can expand the input range. Figure 4 It can be seen that the input signal V IN The range between -9 / 8Vref and 9 / 8Vref is within the redundancy range. Within the allowable range of output amplitude, the input range is increased by ±1Vref / 8, thus providing conditions for adding jitter signals. The maximum amplitude of the jitter signal is ±1 / 8Vref, and the magnitude of the added jitter signal amplitude will not affect the calibration effect.

[0066] Figure 5 This is a transmission curve of 2.5-bit superimposed jitter in the first stage pipeline of the pipelined ADC quantization module 20 provided in this embodiment of the invention. Figure 5 As shown, when the added jitter is positive, the overall curve shifts to the left; when the added jitter is negative, the overall curve shifts to the right. The entire transfer curve exhibits no over-redundancy on the vertical axis. By randomly shifting the transfer function left and right, the nonlinearity existing in a certain interval is evenly distributed nearby, thereby weakening the worst harmonic energy. Furthermore, the overall curve shape remains unchanged, therefore its quantization characteristics are unchanged and quantization performance is not affected.

[0067] Figure 6a This is an uncalibrated ADC spectrum provided in an embodiment of the present invention. Figure 6b This is the ADC spectrum after linearization and calibration provided in this embodiment. Figures 6a-6b As shown, the uncalibrated ADC spectrum exhibits high spurious harmonic power and an uneven spectrum. The harmonic influence is significant due to the nonlinearity of the amplifier and sub-ADC. The calibration linearization technique randomizes these harmonics, distributing them evenly across the noise floor, thus improving spectrum smoothness and linearity. FFT analysis revealed that the ADC linearity before calibration was 82.9 dB and the signal-to-noise ratio (SNR) was 67.2 dB, while the linearity after calibration was 86.6 dB and the SNR was 67.2 dB. Therefore, the calibration method provided by this invention reduces ADC spectral spurious power, improves linearity by 3.7 dB, and maintains the same SNR, which is of great significance for improving ADC linearity.

[0068] Figure 7 This is a flowchart of a linearization calibration method for a pipelined ADC without a sampling and protection structure, provided by an embodiment of the present invention. Figure 7 As shown, this embodiment of the invention also provides a linearization calibration method for a pipelined ADC without a sampling and protection structure, applied to the above-mentioned linearization calibration circuit, including:

[0069] S1. Generate pseudo-random signal D PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D jitter signal V D Includes the first jitter signal and the second jitter signal;

[0070] S2. After processing the first jitter signal and the second jitter signal through different paths, they are respectively compared with the input signal V. IN Superimposed to generate the signal to be calibrated;

[0071] S3. After quantizing the signal to be calibrated into N output digital codes using an N-stage pipeline, based on preset weighting coefficients, the N output digital codes, and the pseudo-random signal D... PRBS The signal to be calibrated is calibrated to obtain the calibration signal.

[0072] Optionally, in step S3 above, the preset weighting coefficients include N first preset weighting coefficients corresponding to the N output digital codes and the pseudo-random signal D. PRBS The corresponding second preset weighting coefficient;

[0073] After quantizing the signal to be calibrated into N output digital codes using an N-stage pipeline, the calibration is then performed based on preset weighting coefficients, the N output digital codes, and a pseudo-random signal D. PRBS The signal to be calibrated is calibrated according to the following formula:

[0074] D OUT_CALI =D1×α1+D2×α2+D N ×α N -D PRBS ×α PRBS

[0075] Where α1, α2, ..., α N α represents the N first preset weight coefficients corresponding to the N output numeric codes. PRBS Represents the pseudo-random signal D PRBS The corresponding second preset weighting coefficient, D OUT_CALI This indicates the calibration signal.

[0076] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0077] This invention provides a linearization calibration circuit and calibration method for a pipelined ADC without a sampling and protection structure. Since the first jitter signal and the second jitter signal have different processing paths and opposite polarities, the injected first jitter signal and second jitter signal can cancel each other out after entering the first stage pipeline of the pipelined ADC quantization module, thus avoiding the jitter signal occupying the redundant range and ensuring the normal operation of the circuit.

[0078] Furthermore, in this invention, the pseudo-random signal can be regarded as a known signal, and the linear calibration module achieves calibration by subtracting the total digital code from the known pseudo-random code, without affecting the signal-to-noise ratio of the ADC in each stage of the pipeline.

[0079] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0080] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0081] Although this application has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in carrying out the claimed application by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0082] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A linearization calibration circuit for a pipelined ADC without a sampling and protection structure, characterized in that, include: The module consists of a signal generation module, a pipelined ADC quantization module, and a linear calibration module; among which, The signal generation module is used to generate a pseudo-random signal D. PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D The jitter signal V is then input to the pipeline ADC quantization module. D Includes the first jitter signal and the second jitter signal; The signal generation module includes a first injection jitter unit, a second injection jitter unit, an inverting reference voltage signal terminal VREFN, and a non-inverting reference voltage signal terminal VREFP. The first injection jitter unit includes multiple sub-units connected in series. The first terminal of the first-level sub-unit is connected to the non-inverting reference voltage signal terminal VREFP, and the second terminal of the last-level sub-unit is connected to the inverting reference voltage signal terminal VREFN. The subunit includes a first jitter signal output terminal, resistors R1, R2, R3, and R4, and switches K1, K2, and K3. R1, R2, R3, and R4 are connected in series. R1 and R2 are connected to a first node N1, R2 and R3 are connected to a second node N2, and R3 and R4 are connected to a third node N3. The first terminals of K1, K2, and K3 are connected to the first node N1, the second node N2, and the third node N3, respectively, and the second terminals are all connected to the reference voltage output terminal. The second injected jitter unit includes: a digital-to-analog converter (DAC) and a calibration capacitor C. D The input terminal of the DAC is connected to the output terminal of the PRBS generation unit, and the output terminal is connected to the calibration capacitor C. D Connect to the first stage pipeline in the N-stage pipeline; The pipelined ADC quantization module is used to process the first jitter signal and the second jitter signal through different paths and then respectively compare them with the input signal V. IN The signals are superimposed, and after generating the signal to be calibrated, the signal to be calibrated is quantized to obtain the output digital code; The linear calibration module is used to perform calibration based on preset weighting coefficients, the output digital code, and the pseudo-random signal D. PRBS The signal to be calibrated is then calibrated to obtain a calibration signal.

2. The linearization calibration circuit for a pipelined ADC without a sampling and protection structure as described in claim 1, characterized in that, The pipelined ADC quantization module includes an N-stage pipeline; The pipelined ADC quantization module is specifically used to process the first jitter signal and the second jitter signal through different paths, and then respectively compare them with the input signal V. IN After superimposing to generate the signal to be calibrated, the N-stage pipeline is used to quantize the signal to be calibrated to obtain N output digital codes.

3. The linearization calibration circuit for a pipelined ADC without a sampling and protection structure as described in claim 2, characterized in that, The preset weighting coefficients include the N first preset weighting coefficients corresponding to the N output digital codes and the pseudo-random signal D. PRBS The corresponding second preset weighting coefficient; The linear calibration module is specifically used to calibrate the signal to be calibrated according to the following formula: D OUT_CALI =D1×α1+D2×α2+……+D N ×α N -D PRBS ×α PRBS Where α1, α2, ..., α N α represents the N first preset weight coefficients corresponding to the N output digital codes. PRBS The pseudo-random signal D represents PRBS The corresponding second preset weighting coefficient, D OUT_CALI This refers to the calibration signal.

4. The linearization calibration circuit for a pipelined ADC without a sampling and protection structure according to claim 1, characterized in that, The signal generation module further includes a PRBS generation unit; wherein... The PRBS generation unit is used to generate a pseudo-random binary sequence and use the pseudo-random binary sequence as a pseudo-random signal D. PRBS The first injection jitter module is used to inject jitter based on the pseudo-random signal D. PRBS A reference voltage is generated, the reference voltage carrying a first jitter signal, and the second jitter module is used to generate a reference voltage based on the pseudo-random signal D. PRBS A second jitter signal is generated.

5. The linearization calibration circuit for a pipelined ADC without a sampling and protection structure according to claim 1, characterized in that, Switches K1 and K3 are controlled by differential signals generated by the PRBS generation unit.

6. A linearization calibration method for an ADC applied to a pipelined ADC without a sampling and protection structure, characterized in that, The linearization calibration circuit applied to any one of claims 1 to 5 includes: Generate pseudo-random signal D PRBS and the pseudo-random signal D PRBS Converted to jitter signal V D The jitter signal V D Includes the first jitter signal and the second jitter signal; After the first jitter signal and the second jitter signal are processed through different paths, they are respectively compared with the input signal V. IN Superimposed to generate the signal to be calibrated; After quantizing the signal to be calibrated into N output digital codes using an N-stage pipeline, the N output digital codes are then used as the basis for the calibration. PRBS The signal to be calibrated is then calibrated to obtain a calibration signal.

7. The linearization calibration method for a pipelined ADC without a sampling and protection structure according to claim 6, characterized in that, The preset weighting coefficients include the N first preset weighting coefficients corresponding to the N output digital codes and the pseudo-random signal D. PRBS The corresponding second preset weighting coefficient; After quantizing the signal to be calibrated into N output digital codes using an N-stage pipeline, the N output digital codes are then used as the basis for the calibration. PRBS The signal to be calibrated is calibrated according to the following formula: D OUT_CALI =D1×α1+D2×α2+……+D N ×α N -D PRBS ×α PRBS Where α1, α2, ..., α N α represents the N first preset weight coefficients corresponding to the N output digital codes. PRBS The pseudo-random signal D represents PRBS The corresponding second preset weighting coefficient, D OUT_CALI This refers to the calibration signal.

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