Electronic devices, communication systems, communication methods and storage media

Abstract

This application provides an electronic device, a communication system, a communication method, and a storage medium. The electronic device includes a first terminal device, which is communicatively connected to a second terminal device via a distributed soft bus. The first terminal device includes a security control unit, a crystal oscillator module, a dedicated integrated circuit for the soft bus, and a communication system-on-a-chip. This application can reduce the CPU usage of distributed soft bus communication and avoid affecting the operation of other programs in the terminal device.

Description

Technical Field

[0001] This application relates to the technical field of soft buses, and more particularly to an electronic device, a communication system, a communication method, and a storage medium. Background Technology

[0002] Distributed soft bus technology can automatically discover other nearby devices and connect them to form a network, enabling communication between devices within a certain distance. Current distributed soft bus communication methods require the electronic devices on both sides to perform functions such as connection, networking, Wireless Local Area Networks (WLAN) services, and communication.

[0003] When communicating via a distributed soft bus, information from both electronic devices must pass through the Central Processing Unit (CPU), and the communication content is processed by processing software. Therefore, the communication speed and latency are strongly correlated with the CPU performance of both electronic devices, and it places a high demand on the system CPU, thus affecting the operation of other programs in the electronic devices. Summary of the Invention

[0004] The main objective of this application is to provide an electronic device, communication system, communication method, and storage medium, which aims to solve the problem that the CPU utilization rate is high when communicating via a distributed soft bus, thereby affecting the operation of other programs in the terminal device.

[0005] In a first aspect, this application provides an electronic device, including a first terminal device, which is communicatively connected to a second terminal device via a distributed soft bus, for transmitting first data resources to the second terminal device; the first terminal device includes a security control unit, a crystal oscillator module, a soft bus application-specific integrated circuit, and a communication system-on-a-chip.

[0006] The security control unit is used to obtain a data access request sent by the second terminal device through the distributed soft bus. The data access request is used to request access to the first data resource. The security control unit is also used to perform security verification on the second terminal device according to the data access request, and to form a network with the second terminal device through the distributed soft bus after the verification is successful.

[0007] The crystal oscillator module is connected to the safety control unit and is used to provide a first clock signal, which is synchronized with the second clock signal of the second terminal device.

[0008] The soft bus dedicated integrated circuit is connected to the crystal oscillator module. The soft bus dedicated integrated circuit is also used to connect to the system bus and output the first data resource transmitted by the system bus to the communication system-on-a-chip through direct memory access and the first clock signal.

[0009] The communication system-on-a-chip is connected to the dedicated soft bus integrated circuit and is used to send the first data resource to the second terminal device through the distributed soft bus.

[0010] Secondly, this application also provides an electronic device, including a second terminal device, which is communicatively connected to a first terminal device via a distributed soft bus and is used to access a second data resource in the first terminal device; the second terminal device includes a security control unit, a crystal oscillator module, a soft bus application-specific integrated circuit, and a communication system-on-a-chip.

[0011] The security control unit is used to perform security verification on the first terminal device, and after the verification is successful, to network with the first terminal device through the distributed soft bus; the security control unit is also used to send a data access request to the first terminal device through the distributed soft bus, the data access request being used to request access to the second data resource of the first terminal device in the manner of direct memory access;

[0012] The communication system-on-a-chip is connected to the dedicated soft bus integrated circuit and is used to receive the second data resources transmitted by the first terminal device in a direct memory access manner through the distributed soft bus.

[0013] The crystal oscillator module is connected to the safety control unit and is used to provide a second clock signal, which is synchronized with the first clock signal of the first terminal device.

[0014] The soft bus ASIC is connected to the crystal oscillator module and is also used to connect to the system bus; the soft bus ASIC is also used to output the second data resources transmitted by the communication system-on-a-chip to the memory file through the system bus based on the second clock signal.

[0015] Thirdly, this application also provides a communication system, including the first terminal device as described above and the second terminal device as described above; wherein the first terminal device is communicatively connected to the second terminal device via a distributed soft bus.

[0016] Fourthly, this application also provides a communication method applied to a first terminal device, wherein the first terminal device is communicatively connected to a second terminal device via a distributed soft bus, and is used to transmit first data resources to the second terminal device; the first terminal device includes a security control unit, a crystal oscillator module, a soft bus dedicated integrated circuit, and a communication system-on-a-chip.

[0017] The security control unit is used to obtain data access requests sent by the second terminal device through the distributed soft bus, and the data access requests are used to request access to the first data resource; the crystal oscillator module is connected to the security control unit; the soft bus dedicated integrated circuit is connected to the crystal oscillator module, and the soft bus dedicated integrated circuit is also used to connect to the system bus; the communication system-on-a-chip is connected to the soft bus dedicated integrated circuit;

[0018] The communication method includes:

[0019] The security control unit performs security verification on the second terminal device according to the data access request, and after the verification is successful, it forms a network with the second terminal device through the distributed soft bus.

[0020] The crystal oscillator module provides a first clock signal, which is synchronized with the second clock signal of the second terminal device.

[0021] The first data resource transmitted by the system bus is output to the communication system-on-a-chip via the soft bus application-specific integrated circuit in a direct memory access manner and using the first clock signal.

[0022] The first data resource is sent to the second terminal device via the distributed soft bus through the communication system-on-a-chip.

[0023] Fifthly, this application also provides a communication method applied to a second terminal device, wherein the second terminal device is communicatively connected to a first terminal device via a distributed soft bus, and is used to access a second data resource in the first terminal device; the second terminal device includes a security control unit, a crystal oscillator module, a soft bus application-specific integrated circuit, and a communication system-on-a-chip.

[0024] The security control unit is used to perform security verification on the first terminal device, and after successful verification, it forms a network with the first terminal device through the distributed soft bus; the crystal oscillator module is connected to the security control unit; the soft bus dedicated integrated circuit is connected to the crystal oscillator module and is also used to connect to the system bus; the communication system-on-a-chip is connected to the soft bus dedicated integrated circuit.

[0025] The communication method includes:

[0026] The security control unit sends a data access request to the first terminal device via the distributed soft bus. The data access request is used to request access to the second data resource of the first terminal device in a direct memory access manner.

[0027] The communication system-on-a-chip utilizes the distributed soft bus to receive the second data resource transmitted by the first terminal device in a direct memory access manner.

[0028] The crystal oscillator module provides a second clock signal, which is synchronized with the first clock signal of the first terminal device.

[0029] Based on the second clock signal, the soft bus application-specific integrated circuit outputs the second data resources transmitted by the communication system-on-a-chip to the memory file via the system bus.

[0030] Sixthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the communication method described above.

[0031] The electronic device provided in this application includes a first terminal device, which communicates with a second terminal device via a distributed soft bus. The first terminal device includes a security control unit, a crystal oscillator module, a dedicated soft bus integrated circuit, and a communication system-on-a-chip. The security control unit performs security verification on the second terminal device and, upon successful verification, networks with it via the distributed soft bus, thereby ensuring data security at the hardware level, accelerating processing speed, hardware-based device networking and inter-certification, and quickly establishing a secure connection channel. The crystal oscillator module, connected to the security control unit, provides a first clock signal synchronized with the second clock signal of the second terminal device, thereby reducing the risk of soft clock synchronization, improving device collaboration efficiency, and reducing the CPU resources used for clock calibration. The dedicated soft bus integrated circuit, also connected to the crystal oscillator module, connects to the system bus and outputs the first data resources transmitted by the system bus to the communication system-on-a-chip via direct memory access and the first clock signal, thus hardware-based hardware-based the core capabilities of the soft bus. The first data resources can be transmitted via direct memory access without going through the CPU, reducing latency and increasing bandwidth. The communication system-on-a-chip (SoC) is connected to a dedicated integrated circuit for the soft bus, used to send first data resources to the second terminal device via a distributed soft bus, thereby realizing bus task processing and physical communication. This method reduces CPU usage during distributed soft bus communication, thus avoiding impact on the operation of other programs on the terminal device. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A schematic block diagram illustrating one embodiment of the first terminal device provided in this application;

[0034] Figure 2 A flowchart of one embodiment of the first terminal device provided in this application;

[0035] Figure 3 A schematic block diagram illustrating one embodiment of the soft bus application-specific integrated circuit provided in this application.

[0036] Figure 4 A flowchart of another embodiment of the first terminal device provided in this application;

[0037] Figure 5 A schematic block diagram illustrating one embodiment of the soft bus control unit provided in this application.

[0038] Figure 6 A flowchart of another implementation of the first terminal device provided in the embodiments of this application;

[0039] Figure 7 A schematic block diagram illustrating another embodiment of the soft bus control unit provided in this application;

[0040] Figure 8 A schematic block diagram illustrating another embodiment of the soft bus application-specific integrated circuit provided in this application.

[0041] Figure 9 A schematic block diagram illustrating one embodiment of the communication system-on-a-chip provided in this application.

[0042] Figure 10 A schematic block diagram illustrating one embodiment of the second terminal device provided in this application;

[0043] Figure 11 This is a flowchart illustrating the steps of a communication method provided in an embodiment of this application.

[0044] Figure 12 This is a flowchart illustrating the steps of another communication method provided in an embodiment of this application.

[0045] Figure 13 A schematic block diagram of a communication system provided in an embodiment of this application;

[0046] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation. Furthermore, although functional modules are divided in the device diagram, in some cases, a different module division may be used.

[0049] This application provides an electronic device that may include a first terminal device and a second terminal device. The first terminal device is used to transmit a first data resource to the second terminal device, and the second terminal device is used to access a second data resource in the first terminal device. The first and second terminal devices may be electronic devices such as mobile phones, tablets, laptops, desktop computers, personal digital assistants, and wearable devices. For example, the first terminal device may be a mobile phone, and the second terminal device may be a smart screen. Another example is that the first terminal device is a tablet computer, and the second terminal device is a laptop computer.

[0050] It should be noted that the first terminal device communicates with the second terminal device via a distributed soft bus. The distributed soft bus integrates and merges various wireless communication and network protocols (such as Bluetooth, Wi-Fi, NFC, and the Internet), thereby shielding the technical details of the underlying protocols and providing a unified interface. The deployment of the distributed soft bus enables hardware cooperation and resource sharing among various electronic devices, providing a unified distributed communication capability for interconnection between electronic devices.

[0051] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0052] Please see Figure 1 , Figure 1 This is a schematic block diagram illustrating one embodiment of the first terminal device provided in this application.

[0053] like Figure 1 As shown, the first terminal device 100 is connected to the second terminal device 200 via a distributed soft bus and is used to transmit the first data resource to the second terminal device 200. The first terminal device 100 includes a security control unit 110, a crystal oscillator module 120, a soft bus application-specific integrated circuit 130, and a communication system-on-a-chip 140.

[0054] The security control unit 110 is used to obtain data access requests sent by the second terminal device 200 through a distributed soft bus. The data access requests are used to request access to the first data resources in the first terminal device 100. The security control unit 110 is also used to perform security verification on the second terminal device 200 according to the data access requests, and to form a network with the second terminal device 200 through the distributed soft bus after the verification is successful.

[0055] It should be noted that the security control unit 110 refers to a control unit equipped with a security mechanism, which includes a security verification function. For example, the security control unit 110 can perform security verification on the second terminal device 200 based on a data access request. The security control unit 110 may include a microcontroller unit (MCU) and a central processing unit (CPU) or other general-purpose processors.

[0056] Specifically, the security control unit 110 can have flexible configuration and programming functions, and can be customized and optimized according to different application requirements. Data access requests can carry the identity and address information of the second terminal device 200. The security control unit 110 can verify the identity and address information of the second terminal device 200 carried in the data access request, thereby determining the identity and integrity of the second terminal device 200 and ensuring that the first terminal device 100 is not maliciously tampered with. This guarantees the trustworthiness of both the first terminal device 100 and the second terminal device 200 during operation.

[0057] It should be noted that the security control unit 110 performs security verification on the second terminal device 200, and after successful verification, it networks with the second terminal device 200 via a distributed soft bus. This ensures data security at the hardware level, accelerates processing speed, and enables hardware-based inter-device authentication for networking, quickly establishing a secure connection channel. The security control unit 110 can hardware-enable cryptographic operations during the security verification process, eliminating the need for software-based verification, thus reducing CPU usage and enhancing network security.

[0058] In one embodiment, the crystal oscillator module 120 is connected to the security control unit 110 and is used to provide a first clock signal, which is synchronized with the second clock signal of the second terminal device 200. The first terminal device 100 and the second terminal device 200 can use a unified crystal oscillator standard, ensuring synchronization between the first clock signal and the second clock signal of the second terminal device 200. This reduces the risk of soft clock synchronization, improves inter-device coordination efficiency, and synchronizes the signal transmission rate and time in digital circuits, reducing CPU usage.

[0059] It should be noted that the function of the crystal oscillator module 120 is to provide a stable clock signal for various digital circuits and microprocessors in the first terminal device 100, thereby ensuring the stable operation of the digital circuits and the coordinated operation between various electronic devices. The first clock signal provided by the crystal oscillator module 120 is synchronized with the second clock signal of the second terminal device 200, which can reduce the risk of soft clock synchronization, improve the equipment coordination efficiency, and reduce the CPU resources used for clock calibration.

[0060] It should be noted that current crystal oscillator standards are inconsistent, with each device using a different crystal, leading to clock differences between devices. This necessitates frequent soft clock synchronization, which consumes system resources. If the crystal oscillator clock signal is unstable or inaccurate, it may cause errors in the processor's internal operations and instruction execution, resulting in electronic device malfunctions or data loss. Therefore, the use of synchronized first and second clock signals in this embodiment is crucial for the normal operation and coordinated functioning of the first terminal device 100 and the second terminal device 200.

[0061] In one embodiment, the application-specific integrated circuit (ASIC) 130 is connected to the crystal oscillator module 120. The ASIC 130 is also used to connect to the system bus 10 and output the first data resources transmitted by the system bus 10 to the communication system-on-a-chip 140 through direct memory access and a first clock signal.

[0062] It should be noted that the transmission function of a traditional soft bus is implemented through software. This embodiment of the application implements the transmission function of the soft bus as an ASIC (Application-Specific Integrated Circuit) and uses Direct Memory Access (DMA) to directly access the first data resources of the first terminal device 100. This enables the first terminal device 100 and the second terminal device 200 to collaborate and communicate as if they were on the same device, effectively connecting the two terminal devices together like a hardware bus.

[0063] By hardwareifying the core capabilities of the soft bus, the first data resource can be transmitted via direct memory access without going through the CPU, thereby reducing latency and increasing bandwidth. In other words, this embodiment uses a soft bus ASIC to directly map the first data resource transmitted by the system bus 10 through the communication system-on-a-chip 140, thereby reducing CPU usage and improving the real-time performance of information transmission.

[0064] In one embodiment, a communication system-on-chip (SOC) 140 is connected to a soft bus application-specific integrated circuit (ASIC) 130, used to send first data resources to a second terminal device 200 via a distributed soft bus. It should be noted that the communication SOC 140 sends the first data resources to the second terminal device 200 via the distributed soft bus, thereby realizing bus task processing and physical communication.

[0065] It should be noted that most chips currently in use are low-frequency single-core MCUs, which take a long time to communicate and process data, significantly impacting the real-time performance of communication. Therefore, this solution can select a multi-core high-frequency chip as a communication SOC to handle bus task processing and physical communication, thereby improving the processing speed.

[0066] In summary, the security control unit 110, crystal oscillator module 120, soft bus dedicated integrated circuit 130, and communication system-on-a-chip 140 designed in this application embodiment are intended to use specific chips to handle specific tasks, reduce the occupation of system resources (CPU), and reduce the repetitiveness of the first terminal device 100's work, improve communication efficiency, and reduce the CPU occupation rate when the distributed soft bus is communicating, thereby avoiding affecting the operation of other programs in the terminal device.

[0067] Those skilled in the art will understand that Figure 1 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the first terminal device 100 to which the present application is applied. The specific first terminal device 100 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0068] For example, please refer to Figure 2 , Figure 2 A flowchart of one embodiment of the first terminal device provided in this application.

[0069] like Figure 2As shown, the security control unit 110 is used to obtain data access requests sent by the second terminal device 200 via a distributed soft bus, perform security verification on the second terminal device 200 according to the data access requests, and form a network with the second terminal device 200 via the distributed soft bus after successful verification. When determining to communicate with the second terminal device 200, the security control unit 110 sends a first control signal to the crystal oscillator module 120, which controls the first clock signal provided by the crystal oscillator module 120. Based on the first control signal, the crystal oscillator module 120 provides the first clock signal to the soft bus application-specific integrated circuit 130. The soft bus application-specific integrated circuit 130 outputs the first data resource transmitted by the system bus 10 to the communication system-on-a-chip 140 via direct memory access and based on the first clock signal. The communication system-on-a-chip 140 sends the first data resource to the second terminal device 200 via the distributed soft bus.

[0070] In one embodiment, the security control unit 110 includes a main control unit, a security verification unit, and a networking unit. The main control unit is used to acquire data access requests sent by the second terminal device 200 via a distributed soft bus. These data access requests request access to a first data resource. The security verification unit is used to obtain device information of the second terminal device 200 from the data access requests and perform security verification on the second terminal device 200 based on the device information, obtaining a security verification result. The networking unit is connected to the security verification unit and is used to network with the second terminal device 200 via the distributed soft bus after the security verification result is successful; the networking unit is also used to stop networking with the second terminal device 200 after the security verification result is unsuccessful.

[0071] It should be noted that the security verification unit refers to a data processing unit equipped with multiple security mechanisms (including secure boot, hardware encryption, secure storage, and identity authentication functions). The security verification unit can possess multiple security mechanisms to protect the device from various security attacks, including physical attacks, side-channel attacks, and software attacks. The networking unit can send feedback signals to the second terminal device 200 and establish a self-connecting network with the second terminal device 200 through these feedback signals.

[0072] For example, the security verification unit can use features such as secure boot, hardware encryption, and secure storage to protect data and code within the device, thereby enhancing security. Therefore, the security control unit 110 can protect valuable or vulnerable assets, such as code, algorithms, user configurations, calibration values, and data, from theft, modification, forgery, or other harmful acts, ensuring the confidentiality, integrity, and availability of these assets.

[0073] In one embodiment, such as Figure 3As shown, the soft bus application-specific integrated circuit 130 includes a soft bus control unit 131, a data buffer unit 132, and a data encapsulation unit 133. The soft bus control unit 131 is connected to the system bus 10 and is also connected to the data buffer unit 132. The soft bus control unit 131 stores the first data resource transmitted by the system bus 10 into the data buffer unit 132 via direct memory access. The data encapsulation unit 133 is connected to the data buffer unit 132 and is used to encapsulate the first data resource stored in the data buffer unit 132 based on a first clock signal, and then outputs the encapsulated first data resource to the communication system-on-a-chip 140.

[0074] It should be noted that the data encapsulation unit 133 can be a User Datagram Protocol (UDP) unit. Under the control of the soft bus control unit 131, the first data resource can be copied to the data buffer unit 132 via the system bus 10 for storage through DMA transfer. Then, under the coordination of the first clock signal, the data encapsulation unit 133 encapsulates the first data resource stored in the data buffer unit 132, enabling transmission via direct memory access without CPU intervention, thus reducing latency and increasing bandwidth.

[0075] For example, please refer to Figure 4 , Figure 4 A flowchart of another embodiment of the first terminal device provided in this application.

[0076] like Figure 4 As shown, the soft bus control unit 131 stores the first data resource transmitted by the system bus 10 into the data buffer unit 132 via direct memory access. The crystal oscillator module 120 provides a first clock signal to the data encapsulation unit 133. Based on the first clock signal, the data encapsulation unit 133 encapsulates the first data resource stored in the data buffer unit 132 and outputs the encapsulated first data resource to the communication system-on-a-chip 140.

[0077] In one embodiment, such as Figure 5As shown, the soft bus control unit 131 includes a bus interface 1311, a mapping controller 1312, and a buffer controller 1313. The input of the bus interface 1311 is connected to the system bus 10, and the output of the bus interface 1311 is connected to the data buffer unit 132. The bus interface 1311 is used to transfer the first data resource transmitted by the system bus 10 via direct memory access to the data buffer unit 132. The mapping controller 1312 is used to generate a mapping control instruction based on the first data resource requested by the data access request; the mapping control instruction includes description information of the first data resource. The input of the buffer controller 1313 is connected to the mapping controller 1312, and the output of the buffer controller 1313 is connected to the data buffer unit 132. The buffer controller 1313 is used to output a buffer control instruction to the data buffer unit 132 according to the mapping control instruction, and the buffer control instruction instructs the data buffer unit 132 to store the first data resource according to the description information of the first data resource.

[0078] It should be noted that the first data resource can be stored in the data buffer unit 132 via the bus interface 1311 in the soft bus control unit 131. The bus interface 1311 is, for example, a PCIe (Peripheral Component Interconnect Express) interface. The system bus 10 maps the first data resource to the bus interface 1311 via direct memory access, and then the bus interface 1311 transmits it to the data buffer unit 132. The distributed soft buses communicate via a network, and the mapping controller 1312 and the buffer controller 1313 control the first data resource stored in the data buffer unit 132.

[0079] For example, please refer to Figure 6 , Figure 6 A flowchart of another embodiment of the first terminal device provided in this application.

[0080] like Figure 6 As shown, the bus interface 1311 is used to transfer the first data resource transmitted by the system bus 10 via direct memory access to the data buffer unit 132. The mapping controller 1312 is used to generate a mapping control instruction according to the first data resource requested by the data access request, and output the mapping control instruction to the buffer controller 1313. The buffer controller 1313 outputs a buffer control instruction to the data buffer unit 132 according to the mapping control instruction. The buffer control instruction is used to instruct the data buffer unit 132 to store the first data resource according to the description information of the first data resource.

[0081] In one embodiment, the soft bus control unit 131 further includes a read / write controller; the read / write controller is connected to the control terminal of the bus interface 1311 and is used to control the reading and writing of the first data resource transmitted by the bus interface 1311.

[0082] For example, such as Figure 7 As shown, the soft bus control unit 131 also includes a read / write controller 1314, which controls the reading and writing of the first data resource transmitted by the bus interface 1311. For example, it outputs a data read command to the bus interface 1311 to read the first data resource transmitted by the system bus 10 through direct memory access.

[0083] In one embodiment, such as Figure 8 As shown, the soft bus application-specific integrated circuit 130 also includes a forward error correction unit 134 and a data encryption unit 135. The forward error correction unit 134 is connected to the data encapsulation unit 133 and is used to perform forward error correction processing on the encapsulated first data resource to obtain the processed first data resource. The data encryption unit 135 is connected to the forward error correction unit 134 and is used to encrypt the processed first data resource and output the encrypted first data resource to the communication system-on-a-chip 140.

[0084] The forward error correction unit 134 can also be called the FEC (Forward Error Correction) unit, and the data encryption unit 135 can also be called the AES unit. It should be noted that most cryptographic operations currently used are processed by software, resulting in poor key security and high system computational resource consumption, leading to poor security performance. This embodiment of the application integrates the forward error correction unit and the data encryption unit into the software bus dedicated integrated circuit 130, eliminating the need for software encryption and decryption of the first data resource, thus reducing CPU usage and improving network security.

[0085] In one embodiment, the communication system-on-a-chip 140 includes a communication control unit and multiple communication units, each communication unit being connected to the communication control unit via its corresponding communication line. The communication control unit is connected to a soft bus dedicated integrated circuit 130 and is used to divide the first data resource output by the soft bus dedicated integrated circuit 130 into multiple first sub-data resources; the communication control unit is also used to distribute the multiple first sub-data resources to each communication unit through multiple communication lines; each communication unit is used to send the multiple first sub-data resources to the second terminal device 200 via a distributed soft bus in a multipath transmission manner.

[0086] It's important to note that this refers to communication SoCs (System on Chip). Communication SoCs offer high integration, combining multiple functions into a single chip, including communication, computing, storage, sensing, and control. This significantly reduces the number of circuit boards and space required, while improving system reliability and stability. Communication SoCs also boast high performance, typically featuring high-performance processors and ample memory, enabling them to process more data and support a wider range of applications. Furthermore, communication SoCs are cost-effective because they utilize relatively small chips, fewer components, and simpler designs, thus reducing overall costs.

[0087] For example, such as Figure 9 As shown, the communication system-on-a-chip 140 includes a communication control unit 141 and multiple communication units 142. Each communication unit 142 includes a Bluetooth communication unit, a 5G communication unit, and a WIFI communication unit. Each communication unit 142 is connected to the communication control unit 141 through its corresponding communication line. The communication control unit 141 is connected to a soft bus dedicated integrated circuit 130 and is used to divide the first data resource output by the soft bus dedicated integrated circuit 130 into multiple first sub-data resources. The communication control unit 141 is also used to distribute the multiple first sub-data resources to each communication unit 142 through multiple communication lines. Each communication unit 142 is used to send the multiple first sub-data resources to the second terminal device 200 through a distributed soft bus in a multipath transmission manner.

[0088] The first terminal device 100 provided in this embodiment includes a security control unit 110, a crystal oscillator module 120, a soft bus ASIC 130, and a communication system-on-a-chip 140. The security control unit 110 performs security verification on the second terminal device 200. After successful verification, it networks with the second terminal device 200 via a distributed soft bus, thereby ensuring data security at the hardware level, accelerating processing speed, hardware-based device networking and inter-authentication, and quickly establishing a secure connection channel. The crystal oscillator module 120 is connected to the security control unit 110 and provides a first clock signal synchronized with the second clock signal of the second terminal device 200, thereby reducing the risk of soft clock synchronization, improving device collaboration efficiency, and reducing the CPU resources used for clock calibration. The soft bus ASIC 130 is connected to the crystal oscillator module 120 and also connects to the system bus 10. Through direct memory access and the first clock signal, it outputs the first data resources transmitted by the system bus 10 to the communication system-on-a-chip 140, thereby hardware-based hardware-based the core capabilities of the soft bus. The first data resources can be transmitted through direct memory access without going through the CPU, reducing latency and increasing bandwidth. The communication system-on-a-chip 140 is connected to the soft bus dedicated integrated circuit 130, and is used to send the first data resource to the second terminal device 200 through the distributed soft bus, thereby realizing bus task processing and physical communication. This method can reduce the CPU utilization rate when the distributed soft bus is communicating, thus avoiding affecting the operation of other programs in the terminal device.

[0089] Please see Figure 10 , Figure 10 This is a schematic block diagram illustrating one embodiment of the second terminal device provided in this application.

[0090] like Figure 10 As shown, the second terminal device 200 is connected to the first terminal device 100 via a distributed soft bus and is used to access the second data resources in the first terminal device 100. The second terminal device 200 includes a security control unit 210, a crystal oscillator module 220, a soft bus application-specific integrated circuit 230, and a communication system-on-a-chip 240.

[0091] The security control unit 210 is used to perform security verification on the first terminal device 100, and after the verification is successful, it forms a network with the first terminal device 100 through a distributed soft bus, thereby ensuring data security at the hardware level, accelerating the computing speed, making the device networking and mutual authentication hardware-based, and quickly establishing a secure connection channel.

[0092] The security control unit 210 is also used to send a data access request to the first terminal device 100 via a distributed soft bus. The data access request is used to request access to the second data resource of the first terminal device 100 in a direct memory access manner.

[0093] The communication system-on-a-chip 240 is connected to the soft bus application-specific integrated circuit 230 and is used to receive the second data resource transmitted by the first terminal device 100 via direct memory access through a distributed soft bus. The communication system-on-a-chip 240 receives the second data resource sent by the first terminal device 100 through the distributed soft bus, thereby realizing bus task processing and physical communication.

[0094] The crystal oscillator module 220 is connected to the safety control unit 210 to provide a second clock signal. The second clock signal is synchronized with the first clock signal of the first terminal device 100, thereby reducing the risk of soft clock synchronization, improving device coordination efficiency, and reducing the CPU resources used for calibrating the clock.

[0095] The soft bus ASIC 230 is connected to the crystal oscillator module 220 and is also used to connect to the system bus 20. The soft bus ASIC 230 is also used to output the second data resource transmitted by the communication system-on-a-chip 240 to the memory file via the system bus 20 based on the second clock signal. By hardware-izing the core capabilities of the soft bus, the first data resource can be transmitted through direct memory access without going through the CPU, thus reducing latency and increasing bandwidth.

[0096] The second terminal device 200 provided in the above embodiments can reduce the CPU usage rate when the distributed soft bus communicates, thereby avoiding affecting the operation of other programs in the terminal device.

[0097] It should be noted that those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of each module and unit in the second terminal device 200 described above can be referred to the corresponding processes in the aforementioned first terminal device 100 embodiment. The difference between the two lies in the different data sending and receiving processes, which will not be repeated here in the embodiments of this application.

[0098] Please refer to Figure 11 , Figure 11 This is a flowchart illustrating the steps of a communication method provided in an embodiment of this application. The communication method can be applied to a first terminal device, which communicates with a second terminal device via a distributed soft bus, for transmitting first data resources to the second terminal device. The first terminal device includes a security control unit, a crystal oscillator module, a dedicated soft bus integrated circuit, and a communication system-on-a-chip.

[0099] The security control unit is used to obtain data access requests sent by the second terminal device through the distributed soft bus. The data access requests are used to request access to the first data resource. The crystal oscillator module is connected to the security control unit. The soft bus dedicated integrated circuit is connected to the crystal oscillator module. The soft bus dedicated integrated circuit is also used to connect to the system bus. The communication system-on-a-chip is connected to the soft bus dedicated integrated circuit.

[0100] like Figure 11 As shown, the electronic device includes steps S301 to S304.

[0101] Step S301: The security control unit performs security verification on the second terminal device according to the data access request, and after the verification is successful, it forms a network with the second terminal device through a distributed soft bus.

[0102] Specifically, the security control unit can have flexible configuration and programming capabilities, and can be customized and optimized according to different application requirements. Data access requests can carry the identity and address information of the second terminal device. The security control unit can verify the identity and address information of the second terminal device carried in the data access request, thereby determining the identity and integrity of the second terminal device and ensuring that the first terminal device cannot be maliciously tampered with.

[0103] In one embodiment, the security control unit includes a main control unit, a security verification unit, and a networking unit. The main control unit is used to acquire data access requests sent by a second terminal device via a distributed soft bus. These data access requests request access to a first data resource. The security verification unit is used to obtain device information of the second terminal device from the data access requests and perform security verification on the second terminal device based on the device information to obtain a security verification result. The networking unit is connected to the security verification unit and is used to network with the second terminal device via the distributed soft bus after the security verification result is successful; the networking unit is also used to stop networking with the second terminal device after the security verification result is unsuccessful.

[0104] Step S302: A first clock signal is provided through the crystal oscillator module, and the first clock signal is synchronized with the second clock signal of the second terminal device.

[0105] The first and second terminal devices can adopt a unified crystal oscillator standard, so that the first clock signal is synchronized with the second clock signal of the second terminal device, thereby reducing the risk of soft clock synchronization, improving the coordination efficiency between devices, and synchronizing the signal transmission rate and time in digital circuits, reducing the CPU usage.

[0106] It should be noted that current crystal oscillator standards are inconsistent, with each device using a different crystal, leading to clock differences between devices. This necessitates frequent soft clock synchronization, which consumes system resources. If the crystal oscillator clock signal is unstable or inaccurate, it may cause errors in the processor's internal operations and instruction execution, resulting in electronic device malfunctions or data loss. Therefore, the embodiments of this application use synchronized first and second clock signals, which are crucial for the normal operation and coordinated functioning of the first and second terminal devices.

[0107] Step S303: Using a dedicated soft bus integrated circuit, the first data resource transmitted by the system bus is output to the communication system-level chip via direct memory access and the first clock signal.

[0108] It should be noted that the transmission function of a traditional soft bus is implemented through software. This embodiment of the application implements the transmission function of the soft bus as an ASIC (Application-Specific Integrated Circuit) and uses Direct Memory Access (DMA) to directly access the first data resources of the first terminal device 100. This enables the first terminal device 100 and the second terminal device 200 to collaborate and communicate as if they were on the same device, effectively connecting the two terminal devices together like a hardware bus.

[0109] By hardwareifying the core capabilities of the soft bus, the first data resource can be transmitted via direct memory access without going through the CPU, thereby reducing latency and increasing bandwidth. In other words, this embodiment uses a soft bus ASIC to directly map the first data resource transmitted by the system bus 10 through the communication system-on-a-chip 140, thereby reducing CPU usage and improving the real-time performance of information transmission.

[0110] Step S304: The first data resource is sent to the second terminal device via a distributed soft bus through a communication system-on-a-chip.

[0111] It should be noted that most chips currently in use are low-frequency single-core MCUs, which take a long time to communicate and process data, significantly impacting the real-time performance of communication. Therefore, this solution can select a multi-core high-frequency chip as a communication SOC to handle bus task processing and physical communication, thereby improving the processing speed.

[0112] The communication method provided in the above embodiments involves a communication system-on-a-chip (SoC) sending first data resources to a second terminal device via a distributed soft bus, thereby realizing bus task processing and physical communication. The design of the security control unit, crystal oscillator module, dedicated soft bus integrated circuit, and communication SoC aims to use specific chips to handle specific tasks, reducing the occupation of system resources (CPU). The purpose of this application's embodiments is to reduce the repetitiveness of the first terminal device's work, improve communication efficiency, and reduce CPU usage during distributed soft bus communication, thereby avoiding impact on the operation of other programs on the terminal device.

[0113] Please refer to Figure 12 , Figure 12 This is a flowchart illustrating the steps of another communication method provided in an embodiment of this application.

[0114] This communication method can be applied to a second terminal device, which communicates with the first terminal device via a distributed soft bus to access the second data resources in the first terminal device. The second terminal device includes a security control unit, a crystal oscillator module, a soft bus application-specific integrated circuit, and a communication system-on-a-chip.

[0115] The security control unit is used to perform security verification on the first terminal device and, after successful verification, to network with the first terminal device via a distributed soft bus; the crystal oscillator module is connected to the security control unit; the dedicated soft bus integrated circuit is connected to the crystal oscillator module and is also used to connect to the system bus; the communication system-on-a-chip is connected to the dedicated soft bus integrated circuit.

[0116] like Figure 12 As shown, the electronic device includes steps S401 to S404.

[0117] Step S401: Send a data access request to the first terminal device via the distributed soft bus through the security control unit.

[0118] The data access request is used to request access to the second data resource of the first terminal device via direct memory access. The security control unit can generate a data access request for the second data resource and send the data access request to the first terminal device using a distributed soft bus.

[0119] Step S402: Receive the second data resource transmitted by the first terminal device via direct memory access through a distributed soft bus using a communication system-on-a-chip.

[0120] The communication system-on-a-chip (SoC) can receive second data resources sent by the first terminal device via a distributed soft bus, thereby enabling bus task processing and physical communication. The second data resource can be transmitted by the first terminal device using direct memory access.

[0121] Step S403: Provide a second clock signal through the crystal oscillator module. The second clock signal is synchronized with the first clock signal of the first terminal device.

[0122] The first and second terminal devices can adopt a unified crystal oscillator standard, so that the first clock signal is synchronized with the second clock signal of the second terminal device, thereby reducing the risk of soft clock synchronization, improving the coordination efficiency between devices, and synchronizing the signal transmission rate and time in digital circuits, reducing the CPU usage.

[0123] Step S404: Based on the second clock signal, the second data resource transmitted by the communication system-on-a-chip is output to the memory file via the system bus through the soft bus dedicated integrated circuit.

[0124] By hardwareifying the core capabilities of the soft bus, primary data resources can be transmitted via direct memory access without going through the CPU, thus reducing latency and increasing bandwidth.

[0125] In one embodiment, the transmission function of the soft bus is implemented using an ASIC (Application-Specific Integrated Circuit), and Direct Memory Access (DMA) is applied to directly access the first data resources of the first terminal device. This enables the first and second terminal devices to collaborate and communicate as if they were on the same device, effectively connecting them like a hardware bus. Therefore, direct mirroring can be achieved through the communication system-on-a-chip 140, reducing CPU usage and improving the real-time performance of information transmission.

[0126] The communication method provided in the above embodiments, by designing a security control unit, a crystal oscillator module, a dedicated integrated circuit for the soft bus, and a communication system-on-a-chip, is designed to use specific chips to handle specific tasks, thereby reducing the occupation of system resources (CPU). The purpose of this application embodiment is to reduce the repetitiveness of terminal device work, improve communication efficiency, and reduce the CPU occupation rate when the distributed soft bus communicates, thereby avoiding affecting the operation of other programs in the terminal device.

[0127] Please refer to Figure 13 , Figure 13 This is a schematic block diagram of a communication system provided in an embodiment of this application.

[0128] like Figure 13 As shown, the communication system 500 includes a first terminal device 510 and a second terminal device 520. The first terminal device 510 is communicatively connected to the second terminal device 520 via a distributed soft bus. For example, the first terminal device 510 may include the aforementioned... Figures 1 to 10 The first terminal device 100 and the second terminal device 520 may include the above-mentioned Figures 1 to 10 The second terminal device 200.

[0129] The key feature of the communication system provided in this application embodiment is that it allows the end-side devices (first terminal device 510 and second terminal device 520) to select a unified soft bus module as much as possible. Based on a heterogeneous distributed hardware architecture, a proprietary integrated circuit for the soft bus is designed. The heterogeneous distributed soft bus module includes four key features: using an architecture of security control unit + communication SOC + soft bus ASIC + unified crystal clock to form a soft bus module hardware framework. This reduces the CPU utilization rate during distributed soft bus communication, thereby avoiding impact on the operation of other programs in the terminal devices.

[0130] In one embodiment, a first terminal device 510 is communicatively connected to a second terminal device 520 via a distributed soft bus, and is used to transmit a first data resource to the second terminal device 520. The first terminal device 510 includes a security control unit, a crystal oscillator module, a dedicated soft bus integrated circuit, and a communication system-on-a-chip. The security control unit is used to obtain a data access request sent by the second terminal device via the distributed soft bus, the data access request being used to request access to the first data resource. The crystal oscillator module is connected to the security control unit. The dedicated soft bus integrated circuit is connected to the crystal oscillator module, and is also used to connect to the system bus. The communication system-on-a-chip is connected to the dedicated soft bus integrated circuit.

[0131] The first terminal device 510 is used for:

[0132] The security control unit performs security verification on the second terminal device according to the data access request, and after the verification is successful, it forms a network with the second terminal device through the distributed soft bus.

[0133] The crystal oscillator module provides a first clock signal, which is synchronized with the second clock signal of the second terminal device.

[0134] The first data resource transmitted by the system bus is output to the communication system-on-a-chip via the soft bus application-specific integrated circuit in a direct memory access manner and using the first clock signal.

[0135] The first data resource is sent to the second terminal device via the distributed soft bus through the communication system-on-a-chip.

[0136] In one embodiment, a second terminal device 520 is communicatively connected to a first terminal device 510 via a distributed soft bus to access a second data resource in the first terminal device 510. The second terminal device 520 includes a security control unit, a crystal oscillator module, a dedicated soft bus integrated circuit, and a communication system-on-a-chip. The security control unit performs security verification on the first terminal device and, upon successful verification, networks with it via the distributed soft bus. The crystal oscillator module is connected to the security control unit. The dedicated soft bus integrated circuit is connected to the crystal oscillator module and is also used to connect to the system bus. The communication system-on-a-chip is connected to the dedicated soft bus integrated circuit.

[0137] The second terminal device 520 is used for:

[0138] The security control unit sends a data access request to the first terminal device via the distributed soft bus. The data access request is used to request access to the second data resource of the first terminal device in a direct memory access manner.

[0139] The communication system-on-a-chip utilizes the distributed soft bus to receive the second data resource transmitted by the first terminal device in a direct memory access manner.

[0140] The crystal oscillator module provides a second clock signal, which is synchronized with the first clock signal of the first terminal device.

[0141] Based on the second clock signal, the soft bus application-specific integrated circuit outputs the second data resources transmitted by the communication system-on-a-chip to the memory file via the system bus.

[0142] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the first terminal device 510 and the second terminal device 520 described above can be referred to the corresponding processes in the aforementioned electronic device embodiments, and will not be repeated here.

[0143] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, and the method implemented when the program instructions are executed can be referred to various embodiments of the communication method of this application.

[0144] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.

[0145] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0146] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0147] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An electronic device, comprising: The first terminal device is connected with a second terminal device through a distributed soft bus, and is configured to transmit a first data resource to the second terminal device; the first terminal device comprises a security control unit, a crystal oscillator module, a soft bus application specific integrated circuit and a communication system level chip; the security control unit is configured to acquire a data access request transmitted by the second terminal device through the distributed soft bus, the data access request being configured to request access to the first data resource; the security control unit is further configured to perform security verification on the second terminal device according to the data access request, and to form a network with the second terminal device through the distributed soft bus after the verification is passed; the crystal oscillator module is connected with the security control unit, and is configured to provide a first clock signal, the first clock signal being synchronized with a second clock signal of the second terminal device; the soft bus application specific integrated circuit is connected with the crystal oscillator module, and is further configured to connect a system bus, and to output a first data resource transmitted by the system bus to the communication system level chip through a direct memory access mode and the first clock signal; the communication system level chip is connected with the soft bus application specific integrated circuit, and is configured to transmit the first data resource to the second terminal device through the distributed soft bus; the soft bus application specific integrated circuit comprises a soft bus control unit, a data buffer unit and a data packaging unit; the soft bus control unit is configured to connect the system bus and the data buffer unit; the soft bus control unit is configured to store the first data resource transmitted by the system bus in the data buffer unit through a direct memory access mode; the data packaging unit is connected with the data buffer unit, and is configured to package the first data resource stored in the data buffer unit based on the first clock signal, and to output the packaged first data resource to the communication system level chip.

2. The electronic device of claim 1, wherein, the soft bus control unit comprises a bus interface, a mapping controller and a buffer controller; an input end of the bus interface is configured to connect the system bus, and an output end of the bus interface is connected with the data buffer unit; the bus interface is configured to transmit the first data resource transmitted by the system bus through a direct memory access mode to the data buffer unit; the mapping controller is configured to generate a mapping control instruction according to the first data resource requested to be accessed by the data access request; the mapping control instruction comprises description information of the first data resource; an input end of the buffer controller is connected with the mapping controller, and an output end of the buffer controller is connected with the data buffer unit; the buffer controller is configured to output a buffer control instruction to the data buffer unit according to the mapping control instruction, the buffer control instruction being configured to instruct the data buffer unit to store the first data resource according to the description information of the first data resource.

3. The electronic device of claim 2, wherein, The soft bus control unit further comprises a read-write controller; the read-write controller is connected with the control end of the bus interface, and is configured to control reading and writing of the first data resource transmitted by the bus interface.

4. The electronic device of claim 1, wherein, The soft bus application-specific integrated circuit further comprises a forward error correction unit and a data encryption unit; The forward error correction unit is connected with the data packaging unit, and is configured to perform forward error correction processing on the packaged first data resource to obtain processed first data resource; The data encryption unit is connected with the forward error correction unit, and is configured to encrypt the processed first data resource and output the encrypted first data resource to the communication system-level chip.

5. The electronic device of any of claims 1-4, wherein, The communication system-level chip comprises a communication control unit and a plurality of communication units, and each communication unit is connected with the communication control unit through a corresponding communication line; The communication control unit is connected with the soft bus application-specific integrated circuit, and is configured to split the first data resource output by the soft bus application-specific integrated circuit to obtain a plurality of first sub-data resources; The communication control unit is further configured to distribute the plurality of first sub-data resources to each communication unit through a plurality of communication lines; and each communication unit is configured to transmit the plurality of first sub-data resources to the second terminal device through the distributed soft bus in a multipath transmission manner.

6. The electronic device of any of claims 1-4, wherein, The security control unit comprises a master control unit, a security verification unit and a networking unit; The master control unit is configured to obtain a data access request transmitted by the second terminal device through the distributed soft bus, and the data access request is used to request access to the first data resource; The security verification unit is configured to obtain device information of the second terminal device from the data access request, and perform security verification on the second terminal device according to the device information to obtain a security verification result; The networking unit is connected with the security verification unit, and is configured to network with the second terminal device through the distributed soft bus when the security verification result is verified; and the networking unit is further configured to stop networking with the second terminal device when the security verification result is not verified.

7. An electronic device, comprising: The second terminal device is connected with the first terminal device through the distributed soft bus, and is configured to access the second data resource in the first terminal device; the second terminal device comprises a security control unit, a crystal oscillator module, a soft bus application-specific integrated circuit and a communication system-level chip; The security control unit is configured to perform security verification on the first terminal device, and network with the first terminal device through the distributed soft bus after verification; and the security control unit is further configured to send a data access request to the first terminal device through the distributed soft bus, and the data access request is used to request to access the second data resource of the first terminal device in a direct memory access manner; The communication system-level chip is connected with the soft bus application-specific integrated circuit, and is configured to receive the second data resource transmitted by the first terminal device in a direct memory access manner through the distributed soft bus. The crystal oscillator module is connected with the safety control unit and is configured to provide a second clock signal, which is synchronized with a first clock signal of the first terminal device; The soft bus application specific integrated circuit is connected with the crystal oscillator module and is further configured to connect a system bus; the soft bus application specific integrated circuit is further configured to output, based on the second clock signal, second data resources transmitted by the communication system level chip to the memory file through the system bus.

8. A communication system, characterized by The first terminal device comprises the safety control unit, the crystal oscillator module, the soft bus application specific integrated circuit and the communication system level chip.

9. A method of communication, comprising: The safety control unit is configured to acquire a data access request transmitted by the second terminal device through the distributed soft bus, and the data access request is configured to request access to the first data resources; the crystal oscillator module is connected with the safety control unit; the soft bus application specific integrated circuit is connected with the crystal oscillator module, and the soft bus application specific integrated circuit is further configured to connect a system bus; the communication system level chip is connected with the soft bus application specific integrated circuit. The communication method comprises: The safety control unit is configured to perform safety verification on the second terminal device according to the data access request, and to form a network with the second terminal device through the distributed soft bus after the verification is passed; The crystal oscillator module is configured to provide a first clock signal, which is synchronized with a second clock signal of the second terminal device; The soft bus application specific integrated circuit is configured to output, in a direct memory access mode and by using the first clock signal, first data resources transmitted by the system bus to the communication system level chip; The communication system level chip is configured to transmit the first data resources to the second terminal device by using the distributed soft bus. The second terminal device comprises the safety control unit, the crystal oscillator module, the soft bus application specific integrated circuit and the communication system level chip.

10. A method of communication, comprising: The safety control unit is configured to perform safety verification on the first terminal device, and to form a network with the first terminal device through the distributed soft bus after the verification is passed; the crystal oscillator module is connected with the safety control unit; the soft bus application specific integrated circuit is connected with the crystal oscillator module, and the soft bus application specific integrated circuit is further configured to connect a system bus; the communication system level chip is connected with the soft bus application specific integrated circuit. The communication method comprises: ​ The security control unit sends a data access request to the first terminal device by using the distributed soft bus, and the data access request is used to request to access a second data resource of the first terminal device in a direct memory access mode; The communication system level chip receives the second data resource transmitted by the first terminal device in a direct memory access mode by using the distributed soft bus; The crystal oscillator module provides a second clock signal, and the second clock signal is synchronized with a first clock signal of the first terminal device; The soft bus application specific integrated circuit outputs the second data resource transmitted by the communication system level chip to a memory file through the system bus based on the second clock signal.

11. A computer readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the communication method in any one of claims 9 to 10 is implemented.

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