Display panel and electronic device

Abstract

The application provides a display panel and an electronic device. The display panel comprises a first substrate, the first substrate comprises a first substrate and a driving layer, the driving layer is carried on the surface of the first substrate, and the driving layer comprises: a driving unit, the driving unit is carried on the first substrate; a second insulating layer, the second insulating layer covers the driving unit; a conductive layer, the conductive layer is arranged on the surface of the second insulating layer away from the first substrate; a passivation layer, the passivation layer covers the conductive layer, and the passivation layer has a first via hole; a pixel electrode, the pixel electrode is arranged on the passivation layer, and the pixel electrode is electrically connected to the driving unit; and a common electrode, the common electrode is arranged on the passivation layer, is electrically connected to the conductive layer through the first via hole, and is arranged to be spaced from the pixel electrode, and the common electrode and the pixel electrode form a storage capacitor. The display panel provided by the application can improve pixel charging and aperture ratio, so as to improve product quality.

Description

Technical Field

[0001] This application relates to the field of display device technology, specifically to display panels and electronic devices. Background Technology

[0002] With societal development, users are increasingly demanding high-quality display products, with a particular focus on high-definition and high-refresh-rate in-plane switching (IPS) products. However, in IPS products, there is a conflict between aperture ratio and pixel charging, resulting in suboptimal product quality. Summary of the Invention

[0003] In a first aspect, this application provides a display panel, including a first substrate, the first substrate including a first substrate base and a driving layer, the driving layer being supported on the surface of the first substrate base, the driving layer including:

[0004] A driving unit, wherein the driving unit is mounted on the first substrate;

[0005] A second insulating layer covers the drive unit;

[0006] A conductive layer is disposed on the surface of the second insulating layer opposite to the first substrate.

[0007] A passivation layer covering the conductive layer, the passivation layer having a first via;

[0008] A pixel electrode, wherein the pixel electrode is disposed on the passivation layer and is electrically connected to the driving unit; and

[0009] A common electrode is disposed on the passivation layer, electrically connected to the conductive layer through the first via, and spaced apart from the pixel electrode. The common electrode and the pixel electrode form a storage capacitor.

[0010] The display panel includes multiple pixel areas, each pixel area corresponds to one driving unit, and different pixel areas correspond to different driving units. The pixel area includes an open area and a non-open area.

[0011] The pixel electrode includes a first pixel electrode and a second pixel electrode, wherein the first pixel electrode and a portion of the driving unit are disposed in the non-opening region, and the second pixel electrode is disposed in the opening region;

[0012] The common electrode includes a first common electrode and a second common electrode, wherein the first common electrode and the conductive layer are disposed in the non-opening region, and the second common electrode is disposed in the opening region.

[0013] The driving unit includes:

[0014] A gate, wherein the gate is disposed on the surface of the first substrate.

[0015] A first insulating layer covers the gate;

[0016] A channel layer is disposed on the first insulating layer and corresponding to the gate;

[0017] The source and the drain are disposed at a distance from each other in the channel layer;

[0018] The driver layer also includes:

[0019] A second insulating layer covers the source, the drain, and the channel layer. The second insulating layer has a second via, and the second via passes through the passivation layer. A portion of the first pixel electrode and the second pixel electrode are located in the second via and are electrically connected to the drain.

[0020] The passivation layer is disposed on the surface of the second insulating layer away from the first substrate. The passivation layer includes a first passivation portion located in the non-opening region and a second passivation portion located in the opening region. The first passivation portion has a first surface away from the first substrate, and the second passivation portion has a second surface away from the first substrate. The first surface is away from the first substrate relative to the second surface, and the height difference between the first surface and the second surface is the thickness of the conductive layer.

[0021] The conductive layer has a first slope on the portion facing the second via, and the passivation layer has a second slope on the portion defining the second via. The inclination angle of the first slope is equal to the inclination angle of the second slope.

[0022] The second via includes:

[0023] The first sub-via penetrates the passivation layer;

[0024] The second sub-hole is connected to the first sub-hole, and the angle of the second sub-hole is smaller than the angle of the first sub-hole. The second sub-hole passes through a portion of the second insulating layer.

[0025] A third sub-hole is connected to the second sub-hole, and the angle of the third sub-hole is smaller than that of the second sub-hole. The third sub-hole passes through another portion of the second insulating layer to expose the drain electrode.

[0026] Wherein, the inner diameter of the third sub-hole at the connection point with the second sub-hole is smaller than the inner diameter of the second sub-hole at the connection point with the first sub-hole;

[0027] The second insulating layer has a gently sloping wall at the junction of the second sub-hole and the third sub-hole, the inclination angle of the gently sloping wall being smaller than the inclination angle of the inner wall of the second sub-hole defined by the second insulating layer.

[0028] The driving layer further includes:

[0029] A first pixel layer is disposed within the second insulating layer and corresponds to the opening area;

[0030] In two adjacent driving layers, the two adjacent first pixel layers have an overlapping area, and the overlapping area corresponds to the non-opening area.

[0031] The display panel further includes a second substrate, which is stacked with the first substrate at a distance, and is disposed on the side of the first substrate that carries the driving layer. The second substrate includes:

[0032] Second substrate;

[0033] A plurality of second pixel layers, the plurality of second pixel layers being spaced apart on the surface of the second substrate facing the first substrate, and being disposed corresponding to the opening region; and

[0034] A light-shielding layer is disposed between two adjacent second pixel layers.

[0035] The pixel electrode includes a plurality of second pixel electrodes, and the common electrode includes a plurality of second common electrodes. The distance between each second pixel electrode and the adjacent second common electrode is the same and is a first distance. The distance between the first pixel electrode and the first common electrode is a second distance. The second distance is greater than the first distance, and the minimum value of the second distance is 4μm to 5μm.

[0036] The display panel provided in this application overcomes the problem of limited distance between metal layers by stacking a conductive layer electrically connected to a common electrode and a driving unit electrically connected to a pixel electrode. This increases the storage capacitance between the common electrode and the pixel electrode. Furthermore, by reducing the space between the conductive layer and the driving unit in the arrangement direction of multiple driving layers, the aperture ratio can be increased while keeping the size of the driving layer unchanged. Therefore, the display panel provided in this application can improve pixel charging and aperture ratio, thereby improving product quality.

[0037] Secondly, this application also provides an electronic device, which includes a display panel as described in the first aspect.

[0038] The electronic device provided in this application has a good display effect and high product quality because the display panel has a high aperture ratio and sufficient storage capacity. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the implementation will be briefly introduced below. Obviously, the drawings described below are some implementations of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a partial layer structure of a display panel in related technologies.

[0041] Figure 2 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application.

[0042] Figure 3 for Figure 2 A partial structural diagram of the display panel after a cross-section along line AA in Embodiment 1.

[0043] Figure 4 for Figure 2 A schematic diagram of the pixel area partitioning of the central display panel.

[0044] Figure 5 for Figure 2 A schematic diagram of the open area and the non-open area.

[0045] Figure 6 for Figure 3 The diagram shows a partially enlarged view of part I in one embodiment.

[0046] Figure 7 for Figure 3 The diagram shows a partially enlarged view of part I in another embodiment.

[0047] Figure 8 for Figure 7 A schematic diagram of the tilt angle α6.

[0048] Figure 9 for Figure 2 A partial structural diagram of the display panel after a cross-section along line AA in Embodiment 2.

[0049] Figure 10 for Figure 2 A partial structural diagram of the display panel after a cross-section along line AA in Embodiment 3.

[0050] Figure 11 for Figure 3 A schematic diagram showing the spacing between the middle pixel electrode and the common electrode.

[0051] Figure 12 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this application.

[0052] Reference numerals in the figures: Electronic device 1; Display panel 10; First substrate 100; First substrate 110; Driving layer 120; Driving unit 121; Gate 1211; First insulating layer 1212; Channel layer 1213; Source 1214; Drain 1215; Conductive layer 122; First ramp 1221; Passivation layer 123; First via 1231; First passivation portion 1232; Second passivation portion 1233; First surface 1234; Second surface 1235; Second ramp 1236; Pixel electrode 124; First pixel electrode 1241; Second pixel electrode 1242; Common Electrode 125; First common electrode 1251; Second common electrode 1252; Second insulating layer 126; Second via 1261; Second passivation layer 1262; Planarization layer 1263; First sub-via 1264; Second sub-via 1265; Third sub-via 1266; Sloping wall 1267; First pixel layer 127; Overlapping region 1271; Pixel region 200; Opening region 210; Non-opening region 220; Second substrate 300; Second substrate 310; Second pixel layer 320; Light-shielding layer 330; First pitch d1; Second pitch d2; Substrate 2; Common electrode trace 3. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0054] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0055] In this document, references to "embodiment" or "implementation" mean that a particular feature, structure, or characteristic described in connection with an embodiment or implementation may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0056] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a partial layer structure of a display panel in related technologies. In these technologies, the display panel 10 includes a substrate 2, a gate electrode 1211, a common electrode trace 3, a source electrode 1214, a drain electrode 1215, a channel layer 1213, a pixel electrode (PXL) 124, and a common electrode (COM) 125. The gate electrode 1211 and the gate trace are integrated. The gate electrode 1211 and the common electrode trace 3 are disposed on the surface of the substrate 2 in the same layer. The source electrode 1214 and the drain electrode 1215 are spaced apart at both ends of the channel layer 1213. The drain electrode 1215, the source electrode 1214, and the channel layer 1213 are stacked and spaced apart from the gate electrode 1211, and are positioned away from the substrate 2 relative to the gate electrode 1211. The pixel electrode 124 and the common electrode 125 are disposed away from the substrate 2 relative to the drain electrode 1215 and the source electrode 1214. The pixel electrode 124 is electrically connected to the source electrode 1214, and the common electrode 125 is electrically connected to the common electrode trace 3. The pixel electrode 124 and the common electrode 125 are spaced apart, and a storage capacitor (Cst) is formed between the pixel electrode 124 and the common electrode 125.

[0057] In related technologies, since the pixel electrode 124 is electrically connected to the source electrode 1214 through a via, and the common electrode 125 is electrically connected to the common electrode trace 3 through a via, the pixel electrode 124 and the common electrode 125 form a planar electric field. When the gate electrode 1211 is at a high level, the channel layer 1213 is turned on. Because the gate lead and the common electrode trace 3 are on the same plane, and the size of the thin-film transistor (TFT) must meet the pixel charging requirements, and the storage capacitance between the pixel electrode 124 and the common electrode 125 must be sufficiently large, the aperture ratio is not high. If the aperture ratio is sufficiently high, the storage capacitance between the pixel electrode 124 and the common electrode 125 will be too small. Therefore, there is a contradiction between the aperture ratio and the storage capacitance, i.e., a contradiction between the aperture ratio and pixel charging.

[0058] To overcome the contradiction between aperture ratio and pixel charging in related technologies, this application provides a display panel 10. Please refer to... Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 3 for Figure 2 This is a partial structural diagram of the display panel 10 after cross-section along line AA in Embodiment 1. In this embodiment, the display panel 10 includes a first substrate 100, which includes a first substrate 110 and a driving layer 120. The driving layer 120 is supported on the surface of the first substrate 110. The driving layer 120 includes a driving unit 121, a second insulating layer 126, a conductive layer 122, a passivation layer 123, a pixel electrode 124, and a common electrode 125. The driving unit 121 is supported on the first substrate 110. The second insulating layer 126 covers the driving unit 121. The conductive layer 122 is disposed on the surface of the second insulating layer 126 facing away from the first substrate 110. The passivation layer 123 covers the conductive layer 122 and has a first via 1231. The pixel electrode 124 is disposed on the passivation layer 123 and is electrically connected to the driving unit 121. The common electrode 125 is disposed on the passivation layer 123, electrically connected to the conductive layer 122 through the first via 1231, and spaced apart from the pixel electrode 124. The common electrode 125 and the pixel electrode 124 form a storage capacitor.

[0059] In this embodiment, the display panel 10 is a liquid crystal display product, which may be, but is not limited to, an in-plane switching (IPS) product, a color filter array (COA) product, etc. The display panel 10 is used in display devices, such as mobile phones, tablet computers, laptops, handheld computers, personal computers (PCs), personal digital assistants (PDAs), etc.

[0060] In this embodiment, the conductive layer 122 is disposed on the surface of the second insulating layer 126 away from the first substrate 110, that is, the conductive layer 122 and the driving unit 121 are stacked and spaced apart, and the conductive layer 122 is away from the first substrate 110 relative to the driving unit 121. The common electrode 125 is disposed on the passivation layer 123 and is electrically connected to the conductive layer 122 through the first via 1231. Simultaneously, the pixel electrode 124 is electrically connected to the driving unit 121. Since the conductive layer 122 is stacked with the driving unit 121, when the driving unit 121 is turned on, the conductive layer 122 and the driving unit 121 overlap in the stacking direction, allowing a storage capacitor to be formed between the pixel electrode 124 and the common electrode 125. Compared to related technologies where the gate 1211 lead and the common electrode 125 trace are located on the same plane, the stacked conductive layer 122 and the driving unit 121 in this application save space in the arrangement direction of the fair electrode traces across multiple driving layers 120, overcoming the limitation of high resolution and high refresh rate caused by the distance between metal layers. This allows for a larger storage capacitor and aperture ratio without changing the size of the driving layer 120, thereby improving the high resolution and high refresh rate of the display panel 10. Furthermore, the increased storage capacitor increases the on-state current. The conductive layer 122 is also called a metal layer or M3 layer, and the driving unit 121 is also called a TFT. The first substrate 110 is also called a TFT substrate.

[0061] Optionally, the common electrode 125 and the pixel electrode 124 are made of light-transmitting and conductive materials, such as indium tin oxide (ITO), conductive polymers, metal meshes, carbon nanorods, silver nanowires, graphene, etc.

[0062] In summary, the display panel 10 provided in this application overcomes the problem of limited distance between metal layers by stacking the conductive layer 122 electrically connected to the common electrode 125 and the driving unit 121 electrically connected to the pixel electrode 124. This increases the storage capacitance between the common electrode 125 and the pixel electrode 124. Furthermore, by reducing the space between the conductive layer 122 and the driving unit 121 in the arrangement direction of the multiple driving layers 120, the aperture ratio can be increased while keeping the size of the driving layer 120 unchanged. Therefore, the display panel 10 provided in this application can improve pixel charging and aperture ratio, thereby improving product quality.

[0063] Please refer to Figure 3 , Figure 4 and Figure 5 , Figure 4 for Figure 2 A schematic diagram of the pixel area partitioning of the central display panel; Figure 5 for Figure 2 A schematic diagram of the opening and non-opening areas. In this embodiment, the display panel 10 includes a plurality of pixel areas 200. Each pixel area 200 corresponds to one driving unit 121, and different pixel areas 200 correspond to different driving units 121. Each pixel area 200 includes an opening area 210 and a non-opening area 220. The pixel electrode 124 includes a first pixel electrode 1241 and a second pixel electrode 1242. The first pixel electrode 1241 and a portion of the driving unit 121 are disposed in the non-opening area 220. The second pixel electrode 1242 is disposed in the opening area 210. The common electrode 125 includes a first common electrode 1251 and a second common electrode 1252. The first common electrode 1251 and the conductive layer 122 are disposed in the non-opening area 220. The second common electrode 1252 is disposed in the opening area 210.

[0064] In this embodiment, each pixel area 200 is provided with a corresponding driving unit 121 to achieve precise control of the light emission of the display panel 10 in each pixel area 200, thereby improving the light emission efficiency of the display panel 10 and thus improving the display effect of the display panel 10.

[0065] In this embodiment, the opening region 210 refers to the area of ​​the driving layer 120 where light is emitted. A portion of the driving unit 121 and the conductive layer 122 are disposed in the non-opening region 220 to prevent the opaque portion of the driving unit 121 and the conductive layer 122 from affecting light emission. Since the driving unit 121 and the conductive layer 122 are stacked in the non-opening region 220, the space occupied by the non-opening region 220 is reduced, thereby increasing the space occupied by the opening region 210, i.e., increasing the aperture ratio. The portion of the driving unit 121 disposed in the non-opening region 220 refers to the gate 1211, channel layer 1213, source 1214, and drain 1215, as described below.

[0066] Please refer to this again. Figure 3 and Figure 5 In this embodiment, the driving unit 121 includes a gate 1211, a first insulating layer 1212, a channel layer 1213, a source 1214, and a drain 1215. The gate 1211 is disposed on the surface of the first substrate 110. The first insulating layer 1212 covers the gate 1211. The source 1214 and the drain 1215 are spaced apart from each other in the channel layer 1213. The driving layer 120 further includes a second insulating layer 126. The second insulating layer 126 covers the source 1214, the drain 1215, and the channel layer 1213. The second insulating layer 126 has a second via 1261, and the second via 1261 passes through the passivation layer 123. A portion of the first pixel electrode 1241 and the second pixel electrode 1242 are located in the second via 1261 and are electrically connected to the drain 1215. The passivation layer 123 is disposed on the surface of the second insulating layer 126 facing away from the first substrate 110. The passivation layer 123 includes a first passivation portion 1232 located in the non-opening region 220 and a second passivation portion 1233 located in the opening region 210. The first passivation portion 1232 has a first surface 1234 facing away from the first substrate 110. The second passivation portion 1233 has a second surface 1235 facing away from the first substrate 110. The first surface 1234 faces away from the first substrate 110 relative to the second surface 1235, and the height difference between the first surface 1234 and the second surface 1235 is equal to the thickness of the conductive layer 122.

[0067] In this embodiment, the height difference between the first surface 1234 and the second surface 1235 is equal to the thickness of the conductive layer 122. That is, in the stacking direction of the first substrate 110 and the driving layer 120, the distance between the first surface 1234 and the first substrate 110 minus the distance between the second surface 1235 and the first substrate 110 is equal to the thickness of the conductive layer 122. This reduces the influence of the edge electric field of the driving layer 120 on the electric field within the opening region 210, thereby improving problems such as poor liquid crystal alignment at the edge.

[0068] Optionally, the thickness of the conductive layer 122 is the same as the thickness of the gate 1211, the drain 1215, and the source 1214, so as to simplify the fabrication process of the driving layer 120 and reduce the design cost.

[0069] In this embodiment, the first insulating layer 1212 is also referred to as the gate insulating layer or the active layer. The second via 1261 of the second insulating layer 126 also penetrates the passivation layer 123.

[0070] Optionally, the second insulating layer 126 includes a second passivation layer 1262 and a planarization layer 1263. The second passivation layer 1262 covers the source 1214, the drain 1215 and the channel layer 1213. The planarization layer 1263 is disposed on the surface of the second passivation layer 1262 away from the first substrate 110, and the portion of the planarization layer 1263 located in the non-opening region 220 carries the conductive layer 122.

[0071] Furthermore, in this embodiment, since the conductive layer 122 is stacked with the driving unit 121, the size of the opening region 210 can be increased, that is, the aperture ratio of each driving layer 120 can be increased. This allows the size of the channel layer 1213 in the direction from the source 1214 to the drain 1215 to be increased without changing or even increasing the size of the opening region 210, and the spacing between the channel layer 1213 and the gate 1211 to be increased, thereby reducing leakage current.

[0072] Please refer to Figure 3 , Figure 5 and Figure 6 , Figure 6 for Figure 3 The image shows a partially enlarged schematic diagram of one embodiment. In this embodiment, the portion of the conductive layer 122 facing the second via 1261 has a first ramp 1221. The passivation layer 123 defines a portion of the second via 1261 with a second ramp 1236. The tilt angle of the first ramp 1221 (i.e., Figure 6 In this context, α1) is equal to the inclination angle of the second slope 1236 (i.e. Figure 6 (α2 in the text).

[0073] In this embodiment, the tilt angle of the first ramp 1221 is equal to the tilt angle of the second ramp 1236, which makes the pixel electrode 124 cross layers more smoothly, thereby enhancing the climbing ability of the pixel electrode 124. The tilt angle of the first ramp 1221 is the tilt angle of the first ramp 1221 relative to the first surface 1234, and the tilt angle of the second ramp 1236 is the tilt angle of the second ramp 1236 relative to the first surface 1234. The second ramp 1236 is the sidewall of the passivation layer 123 that defines the second via 1261 and is close to the conductive layer 122.

[0074] Please refer to this again. Figure 3 , Figure 5 and Figure 7 , Figure 7 for Figure 3 The diagram shows a partially enlarged view of section I in another embodiment. In this embodiment, the second via 1261 includes a first sub-via 1264, a second sub-via 1265, and a third sub-via 1266. The first sub-via 1264 penetrates the passivation layer 123. The second sub-via 1265 communicates with the first sub-via 1264, and the angle of the second sub-via 1265 is smaller than the angle of the first sub-via 1264. The second sub-via 1265 transmits through a portion of the second insulating layer 126. The third sub-via 1266 communicates with the second sub-via 1265, and the angle of the third sub-via 1266 is smaller than the angle of the second sub-via 1265. The third sub-via 1266 transmits through another portion of the second insulating layer 126 to expose the drain 1215.

[0075] In this embodiment, the angles of the first sub-hole 1264, the second sub-hole 1265, and the third sub-hole 1266 decrease sequentially to avoid the second through hole 1261 being too large and crowding the opening area 210, thereby increasing the opening ratio.

[0076] Optionally, the inclination angle of the sidewall of the first sub-hole 1264 relative to the surface of the first substrate 110 that supports the driving layer 120 (i.e., Figure 7 The angle of inclination of the second sub-hole 1265 relative to the surface of the first substrate 110 bearing the driving layer 120 is smaller than the angle of inclination of the second sub-hole 1265 relative to the surface of the first substrate 110 bearing the driving layer 120. Figure 7 α4 in the figure), and less than the tilt angle of the third sub-hole 1266 relative to the surface of the first substrate 110 that carries the driving layer 120 (i.e., Figure 7(α5) to improve the climbing ability of the pixel electrode 124 at the first sub-hole 1264.

[0077] Please refer to this again. Figure 3 , Figure 5 , Figure 7 and Figure 8 , Figure 8 for Figure 7 A schematic diagram of the tilt angle α6. In this embodiment, the inner diameter of the connection between the third sub-hole 1266 and the second sub-hole 1265 is smaller than the inner diameter of the connection between the second sub-hole 1265 and the first sub-hole 1264. The second insulating layer 126 has a gently sloping wall 1267 at the connection between the second sub-hole 1265 and the third sub-hole 1266. The tilt angle of the gently sloping wall 1267 (i.e., Figure 8 α6) is less than the inclination angle of the inner wall of the second sub-hole 1265 defined by the second insulating layer 126 (i.e., Figure 7 (α4 in the text). It should be noted that the inclination angle of the gentle slope wall 1267 can be 0°.

[0078] In this embodiment, a gentle slope wall 1267 is provided at the connection between the second sub-hole 1265 and the third sub-hole 1266. This can avoid problems such as broken lines and uneven film thickness of the pixel electrode 124 caused by rubbing when the pixel electrode 124 climbs up the second via 1261 due to the second via 1261 being too deep, thereby improving the product quality of the display panel 10.

[0079] The tilt angle of the gentle slope wall 1267 refers to the tilt angle of the gentle slope wall 1267 relative to the surface of the first substrate 110 that supports the driving layer 120, and the tilt angle of the inner wall of the second sub-hole 1265 defined by the second insulating layer 126 refers to the tilt angle of the inner wall of the second sub-hole 1265 defined by the second insulating layer 126 relative to the surface of the first substrate 110 that supports the driving layer 120.

[0080] Optionally, the second insulating layer 126 defines the inclination angle of the inner wall of the second sub-hole 1265 as equal to the inclination angle of the inner wall of the third sub-hole 1266 defined by the second insulating layer 126, so as to ensure that the climbing angle of the pixel electrode 124 in the second sub-hole 1265 and the third sub-hole 1266 is consistent, so as to make the cross-layer movement of the pixel electrode 124 in the second sub-hole 1265 and the third sub-hole 1266 smoother.

[0081] Please refer to Figure 3 , Figure 5 and Figure 9 , Figure 9for Figure 2 The diagram shows a partial structural view of the display panel after a cross-section along line AA in Embodiment 2. In this embodiment, the driving layer 120 further includes a first pixel layer 127. The first pixel layer 127 is disposed within the second insulating layer 126 and corresponds to the opening region 210. In two adjacent driving layers 120, the two adjacent first pixel layers 127 have an overlapping region 1271. The overlapping region 1271 corresponds to the non-opening region 220.

[0082] In this embodiment, the first pixel layer 127 is disposed corresponding to the opening region 210, meaning that in the stacking direction of the first substrate 110 and the driving layer 120, the coverage area of ​​the first pixel layer 127 is larger than the opening region 210, so as to ensure sufficient light emission from the first pixel layer 127. The overlapping region 1271 is disposed corresponding to the non-opening region 220, meaning that in the stacking direction of the first substrate 110 and the driving layer 120, the overlapping region 1271 at least partially covers the non-opening region 220, so as to shield the driving unit 121.

[0083] In this embodiment, the overlapping region 1271 is provided corresponding to the non-opening region 220 to at least partially block the driving unit 121, thereby providing a light-shielding effect for the driving unit 121. Furthermore, since the overlapping region 1271 can provide a light-shielding effect without the need for a black matrix (BM), the manufacturing process of the display panel 10 is reduced, and there is no need to align the BM with the non-opening region 220 during the assembly of the display panel 10, thereby improving the assembly efficiency of the display panel 10.

[0084] Please refer to Figure 3 , Figure 5 and Figure 10 , Figure 10 for Figure 2 This is a partial structural diagram of the display panel after a cross-section along line AA in Embodiment 3. In this embodiment, the display panel 10 further includes a second substrate 300. The second substrate 300 is stacked with the first substrate 100 at intervals, and the second substrate 300 is disposed on the side of the first substrate 110 that carries the driving layer 120. The second substrate 300 includes a second substrate 310, a plurality of second pixel layers 320, and a light-shielding layer 330. The plurality of second pixel layers 320 are spaced apart on the surface of the second substrate 310 facing the first substrate 100 and are disposed corresponding to the opening region 210. The light-shielding layer 330 is disposed between two adjacent second pixel layers 320.

[0085] In this embodiment, the second pixel layer 320 is disposed on the second substrate 310, and the second pixel layer 320 is disposed corresponding to the opening region 210. This means that in the stacking direction of the first substrate 100 and the second substrate 300, the size of the second pixel layer 320 is larger than the size of the opening region 210 to ensure sufficient light emission from the second pixel layer 320. The light-shielding layer 330 is disposed between two adjacent second pixel layers 320, blocking the area between the second pixel layers 320 and the edge area outside the second pixel layers 320, thus blocking the driving unit 121 in the non-opening region 220 to prevent the driving unit 121 from being observed from the outside of the display panel 10. The light-shielding layer 330 is also referred to as BM, and the second substrate 310 can be referred to as a color filter (CF) substrate.

[0086] Please refer to Figure 11 , Figure 11 for Figure 3 A schematic diagram illustrating the spacing between the pixel electrode and the common electrode. In this embodiment, the pixel electrode 124 includes a plurality of second pixel electrodes 1242. The common electrode 125 includes a plurality of second common electrodes 1252. The spacing between each second pixel electrode 1242 and its adjacent second common electrode 1252 is the same and is a first spacing d1. The spacing between the first pixel electrode 1241 and the first common electrode 1251 is a second spacing d2. The second spacing d2 is greater than the first spacing d1, and the minimum value of the second spacing d2 is 4μm to 5μm.

[0087] In this embodiment, the first spacing d1 between the second pixel electrode 1242 and the adjacent second common electrode 1252 is the same, so that a uniform electric field can be formed within the opening region 210. The minimum value of the second spacing d2 between the first pixel electrode 1241 and the first common electrode 1251 is 4μm to 5μm to satisfy the storage capacitance between the first pixel electrode 1241 and the first common electrode 1251. For example, the minimum value of the second spacing d2 can be, but is not limited to, 4μm, 4.2μm, 4.4μm, 4.6μm, 4.8μm, 5.0μm, or other values ​​between 4μm and 5μm. If the minimum value of the second spacing d2 is less than 4μm, it will result in an excessively large storage capacitance between the first pixel electrode 1241 and the first common electrode 1251; if the minimum value of the second spacing d2 is greater than 5μm, it will easily result in an excessively small storage capacitance between the first pixel electrode 1241 and the first common electrode 1251. Therefore, the minimum value of the second spacing d2 is 4μm to 5μm, which can satisfy the storage capacitance between the first pixel electrode 1241 and the first common electrode 1251.

[0088] This application also provides an electronic device 1. Please refer to... Figure 12 , Figure 12 This is a schematic diagram of the structure of an electronic device provided according to one embodiment of this application. In this embodiment, the electronic device 1 includes a display panel 10 as described in any of the foregoing embodiments.

[0089] In this embodiment, the electronic device 1 is a display device, such as a mobile phone, tablet computer, laptop computer, handheld computer, PC, PDA, etc.

[0090] In this embodiment, the electronic device 1 has a good display effect and high product quality because the display panel 10 has a high aperture ratio and sufficient storage capacitance.

[0091] Optionally, the electronic device 1 further includes a mid-frame, a power supply, and a back cover. One side of the mid-frame houses the display panel 10, and the other side houses the power supply. The power supply is electrically connected to the display panel 10 to provide power to the display panel 10. The back cover cooperates with the mid-frame to seal the power supply. Alternatively, the electronic device 1 further includes a base frame connected to the display panel 10 to support it. Alternatively, the electronic device 1 further includes a hook connected to the display panel 10 to hang it on a fixed surface (e.g., a wall, cabinet, etc.). The electronic device 1 may also have other structures, which are not limited here.

[0092] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application, and such improvements and refinements are also considered to be within the protection scope of this application.

Claims

1. A display panel, comprising a first substrate, characterized in that, The first substrate includes a first substrate and a driving layer, the driving layer being supported on the surface of the first substrate, the driving layer comprising: A driving unit, wherein the driving unit is mounted on the first substrate; A second insulating layer covers the drive unit; A conductive layer is disposed on the surface of the second insulating layer opposite to the first substrate. A passivation layer covering the conductive layer, the passivation layer having a first via; A pixel electrode, wherein the pixel electrode is disposed on the passivation layer and is electrically connected to the driving unit; and A common electrode is disposed on the passivation layer, electrically connected to the conductive layer through the first via, and spaced apart from the pixel electrode. The common electrode and the pixel electrode form a storage capacitor. The display panel includes multiple pixel areas, each pixel area corresponds to one driving unit, and different pixel areas correspond to different driving units. The pixel area includes an open area and a non-open area. The pixel electrode includes a first pixel electrode and a second pixel electrode, wherein the first pixel electrode and a portion of the driving unit are disposed in the non-opening region, and the second pixel electrode is disposed in the opening region; The common electrode includes a first common electrode and a second common electrode, wherein the first common electrode and the conductive layer are disposed in the non-opening region, and the second common electrode is disposed in the opening region; In each of the opening regions, the pixel electrode includes a plurality of second pixel electrodes, and the common electrode includes a plurality of second common electrodes. The distance between each second pixel electrode and the adjacent second common electrode is the same and is a first distance. The distance between the first pixel electrode and the first common electrode is a second distance, which is greater than the first distance.

2. The display panel as described in claim 1, characterized in that, The driving unit includes: A gate, wherein the gate is disposed on the surface of the first substrate. A first insulating layer covers the gate; A channel layer is disposed on the first insulating layer and corresponding to the gate; The source and the drain are disposed at a distance from each other in the channel layer; The second insulating layer covers the source electrode, the drain electrode, and the channel layer. The second insulating layer has a second via, and the second via passes through the passivation layer. A portion of the first pixel electrode and the second pixel electrode are located in the second via and are electrically connected to the drain electrode. The passivation layer is disposed on the surface of the second insulating layer away from the first substrate. The passivation layer includes a first passivation portion located in the non-opening region and a second passivation portion located in the opening region. The first passivation portion has a first surface away from the first substrate, and the second passivation portion has a second surface away from the first substrate. The first surface is away from the first substrate relative to the second surface, and the height difference between the first surface and the second surface is the thickness of the conductive layer.

3. The display panel as described in claim 2, characterized in that, The portion of the conductive layer facing the second via has a first slope, and the portion of the passivation layer defining the second via has a second slope, wherein the inclination angle of the first slope is equal to the inclination angle of the second slope.

4. The display panel as described in claim 2, characterized in that, The second via includes: The first sub-via penetrates the passivation layer; The second sub-hole is connected to the first sub-hole, and the angle of the second sub-hole is smaller than the angle of the first sub-hole. The second sub-hole passes through a portion of the second insulating layer. A third sub-hole is connected to the second sub-hole, and the angle of the third sub-hole is smaller than that of the second sub-hole. The third sub-hole passes through another portion of the second insulating layer to expose the drain electrode.

5. The display panel as described in claim 4, characterized in that, The inner diameter of the third sub-hole at the connection point with the second sub-hole is smaller than the inner diameter of the second sub-hole at the connection point with the first sub-hole; The second insulating layer has a gently sloping wall at the junction of the second sub-hole and the third sub-hole, the inclination angle of the gently sloping wall being smaller than the inclination angle of the inner wall of the second sub-hole defined by the second insulating layer.

6. The display panel as described in claim 2, characterized in that, The driver layer also includes: A first pixel layer is disposed within the second insulating layer and corresponds to the opening area; In two adjacent driving layers, the two adjacent first pixel layers have an overlapping area, and the overlapping area corresponds to the non-opening area.

7. The display panel as described in claim 2, characterized in that, The display panel further includes a second substrate, which is stacked with the first substrate at a distance, and the second substrate is disposed on the side of the first substrate that carries the driving layer. The second substrate includes: Second substrate; A plurality of second pixel layers, the plurality of second pixel layers being spaced apart on the surface of the second substrate facing the first substrate, and being disposed corresponding to the opening region; and A light-shielding layer is disposed between two adjacent second pixel layers.

8. The display panel as described in claim 1, characterized in that, The minimum value of the second spacing is 4μm~5μm.

9. An electronic device, characterized in that, The electronic device includes a display panel as described in any one of claims 1-8.

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