Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a light emitting element, a pixel circuit and a peripheral driving circuit, the pixel circuit comprising at least a driving module, a first reset module and a compensation module; the peripheral driving circuit provides a circuit signal to the pixel circuit; the display panel comprises at least a power-on stage and a display stage in sequence in a working process, the power-on stage comprising at least a first stage and a second stage in sequence, the power-on stage comprising a plurality of continuous frames, in at least some frames of the power-on stage, the peripheral driving circuit provides a first control signal to a control end of the first reset module, the first reset module is turned on, the peripheral driving circuit provides a second control signal to a control end of the compensation module, and the compensation module is turned on; in the second stage, the peripheral driving circuit provides a first power voltage to a first power voltage signal end and / or a second power voltage to a second power voltage signal end. The display panel improves the problem of power-on flicker.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess characteristics such as self-illumination, fast response, wide color gamut, wide viewing angle, and high brightness. They can be used to fabricate thin and flexible display devices, and are thus gradually becoming a key research focus in the field of display technology. OLEDs require current to drive them. In display applications, driving transistors in the pixel circuit are controlled to provide driving current to the OLEDs, enabling them to emit light. Furthermore, a stable driving current is needed to ensure display performance during application.

[0003] In the prior art, the signal driving the pixel circuit is provided by the peripheral circuit. When the display starts after power-on, the organic light-emitting diode flickers.

[0004] Therefore, there is an urgent need to provide a display panel and display device that can prevent organic light-emitting diodes from flickering upon power-up. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device for improving power-on flicker of light-emitting elements and reducing power consumption of the display panel.

[0006] On one hand, this embodiment provides a display panel, including: a light-emitting element; a pixel circuit, the pixel circuit including at least a driving module, a first reset module, and a compensation module, the driving module and the light-emitting element being connected in series between a first power supply voltage signal terminal and a second power supply voltage signal terminal, wherein the driving module is used to generate a driving current to drive the light-emitting element to emit light; the first reset module is electrically connected to the control terminal of the driving module and is used to initialize the control terminal of the driving module; the compensation module is connected in series between the control terminal and the output terminal of the driving module to compensate the potential of the control terminal of the driving module; and a peripheral driving circuit that provides circuit signals to the pixel circuit.

[0007] The display panel operates by at least a sequential power-on phase and a display phase. The power-on phase includes at least a sequential first phase and a second phase, and includes multiple consecutive frames. During at least some frames of the power-on phase, the peripheral driving circuit provides a first control signal to the control terminal of the first reset module, turning on the first reset module. The peripheral driving circuit also provides a second control signal to the control terminal of the compensation module, turning on the compensation module. In the second phase, the peripheral driving circuit provides a first power supply voltage to the first power supply voltage signal terminal and / or a second power supply voltage to the second power supply voltage signal terminal.

[0008] On the other hand, the present invention also provides a display device including the above-described display panel.

[0009] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0010] The display panel of this invention includes an electrically connected pixel circuit and a light-emitting element. The pixel circuit controls the light-emitting element to emit light. The pixel circuit includes at least a driving module, a first reset module, and a compensation module. The driving module and the light-emitting element are connected in series between a first power supply voltage signal terminal and a second power supply voltage signal terminal. The driving module generates a driving current to drive the light-emitting element to emit light. The first reset module is electrically connected to the control terminal of the driving module and is used to initialize the control terminal of the driving module. The compensation module is connected in series between the control terminal and the output terminal of the driving module to compensate for the potential of the control terminal of the driving module. The compensation module detects and compensates for the deviation of the threshold voltage of the driving module and provides the compensated threshold voltage deviation to the driving module to achieve threshold compensation of the driving module. Since the driving module and the light-emitting element are connected in series between the first power supply voltage signal terminal and the second power supply voltage signal terminal, when the pixel circuit drives the electrically connected light-emitting element to emit light, the driving module generates a driving current to drive the light-emitting element to emit light through the conductive path between the first power supply voltage signal terminal, the driving module, the light-emitting element, and the second power supply voltage signal terminal, thereby achieving the light-emitting effect of the light-emitting element. The peripheral driving circuit of this invention provides circuit signals to the pixel circuit. Since the first power supply voltage of the first power supply voltage signal terminal was connected to the first terminal of the driving module during the previous display, positive charge accumulated at the first terminal of the driving module, and this charge is stored on the parasitic capacitance. When the first control signal controls the first reset module to turn on and the second control signal controls the compensation module to turn on, the driving module turns on because Vgs < Vth. At the same time, the residual charge is released until the driving module turns off. Subsequently, in the early stage of the display phase, since the residual charge has been released during the power-on phase, the light-emitting element will not flicker.

[0011] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0012] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0014] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention;

[0015] Figure 2 yes Figure 1 A schematic diagram of the circuit connection structure of a neutron pixel;

[0016] Figure 3 This is a timing diagram of the pixel circuit in related technologies;

[0017] Figure 4 yes Figure 2 Timing diagram of the middle pixel circuit;

[0018] Figure 5 yes Figure 2 Another timing diagram of the mid-pixel circuit;

[0019] Figure 6 yes Figure 2 Another timing diagram of the mid-pixel circuit;

[0020] Figure 7 yes Figure 2 Another timing diagram of the mid-pixel circuit;

[0021] Figure 8 This is a timing diagram of a display stage provided by the present invention;

[0022] Figure 9 yes Figure 2 Another timing diagram of the mid-pixel circuit;

[0023] Figure 10 yes Figure 9 A magnified view of a portion of region M in the middle;

[0024] Figure 11 yes Figure 2 Another timing diagram of the mid-pixel circuit;

[0025] Figure 12 yes Figure 2 Another timing diagram of the mid-pixel circuit;

[0026] Figure 13 yes Figure 1A schematic diagram of another circuit connection structure for neutron pixels;

[0027] Figure 14 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels;

[0028] Figure 15 yes Figure 14 Timing diagram of the middle pixel circuit;

[0029] Figure 16 yes Figure 14 Another timing diagram of the mid-pixel circuit;

[0030] Figure 17 This is a schematic diagram of the planar structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0031] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0032] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0033] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0034] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0036] Reference Figure 1 , Figure 2 , Figure 4 and Figure 5 , Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of the circuit connection structure of a neutron pixel. Figure 4 yes Figure 2 Timing diagram of the mid-pixel circuit. Figure 5 yes Figure 2Another timing diagram of the pixel circuit is provided in this embodiment. A display panel 100 is provided, including: a light-emitting element 20; a pixel circuit 10, which includes at least a driving module 101, a first reset module 102, and a compensation module 103. The driving module 101 and the light-emitting element 20 are connected in series between a first power supply voltage signal terminal PVDD and a second power supply voltage signal terminal PVEE. The driving module 101 generates a driving current to drive the light-emitting element 20 to emit light. The first reset module 102 is electrically connected to the control terminal of the driving module 101 and is used to initialize the control terminal of the driving module 101. The compensation module 103 is connected in series between the control terminal and the second terminal of the driving module 101 to compensate for the potential of the control terminal of the driving module 101. An external driving circuit 30 provides driving signals to the pixel circuit 10.

[0037] The display panel 100 includes at least a sequential power-on phase T1 and a display phase T2 during operation. The power-on phase T1 includes at least a sequential first phase T11 and a second phase T12. The power-on phase T1 includes multiple consecutive frames. In at least some frames of the power-on phase T1, the peripheral driving circuit 30 provides a first control signal S1 to the control terminal of the first reset module 102, and the first reset module 102 is turned on. The peripheral driving circuit 30 provides a second control signal S2 to the control terminal of the compensation module 103, and the compensation module 103 is turned on. In the second phase T12, the peripheral driving circuit 30 provides a first power supply voltage VPvdd to the first power supply voltage signal terminal PVDD and / or provides a second power supply voltage VPvee to the second power supply voltage signal terminal PVEE. Figure 4 STV_S1 is the trigger signal for the first control signal S1, and STV_S2 is the trigger signal for the second control signal S2.

[0038] Specifically, the display panel 100 provided in this embodiment can be an organic light-emitting display panel 100, or it can be any other display panel 100 that provides a driving current to the light-emitting element 20 by controlling the driving module 101 in the pixel circuit 10 to emit light. The light-emitting element 20 in this embodiment can be an organic light-emitting diode, or in some other optional embodiments, the light-emitting element 20 can also be a micro light-emitting diode or a sub-millimeter light-emitting diode. This embodiment does not limit this. This embodiment takes an organic light-emitting diode display panel 100 as an example for illustration.

[0039] The display panel 100 in this embodiment includes a plurality of sub-pixels 00. Optionally, the plurality of sub-pixels 00 in this embodiment can be arranged in an array, that is, the plurality of sub-pixels 00 are arranged along a first direction X to form a row of sub-pixels 00, the plurality of sub-pixel 00 rows are arranged along a second direction Y, the plurality of sub-pixels 00 are arranged along the second direction Y to form a column of sub-pixels 00, and the plurality of sub-pixel 00 columns are arranged along the first direction X to form an array-arranged sub-pixel 00 structure; wherein the first direction X and the second direction Y can be understood as intersecting or perpendicular to each other in a direction parallel to the plane on which the display panel 100 is located. Alternatively, in some other optional embodiments, the plurality of sub-pixels 00 can also be arranged in other ways, which is not limited in this embodiment. Figure 1 This example illustrates the concept using an array of multiple sub-pixels 00. The sub-pixels 00 form a pixel row in the first direction X, and the display panel scans these pixel rows one by one during operation.

[0040] Sub-pixel 00 may include an electrically connected pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 is used to control the light-emitting element 20 to emit light. Since the light-emitting element 20 in the organic light-emitting diode display panel 100 can generally be an organic light-emitting diode, and organic light-emitting diodes are current-driven devices, a corresponding pixel circuit 10 needs to be set to provide driving current to the light-emitting element 20 so that the light-emitting element 20 can emit light. In this embodiment, the pixel circuit 10 includes at least a driving module 101, a first reset module 102, and a compensation module 103.

[0041] The driving module 101 and the light-emitting element 20 are connected in series between the first power supply voltage signal terminal PVDD and the second power supply voltage signal terminal PVEE. Optionally, the driving module 101 may include a driving transistor M0. The first terminal of the driving transistor M0 is electrically connected to the first power supply voltage signal terminal PVDD, and the second terminal of the driving transistor M0 is electrically connected to the second power supply voltage signal terminal PVEE. The driving transistor M0 is used to generate a driving current. The first terminal of the driving transistor M0 can be understood as the source of the driving transistor M0, and the second terminal of the driving transistor M0 can be understood as the drain of the driving transistor M0. Alternatively, the first terminal of the driving transistor M0 can be understood as the drain of the driving transistor M0, and the second terminal of the driving transistor M0 can be understood as the source of the driving transistor M0. This embodiment does not limit this. The gate of the driving transistor M0 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3.

[0042] The first reset module 102 is electrically connected to the control terminal of the drive module 101 and is used to initialize the control terminal of the drive module 101. When the first reset module 102 is turned on, the potential of the control terminal of the drive module 101 is the reset signal VREF input by the first reset module 102, which resets the control terminal of the drive module 101, thereby facilitating the turn-on of the drive module 101 during threshold compensation. Optionally, the first reset module 102 may include a first transistor M1. The gate of the first transistor M1 is input to the first control signal S1, the first terminal of the first transistor M1 is input to the reset signal VREF, and the second terminal of the first transistor M1 is electrically connected to the gate of the drive transistor M0. When the first transistor M1 is turned on, the reset signal VREF is input to the gate of the drive transistor M0, resetting the gate of the drive transistor M0, thereby facilitating the turn-on of the drive transistor M0 during threshold compensation.

[0043] The compensation module 103 is connected in series between the control terminal and the second terminal of the drive module 101 to compensate the potential of the control terminal of the drive module 101. Optionally, the compensation module 103 is used to detect and compensate the deviation of the threshold voltage of the drive transistor M0, and provide the compensated threshold voltage deviation to the drive transistor M0 to achieve threshold compensation of the drive transistor M0.

[0044] Figure 2 The illustration is based on the example of driving transistor M0 being a P-type transistor and first transistor M1 and second transistor M2 being N-type transistors. Of course, driving transistor M0 can also be an N-type transistor, and first transistor M1 and second transistor M2 can also be P-type transistors. No specific limitation is made here.

[0045] It should be noted that, in specific implementation, the connection structure of the pixel circuit 10 in this embodiment includes, but is not limited to, the above-described structure and driving timing, and may also be other connection structures and driving methods. This embodiment does not limit these.

[0046] Reference Figure 1The peripheral circuit 30 of this invention schematically includes a first gate driving circuit 301 and a second gate driving circuit 302. The driver chip IC sends a start signal STV_S1 to the first stage of the first gate driving circuit 301. The first gate driving circuit 301 can provide a first control signal S1 to the pixel circuit 10 step by step. The driver chip IC sends a start signal STV_S2 to the first stage of the second gate driving circuit 302. The second gate driving circuit 302 can provide a second control signal S2 to the pixel circuit 10 step by step. The peripheral driving circuit 30 also includes a third gate driving circuit 303. The driver chip IC sends a start signal STV_E to the first stage of the third gate driving circuit 303. The third gate driving circuit 303 can provide a third control signal E to the pixel circuit 10 step by step. Of course, the first power supply voltage VPvdd, the second power supply voltage VPvee, and the reset signal VREF are also provided by the driver chip IC. Figure 1 The diagram shows a first scan signal line 1, a second scan signal line 2, a reset signal line 3, a first power supply voltage signal line 5, and a third control signal line 4. The first scan signal line 1 is used to transmit the first control signal S1, the second scan signal line 2 is used to transmit the second control signal S2, the reset signal line 3 transmits the reset signal VREF, and the third control signal line 4 transmits the third control signal E. This is for illustrative purposes only. Figure 4 STV_E in the middle represents the trigger start signal of the third control signal E.

[0047] In related technologies, refer to Figure 3 , Figure 3 This is a timing diagram of the pixel circuit in the prior art. Figure 3 The display panel includes a power-on phase T01, a display phase T02, and a power-off phase T03. E is the third control signal, S is the fourth control signal controlling the data writing module to turn on, S1 is the first control signal, S2 is the second control signal, CK is the clock signal, VPvdd is the first power supply voltage, VPvee is the second power supply voltage, and VREF is the reset signal VREF. In the power-on phase T1, the first power supply voltage VPvdd and the second power supply voltage VPvee are provided in the later part of the power-on phase (near the display phase T2). In the display phase T2, multiple signals are simultaneously output to the pixel circuit 10, including the first control signal S1, the second control signal S2, the fourth control signal S, the third control signal E, the reset signal VREF, the first power supply voltage VPvdd, and the second power supply voltage VPvee. When the display panel is off, the previous frame's display image and static electricity can cause residual charge, resulting in screen flickering at the moment of power-on.

[0048] E is the third control signal, and S is the control data writing module. Figure 2 Not shown in the image, please refer to the image below. Figure 13The fourth control signal is activated. STV_S represents the trigger start signal for the fourth control signal S. S1 is the first control signal, S2 is the second control signal, CK is the clock signal, VPvdd is the first power supply voltage, VPvee is the second power supply voltage, and VREF is the reset signal. Figure 4 In the power-on phase T1, both the first stage T11 and the second stage T12 provide a first control signal S1 and a second control signal S2. This is illustrated using only the first control signal S1 as a pulse signal and the second control signal S2 as a high-level signal. Alternatively, the first control signal S1 and the second control signal S2 can be provided only in the second stage T12. Figure 5 As shown, Figure 5 The first control signal S1 and the second control signal S2 are only provided in the second stage T12, as long as they can control the first reset module 102 and the compensation module 103 to conduct in the power-on stage T1. It should be noted that the first control signal S1 and the second control signal S2 are high level here because the first transistor M1 and the second transistor M2 are N-type transistors, which conduct at a high potential. If the first transistor M1 and the second transistor M2 were P-type transistors, the first control signal S1 and the second control signal S2 would need to be low level.

[0049] In this invention, the power-on stage T1 precedes the display stage T2. The power-on stage T1 includes a first stage T11 and a second stage T12. In the first stage T11, the peripheral driving circuit 30 only provides the first control signal S1 to the control terminal of the first reset module 102 of the pixel circuit 10. Since the second node N2 is connected to the first power supply voltage signal terminal PVDD with the first power supply voltage VPvdd during the previous display, the second node N2 accumulates positive charge, which is stored on the parasitic capacitance. When the first control signal S1 controls the first reset module 102 to turn on and the second control signal S2 controls the compensation module 103 to turn on, since Vgs < Vth of the driving transistor M0, the driving transistor M0 turns on, and the residual charge is released until the driving transistor M0 turns off. Subsequently, in the early stage of the display stage T2, the light-emitting element 20 will not flicker.

[0050] Figure 4 In the middle, the second control signal S2 is continuously high, while the first control signal S1 is a pulse signal. After the first control signal S1 pulse signal turns off the first reset module 102 of the current row, since the compensation module 103 is still conducting, the residual charge can still be released to the storage capacitor Cst until the driving transistor M0 is turned off. Since the residual charge of the previous display screen has been released in the power-on stage T1, the light-emitting element 20 will not flicker in the early stage of the display stage T2.

[0051] In some alternative embodiments, refer to Figure 6 , Figure 6 yes Figure 2 Another working timing diagram of the mid-pixel circuit: during the power-on phase T1, the first control signal S1 is continuously active for at least a portion of the frame period, and the second control signal S2 is continuously active for at least a portion of the frame period.

[0052] In this embodiment, only N-type transistors as the first transistor M1 and the second transistor M2 are used as examples for illustrative purposes. Figure 6 In the power-on phase T1, the first control signal S1 remains high and the second control signal S2 remains high throughout the entire frame period. This is merely illustrative. Alternatively, the first control signal S1 and the second control signal S2 may remain high for only a portion of the frames in the power-on phase T1. When the first transistor M1 and the second transistor M2 are P-type transistors, the first control signal S1 remains low and the second control signal S2 remains low for at least a portion of the frame period in the power-on phase T1.

[0053] Figure 2 The first transistor M1 and the second transistor M2 are N-type transistors. When the first control signal S1 is high, the first reset module 102 is turned on. When the second control signal S2 is high, the compensation module 103 is turned on. The reset signal VREF is written to the control terminal of the drive module 101. Since Vgs < Vth of the drive transistor M0, the drive transistor M0 is turned on. The second control signal S2 is continuously high, and the compensation module 103 is turned on. Therefore, the residual charge is released to the storage capacitor Cst until the drive transistor M0 is turned off. The residual charge of the previous display screen has been released in the power-on stage T1. When entering the display stage T2, there will be no flickering problem.

[0054] Optionally, the first transistor M1 and the second transistor M2 are P-type transistors. When the first control signal S1 is low, the first reset module 102 is turned on. When the second control signal S2 is low, the compensation module 103 is turned on. The reset signal VREF is written to the control terminal of the drive module 101. Since Vgs < Vth of the drive transistor M0, the drive transistor M0 is turned on. The second control signal S2 is continuously high, and the compensation module 103 is turned on. Therefore, the residual charge is released to the storage capacitor Cst until the drive transistor M0 is turned off. In the power-on stage T1, the residual charge of the previous display screen has been released. When entering the display stage T2, there will be no flickering problem.

[0055] In this embodiment, during at least a portion of the frame period of the power-on phase T1, the first control signal S1 remains at an active level, and the second control signal S2 remains at an active level. Therefore, during this portion of the frame period of the power-on phase T1, it is equivalent to all pixel rows undergoing electrostatic discharge simultaneously, which consumes less time than electrostatic discharge performed row by row, resulting in higher electrostatic discharge efficiency. For example, if the display panel includes 2000 pixel rows, and electrostatic discharge is performed row by row, the total discharge time would be k1. However, in this embodiment, with both the first control signal S1 and the second control signal S2 remaining active, all 2000 pixel rows undergo electrostatic discharge simultaneously, reducing the total discharge time to only 1 / 2000k1, significantly shortening the discharge time and improving the discharge efficiency.

[0056] In some alternative embodiments, refer to Figure 7 , Figure 7 yes Figure 2 Another working timing diagram of the mid-pixel circuit: during the power-on phase, in the n consecutive frames, the first control signal S1 in the i-th frame is continuously at an active level, and the second control signal S2 is continuously at an inactive level; in the (i+1)-th frame, both the first control signal S1 and the second control signal S2 are continuously at active levels, where n is a positive integer greater than or equal to 2, i is a positive integer, and i is less than or equal to n-1.

[0057] In this embodiment, only N-type transistors as the first transistor M1 and the second transistor M2 are used as examples for illustrative purposes. Figure 7 In the power-on phase T1, which consists of 6 frames, the first control signal S1 remains high during the 3rd frame, the second control signal S2 remains low during frames 1 to 3, and both the first and second control signals S1 remain high during the 4th frame. That is, the second control signal S2 starts being high after the first control signal S1 is high. Figure 7 The number of frames in the power-on phase T1 is for illustrative purposes only.

[0058] It should be noted that these consecutive n frames can be continuous with display phase T2, meaning display phase T2 is after the nth frame, or they can be discontinuous with display phase T2. This is sufficient as long as the static electricity from the previous displayed image is released during power-on phase T1 to prevent flickering at the beginning of display phase T2.

[0059] Understandable, Figure 7In the i-th frame, the first control signal S1 is high, at which time the first reset module 102 is turned on, the reset signal VREF is written to the control terminal of the drive module 101, the reset signal VREF is high, the drive module 101 is turned on, the compensation module 103 is not turned on in the i-th frame, the second control signal S2 is high in the i+1-th frame, the compensation module 103 is turned on. Since the first reset module 102 has been in the turned-on state since the i-th frame, the drive module 101 is also in the turned-on state. Therefore, when the compensation module 103 is turned on, the residual charge is released to the storage capacitor Cst until the drive transistor M0 is turned off. In the power-on stage T1, the residual charge of the previous display screen has been released.

[0060] This embodiment not only enables electrostatic discharge during the power-on phase T1 to prevent flickering of the light-emitting element 20 in the early stage of the display phase T2, but also ensures that the first control signal S1 is continuously active and the second control signal S2 is continuously inactive in the i-th frame; and that both the first control signal S1 and the second control signal S2 are continuously active in the (i+1)-th frame, thus reducing the load. It is understood that if the first control signal S1 and the second control signal S2 simultaneously control the first reset module 102 and the compensation module 103 to conduct, it would be equivalent to simultaneously releasing the charge stored in the first node N1 capacitor, and also releasing the residual charge of the parasitic capacitors of the second node N2 and the third node N3. In this embodiment, the first reset module 102 is first activated by the first control signal S1, and then the compensation module 103 is activated by the second control signal S2. This is equivalent to first releasing only the charge stored in the first node N1 capacitor, and then releasing the residual charge of the second node N2 and the third node N3, thus reducing the load problem after simultaneously activating all pixel rows.

[0061] In some alternative embodiments, reference continues to be made to... Figure 4 During the power-on phase, the second control signal S2 remains active, the first control signal S1 is a pulse signal, and the peripheral drive circuit 30 transmits the pulse signal line by line to the control terminal of the first reset module 102.

[0062] In this embodiment, only N-type transistors as the first transistor M1 and the second transistor M2 are used as examples for illustrative purposes. Figure 4The first control signal S1 is a pulse signal, while the second control signal S2 is continuously high. The peripheral driving circuit 30 transmits pulse signals line by line to the control terminal of the first reset module 102. It can be understood that the pulse signal will have a part of high potential signal. When the pulse signal is a valid pulse, the first reset module 102 is turned on, and the reset signal VREF is written to the control terminal of the driving module 101 to perform electrostatic discharge on the first node N1. When the reset signal VREF is high, the driving module 101 is turned on, and the second control signal S2 is high. When the compensation module 103 is turned on, electrostatic discharge is performed on the second node N2 and the third node N3 to prevent the light-emitting element 20 from flickering in the early stage of the display phase T2.

[0063] Optionally, when the first transistor M1 and the second transistor M2 are P-type transistors, the first control signal S1 is a pulse signal, and the effective pulse is low level, while the second control signal S2 can remain low level, which will not be elaborated here.

[0064] During the power-on phase T1, the first control signal S1 is a pulse signal, which allows for electrostatic discharge of the first node N1 row by row, resulting in a relatively small instantaneous load on the reset signal VREF. Because the reset signal VREF is transmitted row by row in the subsequent display phase T2, it does not require a large load capacity. If electrostatic discharge were performed on the first node N1 of all pixel rows simultaneously during the power-on phase T1, the reset signal VREF would require a very strong load capacity, thus occupying a significant amount of space in the driver chip IC.

[0065] In some alternative embodiments, reference continues to be made to... Figure 1 , Figure 2 and Figure 4 During the display phase T2, the peripheral driving circuit 30 provides the first display control signal 3 to the control terminal of the first reset module 102;

[0066] During the power-on phase T1, the effective pulse width of the first control signal S1 is equal to the effective pulse width of the first display control signal 3.

[0067] Reference Figure 8 , Figure 8 This is a timing diagram of a display stage provided by the present invention. The display stage T2 may include a reset stage, a data writing stage and a light emission stage. At this time, the peripheral driving circuit 30 still inputs the first display control signal 3 to the control terminal of the first reset module 102. The first display control signal 3 is also a pulse signal, which ensures that the first reset module 102 is turned on to reset the control terminal of the driving module 101 when the pulse signal is in a valid pulse.

[0068] In this embodiment, the effective pulse width of the first control signal S1 in the power-on stage T1 is equal to the effective pulse width of the first display control signal 3. In this way, the first control signal S1 provided by the peripheral driving circuit 30 is the same, and there is no need to switch or change the first control signal S1 in the power-on stage T1 and the first display control signal 3 in the display stage T2. This can reduce the working pressure of the driver chip IC and reduce power consumption.

[0069] In some alternative embodiments, refer to Figure 9 , Figure 9 yes Figure 2 Another working timing diagram of the mid-pixel circuit: the first control signal S1 is the first pulse signal 1, and the second control signal S2 is the second pulse signal 2; the peripheral driving circuit 30 transmits the first pulse signal 1 to the control terminal of the first reset module 102 line by line, and the peripheral driving circuit 30 transmits the second pulse signal 2 to the control terminal of the compensation module 103 line by line. The effective pulses of the first pulse signal 1 and the effective pulses of the second pulse signal 2 at least partially overlap.

[0070] Figure 9 In this embodiment, both the first control signal S1 and the second control signal S2 are pulse signals. Specifically, the first control signal S1 is a first pulse signal 1, and its effective pulse controls the first reset module 102 to turn on. The reset signal VREF is written to the control terminal of the drive module 101, and when VREF is high, the drive module 101 is turned on. The second control signal S2 is a second pulse signal 2, and its effective pulse controls the compensation module 103 to turn on. In this embodiment, the effective pulses of the first pulse signal 1 and the second pulse signal 2 overlap. The start time of the effective pulse of the second pulse signal 2 is between the start and end times of the effective pulse of the first pulse signal 1, and the end time of the effective pulse of the second pulse signal 2 is after the end time of the effective pulse of the first pulse signal 1. Furthermore, the end time of the effective pulse of the first pulse signal 1 is between the start and end times of the effective pulse of the second pulse signal 2.

[0071] In this embodiment, the effective pulses of the first pulse signal 1 and the second pulse signal 2 overlap at least partially. After the effective pulse of the first pulse signal 1 is transmitted to the first reset module 102, the first reset module 102 is turned on to release the electrostatic discharge of the first node N1. Then, before the effective pulse of the first pulse signal 1 stops, the effective pulse of the second pulse signal 2 is transmitted to the compensation module 103. The compensation module 103 is turned on to release the electrostatic discharge of the second node N2 and the third node N3, preventing the light-emitting element 20 from flickering in the early stage of the display phase T2.

[0072] In this embodiment, during the power-on phase T1, both the first control signal S1 and the second control signal S2 are pulse signals. The fact that both the first and second control signals S1 and S2 are pulse signals allows for electrostatic discharge of the first node N1, second node N2, and third node N3 row by row, resulting in a relatively small instantaneous load on the reset signal VREF. Because the reset signal VREF is transmitted row by row in the subsequent display phase T2, it does not require a large load capacity. If electrostatic discharge were performed on the first node N1 of all pixel rows simultaneously during the power-on phase T1, the reset signal VREF would require a very strong load capacity, occupying a significant amount of space in the driver chip IC. The signal is high only during valid pulses and low during invalid pulses, saving power during the invalid pulse period.

[0073] Of course, in this embodiment, the start time of the effective pulse of the second pulse signal 2 is located between the start time and the end time of the effective pulse of the first pulse signal 1. First, the first control signal S1 controls the first reset module 102 to be turned on, and then the second control signal S2 controls the compensation module 103 to be turned on. This is equivalent to releasing the charge of the storage capacitor of the first node N1 first, and then releasing the residual charge of the second node N2 and the third node N3. This can reduce the load problem after all pixel rows are turned on at the same time. If the first control signal S1 and the second control signal 2 control the first reset module 102 and the compensation module 103 to be turned on at the same time, it is equivalent to releasing the charge of the storage capacitor of the first node N1 at the same time, and also releasing the residual charge of the parasitic capacitors of the second node N2 and the third node N3.

[0074] In some alternative embodiments, reference continues to be made to... Figure 9 and reference Figure 10 , Figure 10 yes Figure 9 A magnified view of the M region shows that during the power-on phase T1, the effective pulse width of the first pulse signal 1 and the time during which the effective pulse width of the second pulse signal 2 overlap are t1.

[0075] During the display phase T2, the peripheral driving circuit 30 provides a first display control signal 3 to the control terminal of the first reset module 102, and the peripheral driving circuit 30 provides a second display control signal 4 to the control terminal of the compensation module 103. During the display phase T2, the time during which the effective pulse width of the second display control signal 4 overlaps with the pulse width of the first display control signal 3 is t2.

[0076] Where t1 = t2.

[0077] During the power-on phase T1, the effective pulses of the first pulse signal 1 and the second pulse signal 2 overlap. The start time of the effective pulse of the second pulse signal 2 is between the start time and the end time of the effective pulse of the first pulse signal 1, and the end time of the effective pulse of the second pulse signal 2 is after the end time of the effective pulse of the first pulse signal 1. The end time of the effective pulse of the first pulse signal 1 is between the start time and the end time of the effective pulse of the second pulse signal 2. The overlap time between the effective pulse width of the first pulse signal 1 and the effective pulse width of the second pulse signal 2 is t1.

[0078] During the display phase T2, the start time of the effective pulse of the second display control signal 4 is between the start time and the end time of the effective pulse of the first display control signal 3, and the end time of the effective pulse of the first display control signal 3 is between the start time and the end time of the effective pulse of the second display control signal 4. The effective pulse width of the second display control signal 4 and the time during which it overlaps with the pulse width of the first display control signal 3 is t2.

[0079] In this embodiment, t1 = t2, so the first display control signal 3 and the first pulse signal 1 provided by the peripheral driving circuit 30 are the same, and the second display control signal 4 and the second pulse signal 2 provided by the peripheral driving circuit 30 are the same. There is no need to change the first pulse signal 1 in the power-on stage T1 and the first display control signal 3 in the display stage T2, nor is there need to change the second pulse signal 2 in the power-on stage T1 and the second display control signal 4 in the display stage T2. This can reduce the working pressure of the driver chip IC and reduce power consumption.

[0080] Of course, in the display stage T2, the start time of the effective pulse of the second display control signal 4 is located between the start time and the end time of the effective pulse of the first display control signal 3. In the display stage T2, the first reset module 102 is first turned on by the first display control signal 3, and then the compensation module 103 is turned on by the second display control signal 4. This is equivalent to resetting the first node N1 first, and then resetting the second node N2 and the third node N3. This can reduce the load problem after all pixel rows are turned on at the same time. If the first display control signal 3 and the second display control signal 4 simultaneously turn on the first reset module 102 and the compensation module 103, then it is equivalent to resetting the first node N1 at the same time, and also resetting the second node N2 and the third node N3.

[0081] In some alternative embodiments, reference continues to be made to... Figure 11 , Figure 11 yes Figure 2Another working timing diagram of the mid-pixel circuit: the first control signal S1 is the first pulse signal 1, and the second control signal S2 is the second pulse signal 2; the peripheral driving circuit 30 transmits the first pulse signal 1 to the control terminal of the first reset module 102 line by line, and the peripheral driving circuit 30 transmits the second pulse signal 2 to the control terminal of the compensation module 103 line by line. In each frame, the start time of the effective pulse of the second pulse signal 2 is located after the end time of the effective pulse of the first pulse signal 1.

[0082] Figure 11 In the process, the effective pulses of the first pulse signal 1 and the second pulse signal 2 do not overlap. The start time of the effective pulse of the second effective signal is after the end time of the effective pulse of the first pulse signal 1. Thus, the first pulse signal 1 and the second pulse signal 2 do not overlap. When the first pulse signal 1 is an effective pulse, the first reset module 102 is turned on, and the reset signal VREF is written to the control terminal of the drive module 101. The reset signal VREF is high (effective level), and the drive module 101 is turned on. When the first pulse signal 1 is an effective pulse, the second pulse signal 2 is an ineffective pulse. After the effective pulse of the first pulse signal 1 ends, the second pulse signal 2 becomes an effective pulse, and the compensation module 103 is turned on.

[0083] On one hand, during the power-on phase T1, both the first control signal S1 and the second control signal S2 are pulse signals. The fact that both S1 and S2 are pulse signals allows for electrostatic discharge of the first node N1, second node N2, and third node N3 row by row, resulting in a relatively small instantaneous load on the reset signal VREF. Because the reset signal VREF is transmitted row by row in the subsequent display phase T2, it doesn't require a large load capacity. If electrostatic discharge were performed on the first node N1 of all pixel rows simultaneously during power-on phase T1, the reset signal VREF would require a very strong load capacity, occupying a significant amount of space in the driver chip IC. The signal is high only during valid pulses and low during invalid pulses, saving power during the invalid pulse period.

[0084] On the other hand, in each frame of the power-on phase T1, the start time of the effective pulse of the second pulse signal 2 is after the end time of the effective pulse of the first pulse signal 1. In this embodiment, the first reset module 102 is first turned on by the first control signal S1, and the compensation module 103 is turned on by the second control signal S2. This is equivalent to releasing the charge of the storage capacitor of the first node N1 first, and then releasing the residual charge of the second node N2 and the third node N3. This can reduce the load problem after all pixel rows are turned on at the same time. If the first control signal S1 and the second control signal 2 simultaneously turn on the first reset module 102 and the compensation module 103, it is equivalent to releasing the charge of the storage capacitor of the first node N1 at the same time, and also releasing the residual charge of the parasitic capacitors of the second node N2 and the third node N3.

[0085] In some alternative embodiments, reference continues to be made to... Figure 11 During the display stage T2, the peripheral driving circuit 30 provides a first display control signal 3 to the control terminal of the first reset module 102, and the peripheral driving circuit 30 provides a second display control signal 4 to the control terminal of the compensation module 103.

[0086] The pulse width of the first pulse signal 1 in the power-on phase T1 is equal to the pulse width of the first display control signal 3 in the display phase T2;

[0087] The pulse width of the second pulse is equal to the pulse width of the second display control signal 4S2 in the display stage T2.

[0088] During the display phase T2, when one frame ends and the next frame begins, the drive module 101 also needs to be reset. At this time, the peripheral drive circuit 30 still inputs the first display control signal 3 to the control terminal of the first reset module 102 and provides the second display control signal 4 to the control terminal of the compensation module 103. The first display control signal 3 and the second display control signal 4 are also pulse signals, ensuring that the first reset module 102 and the compensation module 103 are turned on when the pulse signal is at a high potential, and the control terminal, the first terminal and the second terminal of the drive module 101 are reset.

[0089] In this embodiment, the effective pulse width of the first pulse signal 1 in the power-on stage T1 is equal to the pulse width of the first display control signal 3 in the display stage T2, and the pulse width of the second pulse signal 2 is equal to the pulse width of the second display control signal 4 in the display stage T2. In this way, the first pulse signal 1 and the first display control signal 3 provided by the peripheral driving circuit 30 are the same, and the second pulse signal 2 and the second display control signal 4 are the same. There is no need to change the first pulse signal 1 in the power-on stage T1 and the first display control signal 3 in the display stage T2, nor is there any need to change the second pulse signal 2 in the power-on stage T1 and the second display control signal 4 in the display stage T2. This reduces the working pressure of the driver chip IC and also reduces power consumption.

[0090] Of course, in the display stage T2, the first display control signal 3 controls the first reset module 102 to be turned on, and then the second display control signal 4 controls the compensation module 103 to be turned on. This is equivalent to resetting the first node N1 first, and then resetting the second node N2 and the third node N3. This can reduce the load problem after all pixel rows are turned on at the same time. If the first display control signal 3 and the second display control signal 4 control the first reset module 102 and the compensation module 103 to be turned on at the same time, then it is equivalent to resetting the first node N1 at the same time, and also resetting the second node N2 and the third node N3.

[0091] In some alternative embodiments, refer to Figure 14 and Figure 15 , Figure 14 yes Figure 1 A schematic diagram of another circuit connection structure for neutron pixels. Figure 15 yes Figure 14 The timing diagram of the operation of the pixel circuit is shown. The pixel circuit 10 also includes a data writing module 104, which is used to write data signals into the driving module 101.

[0092] The pixel circuit 10 also includes a bias module 106, the output of which is electrically connected to the output of the data writing module 104 and the first end of the driving module 101.

[0093] During the power-on phase T1, the peripheral drive circuit 30 transmits the fifth control signal SP to the control terminal of the bias module 106, and the bias module 106 is turned on.

[0094] Specifically, the pixel circuit 10 in this embodiment is an 8T1C circuit. During the power-on stage T1, the peripheral driving circuit 30 transmits the fifth control signal SP to the control terminal of the bias module 106, and the bias module 106 is turned on. The first terminal of the bias module 106 is electrically connected to the bias voltage DVH, and the second terminal of the bias module 106 is electrically connected to the output terminal of the data writing module 104 and the second node N2. The bias voltage DVH is written to the second node N2. Of course, since the first control signal S1 controls the driving transistor M0 to turn on, and the second control signal S2 controls the compensation module 103 to turn on, the residual charge in the previous display screen can be eliminated by the bias voltage DVH, that is, the static charge of the second node N2 and the third node N3 is eliminated.

[0095] It should be noted that during the power-on phase T1, when the bias module 106 is turned on, the data writing module 104 is turned off. No data needs to be written during the power-on phase T1, and turning off the data writing module 104 can reduce power consumption.

[0096] Additionally, during the display phase T2, the peripheral driving circuit 30 transmits a fifth control signal SP to the control terminal of the bias module 106, turning on the bias module 106. By controlling the bias module 106 to write a bias voltage DVH to the first terminal of the driving module 101 during the partial operation of the pixel circuit 10, the bias state of the driving module 101 is adjusted, improving the threshold drift problem of the driving module 101 and enhancing the display effect. It is understood that during the display phase T2, the operating time of the bias module 106 is not limited, only requiring it to operate before the light-emitting element 20 emits light. Optionally, in this embodiment, the bias voltage DVH can be provided by the bias signal line (not shown in the figure) in the display panel 100. Alternatively, in some other optional embodiments, the bias voltage DVH can also reuse the driving signal included in the pixel circuit 10 itself, such as reusing the data signal DATA to achieve bias adjustment. Or, when adjusting the bias voltage of the current row, the data signal DATA of the next row can be reused to adjust the bias voltage of the driving module 101 of the current row. This embodiment does not limit this, and you can refer to the bias adjustment structure in the related technology for a specific understanding. It is understood that the dynamic adjustment of the second power supply voltage VPvee and the bias voltage DVH in this embodiment can be directly adjusted by the second power supply voltage VPvee line (not shown in the figure) and the bias voltage signal line of the bias voltage DVH. For example, the second power supply voltage VPvee line and the bias voltage signal line can be connected to the driver chip IC or flexible circuit board bonded on the display panel 100. The dynamic values ​​of the second power supply voltage VPvee and the bias voltage DVH can be directly changed by the potential signal supplied by the input pad of the driver chip IC or the flexible circuit board. Alternatively, the dynamic adjustment of the bias voltage DVH can also be achieved by changing the conduction time of the bias module 106. For example, controlling the duration of the effective level of the fifth control signal SP can also change the value of the bias voltage DVH to follow the dynamic changes of the second power supply voltage VPvee and ensure the display quality of the display panel 100. This embodiment does not limit the method of dynamic adjustment.

[0097] In this embodiment, in the first stage T11, the peripheral driving circuit 30 only provides the first control signal S1 to the control terminal of the first reset module 102 of the pixel circuit 10 to perform electrostatic discharge on the first node N1. At this time, the reset signal VREF is input to the control terminal of the driving module 101, the driving module 101 is turned on, and the second control signal S2 is provided to the control terminal of the compensation module 103, the compensation module 103 is turned on, and at the same time the bias module 106 is turned on, and the residual charge in the previous display screen is eliminated by the bias voltage DVH, that is, the electrostatic charge of the second node N2 and the third node N3 is eliminated.

[0098] In some alternative embodiments, refer to Figure 16 , Figure 16 yes Figure 14 Another timing diagram of the middle pixel circuit: the first stage T11 includes a first sub-stage T111 and a second sub-stage T112. The second sub-stage T112 is located at the moment when the first sub-stage T111 is close to the second stage T12. The voltage input to the input terminal of the bias module 106 in the first sub-stage T111 is less than the voltage input to the input terminal of the bias module 106 in the second sub-stage T112.

[0099] Figure 16 In the first stage T11, there is a first sub-stage T111 and a second sub-stage T112 located near the second stage T12. The bias voltage of the first sub-stage T111 is less than the bias voltage of the second sub-stage T112. Optionally, the bias voltage of the second sub-stage T112 can be equal to the bias voltage of the display stage T2. The voltage input to the bias module 106 in the first sub-stage T111 is less than the voltage input to the bias module 106 in the second sub-stage T112. It can be understood that in the early stage of the power-on stage T1, i.e., the first sub-stage T111, all the transistors in the display panel are not yet in the optimal conduction state. If the bias voltage DVH transmitted at this time is too large, it may cause some transistors in the display panel to short-circuit. Therefore, the bias voltage input in the first sub-stage T111 is less than the bias voltage input in the second sub-stage T112 to prevent some transistors in the display panel from short-circuiting. On the other hand, during the power-on phase T1, it is necessary to ensure that no current flows to the anode of the light-emitting element 20, otherwise the light-emitting element 20 will emit light. Therefore, the bias voltage DVH should be set to a low level before the start of the first power supply voltage VPvdd, thereby eliminating the static charge of the second node N2 and the third node N3.

[0100] In some alternative embodiments, reference continues to be made to... Figures 4 to 11 The number of T1 frames during the power-on phase is greater than or equal to 5 and less than or equal to 15.

[0101] Understandably, the number of T1 frames during the power-on phase cannot be too large or too small. If the number of T1 frames is too small, the electrostatic discharge of the three terminals (i.e., the first node N1, the second node N2, and the third node N3) of the drive module 101 cannot be performed effectively. If the number of T1 frames is too large, the power-on phase T1 will take too long, affecting the display. In this embodiment, the number of T1 frames during the power-on phase is between 5 and 15, which is sufficient to perform good electrostatic discharge of the three terminals of the drive module 101 without taking too long.

[0102] In some alternative embodiments, reference continues to be made to... Figures 4 to 11In the second stage T12, the peripheral drive circuit 30 provides the reset signal VREF to the first terminal of the first reset module 102 before the start time of the first power supply voltage VPvdd.

[0103] Specifically, if the start time of the reset signal VREF is after the start time of the first power supply voltage VPvdd, then the first power supply voltage VPvdd will be written to the first terminal of the driver module 101. When the reset signal VREF is written to the control terminal of the driver module 101, a voltage difference will be formed between the control terminal and the input terminal of the driver module 101. In the second stage T12 of this embodiment, the peripheral driving circuit 30 provides the first terminal of the first reset module 102 with the start time of the reset signal VREF before the start time of the first power supply voltage VPvdd. This can prevent the first power supply voltage VPvdd from being written to the first terminal of the driver module 101 before resetting the driver module 101, which would cause a voltage difference between the first terminal and the control terminal of the driver module 101 and result in an overly bright screen.

[0104] Optionally, the reset signal VREF starts at the first stage T11, which ensures that the reset signal VREF starts before the start of the first power supply voltage VPvdd.

[0105] In some alternative embodiments, refer to Figure 12 , Figure 12 yes Figure 2 Another timing diagram for the operation of the mid-pixel circuit: In the first stage T11, the reset signal VREF includes a first sub-reset signal and a second sub-reset signal. The voltage of the first sub-reset signal VREF1 is V1. In the second stage T12, the voltage of the second sub-reset signal VREF2 is V2. V1 is less than V2. In the display stage T2, the reset signal includes a third sub-reset signal VREF3 and a fourth sub-reset signal VREF4. The potential of the third sub-reset signal VREF is V3, and the potential of the fourth sub-reset signal is V4. Within a preset range, V1 equals V3, and within a preset range, V2 = V4.

[0106] like Figure 12 In the first stage T11, the voltage V1 of the first sub-reset signal VREF1 is less than the voltage V2 of the second sub-reset signal VREF2 in the second stage T12, and the voltage V3 of the third sub-reset signal VREF is less than the voltage V4 of the fourth sub-reset signal VREF. This is within a preset range and may be due to fluctuations caused during signal transmission.

[0107] In this embodiment, during the power-on phase T1, the voltage V1 of the first sub-reset signal VREF1 in the first phase T11 is less than the voltage V2 of the second sub-reset signal VREF2 in the second phase T12, which reduces power consumption. Similarly, the third sub-reset signal VREF3 is less than the fourth sub-reset signal VREF4, which also reduces power consumption. V1 = V3 and V2 = V4 enable the first sub-reset signal VREF1, the second sub-reset signal VREF2, the third sub-reset signal VREF3, and the fourth sub-reset signal VREF4 to alternate in a regular pattern, which facilitates the driver chip IC to periodically and dynamically provide reset signals.

[0108] In some alternative embodiments, refer to Figure 13 , Figure 13 yes Figure 1 A schematic diagram of another circuit connection structure for a neutron pixel is shown. The pixel circuit 10 also includes a data writing module 104 and a light emission control module 105. The light emission control module 105 is used to control the light emission element 20 to emit light. The first electrode of the light emission element 20 is electrically connected to the output terminal of the light emission control module 105, and its second electrode is electrically connected to the second power supply voltage signal terminal PVEE. The data writing module 104 is used to write data signals to the driving module 101.

[0109] During the power-on phase T1, the light-emitting control module 105 and the data writing module 104 are turned off. During the display phase T2, the peripheral driving circuit 30 provides the third control signal E to the control terminal of the light-emitting control module 105 line by line. The third control signal E is an inactive level. The peripheral driving circuit 30 provides the fourth control signal S to the control terminal of the data writing module 104. The fourth control signal S is an inactive level. The data writing module 104 and the light-emitting control module 105 are turned off.

[0110] Specifically, the first terminal of the data writing module 104 is electrically connected to the data signal DATA, and the second terminal of the data writing module 104 is electrically connected to the first terminal of the driving module 101. The data writing module 104 is used to provide the data signal DATA to the driving module 101. Optionally, the data writing module 104 includes a third transistor M3, the gate of the third transistor M3 is connected to a fourth control signal S, the source of the third transistor M3 is connected to the data signal DATA, and the drain of the third transistor M3 is electrically connected to the first terminal of the driving module 101 (the source of the driving transistor M0, i.e., the second node N2). The pixel circuit 10 includes a data writing stage in the display stage T2. The peripheral driving circuit provides a fourth control signal S to the control terminal of the data writing module 104. When the fourth control signal S is at an active level, the data writing module 104 is turned on, and the data signal DATA on the data line can be transmitted to the driving module 101.

[0111] Optionally, the light-emitting control module 105 includes a first light-emitting control module 1051 and a second light-emitting control module 1052. The first terminal of the first light-emitting control module 1051 is electrically connected to the first power supply voltage signal terminal PVDD, and the second terminal of the first light-emitting control module 1051 is electrically connected to the first terminal of the driving module 101. The first terminal of the second light-emitting control module 1052 is electrically connected to the second terminal of the driving module 101, and the second terminal of the second light-emitting control module 1052 is electrically connected to the light-emitting element 20. Optionally, the first light-emitting control module 1051 includes a fourth transistor M4. The gate of the fourth transistor M4 is connected to the third control signal E, the source of the fourth transistor M4 is connected to the first power supply voltage signal terminal PVDD, and the drain of the fourth transistor M4 is connected to the first terminal of the driving module 101.

[0112] In the display stage T2, the pixel circuit 10 includes a light-emitting stage. The peripheral driving circuit 30 transmits the third control signal E line by line to the control terminal of the light-emitting control module 105. When the third control signal E is at an effective level, the light-emitting control module 105 is turned on, that is, the first light-emitting control module 1051 and the second light-emitting control module 1052 are turned on. A conducting circuit is formed between the first power supply voltage VPvdd and the second power supply voltage VPvee, and the light-emitting element 20 emits light. The first light-emitting control module 1051 and the second light-emitting control module 1052 cooperate to provide driving current to the light-emitting element 20. Specifically, when the first light-emitting control module 1051 is turned on, the positive voltage signal provided by the first power supply voltage VPvdd is provided to the first terminal of the driving module 101. Under the control of its gate voltage, the driving module 101 is turned on and provides the voltage signal of the first terminal of the driving module 101 to the second terminal of the driving module 101. When the second light-emitting control module 1052 is turned on, the voltage signal of the second terminal of the driving module 101 is provided to the light-emitting element 20, so that the driving current flows through the light-emitting element 20 and controls the light-emitting element 20 to emit light.

[0113] Of course, when the compensation module 103 is turned on, threshold compensation can be performed on the drive module 101. When the first reset module 102 is turned on, the control terminal potential of the drive module 101 is the reset signal VREF, which resets the control terminal of the drive module 101, thereby facilitating the turn-on of the drive module 101 during threshold compensation.

[0114] In this embodiment, during the power-on phase T1, the light-emitting control module 105 and the data writing module 104 are turned off. During the display phase T2, the third control signal E provided by the peripheral driving circuit 30 to the control terminal of the light-emitting control module 105 is at an effective level, and the fourth control signal S provided to the control terminal of the data writing module 104 is at an effective level. The light-emitting control module 105 and the data writing module 104 are turned on. In this way, it is not necessary to provide control signals to control the light-emitting control module 105 and the data writing module 104 to turn on during the power-on phase T1, which can reduce the power consumption of the display panel 100.

[0115] In some alternative embodiments, reference continues to be made to... Figure 13 The pixel circuit 10 also includes a second reset module 106, which is connected between the output terminal of the light-emitting control module 105 and the first pole of the light-emitting element 20, and is used to initialize the first pole of the light-emitting element 20. In the power-on stage T1, the second reset module 106 is turned off. The display stage T2 includes a reset stage between the data writing stages. In the reset stage, the second reset module 106 is turned on.

[0116] Specifically, in this embodiment, the pixel circuit 10 is a 7T1C circuit. During the display stage T2, when the second reset module 106 is turned on, the anode potential of the light-emitting element 20 is the reset signal VREF2. The reset signal VREF2 initializes the anode of the light-emitting element 20, thereby improving the retention of the previous frame data signal DATA, reducing ghosting, and enhancing the display effect of the display panel. Optionally, the second reset module 106 includes a sixth transistor M6, the gate of which is connected to the reset signal VREF2; the source of the sixth transistor M6 is electrically connected to the output terminal of the second light-emitting control module 1052, and the drain of the sixth transistor M6 is electrically connected to the anode of the light-emitting element 20.

[0117] During the power-on phase T1, the second reset module 106 is turned off. During the reset phase of the display phase T2, the second reset module 106 is turned on. Therefore, it is not necessary to provide a control signal to control the second reset module 106 to turn on during the power-on phase T1, which can reduce the power consumption of the power-on phase T1.

[0118] In some alternative embodiments, reference continues to be made to... Figures 4 to 12 and reference Figure 15 and Figure 16 During operation, the display panel 100 includes a power-down phase T3 after the display phase T2. The power-down phase T3 includes at least a third phase T31 and a fourth phase T32 in sequence.

[0119] In the third stage T31, the peripheral driving circuit 30 provides the first power supply voltage VPvdd to the first power supply voltage signal terminal PVDD and / or provides the second power supply voltage VPvee to the second power supply voltage signal terminal PVEE; in the fourth stage T32, the peripheral driving circuit 30 stops providing the first power supply voltage VPvdd to the first power supply voltage signal terminal PVDD and / or provides the second power supply voltage VPvee to the second power supply voltage signal terminal PVEE.

[0120] In the third stage T31 and the fourth stage T32, the peripheral drive circuit 30 provides a first control signal S1 to the control terminal of the first reset module 102 and a second control signal S2 to the control terminal of the compensation module 103.

[0121] In this invention, the power-down phase T3 follows the display phase T2. The power-down phase T3 includes a third phase T31 and a fourth phase T32. In the third phase T31, the first power supply voltage VPvdd and the second power supply voltage VPvee are maintained for a certain period of time. In the fourth phase T32, the input of the first power supply voltage VPvdd and / or the second power supply voltage VPvee is stopped.

[0122] During at least a portion of the frames of the entire power-down phase T3, the peripheral driving circuit 30 only provides the first control signal S1 to the control terminal of the first reset module 102 of the pixel circuit 10. At this time, the reset signal VREF is input to the control terminal of the driving module 101 to perform electrostatic discharge on the first node N1. Simultaneously, the driving module 101 is turned on and provides the second control signal S2 to the control terminal of the compensation module 103. The compensation module 103 is turned on and performs electrostatic discharge on the second node N2 and the third node N3. In this way, electrostatic discharge is performed on the first node N1, the second node N2 and the third node N3 during the power-down process. In the next power-on phase T1, electrostatic discharge can be further performed, so that the light-emitting element 20 will not flicker.

[0123] In some alternative embodiments, please refer to Figure 17 , Figure 17 This is a schematic diagram of the planar structure of the display device provided in the embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. Figure 17 This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0124] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0125] The display panel of this invention includes an electrically connected pixel circuit and a light-emitting element. The pixel circuit controls the light-emitting element to emit light. The pixel circuit includes at least a driving module, a first reset module, and a compensation module. The driving module and the light-emitting element are connected in series between a first power supply voltage signal terminal and a second power supply voltage signal terminal. The driving module generates a driving current to drive the light-emitting element to emit light. The first reset module is electrically connected to the control terminal of the driving module and is used to initialize the control terminal of the driving module. The compensation module is connected in series between the control terminal and the output terminal of the driving module to compensate for the potential of the control terminal of the driving module. The compensation module detects and compensates for the deviation of the threshold voltage of the driving module and provides the compensated threshold voltage deviation to the driving module to achieve threshold compensation of the driving module. Since the driving module and the light-emitting element are connected in series between the first power supply voltage signal terminal and the second power supply voltage signal terminal, when the pixel circuit drives the electrically connected light-emitting element to emit light, the driving module generates a driving current to drive the light-emitting element to emit light through the conductive path between the first power supply voltage signal terminal, the driving module, the light-emitting element, and the second power supply voltage signal terminal, thereby achieving the light-emitting effect of the light-emitting element. The peripheral driving circuit of this invention provides circuit signals to the pixel circuit. Since the first power supply voltage of the first power supply voltage signal terminal was connected to the first terminal of the driving module during the previous display, positive charge accumulated at the first terminal of the driving module, and this charge is stored on the parasitic capacitance. When the first control signal controls the first reset module to turn on and the second control signal controls the compensation module to turn on, the driving module turns on because Vgs < Vth. At the same time, the residual charge is released until the driving module turns off. Subsequently, in the early stage of the display phase, since the residual charge has been released during the power-on phase, the light-emitting element will not flicker.

[0126] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, include: Light-emitting elements; A pixel circuit, comprising at least a driving module, a first reset module, and a compensation module, wherein the driving module and the light-emitting element are connected in series between a first power supply voltage signal terminal and a second power supply voltage signal terminal, wherein the driving module is used to generate a driving current to drive the light-emitting element to emit light; The first reset module is electrically connected to the control terminal of the drive module and is used to initialize the control terminal of the drive module; the compensation module is connected in series between the control terminal of the drive module and the second terminal of the drive module to compensate the potential of the control terminal of the drive module. A peripheral driving circuit provides a driving signal to the pixel circuit. The display panel operates by comprising at least a sequential power-on phase and a display phase. The power-on phase includes at least a sequential first phase and a second phase, and includes multiple consecutive frames. During at least a portion of the frame period of the power-on phase, the peripheral driving circuit provides a first control signal to the control terminal of the first reset module, and the first reset module is turned on. The peripheral driving circuit also provides a second control signal to the control terminal of the compensation module, and the compensation module is turned on. In the second phase, the peripheral driving circuit provides a first power supply voltage to the first power supply voltage signal terminal and / or a second power supply voltage to the second power supply voltage signal terminal.

2. The display panel according to claim 1, characterized in that, During at least a portion of the frame period of the power-on phase, the first control signal remains active; during at least a portion of the frame period of the power-on phase, the second control signal remains active.

3. The display panel according to claim 2, characterized in that, During the power-on phase, in n consecutive frames, the first control signal is continuously active in the i-th frame, and the second control signal is continuously inactive; in the (i+1)-th frame, both the first control signal and the second control signal are continuously active, where n is a positive integer greater than or equal to 2, i is a positive integer, and i is less than or equal to n-1.

4. The display panel according to claim 1, characterized in that, During the power-on phase, the second control signal remains active, the first control signal is a pulse signal, and the peripheral drive circuit transmits the pulse signal line by line to the control terminal of the first reset module.

5. The display panel according to claim 4, characterized in that, During the display phase, the peripheral driving circuit provides a first display control signal to the control terminal of the first reset module; During the power-on phase, the effective pulse width of the first control signal is equal to the effective pulse width of the first display control signal.

6. The display panel according to claim 1, characterized in that, The first control signal is a first pulse signal, and the second control signal is a second pulse signal; the peripheral driving circuit transmits the first pulse signal to the control terminal of the first reset module line by line, and the peripheral driving circuit transmits the second pulse signal to the control terminal of the compensation module line by line, wherein the effective pulses of the first pulse signal and the effective pulses of the second pulse signal at least partially overlap.

7. The display panel according to claim 6, characterized in that, During the power-on phase, the time during which the effective pulse width of the first pulse signal overlaps with the effective pulse width of the second pulse signal is t1. During the display phase, the peripheral driving circuit provides a first display control signal to the control terminal of the first reset module, and the peripheral driving circuit provides a second display control signal to the control terminal of the compensation module; during the display phase, the effective pulse width of the second display control signal and the time during which the pulse width of the first display control signal overlap is t2. Where t1 = t2.

8. The display panel according to claim 6, characterized in that, The first control signal is a first pulse signal, and the second control signal is a second pulse signal; the peripheral driving circuit transmits the first pulse signal to the control terminal of the first reset module line by line, and the peripheral driving circuit transmits the second pulse signal to the control terminal of the compensation module line by line. The start time of the effective pulse of the second pulse signal is after the end time of the effective pulse of the first pulse signal.

9. The display panel according to claim 8, characterized in that, During the display phase, the peripheral driving circuit provides a first display control signal to the control terminal of the first reset module, and the peripheral driving circuit provides a second display control signal to the control terminal of the compensation module. During the power-on phase, the pulse width of the first pulse signal is equal to the pulse width of the first display control signal during the display phase. The pulse width of the second pulse signal is equal to the pulse width of the second display control signal in the display phase.

10. The display panel according to claim 6, characterized in that, The pixel circuit further includes a data writing module, which is used to write data signals into the driving module; The pixel circuit also includes a bias module, the output of which is electrically connected to the output of the data writing module and the input of the driving module. During the power-on phase, the peripheral drive circuit transmits a fifth control signal to the control terminal of the bias module, and the bias module is turned on.

11. The display panel according to claim 10, characterized in that, The first stage includes a first sub-stage and a second sub-stage. The second sub-stage is located at a moment when the first sub-stage is close to the second stage. The voltage input to the input terminal of the bias module in the first sub-stage is less than the voltage input to the input terminal of the bias module in the second sub-stage.

12. The display panel according to claim 1, characterized in that, The number of frames in the power-on phase is greater than or equal to 5 and less than or equal to 15.

13. The display panel according to claim 1, characterized in that, In the second stage, the peripheral driving circuit provides a reset signal to the first terminal of the first reset module at a time that precedes the start time of the first power supply voltage.

14. The display panel according to claim 13, characterized in that, During the power-on phase, the reset signal includes a first sub-reset signal and a second sub-reset signal. In the first phase, the voltage of the first sub-reset signal is V1, and in the second phase, the voltage of the second sub-reset signal is V2, where V1 is less than V2. During the display phase, the reset signal includes a third sub-reset signal and a fourth sub-reset signal. The potential of the third sub-reset signal is V3, and the potential of the fourth sub-reset signal is V4. Within a preset range, V1 equals V3, and within a preset range, V2 = V4.

15. The display panel according to claim 1, characterized in that, The pixel circuit further includes a data writing module and a light emission control module. The light emission control module is used to control the light emission element to emit light. The first electrode of the light emission element is electrically connected to the output terminal of the light emission control module, and the second electrode is electrically connected to the second power supply voltage signal terminal. The data writing module is used to write data signals into the driving module. During the power-on phase, the light-emitting control module and the data writing module turn off the peripheral driving circuit and transmit the third control signal line by line to the control terminal of the light-emitting control module. The third control signal is an inactive level. The peripheral driving circuit provides a fourth control signal to the control terminal of the data writing module. The fourth control signal is an inactive level. The display stage includes a data writing stage and a light emission stage. In the data writing stage, the peripheral driving circuit provides a fourth control signal to the control terminal of the data writing module, and the fourth control signal is at an active level. In the light emission stage, the peripheral driving circuit transmits a third control signal line by line to the control terminal of the light emission control module, and the third control signal is at an active level.

16. The display panel according to claim 15, characterized in that, The pixel circuit also includes a second reset module connected between the output terminal of the light-emitting control module and the first electrode of the light-emitting element, for initializing the first electrode of the light-emitting element. During the power-on phase, the second reset module is turned off. The display phase includes a reset phase prior to the data writing phase, during which the second reset module is turned on.

17. The display panel according to claim 1, characterized in that, During operation, the display panel includes a power-down phase after the display phase. The power-down phase includes at least a third and a fourth phase in sequence. In the third stage, the peripheral driving circuit provides a first power supply voltage to the first power supply voltage signal terminal and / or provides a second power supply voltage to the second power supply voltage signal terminal; in the fourth stage, the peripheral driving circuit stops providing the first power supply voltage to the first power supply voltage signal terminal and / or providing the second power supply voltage to the second power supply voltage signal terminal. In both the third and fourth stages, the peripheral driving circuit provides a first control signal to the control terminal of the first reset module, and the peripheral driving circuit provides a second control signal to the control terminal of the compensation module.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

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