A multi-functional sgt power device and a manufacturing method thereof

Abstract

The application provides a multifunctional SGT power device and a manufacturing method thereof. The device has an adjusting pad, a gate pad and a source pad, and has adjusting gate polysilicon, gate polysilicon and shielding gate polysilicon in a device groove. The adjusting gate polysilicon is above the shielding gate polysilicon, the gate polysilicon includes a middle part and flanking parts, the middle part is between the adjusting gate polysilicon and the shielding gate polysilicon, and the flanking parts are on both sides of the adjusting gate polysilicon and connected with the middle part. Different performance devices can be realized through different wire bonding modes. When the adjusting pad and the gate pad are short-circuited through wire bonding, the device has small gate-source capacitance, can switch quickly and is suitable for high-frequency application. When the adjusting pad and the source pad are short-circuited through wire bonding, the device has large gate-source capacitance, can reduce switching oscillation, has strong impact resistance, can reduce the ratio of reverse transmission capacitance to input capacitance, and is suitable for application in a battery management system and motor control.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a multifunctional SGT power device and its fabrication method. Background Technology

[0002] Power devices are a class of devices used in power management, power transmission, and high-speed switching control. Unlike ordinary low-frequency signal amplification devices, power devices are primarily used for operation at higher voltages and currents.

[0003] Based on their operating principles, power devices can be classified into several types, including junction field-effect transistors (JFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), and thyristors (SCRs). According to their current and voltage handling capabilities, they can be divided into three categories: small-signal power devices, medium-power devices, and high-power devices.

[0004] Power devices can stably regulate the input and output of electrical energy, providing efficient power management for various electrical equipment. In electrical control systems, power devices can perform various operations such as switching on / off, regulating voltage, controlling transformer current, and driving electromechanical equipment. Furthermore, on solar panels, power devices can adjust the output power under different lighting conditions, improving the efficiency of solar energy utilization.

[0005] In MOSFET power devices, trench MOSFETs are mainly used in low-voltage (e.g., 100V) applications, shielded gate trench (SGT) MOSFETs are mainly used in medium-low voltage (e.g., 200V) applications, and superjunction MOSFETs (SJ-MOSFETs) are mainly used in high-voltage (e.g., 600V-800V) applications.

[0006] Among them, the shielded-gate trench MOSFET power device is an improved trench power MOSFET based on the traditional trench MOSFET. Based on charge balance technology, it adds an additional polysilicon field plate to the traditional trench MOSFET for electric field modulation, thereby improving voltage withstand and reducing on-resistance. It features low on-resistance, low switching loss, and good frequency characteristics. Its shielded gate acts as a body field plate in the drift region, giving the shielded-gate trench MOSFET significant advantages in specific on-resistance R_(ON(SP)) and quality factor (FOM = Ron * Qg), effectively improving the system's energy efficiency. Therefore, the shielded-gate trench MOSFET is used as a switching device in motor drive systems, inverter systems, and power management systems in fields such as new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances, and is a core power control component.

[0007] In shielded gate trench MOSFETs, the upper gate polysilicon layer is connected to the gate, and the lower shielded gate polysilicon layer is connected to the source. The gate-source capacitance is typically fixed, resulting in a relatively simple device function. How to improve the structure of SGT power devices to make their gate-source capacitance adjustable, thereby enabling the devices to possess different performance characteristics and achieve multi-functional applications, has become an important technical problem urgently needing to be solved by those skilled in the art.

[0008] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multifunctional SGT power device and its manufacturing method, so as to solve the problem that the existing power devices have relatively limited functions.

[0010] To achieve the above and other related objectives, the present invention provides a multifunctional SGT power device, comprising:

[0011] Semiconductor layer;

[0012] Multiple trenches are located in the semiconductor layer and are spaced apart in the horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward;

[0013] A shielding gate polysilicon, a regulating gate polysilicon, and a gate polysilicon are located in the trench. The regulating gate polysilicon is located above the shielding gate polysilicon. The gate polysilicon includes a middle portion and side portions. The middle portion is located between the regulating gate polysilicon and the shielding gate polysilicon. The side portions are located on both sides of the regulating gate polysilicon and are connected to the middle portion.

[0014] The system comprises a first isolation layer, a second isolation layer, a third isolation layer, and a gate dielectric layer. The first isolation layer is located between the inner wall of the trench and the outer wall of the shielding gate polysilicon. The second isolation layer is located between the shielding gate polysilicon and the gate polysilicon. The third isolation layer is located between the adjustment gate polysilicon and the gate polysilicon. The gate dielectric layer is located between the inner wall of the trench and the outer wall of the gate polysilicon.

[0015] An adjustment metal line, a gate metal line, and a source metal line are located above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, and the source metal line is electrically connected to the shielding gate polysilicon.

[0016] An adjustment pad, a gate pad, and a source pad are located above the semiconductor layer. The adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

[0017] Optionally, the plurality of trenches are spaced apart in a first horizontal direction and all extend in a second horizontal direction perpendicular to the first horizontal direction. The shielded gate trench power device further includes a polysilicon lead-out portion located in the trench. The polysilicon lead-out portion is located at both ends of the shielded gate polysilicon in the second horizontal direction and is connected to the shielded gate polysilicon. The top surface of the polysilicon lead-out portion is higher than the top surface of the shielded gate polysilicon.

[0018] Optionally, the multifunctional SGT power device further includes a first contact hole disposed on the polysilicon lead-out portion, a second contact hole disposed on the regulating gate polysilicon, and a third contact hole disposed on the gate polysilicon. The source metal line is electrically connected to the shielding gate polysilicon through the first contact hole and the polysilicon lead-out portion, the regulating gate metal line is electrically connected to the regulating gate polysilicon through the second contact hole, and the gate metal line is electrically connected to the gate polysilicon through the third contact hole.

[0019] Optionally, the multifunctional SGT power device further includes a body region, a source region, and a fourth contact hole. The body region is located on the upper surface of the semiconductor layer on both sides of the trench, the source region is located on the upper surface of the body region, the fourth contact hole is located on the source region, and the source pad is electrically connected to the source region through the fourth contact hole.

[0020] Optionally, the adjustment pad is electrically connected to the gate pad, or the adjustment pad is electrically connected to the source pad.

[0021] This invention also provides a method for fabricating a multifunctional SGT power device, comprising the following steps:

[0022] A semiconductor layer is provided, in which a plurality of trenches are formed at intervals in a horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward therefrom;

[0023] A first isolation layer and a shielding gate polysilicon are formed in the trench, and the inner wall of the trench and the shielding gate polysilicon are separated by the first isolation layer;

[0024] A second isolation layer is formed in the trench, the second isolation layer covering the upper surface of the shielding gate polysilicon;

[0025] A gate dielectric layer and a gate polysilicon are formed in the trench, the gate polysilicon and the shielding gate polysilicon are separated by a second isolation layer, and the gate polysilicon and the inner wall of the trench are separated by the gate dielectric layer.

[0026] A groove is formed in the gate polysilicon, the groove opening from the top surface of the gate polysilicon and extending downward to divide the gate polysilicon into a middle portion and a side portion, the side portion connecting the two ends of the middle portion;

[0027] A third isolation layer and a regulating gate polysilicon are formed in the groove, and the inner wall of the groove and the outer wall of the regulating gate polysilicon are separated by the third isolation layer;

[0028] An adjustment metal line, a gate metal line, a source metal line, an adjustment pad, a gate pad, and a source pad are formed above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, the source metal line is electrically connected to the shield gate polysilicon, the adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

[0029] Optionally, the plurality of said trenches are spaced apart in a first horizontal direction and all extend in a second horizontal direction perpendicular to the first horizontal direction. The method for manufacturing the multifunctional shielded gate trench type power device further includes the following steps:

[0030] Polysilicon leads are formed at both ends of the shielding gate polysilicon in a second horizontal direction. The polysilicon leads are located in the trench and the top surface of the polysilicon leads is higher than the top surface of the shielding gate polysilicon.

[0031] Optionally, the following steps are also included:

[0032] The solid regions are formed on the upper surface of the semiconductor layer on both sides of the trench;

[0033] The source region is formed on the upper surface layer of the body region;

[0034] An interlayer dielectric layer is formed above the semiconductor layer;

[0035] A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed in the interlayer dielectric layer. The first contact hole is located on the polysilicon lead-out portion, the second contact hole is located on the adjustment gate polysilicon, the third contact hole is located on the gate polysilicon, and the fourth contact hole is located on the source region.

[0036] Conductive plugs are formed in the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole;

[0037] The source metal line is electrically connected to the shielding gate polysilicon through the first contact hole and the polysilicon lead-out portion; the regulating gate metal line is electrically connected to the regulating gate polysilicon through the second contact hole; the gate metal line is electrically connected to the gate polysilicon through the third contact hole; and the source pad is electrically connected to the source region through the fourth contact hole.

[0038] Optionally, the top surface of the regulating gate polysilicon is lower than or flush with the top surface of the side wing.

[0039] Optionally, the method for fabricating the multifunctional SGT power device further includes the step of forming a bonding wire, one end of which is connected to the adjustment pad and the other end of which is connected to the gate pad or the source pad.

[0040] As described above, the multifunctional SGT power device of the present invention has an adjustment pad, a gate pad, and a source pad. The device trench contains an adjustment gate polysilicon, a gate polysilicon, and a shielding gate polysilicon. The adjustment gate polysilicon is located above the shielding gate polysilicon. The gate polysilicon includes a central portion and side portions. The central portion is located between the adjustment gate polysilicon and the shielding gate polysilicon, and the side portions are located on both sides of the adjustment gate polysilicon and connected to the central portion. Different bonding methods can achieve devices with different performance characteristics. When the adjustment pad and the gate pad are short-circuited by a bonding wire, the device's gate-source capacitance Cgs is small, enabling fast switching and suitable for high-frequency applications. When the adjustment pad and the source pad are short-circuited by a bonding wire, the device's gate-source capacitance Cgs is large, reducing switching oscillations, providing strong shock resistance, and lowering the ratio of reverse transfer capacitance to input capacitance (Crss / Ciss), making it suitable for applications in battery management systems (BMS) and motor control. Attached Figure Description

[0041] Figure 1 The diagram shown is a schematic cross-sectional view of an example of the multifunctional SGT power device of the present invention.

[0042] Figure 2 The diagram shown is a schematic representation of an example planar layout structure of the multifunctional SGT power device of the present invention.

[0043] Figure 3 The diagram shown illustrates a wire bonding method for the multifunctional SGT power device of this invention.

[0044] Figure 4 This diagram illustrates another wire bonding method for the multifunctional SGT power device of the present invention.

[0045] Figure 5The diagram shown illustrates the process flow of the fabrication method for the multifunctional SGT power device of the present invention.

[0046] Figure 6 The diagram shows a structural schematic after a mask layer is deposited on a semiconductor layer, which is a method for fabricating the multifunctional SGT power device of the present invention.

[0047] Figure 7 The diagram shows the structure after the trench is formed in the fabrication method of the multifunctional SGT power device of the present invention.

[0048] Figure 8 The diagram shows the structure after the first oxide layer and the first polysilicon layer are grown, according to the fabrication method of the multifunctional SGT power device of the present invention.

[0049] Figure 9 The diagram shown illustrates the structure of the multifunctional SGT power device of the present invention after the shielding gate polysilicon is formed.

[0050] Figure 10 The diagram shows the structure of the multifunctional SGT power device of the present invention after forming a second oxide layer in the trench and planarizing it.

[0051] Figure 11 The diagram shows the structure of the multifunctional SGT power device of the present invention after etching back the second oxide layer to obtain the second isolation layer and forming the gate dielectric layer and the gate polysilicon in the trench.

[0052] Figure 12 The diagram shown is a structural schematic of the multifunctional SGT power device fabrication method of the present invention after forming a mask layer with openings.

[0053] Figure 13 The diagram shows the structure of the multifunctional SGT power device of the present invention after forming the groove, the third isolation layer and the tuning gate polysilicon.

[0054] Component designation explanation

[0055] 1 Semiconductor layer

[0056] 2. Trench

[0057] 3. Shielded gate polycrystalline silicon

[0058] 4. Adjustable gate polysilicon

[0059] 5-Gate Polysilicon

[0060] 501 Middle Section

[0061] 502 Flanking Section

[0062] 6 First isolation layer

[0063] 7 Second isolation layer

[0064] 8 Third isolation layer

[0065] 9 Gate dielectric layer

[0066] 10. Adjust the metal wire

[0067] 11 Gate metal line

[0068] 12 source metal wires

[0069] 13 Adjust the pads

[0070] 14 Gate pads

[0071] 15 Source pads

[0072] 16 Polycrystalline silicon lead-out section

[0073] 17, 28 mask layers

[0074] 18 First contact hole

[0075] 19 Second contact hole

[0076] 20 Third contact hole

[0077] 21 Fourth contact hole

[0078] Wires 22 and 23

[0079] 24 First Oxide Layer

[0080] 25 First polycrystalline silicon layer

[0081] 26 Second Oxide Layer

[0082] 27 Third Oxide Layer

[0083] Steps S1 to S7 Detailed Implementation

[0084] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0085] Please see Figures 1 to 13It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0086] Example 1

[0087] This embodiment provides a multifunctional SGT power device. Please refer to [link / reference]. Figure 1 The diagram shows an example cross-sectional structure of the multifunctional SGT power device, including...

[0088] It includes a semiconductor layer 1, trenches 2, a shielding gate polysilicon 3, a regulating gate polysilicon 4, and a gate polysilicon 5, wherein the number of trenches 2 is multiple. Figure 1 (Only one is shown in the image). A plurality of trenches 2 are located in the semiconductor layer 1 and are arranged at intervals in the horizontal direction. The trenches 2 open from the top surface of the semiconductor layer 1 and extend downward. The shielding gate polysilicon 3, the regulating gate polysilicon 4 and the gate polysilicon 5 are all located in the trenches 2. The regulating gate polysilicon 4 is located above the shielding gate polysilicon 3 and is spaced apart from the shielding gate polysilicon 3. The gate polysilicon 5 includes a middle portion 501 and a side portion 502. The middle portion 501 is located between the regulating gate polysilicon 4 and the shielding gate polysilicon 3. The side portion 502 is located on both sides of the regulating gate polysilicon 4 and is connected to the middle portion 501.

[0089] Specifically, the semiconductor layer 1 can be a single-layer or multi-layer structure. For example, it can be a single substrate or a stacked structure consisting of a single substrate and an epitaxial layer thereon. The material, doping type, and doping concentration of the substrate and / or epitaxial layer can be selected as needed and are not excessively limited here. For example, the substrate material can be selected from silicon, germanium silicon, III-V compound, silicon carbide, or other suitable semiconductor materials, and its doping type can be N-type or P-type. In this embodiment, the semiconductor layer 1 is an example of N-type doped silicon.

[0090] Specifically, the depth of the trench 2 can be set according to the specific device performance requirements.

[0091] Specifically, the multifunctional SGT power device further includes a first isolation layer 6, a second isolation layer 7, a third isolation layer 8, and a gate dielectric layer 9 located in the trench 2. The first isolation layer 6 is located between the inner wall of the trench 2 and the outer wall of the shielding gate polysilicon 3. The second isolation layer 7 is located between the shielding gate polysilicon 3 and the gate polysilicon 5. The third isolation layer 8 is located between the adjustment gate polysilicon 4 and the gate polysilicon 5. The gate dielectric layer 9 is located between the inner wall of the trench 2 and the outer wall of the gate polysilicon 5.

[0092] As an example, the first isolation layer 6, the second isolation layer 7, and the third isolation layer 8 can be selected from silicon oxide or other suitable insulating materials. The first isolation layer 6 acts as a field oxide layer for electrically isolating the semiconductor layer 1 from the shielding gate polysilicon 3, the second isolation layer 7 is used to electrically isolate the shielding gate polysilicon 3 from the gate polysilicon 5, and the third isolation layer 8 is used to electrically isolate the regulating gate polysilicon 4 from the gate polysilicon 5.

[0093] As an example, the gate dielectric layer 9 can be made of silicon oxide or other suitable materials, and its thickness can be set according to the specific device performance requirements.

[0094] Please see Figure 2 The diagram shows an example planar layout structure of a multifunctional SGT power device according to this embodiment, wherein the plurality of trenches 2 are arranged in a first horizontal direction ( Figure 2 Arranged at intervals along the X-direction and all pointing towards the second horizontal direction perpendicular to the first horizontal direction. Figure 2 Extending in the Y direction.

[0095] Specifically, the multifunctional SGT power device also includes an adjustment metal line 10, a gate metal line 11, and a source metal line 12 located above the semiconductor layer 1, and a drain metal layer (not shown) located on the lower surface of the semiconductor layer 1. The adjustment metal line 10 is electrically connected to the adjustment gate polysilicon 4, the gate metal line 11 is electrically connected to the gate polysilicon 5, and the source metal line 12 is electrically connected to the shielding gate polysilicon 3.

[0096] Specifically, the SGT power device also includes an adjustment pad 13, a gate pad 14 and a source pad 15 located above the semiconductor layer 1. The adjustment pad 13 is connected to the adjustment metal line 10, the gate pad 14 is connected to the gate metal line 11, and the source pad 14 is connected to the source metal line 12.

[0097] As an example, the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be located in the same metal layer or in different metal layers as needed. The materials of the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be aluminum or other suitable conductive metal materials.

[0098] As an example, the multifunctional shielded gate trench power device further includes a polysilicon lead-out portion 16 located in the trench 2, the polysilicon lead-out portion 16 being located in the second horizontal direction of the shielded gate polysilicon 3. Figure 2 The polysilicon lead-out portion 16 is connected to both ends of the shielding gate polysilicon 3 in the Y direction, and the top surface of the polysilicon lead-out portion 16 is higher than the top surface of the shielding gate polysilicon 3.

[0099] As an example, the multifunctional SGT power device further includes a first contact hole 18 disposed on the polysilicon lead-out portion 16, a second contact hole 19 disposed on the regulating gate polysilicon 4, and a third contact hole 20 disposed on the gate polysilicon 5. The source metal line 12 is electrically connected to the shielding gate polysilicon 3 through the first contact hole 18 and the polysilicon lead-out portion 16. The regulating metal line 10 is electrically connected to the regulating gate polysilicon 4 through the second contact hole 19. The gate metal line 11 is electrically connected to the gate polysilicon 5 through the third contact hole 20.

[0100] As an example, the multifunctional SGT power device further includes a body region (not shown), a source region (not shown), and a fourth contact hole 21. The body region is located on the upper surface of the semiconductor layer 1 on both sides of the trench 2, the source region is located on the upper surface of the body region, the fourth contact hole 21 is located on the source region, and the source pad 15 is electrically connected to the source region through the fourth contact hole 21.

[0101] Please see Figure 3 The diagram shows a wire bonding method for a multifunctional SGT power device in this embodiment. The adjustment pad 13 and the gate pad 14 are electrically connected by a wire 22, which is equivalent to the adjustment gate polysilicon 4 being shorted to the gate polysilicon 5. In this case, the adjustment gate polysilicon 4 acts as part of the gate polysilicon. The device is similar to a device using a planar gate polysilicon. The device has a small gate-source capacitance Cgs, which enables fast switching and is suitable for high-frequency applications.

[0102] Please see Figure 4The diagram shows another bonding method for the multifunctional SGT power device in this embodiment, wherein the adjustment pad 13 and the source pad 15 are electrically connected by bonding wire 23 (e.g., Figure 4 As shown in the diagram, this is equivalent to the regulating gate polysilicon 4 being short-circuited with the shielding gate polysilicon 3. In this case, the regulating gate polysilicon 4 constitutes part of the source polysilicon. The device gate-source capacitance Cgs includes not only the capacitance between the gate polysilicon 5 and the shielding gate polysilicon 3, but also the capacitance between the gate polysilicon 5 and the regulating gate polysilicon 4. This makes the device gate-source capacitance Cgs larger, which can reduce switching oscillation, has strong shock resistance, and can reduce the ratio of reverse transmission capacitance to input capacitance Crss / Ciss. This makes it suitable for applications such as battery management systems (BMS) and motor control.

[0103] In other words, this invention can achieve devices with different performance characteristics by using different wire bonding methods.

[0104] Specifically, in the SGT power device of this embodiment, since the gate polysilicon 5 includes a middle portion 501 located below the adjustment gate polysilicon 4 and side wing portions 502 located on both sides of the adjustment gate polysilicon 4 and connected to the middle portion 501, the cross-section of the gate polysilicon 5 is U-shaped, forming a wrapping around the adjustment gate polysilicon 4. When the adjustment gate polysilicon 4 is short-circuited with the shielding gate polysilicon 3, it not only adds an additional component of the device's gate-source capacitance Cgs (i.e., the capacitance between the gate polysilicon 5 and the shielding gate polysilicon 3), but also, since the cross-section of the gate polysilicon 5 is U-shaped, compared to the planar gate polysilicon structure, the U-shaped gate polysilicon 5 and the source polysilicon (at this time, the adjustment gate polysilicon 4 is part of the source polysilicon) have a larger relative area, thereby significantly increasing the device's gate-source parasitic capacitance.

[0105] Specifically, the position of the top surface of the regulating gate polysilicon 4 affects the relative area of ​​the gate polysilicon 5 and the regulating gate polysilicon 4, and thus affects the size of the device gate-source capacitance Cgs when the regulating gate polysilicon 4 and the shielding gate polysilicon 3 are short-circuited. The lower the top surface of the regulating gate polysilicon 4, the smaller the device gate-source capacitance Cgs. In this invention, the depth of the top surface of the regulating gate polysilicon 4 can be adjusted as needed. For example, the top surface of the regulating gate polysilicon 4 can be lower than or flush with the top surface of the side wing portion 502 of the gate polysilicon 5.

[0106] Specifically, the thickness of the shielding gate polysilicon 3 in the vertical direction can be adjusted according to application requirements. For example, the thickness of the shielding gate polysilicon 3 in the vertical direction is greater than the thickness of the side wing portion 502 of the gate polysilicon 5 in the vertical direction. In this embodiment, the thickness of the shielding gate polysilicon 3 in the vertical direction is preferably greater than half the depth of the trench 2 to ensure the withstand voltage performance and low on-resistance of the shielding gate trench power device.

[0107] Specifically, the thicknesses of the second isolation layer 7 and the third isolation layer 8 in the vertical direction can be adjusted according to application requirements. For example, the thickness of the second isolation layer 7 in the vertical direction can be greater than that of the third isolation layer 8. When the regulating gate polysilicon 4 and the gate polysilicon 5 are shorted, it is for fast-switching applications, requiring a small gate-source capacitance. Therefore, the thickness of the second isolation layer 7 needs to be thicker (the thinner the dielectric thickness between the gate polysilicon and the source polysilicon, the larger the gate-source capacitance). When the regulating gate polysilicon 4 and the shielding gate polysilicon 3 are shorted, it is for slow-switching applications to reduce switching oscillations. Therefore, a larger gate-source capacitance is required, thus requiring a thinner third isolation layer 8. The specific thicknesses of the second isolation layer 7 and the third isolation layer 8 can be designed according to specific performance parameter requirements and are not specifically limited here.

[0108] As described above, the multifunctional SGT power device of this embodiment not only has gate pads and source pads, but also adjustment pads. The device trench not only has gate polysilicon and shielding gate polysilicon, but also adjustment gate polysilicon. By flexibly using the bonding method of the adjustment pads, devices with different performance can be realized.

[0109] Example 2

[0110] This embodiment provides a method for fabricating a multifunctional SGT power device. Please refer to [link / reference]. Figure 5 The diagram shows the process flow of this method, which includes the following steps:

[0111] S1: A semiconductor layer is provided, in which a plurality of trenches are formed at intervals in a horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward therefrom;

[0112] S2: A first isolation layer and a shielding gate polysilicon are formed in the trench, and the inner wall of the trench and the shielding gate polysilicon are separated by the first isolation layer;

[0113] S3: A second isolation layer is formed in the trench, the second isolation layer covering the upper surface of the shielding gate polysilicon;

[0114] S4: A gate dielectric layer and a gate polysilicon are formed in the trench, the gate polysilicon and the shielding gate polysilicon are separated by the second isolation layer, and the gate polysilicon and the inner wall of the trench are separated by the gate dielectric layer;

[0115] S5: A groove is formed in the gate polysilicon, the groove opening from the top surface of the gate polysilicon and extending downward to divide the gate polysilicon into a middle part and a side part, the side part connecting the two ends of the middle part;

[0116] S6: A third isolation layer and a regulating gate polysilicon are formed in the groove, wherein the inner wall of the groove and the outer wall of the regulating gate polysilicon are separated by the third isolation layer;

[0117] S7: Form an adjustment metal line, a gate metal line, a source metal line, an adjustment pad, a gate pad, and a source pad above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, the source metal line is electrically connected to the shield gate polysilicon, the adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

[0118] Please refer to the following first. Figures 6-7 Perform step S1: Provide a semiconductor layer 1, and form a plurality of trenches 2 arranged at intervals in the horizontal direction in the semiconductor layer 1. The trenches 2 open from the top surface of the semiconductor layer 1 and extend downward.

[0119] As an example, the semiconductor layer 1 can be a single-layer structure or a multi-layer structure. For example, it can be a single substrate or a stacked structure consisting of a single substrate and an epitaxial layer thereon. The material, doping type, and doping concentration of the substrate and / or epitaxial layer can be selected as needed, without excessive limitations. For example, the substrate material can be selected from silicon, germanium-silicon, III-V compound semiconductors, silicon carbide, or other suitable semiconductor materials, and its doping type can be N-type or P-type. In this embodiment, the semiconductor layer 1 is exemplified by N-type doped silicon.

[0120] As an example, such as Figure 6 As shown, a mask layer 17 is first deposited on the semiconductor layer 1. The mask layer 17 can be selected from silicon oxide, silicon nitride or other suitable material layers.

[0121] like Figure 7 As shown, openings are formed in the mask layer 17 using semiconductor patterning processes such as photolithography and etching, and the semiconductor layer 1 is etched based on the mask layer 17 with openings to obtain the trench 2. The depth of the trench 2 can be set according to specific device performance requirements.

[0122] Please see again Figures 8-9 S2 is performed: a first isolation layer 6 and a shielding gate polysilicon 3 are formed in the trench 2, and the inner wall of the trench 2 and the shielding gate polysilicon 3 are separated by the first isolation layer 6.

[0123] As an example, the first isolation layer 6 can be made of silicon oxide or other suitable insulating material, wherein the first isolation layer 6 acts as a field oxide layer for electrically isolating the semiconductor layer 1 from the shielding gate polysilicon 3.

[0124] As an example, such as Figure 8 As shown, the mask layer 17 is first removed (see...) Figure 7 Then, a first oxide layer 24 is grown and a first polysilicon layer 25 is deposited. The first oxide layer 24 covers the sidewalls and bottom surface of the trench 2 and the upper surface of the semiconductor layer 1. The first polysilicon 12 fills the remaining space in the trench 2 and covers the upper surface of the portion of the first oxide layer 24 located outside the trench 2.

[0125] like Figure 9 As shown, the first polysilicon layer 25 is planarized until the upper surface of the first polysilicon layer 25 is flush with or approximately flush with the upper surface of the semiconductor layer 1. The first polysilicon layer 25 in the preset area is etched back using semiconductor patterning processes such as photolithography and etching to obtain the shielding gate polysilicon 3 located in the trench 2. The top surface of the shielding gate polysilicon 3 is lower than the top surface of the semiconductor layer 1.

[0126] As an example, when the first polysilicon layer 25 in the preset area is etched back using semiconductor patterning processes such as photolithography and etching, a portion of the first polysilicon layer 25 in the trench 2 is shielded by photoresist or other mask layers and is not etched. The top surface of this un-etched portion of the first polysilicon layer 25 is still flush or approximately flush with the upper surface of the semiconductor layer 1, serving as the lead-out portion of the shielding gate polysilicon 3. Subsequently, the shielding gate polysilicon 3 is electrically connected to the source metal line through this lead-out portion and the contact hole located on the lead-out portion.

[0127] Specifically, the portion of the first oxide layer 24 located between the inner wall of the trench 2 and the shielding gate polysilicon 3 serves as at least part of the first isolation layer 6.

[0128] Please see again Figure 10 and Figure 11Steps S3 and S4 are performed: a second isolation layer 7, a gate dielectric layer 9, and a gate polysilicon 5 are formed in the trench 2. The second isolation layer 7 covers the upper surface of the shielding gate polysilicon 3. The gate polysilicon 5 and the shielding gate polysilicon 3 are separated by the second isolation layer 7. The gate polysilicon 5 and the inner wall of the trench 2 are separated by the gate dielectric layer 9.

[0129] As an example, the second isolation layer 7 can be made of silicon oxide or other suitable insulating materials, wherein the second isolation layer 7 is used to electrically isolate the gate polysilicon 5 from the shielding gate polysilicon 3; the gate dielectric layer 9 can be made of silicon oxide or other suitable materials, and its thickness can be set according to the specific device performance requirements.

[0130] As an example, such as Figure 10 As shown, a second oxide layer 26 is first formed in the trench 2 and on the upper surface of the first oxide layer 24 outside the trench 2 using high-density plasma chemical vapor deposition (HDP CVD). Then, the second oxide layer 26 is planarized by chemical mechanical polishing (CMP) until the upper surface of the second oxide layer 26 is flush or approximately flush with the upper surface of the semiconductor layer 1. At this time, the portion of the first oxide layer 24 located outside the trench 2 is also removed.

[0131] like Figure 11 As shown, semiconductor processes such as coating, exposure, development, and wet etching are used to etch back the second oxide layer 26 to a preset thickness to obtain the second isolation layer 7. At this time, a portion of the first oxide layer 24 is also etched back to expose a portion of the side of the trench 2. The remaining first oxide layer 24 serves as the first isolation layer 6. Then, the photoresist is removed, and a third oxide layer 27 is grown using thermal oxidation or other suitable methods. In this embodiment, the third oxide layer 27 is grown on the exposed sidewall of the trench 2 and the upper surface of the semiconductor layer 1. The portion of the third oxide layer 27 grown on the exposed sidewall of the trench 2 serves as the gate dielectric layer 9. Then, a second polysilicon layer is deposited in the trench 2 and above the semiconductor layer 1, and the second polysilicon layer is etched back until the upper surface of the second polysilicon layer is flush with or approximately flush with the upper surface of the semiconductor layer 1, thereby obtaining the gate polysilicon 5 located in the trench 2.

[0132] It should be noted that the portion of the third oxide layer 27 located on the upper surface of the semiconductor layer 1 can be retained or removed as needed. In this embodiment, the portion of the third oxide layer 27 located on the upper surface of the semiconductor layer 1 is retained to protect the upper surface of the semiconductor layer 1 during subsequent processes.

[0133] Please see again Figures 12-13Then, perform steps S5 and S6: form a groove in the gate polysilicon 5, the groove opens from the top surface of the gate polysilicon and extends downward to divide the gate polysilicon 5 into a middle part 501 and a side part 502, the side part 502 connects the two ends of the middle part 501, and then form a third isolation layer 8 and a regulating gate polysilicon 4 in the groove, the inner wall of the groove and the outer wall of the regulating gate polysilicon 4 are separated by the third isolation layer 8.

[0134] As an example, such as Figure 12 As shown, a mask layer 28 is first deposited on the semiconductor layer 1. The mask layer 28 can be a silicon nitride layer, a silicon oxide layer, or other suitable material layer. Then, semiconductor patterning processes such as photolithography and etching are used to form openings in the mask layer 28.

[0135] like Figure 13 As shown, the gate polysilicon 5 is etched based on the mask layer 28 with openings to obtain the trench. The trench divides the gate polysilicon 5 into a central portion 501 and side portions 502 located at both ends of the central portion 501, making the cross-section of the gate polysilicon 5 U-shaped. Then, a fourth oxide layer is formed on the inner wall of the trench using thermal oxidation or other suitable methods to obtain the third isolation layer 8. Then, a third polysilicon layer is deposited in the trench 2 and above the semiconductor layer 1, and the third polysilicon layer is etched back until the upper surface of the third polysilicon layer is flush with or approximately flush with the upper surface of the semiconductor layer 1, thereby obtaining the adjustment gate polysilicon 4 located in the trench 2. Subsequently, the mask layer 28 is removed.

[0136] Specifically, the depth of the top surface of the regulating gate polysilicon 4 can be adjusted as needed. For example, the top surface of the regulating gate polysilicon 4 can be lower than or flush with the top surface of the side wing portion 502 of the gate polysilicon 5. The thickness of the second isolation layer 7 and the thickness of the third isolation layer 8 in the vertical direction can also be adjusted according to application requirements. For example, the thickness of the second isolation layer 7 in the vertical direction can be greater than the thickness of the third isolation layer 8 in the vertical direction.

[0137] Please see Figure 2Next, step S7 is executed: forming an adjustment metal line 10, a gate metal line 11, a source metal line 12, an adjustment pad 13, a gate pad 14, and a source pad 15 above the semiconductor layer 1. The adjustment metal line 10 is electrically connected to the adjustment gate polysilicon 4, the gate metal line 11 is electrically connected to the gate polysilicon 5, the source metal line 12 is electrically connected to the shielding gate polysilicon 3, the adjustment pad 13 is connected to the adjustment metal line 10, the gate pad 14 is connected to the gate metal line 11, and the source pad 14 is connected to the source metal line 12.

[0138] As an example, a body region (e.g., a P-type doped region) is first formed on the upper surface of the semiconductor layer 1 on both sides of the trench 2 using ion implantation. Then, a source region (e.g., a higher concentration N-type doped region) is formed on the upper surface of the body region using ion implantation. Next, an interlayer dielectric layer is deposited above the semiconductor layer 1, and a first contact hole 18, a second contact hole 19, a third contact hole 20, and a fourth contact hole 21 are formed in the interlayer dielectric layer using semiconductor patterning processes such as photolithography and etching. Then, conductive plugs (e.g., W-plugs) are formed in the first contact hole 18, the second contact hole 19, the third contact hole 20, and the fourth contact hole 21. Finally, a metal layer is formed on the interlayer dielectric layer and patterned to obtain an adjustment metal line 10, a gate metal line 11, a source metal line 12, an adjustment pad 13, a gate pad 14, and a source pad 15. In this embodiment, a drain metal layer (not shown) is also formed on the lower surface of the semiconductor layer 1.

[0139] Specifically, the source metal line 12 is electrically connected to the shielding gate polysilicon 3 through the first contact hole 18 and the polysilicon lead-out portion 16, the regulating metal line 10 is electrically connected to the regulating gate polysilicon 4 through the second contact hole 19, the gate metal line 11 is electrically connected to the gate polysilicon 5 through the third contact hole 20, and the source pad 15 is electrically connected to the source region through the fourth contact hole 21.

[0140] As an example, the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be located in the same metal layer or in different metal layers as needed. The materials of the adjustment metal line 10, the gate metal line 11, the source metal line 12, the adjustment pad 13, the gate pad 14, and the source pad 15 can be aluminum or other suitable conductive metal materials.

[0141] Please see Figure 3In some embodiments, the regulating pad 13 and the gate pad 14 are electrically connected by a bonding wire 22, thereby the regulating gate polysilicon 4 is shorted to the gate pad 14 in sequence through the second contact hole 19, the regulating metal line 10, the regulating pad 13, and the bonding wire 22. In this case, in the fabricated multifunctional SGT power device, the regulating gate polysilicon 4 acts as part of the gate polysilicon. The device is similar to a device using a planar gate polysilicon, with a small gate-source capacitance Cgs, enabling fast switching and making it suitable for high-frequency applications.

[0142] Please see Figure 4 In other embodiments, the regulating pad 13 and the source pad 15 are electrically connected by a bonding wire 23, thereby shorting the regulating gate polysilicon 4 to the source pad 15 in sequence through the second contact hole 19, the regulating metal line 10, the regulating pad 13, and the bonding wire 23. In this case, in the fabricated multifunctional SGT power device, the regulating gate polysilicon 4 constitutes part of the source polysilicon. The device gate-source capacitance Cgs includes not only the capacitance between the gate polysilicon 5 and the shielding gate polysilicon 3, but also the capacitance between the gate polysilicon 5 and the regulating gate polysilicon 4. This results in a larger device gate-source capacitance Cgs, which can reduce switching oscillation, enhance shock resistance, and reduce the ratio of reverse transfer capacitance to input capacitance Crss / Ciss. This makes it suitable for applications in battery management systems (BMS) and motor control, etc.

[0143] As described above, the fabrication method of the multifunctional SGT power device in this embodiment is simple. The trench of the fabricated multifunctional SGT power device not only has gate pads and source pads, but also adjustment pads. The device trench not only has gate polysilicon and shielding gate polysilicon, but also adjustment gate polysilicon. By flexibly using the bonding method of the adjustment pads, devices with different performance can be realized.

[0144] In summary, the multifunctional SGT power device of the present invention has an adjustment pad, a gate pad, and a source pad. The device trench contains an adjustment gate polysilicon, a gate polysilicon, and a shielding gate polysilicon. The adjustment gate polysilicon is located above the shielding gate polysilicon. The gate polysilicon includes a central portion and side portions. The central portion is located between the adjustment gate polysilicon and the shielding gate polysilicon, and the side portions are located on both sides of the adjustment gate polysilicon and connected to the central portion. Different bonding methods can achieve devices with different performance characteristics. When the adjustment pad and the gate pad are short-circuited by a bonding wire, the device's gate-source capacitance Cgs is small, enabling fast switching and suitable for high-frequency applications. When the adjustment pad and the source pad are short-circuited by a bonding wire, the device's gate-source capacitance Cgs is large, reducing switching oscillations, providing strong shock resistance, and lowering the ratio of reverse transfer capacitance to input capacitance (Crss / Ciss), making it suitable for applications in battery management systems (BMS) and motor control. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0145] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A multifunctional SGT power device, characterized in that, include: Semiconductor layer; Multiple trenches are located in the semiconductor layer and are spaced apart in the horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward; A shielding gate polysilicon, a regulating gate polysilicon, and a gate polysilicon are located in the trench. The regulating gate polysilicon is located above the shielding gate polysilicon. The gate polysilicon includes a middle portion and side portions. The middle portion is located between the regulating gate polysilicon and the shielding gate polysilicon. The side portions are located on both sides of the regulating gate polysilicon and are connected to the middle portion. The system comprises a first isolation layer, a second isolation layer, a third isolation layer, and a gate dielectric layer. The first isolation layer is located between the inner wall of the trench and the outer wall of the shielding gate polysilicon. The second isolation layer is located between the shielding gate polysilicon and the gate polysilicon. The third isolation layer is located between the adjustment gate polysilicon and the gate polysilicon. The gate dielectric layer is located between the inner wall of the trench and the outer wall of the gate polysilicon. An adjustment metal line, a gate metal line, and a source metal line are located above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, and the source metal line is electrically connected to the shielding gate polysilicon. An adjustment pad, a gate pad, and a source pad are located above the semiconductor layer. The adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

2. The multifunctional SGT power device according to claim 1, characterized in that: The multiple trenches are spaced apart in a first horizontal direction and extend in a second horizontal direction perpendicular to the first horizontal direction. The shielded gate trench power device also includes a polysilicon lead-out portion located in the trench. The polysilicon lead-out portion is located at both ends of the shielded gate polysilicon in the second horizontal direction and is connected to the shielded gate polysilicon. The top surface of the polysilicon lead-out portion is higher than the top surface of the shielded gate polysilicon.

3. The multifunctional SGT power device according to claim 2, characterized in that: The multifunctional SGT power device further includes a first contact hole disposed on the polysilicon lead-out portion, a second contact hole disposed on the regulating gate polysilicon, and a third contact hole disposed on the gate polysilicon. The source metal line is electrically connected to the shielding gate polysilicon through the first contact hole and the polysilicon lead-out portion. The regulating metal line is electrically connected to the regulating gate polysilicon through the second contact hole. The gate metal line is electrically connected to the gate polysilicon through the third contact hole.

4. The multifunctional SGT power device according to claim 1, characterized in that: The multifunctional SGT power device further includes a body region, a source region, and a fourth contact hole. The body region is located on the upper surface of the semiconductor layer on both sides of the trench. The source region is located on the upper surface of the body region. The fourth contact hole is located on the source region. The source pad is electrically connected to the source region through the fourth contact hole.

5. The multifunctional SGT power device according to claim 1, characterized in that: The adjustment pad is electrically connected to the gate pad, or the adjustment pad is electrically connected to the source pad.

6. A method for fabricating a multifunctional SGT power device, characterized in that, Includes the following steps: A semiconductor layer is provided, in which a plurality of trenches are formed at intervals in a horizontal direction, the trenches opening from the top surface of the semiconductor layer and extending downward therefrom; A first isolation layer and a shielding gate polysilicon are formed in the trench, and the inner wall of the trench and the shielding gate polysilicon are separated by the first isolation layer; A second isolation layer is formed in the trench, the second isolation layer covering the upper surface of the shielding gate polysilicon; A gate dielectric layer and a gate polysilicon are formed in the trench, the gate polysilicon and the shielding gate polysilicon are separated by a second isolation layer, and the gate polysilicon and the inner wall of the trench are separated by the gate dielectric layer. A groove is formed in the gate polysilicon, the groove opening from the top surface of the gate polysilicon and extending downward to divide the gate polysilicon into a middle portion and a side portion, the side portion connecting the two ends of the middle portion; A third isolation layer and a regulating gate polysilicon are formed in the groove, and the inner wall of the groove and the outer wall of the regulating gate polysilicon are separated by the third isolation layer; An adjustment metal line, a gate metal line, a source metal line, an adjustment pad, a gate pad, and a source pad are formed above the semiconductor layer. The adjustment metal line is electrically connected to the adjustment gate polysilicon, the gate metal line is electrically connected to the gate polysilicon, the source metal line is electrically connected to the shield gate polysilicon, the adjustment pad is connected to the adjustment metal line, the gate pad is connected to the gate metal line, and the source pad is connected to the source metal line.

7. The method for fabricating the multifunctional SGT power device according to claim 6, characterized in that, The plurality of said trenches are arranged at intervals in a first horizontal direction and all extend in a second horizontal direction perpendicular to the first horizontal direction. The method for manufacturing the multifunctional shielded gate trench type power device further includes the following steps: Polysilicon leads are formed at both ends of the shielding gate polysilicon in a second horizontal direction. The polysilicon leads are located in the trench and the top surface of the polysilicon leads is higher than the top surface of the shielding gate polysilicon.

8. The method for fabricating the multifunctional SGT power device according to claim 7, characterized in that, It also includes the following steps: The solid regions are formed on the upper surface of the semiconductor layer on both sides of the trench; The source region is formed on the upper surface layer of the body region; An interlayer dielectric layer is formed above the semiconductor layer; A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed in the interlayer dielectric layer. The first contact hole is located on the polysilicon lead-out portion, the second contact hole is located on the adjustment gate polysilicon, the third contact hole is located on the gate polysilicon, and the fourth contact hole is located on the source region. Conductive plugs are formed in the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole; The source metal line is electrically connected to the shielding gate polysilicon through the first contact hole and the polysilicon lead-out portion; the adjustment metal line is electrically connected to the adjustment gate polysilicon through the second contact hole; the gate metal line is electrically connected to the gate polysilicon through the third contact hole; and the source pad is electrically connected to the source region through the fourth contact hole.

9. The method for fabricating the multifunctional SGT power device according to claim 6, characterized in that: The top surface of the regulating gate polysilicon is lower than or flush with the top surface of the side wing.

10. The method for fabricating the multifunctional SGT power device according to claim 6, characterized in that: The fabrication method of the multifunctional SGT power device further includes the step of forming a bonding wire, one end of which is connected to the adjustment pad and the other end of which is connected to the gate pad or the source pad.

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