Methods and apparatus for facilitating de-rate matching of bits of transmission symbols formed after a rate matching process

Abstract

The present disclosure proposes a method used by a receiver to facilitate de-rate matching bits of a symbol formed after a rate matching process from a transmitter, wherein the transmitter selects Z bits from channel coded bits and then generates E bits by concatenating the Z bits and their copies for the rate matching process. The method comprises: demodulating the symbol to obtain E soft bits corresponding to the E bits; zeroing values of Z consecutive locations of a memory, wherein the Z consecutive locations correspond to bit locations of the Z bits; writing the E soft bits into a buffering device; for each soft bit in the E soft bits in the buffering device, directly adding a value of the soft bit and a value of one location of the Z consecutive locations and storing the addition result back to the location, wherein one bit in the E bits corresponding to the soft bit is one bit in the Z bits corresponding to the location or is one copy of the bit in the Z bits; and recovering the Z bits from final results of the Z consecutive locations. The method facilitates de-rate matching by reducing its storage usage and processing delay.

Description

Technical Field

[0001] The non-limiting and exemplary embodiments of this disclosure relate to the technical field of mobile communication networks, and in particular to methods and apparatus for facilitating de-rate matching of bits of transmission symbols formed after a rate matching process in a mobile communication network. Background Technology

[0002] This section introduces aspects that may help in a better understanding of this disclosure. Therefore, the statements in this section should be understood in this context and should not be construed as an admission of content that is in the prior art or not in the prior art.

[0003] In today's mobile communication networks, rate matching is frequently used to match coded bits with the resources allocated for transmission. Rate matching can occur within the physical layer of the mobile communication network.

[0004] For example, a typical processing flow of the physical layer of a fifth-generation (5G) mobile communication network is as follows: Figure 1 As shown. This processing flow follows a structure similar to that of fourth-generation (4G) mobile communication networks.

[0005] from Figure 1 As can be seen, within each transmission time interval (TTI), a dynamically sized transport block is transmitted from the MAC layer to the physical layer. Cyclic Redundancy Check (CRC) is added to each transport block for error detection, followed by error correction coding using Low Density Parity Check (LDPC) codes. Rate matching, including physical layer hybrid ARQ (Automatic Repeat Request) functionality, adapts the number of coded bits to the scheduling resources. These bits are scrambled and fed to the modulator, and finally, the modulated symbols are mapped to physical resources, including the spatial domain.

[0006] In 5G networks, the LDPC encoder is defined as having a certain block size (base). Figure 1 It could be 8424 bits, base Figure 2 (Possibly 3840 bits). To handle transport blocks larger than this, block segmentation is used, where the transport block (including CRC) is divided into multiple equal-sized blocks, such as... Figure 2 As shown.

[0007] from Figure 2 As can be seen, code block segmentation also means that an additional CRC (different from the transport block CRC mentioned above) must be calculated and appended for each code block. In the case of single code block transmission, no additional code block CRC is appended.

[0008] Rate matching is performed separately for each code block. First, some or all of the coded bits from the channel coding are written to a circular buffer. For example, some systematic bits from the channel coding may be punctured. The proportion of punctured systematic bits may be relatively high, up to one-third of the systematic bits, depending on the code block size. The remaining coded bits are written to the circular buffer, starting with the unpunctured systematic bits, followed by the parity bits, such as... Figure 3 As shown. The selection of bits to be transmitted is based on the number of bits required to be read from the circular buffer, where the exact set of bits to be transmitted depends on the redundancy version (RV) corresponding to different starting positions (or different offsets) in the circular buffer. Therefore, by selecting different redundancy versions, different coded bit sets representing the same set of information bits can be generated, which is used when implementing hybrid ARQ with increasing redundancy. The starting point in the circular buffer is defined such that RV0 and RV3 are both self-decoding, i.e., including the system bits in a typical scenario. This is also... Figure 3 The reason RV3 is located after the "nine o'clock" position is to allow more system bits to be included in the transmission. It should be noted that while bit selection in 5G networks uses the offset corresponding to RV, other types of offsets or no offset at all can be used for bit selection in other mobile communication networks.

[0009] The rate matching process may also include a step of interleaving bits using a block interleaver and collecting bits from each code block. Figure 4 This illustrates an example of interleaved bits, where bits generated by bit selection are written row-by-row to a block interleaver and read column-by-column. The number of rows in the interleaver is determined by the modulation order, so bits in one column correspond to one modulation symbol. This results in system bits being distributed across modulation symbols, thereby improving communication performance.

[0010] The rate matching and physical layer hybrid ARQ function serves two purposes: extracting an appropriate number of coded bits to match the resources allocated to the transmission, and generating different redundant versions of the hybrid ARQ protocol. For example, the number of bits transmitted on the PDSCH or PUSCH depends on a variety of factors, including not only the number of resource blocks and scheduled OFDM symbols, but also the number of overlapping resource elements used for other purposes such as reference signals, control channels, or system information. In the downlink, it is also possible to define reserved resources as a tool to provide future compatibility, which affects the number of resource elements available for the PDSCH.

[0011] In the receiver, soft combining is a crucial component of hybrid ARQ functionality. A soft value representing the received coded bits is buffered. If a retransmission occurs, the buffered bits are combined with the retransmitted coded bits for decoding. Besides accumulating the received Eb / N0 gain, using different coded bits in different transmission attempts yields additional parity bits. Soft combining results in a lower coding rate, but achieves a corresponding coding gain.

[0012] Figure 5 This displays an example block diagram illustrating physical layer processing. From Figure 5 The right half shows that the transmitter generates a code block with X bits. Then, the transmitter places the Y coded bits obtained after channel coding into a circular buffer of length Y bits. It should be noted that the Y coded bits can be a subset of all the coded bits obtained after channel coding as described above, or they can include some padding bits from code block segmentation. Next, E bits are selected from the Y bits in the circular buffer, for example, starting from the position corresponding to the offset, skipping the padding bits. Since the selected E bits may be more than the Y bits to match the resources allocated for transmission, and the selection is performed on the circular buffer, selecting E bits can be seen as selecting Z bits (starting from the position corresponding to the offset), which may be all the bits in the Y bits except for the padding bits. Then, the Z bits and their copies are concatenated to generate the E bits (note that the number of copies is not necessarily an integer multiple of Z). The E bits will be interleaved and modulated (in... Figure 5 The right half (not shown) is used to generate modulation symbols, which are then transmitted to the receiver. After demodulating the received modulation symbols to obtain E soft bits representing E bits, the receiver performs rate matching on the E soft bits, including de-interleaving and de-bit selection, to recover the Z bits. The receiver can then use the Z bits to recover the Y bits and decode the Y bits to recover the X bits of the code block.

[0013] In existing technologies, the step-by-step operations of deinterlacing are as follows: Figure 6 As shown. Figure 6 As shown, in step 1, the receiver stores the demodulated E soft bits column by column into the first memory, where the number of rows used to store the soft bits in the first memory is Q, which is the number of bits that make up a modulation symbol. In step 2, the receiver reads the E soft bits row by row from the first memory into the second memory for de-bit selection.

[0014] In existing technologies, the step-by-step operation of bit selection is as follows: Figure 7 As shown. Figure 7As shown, in step 3, the receiver reads the E soft bits from the second memory and, starting from the starting position corresponding to the offset used in the transmitter to select the Z bits, reassembles the E soft bits row by row into the third memory. The number of columns reassembled is Z, therefore the number of rows reassembled is ceil((E+K) / Z), where ceil(X) is a function that maps the real number X to the smallest integer greater than or equal to X. Through reassembly, the first soft bit in a column corresponds to a bit in the Z bits, and each other soft bit in the same column corresponds to a copy of that bit in the Z bits. Furthermore, the receiver fills the reassembled E soft bits with zeros before and after them, as shown below. Figure 7 As shown. In step 4, the receiver combines the soft bits of each column in the third memory by averaging them to generate the Z soft bit, which is stored in the fourth memory and can be used to recover the Z bit. Summary of the Invention

[0015] However, the inventors of this invention have discovered that the step-by-step operation of rate matching in the prior art requires high storage and high processing latency, which may reduce resource utilization efficiency and communication speed, thereby degrading the user experience. Specifically, the storage and latency required for each step in steps 1-4 are shown in Table 1 below. Therefore, for all four steps, the total storage required is (E+E+Z×ceil((E+K) / Z)+Z)×L bytes (assuming L is the number of bytes occupied by each E soft bit), and the total latency required is T1+T2+T3+T4.

[0016]

[0017]

[0018] Table 1 shows the storage and latency required for each step 1-4.

[0019] To address or mitigate the aforementioned problems, which is one of the objectives of this disclosure, the inventors have conceived a solution that generates Z soft bits by directly adding the demodulated E soft bits in a specific manner, without performing steps 2 and 3 as described above. This reduces the storage requirements and processing latency needed for rate matching resolution, thereby facilitating rate matching resolution. This solution can be further accelerated by introducing pipelined processing.

[0020] According to a first aspect of this disclosure, this objective is achieved by a method used by a receiver that facilitates de-rate matching of bits of a symbol formed after a rate matching process from a transmitter, wherein the transmitter selects Z bits from channel-coded bits and then generates E bits by concatenating the Z bits and their copies to perform the rate matching process, forming a symbol per Q bits. The method includes: demodulating the symbol to obtain E soft bits corresponding to the E bits; setting the values ​​of Z consecutive locations in a memory to zero, wherein the Z consecutive locations correspond to bit positions of the Z bits; writing the E soft bits into a buffer; for each soft bit in the buffer, directly adding the value of the soft bit to the value of one of the Z consecutive locations, and storing the result back into that location, wherein the bit in the E bits corresponding to that soft bit is either a bit in the Z bits corresponding to that location or a copy of that bit in the Z bits; and recovering the Z bits from the final result of the Z consecutive locations.

[0021] According to a second aspect of this disclosure, this objective is achieved by a receiver for facilitating derate-matching of bits of a symbol formed after a rate-matching process from a transmitter, wherein the transmitter selects Z bits from channel-coded bits and then generates E bits by concatenating the Z bits and their copies for the rate-matching process, forming a symbol per Q bits. The receiver includes: a demodulator for demodulating the symbol to obtain E soft bits corresponding to the E bits; a memory having Z consecutive locations corresponding to bit positions of the Z bits, wherein the values ​​of the Z consecutive locations are cleared before the following addition; a buffer for writing the E soft bits; an adder for directly adding the value of each soft bit in the buffer to the value of one of the Z consecutive locations and storing the result back at that location, wherein the bit in the E bits corresponding to that soft bit is either the bit in the Z bits corresponding to that location or a copy of that bit in the Z bits; and a restorer for recovering the Z bits from the final result of the Z consecutive locations.

[0022] According to a third aspect of this disclosure, the objective is achieved by a receiver comprising: a processor; and a memory storing instructions which, when executed by the processor, cause the receiver to perform the method according to the first aspect.

[0023] According to a fourth aspect of this disclosure, this objective is achieved by a machine-readable medium storing instructions that, when executed on a receiver, cause the receiver to perform the method according to the first aspect.

[0024] The solution of this invention promotes solution rate matching by reducing its storage usage and processing latency, thereby improving resource utilization efficiency and communication speed, and thus improving user experience. Attached Figure Description

[0025] The above and other aspects, features, and benefits of this disclosure will become clearer from the following detailed description with reference to the accompanying drawings, in which the same reference numerals or letters are used to indicate the same or equivalent elements. The drawings are illustrated to facilitate a better understanding of embodiments of the invention and are not necessarily drawn to scale, wherein:

[0026] Figure 1 This is a typical processing flow of the physical layer of a 5G mobile communication network;

[0027] Figure 2 This is a schematic diagram of code block segmentation and code block CRC appending;

[0028] Figure 3 This diagram shows an exemplary cyclic buffer used for incremental redundancy;

[0029] Figure 4 Show an example of interleaved bits;

[0030] Figure 5 This is an example block diagram reflecting physical layer processing;

[0031] Figure 6 This demonstrates the step-by-step deinterlacing operation in the prior art;

[0032] Figure 7 This demonstrates the step-by-step operation of bit selection in the prior art;

[0033] Figure 8 A flowchart showing the method of this disclosure used by the receiver is shown;

[0034] Figure 9 This shows the relationship between the position indices in the Z consecutive positions of this disclosure and the soft bit indices in the E soft bit sequence;

[0035] Figure 10 This disclosure shows an example of pipelined processing;

[0036] Figure 11 This disclosure shows three scenarios for accessing a memory containing Z consecutive locations in one embodiment of the present disclosure;

[0037] Figure 12 Exemplary embodiments of the memory disclosed herein are shown;

[0038] Figure 13 This is a schematic block diagram of the receiver disclosed herein;

[0039] Figure 14 This is another schematic block diagram of the receiver disclosed herein. Detailed Implementation

[0040] Embodiments of the invention will now be described more fully with reference to the accompanying drawings. However, the embodiments herein may be embodied in many different forms and should not be construed as limiting the scope of the appended claims.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The singular forms “a” and “the” as used herein also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and “including”, as used herein, specifically describe the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0042] Furthermore, the use of sequential terms such as “first,” “second,” and “third” to modify an element in this paper does not imply any priority, order, or sequence of one element relative to another, nor does it imply the chronological order of the steps of a method. Rather, they are merely labels used to distinguish elements with a specific name from another element with the same name (but using sequential terms) to differentiate these elements.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood. It should also be understood that the terms used herein are to be interpreted as having the meaning consistent with their meaning in this specification and the relevant technical context, and are not to be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0044] Figure 8 A flowchart of a method 800 used by a receiver to facilitate rate matching of bits formed after a rate matching process from a transmitter is shown. The transmitter selects Z bits from channel-coded bits and then generates E bits by concatenating the Z bits and their copies for the rate matching process, with each Q bits forming a symbol. Method 800 includes: step 801, demodulating the symbol to obtain E soft bits corresponding to the E bits; step 802, setting the values ​​of Z consecutive locations in a memory to zero, where the Z consecutive locations correspond to bit positions of the Z bits; step 803, writing the E soft bits to a buffer; step 804, for each soft bit in the buffer, directly adding the value of the soft bit to the value of one of the Z consecutive locations, and storing the result back at that location, where the bit in the E bits corresponding to the soft bit is either the bit in the Z bits corresponding to that location, or a copy of that bit in the Z bits; and step 805, recovering the Z bits from the final result of the Z consecutive locations.

[0045] Now, further embodiments of the method will be described in conjunction with receivers in 5G networks. It is understood that although the embodiments described herein are in the context of 5G networks, this embodiment can also be applied to receivers in other mobile communication networks if the rate matching mechanism in other mobile communication networks has the same problem. It should also be understood that although specific terminology is used in the embodiments, these specific terms can refer to different entities in different contexts. For example, in the downlink, the term "transmitter" can refer to, for example, an access point, base station, macro base station, femtobase station, NodeB (NB), eNodeB (eNB), gNodeB (gNB), etc., and "receiver" can refer to, for example, a user equipment (UE), user terminal, station, terminal, terminal node, etc.; while in the uplink, the term "transmitter" herein can refer to, for example, a user equipment (UE), user terminal, station, terminal, terminal node, etc., and "receiver" can refer to, for example, an access point, base station, macro base station, femtobase station, NodeB (NB), eNodeB (eNB), gNodeB (gNB), etc.

[0046] As mentioned above Figure 6 and Figure 7 The description states that in the prior art de-rate matching, after the receiver deinterleaves the demodulated E soft bits, it stores the E soft bits in memory, reads them from memory, and reassembles them row by row into another memory starting from a starting position corresponding to an offset (which is used to select Z bits from the transmitter). Thus, the first soft bit in a column corresponds to a bit in the Z bits, and each other soft bit in the same column corresponds to a copy of that bit in the Z bits. The soft bits in each column are then combined by taking their average to generate the Z soft bits.

[0047] Conversely, in the method of this disclosure, Z soft bits are generated by directly adding demodulated E soft bits in a specific manner without performing deinterleaving and recombination, thereby facilitating rate matching. Specifically, if the transmitter selects Z bits from the channel-coded bits and then generates E bits by concatenating the Z bits and their copies for a rate matching process, then, according to this disclosure, the operation for facilitating rate matching of the receiver for symbol bits formed after the rate matching process from the transmitter includes: demodulating the symbols to obtain E soft bits corresponding to the E bits; setting the values ​​of Z consecutive locations in the memory to zero, where the Z consecutive locations correspond to bit positions of the Z bits; writing the E soft bits to a buffer; and for each soft bit in the E soft bits in the buffer, directly adding the value of that soft bit to the value of one of the Z consecutive locations, and storing the result back at that location, provided that the bit in the E bits corresponding to that soft bit is either a bit in the Z bits corresponding to that location or a copy of that bit in the Z bits. According to this disclosure, direct addition will ensure that for each bit in the Z bits, only the soft bits corresponding to it or its copies are added together, thus eliminating the need for separate deinterleaving and recombination.

[0048] In one embodiment, assuming i represents the index of a soft bit in the sequence of E soft bits, and K represents the offset used when selecting Z bits during rate matching, then the condition can be guaranteed by the relationship between the position indices in the Z consecutive positions and the soft bit indices in the sequence of E soft bits, i.e., the position index associated with the addition of soft bits in the Z consecutive positions is f – floor(f / Z) × Z, where f = K + (i - floor(i / Q) × Q) × (E / Q) + floor(i / Q), where floor(X) is a function that maps a real number X to the largest integer less than or equal to X.

[0049] Reference Figure 9 This allows for a better understanding of the relationship between the two indexes mentioned above. For example... Figure 9 As shown, when the sequence of E soft bits (in) Figure 9 When the "interleaved soft bit sequence" (labeled as "interleaved soft bit sequence") is arranged column-wise into a matrix of Q rows and E / Q columns, for the soft bit at index i in the interleaved soft bit sequence, there will be a total of (i - floor(i / Q) × Q) × (E / Q) soft bits at the top of that soft bit in the matrix, and floor(i / Q) soft bits to the left of that soft bit in the same row. On the other hand, the E soft bits in the matrix can also be regarded as another sequence formed after deinterleaving (in... Figure 9The sequence is labeled as the "deinterleaved soft bit sequence". Here, the E soft bits are formed row-by-row according to the deinterleaving principle. Therefore, in the deinterleaved soft bit sequence, this soft bit should have an index (i - floor(i / Q) × Q) × (E / Q) + floor(i / Q). It should be noted that although... Figure 9 The image shows a "deinterleaved soft bit sequence" for illustration, but the method of the present invention does not perform deinterleaving separately. Furthermore, in a sequence including E soft bits and padding zeros (if the E soft bits are rearranged) (in... Figure 9 The sequence is labeled as "recombined soft bit sequence", and the index of the soft bit is ( Figure 9 The subscript "f" should be: K + (i - floor(i / Q) × Q) × (E / Q) + floor(i / Q). It should be noted that although... Figure 9 The text shows "reconstructing the soft bit sequence" for illustration, but the method of this invention does not perform reconstruction separately. Finally, since the index of the column containing the soft bit with index f in the reconstructed soft bit sequence is f-floor(f / Z)×Z, the index of the position where the soft bit is added in Z consecutive positions is also f-floor(f / Z)×Z.

[0050] The method disclosed herein can further accelerate the solution rate matching by incorporating pipelined processing into the solution rate matching. For example, in one embodiment, the E soft bits are divided into multiple parts, and the buffering device includes two buffers. The method of the present invention pipelines the writing and addition by: alternately writing (i.e., storing) different parts of the multiple parts into one of the two buffers in writing order; if the part is not the first part of the multiple parts, simultaneously reading the soft bits of the preceding part from the other of the two buffers in reading order to add the soft bits of the preceding part; reading the soft bits of the last part of the multiple parts from one of the two buffers (which stores the last part) in reading order to add the soft bits of the last part. It should be noted that in this embodiment, the writing order and the reading order can be any order that is convenient for processing, because the method of the present invention is concerned with the above-mentioned conditions regarding the soft bits and Z consecutive positions, rather than these two orders.

[0051] Figure 10 An example of pipelined processing is shown. As shown, the E soft bits are divided into multiple parts, each part having P×Q soft bits, treated as a Q-row, P-column matrix. The buffering devices include buffer A and buffer B. The pipelined processing for writing and adding includes: alternately writing (i.e., storing) different parts of the multiple parts as Q-row, P-column soft bits in column-by-column order into one of buffers A and B, if the part is not the first part of the multiple parts (in... Figure 10 In the example, if the first part is written into buffer A), then Q rows and P columns of soft bits of the previous part before this part are read in row-by-row order from the other buffer between buffer A and buffer B, and the soft bits of the previous part are added together; Q rows and P columns of soft bits of the last part of multiple parts are read row by row from the buffer (in the example of Figure 10 , buffer B stores the last part) that stores the last part between buffer A and buffer B to add together the soft bits of the last part.

[0052] To improve efficiency, considering that some memory chips can only read and write in units of blocks, the direct addition process of multiple soft bits involved in the present invention (including the execution of direct addition and the storage of its result) can be carried out once. For example, in a further embodiment of the above example, the width W (bytes) of the memory containing Z consecutive positions is set to an integer multiple of P×L bytes (where L is the number of bytes occupied by each E soft bit, as described above), which facilitates the processing of direct addition involving reading P soft bits in a row from buffer A or buffer B at one time in some cases. However, it should be noted that W and P can be any arbitrary numbers suitable for processing.

[0053] In the above further embodiment, if the direct addition involves P soft bits at one time, there are three cases of accessing the memory containing Z consecutive positions, as Figure 11 shown. As can be seen from Figure 11 , Z consecutive positions are regarded as part of a matrix with a memory width of W (bytes) (W = P×L, as described above), although several positions after the Z consecutive positions at the end of the matrix may be invalid (because Z×L is not necessarily an integer multiple of W). If the index of the first soft bit among P soft bits is g, then the number of rows above the first soft bit in the matrix is h = floor((g×L) / W). Therefore, for the direct addition process at one time, (1) in the case of g×L = h×W and g×L + W <= Z×L, only one row in the matrix needs to be accessed (marked as "Case 1" in Figure 11 ), (2) in the case of h×W < g×L and g×L + W <= Z×L, two consecutive rows in the matrix need to be accessed (marked as "Case 2" in Figure 11 ), (3) in the case of g×L + W > Z×L, the last two rows and the first row in the matrix need to be accessed (marked as "Case 3" in Figure 11 ).

[0054] In view of the above three situations, in an exemplary implementation of the memory in another embodiment described above, the memory is implemented using two blocks of RAM and a register, where one RAM serves as a storage area consisting of all even-numbered rows of the memory, the other RAM serves as a storage area consisting of all odd-numbered rows of the memory, and the register serves as a storage area consisting of the first row of the memory, as shown above. Figure 12 As shown. For a block RAM of the implementation portion of the memory, each row of the aforementioned matrix in the block RAM has a corresponding address, and accessing that address may result in an access to the entire row. Therefore, in this implementation, for the second case ( Figure 11 In case 2), it is possible to access two consecutive addresses relative to two blocks of RAM to simultaneously access two consecutive rows in the matrix. For the third case (… Figure 11 In "Case 3" in the example, the last two addresses of the two RAM blocks are accessed simultaneously to access the last two rows of the matrix and the first row of the matrix from the register at the same time, thereby improving the processing speed.

[0055] After processing all the direct sums of the E soft bits, the Z bits can be recovered from the final result of the Z consecutive positions. Since a soft bit is a value representing the probability that the corresponding bit is 1 or 0, the sum of the soft bit values ​​corresponding to a bit or a copy of that bit can also be regarded as a value representing the probability that the bit is 1 or 0; in other words, the sum can also be regarded as the soft bit of that bit. Therefore, in one embodiment, the final result of the Z consecutive positions can be regarded as the soft bits of the Z bits respectively to recover the Z bits accordingly. In another embodiment, the final result of the Z consecutive positions is normalized by dividing each of these final results by ceil(E / Z) to be regarded as the soft bits of the Z bits respectively to recover the Z bits accordingly, where ceil(X) is a function that maps the real number X to the smallest integer greater than or equal to X, as described above.

[0056] In another embodiment, 1 / ceil(E / Z) is quantized by approximating it as the sum of negative powers of 2. This quantization speeds up the normalization process while maintaining sufficient accuracy for normalization. Table 2 shows an example of quantizing 1 / ceil(E / Z).

[0057]

[0058] Table 2 shows an example of quantizing 1 / ceil (E / Z).

[0059] Compared to the step-by-step operation of rate matching in the prior art, the method of the present invention requires less storage and processing latency. For example, in the pipelined processing example above, the storage and processing latency required for pipelined processing are 2×P×Q×L bytes and T1 (as described in Table 1 above), respectively, for writing E soft bits (writing to buffers A and B); the storage and processing latency required for the direct addition of E soft bits are Z×L bytes and T4 (as described in Table 1 above), respectively. Therefore, the total storage required by the method of the present invention is (2×P×Q+Z)×L bytes, and the total processing latency of the method of the present invention is less than T1+T4 because pipelined processing may overlap with the direct addition processing portion.

[0060] Figure 13 A schematic block diagram of the receiver 1300 of this disclosure is shown. The receiver 1300 may include: a demodulator 1301 for demodulating symbols to obtain E soft bits corresponding to E bits; a memory 1302 having Z consecutive locations corresponding to bit positions of Z bits, wherein the values ​​of the Z consecutive locations are cleared to zero before subsequent addition; a buffer 1303 for writing E soft bits; an adder 1304 for directly adding the value of each soft bit in the buffer to the value of one of the Z consecutive locations and storing the addition result back to that location, wherein the bit in the E bits corresponding to that soft bit is either the bit in the Z bits corresponding to that location, or a copy of that bit in the Z bits; and a restorer 1305 for recovering the Z bits from the final result of the Z consecutive locations. The receiver of this disclosure can perform all the above operations of the method of this disclosure, which will not be described in detail here.

[0061] It is understood that the receiver 1300 described herein can be implemented by various components; therefore, the receiver 1300 implementing one or more functions described in this embodiment may include not only... Figure 13 The components shown may also include other components for implementing one or more of their functions. Furthermore, receiver 1300 may include a single component configured to perform two or more functions, or a separate component for each individual function. Moreover, these components may be implemented in hardware, firmware, software, or any combination thereof. For example, those skilled in the art will fully appreciate that adder 1304 may be implemented using a field-programmable gate array (FPGA), complex programmable logic device (CPLD), digital signal processor (DSP), or any other device / circuit suitable for implementing the function of adder 1304; similarly, restorer 1305 may be implemented using an FPGA, CPLD, DSP, or any other device / circuit suitable for implementing the function of restorer 1305.

[0062] It should be understood that the blocks shown in the block diagrams and / or flowcharts, and combinations of blocks shown in the block diagrams and / or flowcharts, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, and / or other programmable data processing apparatus to produce a machine such that the instructions are executed by the processor of the computer and / or other programmable data processing apparatus to create means for implementing the functions / actions specified in the blocks in the block diagrams and / or flowcharts.

[0063] It should also be understood that the functions / actions marked in the blocks of a flowchart may not occur in the order indicated in the operating instructions. For example, two blocks shown consecutively may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order, depending on the functions / actions involved. Although some diagrams include arrows on communication paths to show the main direction of communication, it should be understood that communication may occur in the opposite direction to the arrows depicted.

[0064] Furthermore, the solutions disclosed herein can take the form of a computer program on memory, having computer-usable or computer-readable program code contained in a medium for use by or in connection with an instruction execution system. In the context of this document, memory can be any medium capable of containing, storing, or adapted to transfer programs for use by or connected to an instruction execution system, apparatus, or device.

[0065] Therefore, this disclosure also provides a receiver 1400, including a processor 1401 and a memory 1402, such as Figure 14 As shown. In receiver 1400, memory 1402 stores instructions that, when executed by processor 1401, cause receiver 1400 to perform the receiver method described in the above embodiment.

[0066] This disclosure also provides a machine-readable medium (not shown) storing instructions that, when executed on a receiver, cause the receiver to perform the receiver method described in the above embodiments.

[0067] While this specification contains numerous specific implementation details, these should not be construed as limiting any implementation or the scope of any claim, but rather as descriptions of specific features of particular embodiments of a particular implementation. Certain features described in individual embodiments of this specification may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although the foregoing features may be described as functioning in certain combinations, or even originally claimed in this way, in some cases one or more features may be removed from the claimed combination, and the claimed combination may be for a sub-combination or a variation of a sub-combination.

[0068] It will be apparent to those skilled in the art that the inventive concept can be implemented in various ways as technology advances. The above embodiments are for illustrative purposes and not for limiting the scope of this disclosure. It should be understood that various modifications and variations can be made without departing from the spirit and scope of this disclosure, as is readily apparent to those skilled in the art. Such modifications and variations are considered to be within the scope of this disclosure and the appended claims. The scope of protection of this disclosure is determined by the appended claims.

Claims

1. A method used by a receiver to facilitate derate matching of bits of a symbol formed after a rate matching process from a transmitter, wherein the transmitter selects Z bits from channel-coded bits and then generates E bits by concatenating the Z bits and their copies for the rate matching process, forming a symbol per Q bits, the method comprising: The symbol is demodulated to obtain the E soft bit corresponding to the E bit; Set the values ​​of Z consecutive locations in the memory to zero, where the Z consecutive locations correspond to the bit positions of the Z bits; Write the E soft bit into the buffer device; For each soft bit in the E soft bit in the buffer device, the value of the soft bit is directly added to the value of one of the Z consecutive positions, and the addition result is stored back at that position, wherein the bit in the E bit corresponding to the soft bit is the bit in the Z bit corresponding to that position, or a copy of the bit in the Z bit; as well as Recover the Z bits from the final result of the Z consecutive positions.

2. The method of claim 1, wherein assuming i represents the index of a soft bit in the sequence of E soft bits, and K represents the offset used when selecting the Z bits during the rate matching process, then the index of the position associated with the addition of the soft bits in the Z consecutive positions is f – floor(f / Z) × Z, where f = K + (i - floor(i / Q) × Q) × (E / Q) + floor(i / Q), where floor(X) is a function that maps a real number X to the largest integer less than or equal to X.

3. The method of claim 1, wherein the E soft bit is divided into multiple parts, the buffer device includes two buffers, and the method pipelines the write and the addition by means of the following operations: Different portions of the plurality of portions are written alternately to one of the two buffers in the writing order. If the portion is not the first portion of the plurality of portions, the soft bits of the previous portion preceding the portion are read from the other of the two buffers in the reading order to perform the addition operation on the soft bits of the previous portion. The soft bits of the last part of the plurality of parts are read from the buffer storing the last part in the two buffers in the order of reading, so as to perform an addition operation on the soft bits of the last part.

4. The method according to claim 3, wherein each of the plurality of portions consists of P×Q soft bits, regarded as a Q-row P-column matrix, the writing order is column-by-column, and the reading order is row-by-row.

5. The method according to claim 4, wherein the width of the memory is an integer multiple of P×L bytes, where L is the number of bytes occupied by each soft bit in the E soft bits.

6. The method of claim 5, wherein the memory is implemented using two blocks of RAM and a register, wherein one RAM serves as a storage area consisting of all even-numbered rows of the memory, the other RAM serves as a storage area consisting of all odd-numbered rows of the memory, and the register serves as a storage area consisting of the first row of the memory.

7. The method of claim 1, wherein recovering the Z bits from the final result of the Z consecutive positions comprises: The final results of the Z consecutive positions are used as the soft bits of the Z bits, and the Z bits are recovered accordingly. or The Z bits are normalized by dividing each of the final results by ceil(E / Z) to obtain soft bits of the Z bits, thereby recovering the Z bits accordingly, where ceil(X) is a function that maps a real number X to the smallest integer greater than or equal to X.

8. The method of claim 7, wherein 1 / ceil(E / Z) is quantized by approximating 1 / ceil(E / Z) to the sum of negative powers of 2.

9. A receiver for facilitating rate matching de-rate matching of bits of a symbol formed after a rate matching process from a transmitter, wherein the transmitter selects Z bits from channel-coded bits and then generates E bits by concatenating the Z bits and their copies for the rate matching process, wherein each Q bit forms a symbol, the receiver comprising: A demodulator is used to demodulate the symbol to obtain the E soft bit corresponding to the E bit; A memory having Z consecutive locations corresponding to the bit positions of the Z bits, wherein the values ​​of the Z consecutive locations are cleared to zero before being added together below; A buffer device is used to write the E soft bit; An adder, for each soft bit in the E soft bits of the buffer device, is used to directly add the value of the soft bit to the value of one of the Z consecutive positions, and store the addition result back to the position, wherein the bit in the E bits corresponding to the soft bit is a bit in the Z bits corresponding to the position, or a copy of the bit in the Z bits; as well as A restorer is used to recover the Z bits from the final result of the Z consecutive positions.

10. The receiver of claim 9, wherein assuming i represents the index of a soft bit in the sequence of E soft bits, and K represents the offset used when selecting the Z bits during the rate matching process, the index of the position relating to the addition of the soft bits in the Z consecutive positions is f – floor(f / Z) × Z, where f = K + (i - floor(i / Q) × Q) × (E / Q) + floor(i / Q), where floor(X) is a function that maps a real number X to the largest integer less than or equal to X.

11. The receiver of claim 9, wherein the E soft bit is divided into multiple parts, the buffering device includes two buffers, and the receiver pipelines the write and the addition by: Different portions of the plurality of portions are written alternately to one of the two buffers in the writing order. If the portion is not the first portion of the plurality of portions, the soft bits of the previous portion preceding the portion are read from the other of the two buffers in the reading order to perform the addition operation on the soft bits of the previous portion. The soft bits of the last part of the plurality of parts are read from the buffer storing the last part in the two buffers in the order of reading, so as to perform an addition operation on the soft bits of the last part.

12. The receiver of claim 11, wherein each of the plurality of portions consists of P×Q soft bits, regarded as a Q-row P-column matrix, the writing order is column-by-column, and the reading order is row-by-row.

13. The receiver according to claim 12, wherein the width of the memory is an integer multiple of P×L bytes, where L is the number of bytes occupied by each soft bit in the E soft bits.

14. The receiver of claim 13, wherein the memory is implemented using two block RAMs and a register, wherein one RAM serves as a storage area consisting of all even-numbered rows of the memory, the other RAM serves as a storage area consisting of all odd-numbered rows of the memory, and the register serves as a storage area consisting of the first row of the memory.

15. The receiver of claim 9, wherein recovering the Z bits from the final result of the Z consecutive positions comprises: The final results of the Z consecutive positions are used as the soft bits of the Z bits, and the Z bits are recovered accordingly. or The Z bits are normalized by dividing each of the final results by ceil(E / Z) to obtain soft bits of the Z bits, thereby recovering the Z bits accordingly, where ceil(X) is a function that maps a real number X to the smallest integer greater than or equal to X.

16. The receiver of claim 15, wherein 1 / ceil(E / Z) is quantized by approximating 1 / ceil(E / Z) to the sum of negative powers of 2.

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