Railway train operation control system with redundant diagnostic circuit and control method

Abstract

The present invention discloses a railway train operation control system and control method with a redundant diagnostic circuit, belonging to the field of train control technology. The control system includes a communication interface device, which includes a communication unit A and a communication unit B. Communication units A and B are redundantly configured via a redundant diagnostic circuit unit; the redundant diagnostic circuit unit includes a communication unit A diagnostic circuit and a communication unit B diagnostic circuit, which includes a self-diagnosis circuit and a redundant detection circuit; the self-diagnosis circuit includes a fault logic judgment circuit and a phase-discrimination safety door drive circuit; and the control method includes the following steps: (1) communication unit A is in an operating state and communication unit B is in a standby state; a. performs fault monitoring on communication unit A; b. performs redundant diagnosis; (2) communication unit B is in an operating state and communication unit A is in a standby state; a. performs fault monitoring on communication unit B; b. performs redundant diagnosis. The control method has the characteristics of safety, reliability, and high computing speed.

Description

Technical Field

[0001] The present invention relates to the technical field of train control. Background Art

[0002] With the continuous improvement of my country's economic strength and overall national power, the mileage of railway construction continues to increase rapidly. In particular, the rapid construction and development of the high-speed railway network has profoundly influenced the travel choices of Chinese people. The increase in network density and train frequency has placed higher demands on driving safety and transportation efficiency. With the golden age of high-speed rail development, high-speed rail train control technology has also been developed in parallel to meet the higher requirements of railway transportation.

[0003] In the current railway train operation control system, the interlocking logic operation unit exchanges data with the track inspection and control equipment through the communication interface device. To ensure the reliability of data exchange, the communication interface device adopts a redundant setting with one backup and one backup. Its redundancy control is implemented through software, which increases the software operation burden of the equipment and also increases the workload of software development and maintenance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a railway train operation control system and control method with redundant diagnostic circuits, which have the characteristics of safety, reliability, high operation speed, etc.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A railway train operation control system with a redundant diagnostic circuit includes an interlocking logic operation unit, a communication interface device, a track inspection and control device, and an electronic coding unit;

[0007] Track inspection and control equipment includes track detection equipment and track execution equipment;

[0008] The interlocking logic operation unit performs logic operations by reading the manually input driving instructions and the detection signals sent by the track detection equipment to generate the execution device control signal and the code position signal; the execution device control signal is sent to the track execution device, causing the track execution device to perform the corresponding operation;

[0009] The code position signal is sent to the electronic coding unit, which converts the received code position signal into a corresponding code position frequency signal and sends it to the locomotive signal control system on the locomotive for safety control of the locomotive;

[0010] The interlocking logic operation unit exchanges data with the track inspection and control equipment through the communication interface device. The communication interface device is used to perform consistency detection on the exchanged data to undertake the corresponding work tasks of the interlocking logic operation unit and form a distributed communication structure.

[0011] The communication interface device includes a communication unit A and a communication unit B. The communication unit A and the communication unit B have the same structure: they include a communication processor CPU1 and a communication processor CPU2, and the communication processors CPU1 and CPU2 are arranged in two-in-two configurations; the communication unit A and the communication unit B are arranged in a redundant configuration with one backup and one active.

[0012] The communication unit A and the communication unit B are redundantly provided via a redundant diagnostic circuit unit;

[0013] The redundant diagnostic circuit unit includes a communication unit A diagnostic circuit and a communication unit B diagnostic circuit; the communication unit A diagnostic circuit and the communication unit B diagnostic circuit have the same structure: including a self-diagnosis circuit and a redundant detection circuit;

[0014] The self-diagnosis circuit includes a fault logic judgment circuit and a phase-discrimination safety door drive circuit;

[0015] The fault logic judgment circuit includes an OR gate 1 logic circuit and an OR gate 2 logic circuit;

[0016] The OR gate 1 logic circuit includes an OR gate 1, a first input circuit of the OR gate 1, and a second input circuit of the OR gate 1; the signal input end of the first input circuit of the OR gate 1 is used to receive a CPU1 enable control signal sent by the communication processor CPU1, and the CPU1 enable control signal controls the opening and closing of the multivibrator. The output signal of the multivibrator is transmitted to the first signal input end of the OR gate 1, thereby forming the first input circuit of the OR gate 1; the signal input end of the second input circuit of the OR gate 1 is used to receive a CPU2 enable control signal sent by the communication processor CPU2, and the CPU2 enable control signal is connected to the second signal input end of the OR gate 1 via the NOT gate 1, thereby forming the second input circuit of the OR gate 1;

[0017] When the communication processor CPU1 is in normal working state, the CPU1 enable control signal is a high-level signal to control the multivibrator to start, and the rectangular pulse signal output by the multivibrator is received by the first signal input terminal of the OR gate 1; when the communication processor CPU2 is in normal working state, the CPU2 enable control signal is a high-level signal, which is inverted by the NOT gate 1, and the NOT gate 1 outputs a low-level signal which is received by the second signal input terminal of the OR gate 1, so that the rectangular pulse signal received by the first signal input terminal of the OR gate 1 is output by the signal output terminal of the OR gate 1;

[0018] The OR gate 2 logic circuit includes an OR gate 2, a first input circuit of the OR gate 2, and a second input circuit of the OR gate 2; the signal input end of the first input circuit of the OR gate 2 is used to receive a CPU1 enable control signal sent by the communication processor CPU1, the CPU1 enable control signal controls the switching of the multivibrator, and the output signal of the multivibrator is connected to the first signal input end of the OR gate 2 via the NOT gate 2, thereby forming the first input circuit of the OR gate 2; the signal input end of the second input circuit of the OR gate 2 is used to receive a CPU2 enable control signal sent by the communication processor CPU2, and the CPU2 enable control signal is connected to the second signal input end of the OR gate 2 via the NOT gate 1, thereby forming the second input circuit of the OR gate 2;

[0019] When the communication processor CPU1 is in a normal working state, the CPU1 enable control signal is a high-level signal to control the multivibrator to start, and the rectangular pulse signal output by the multivibrator is inverted by the NOT gate 2, and the inverted rectangular pulse signal output by the NOT gate 2 is received by the first signal input terminal of the OR gate 2; when the communication processor CPU2 is in a normal working state, the CPU2 enable control signal is a high-level signal, which is inverted by the NOT gate 1, and the NOT gate 1 outputs a low-level signal which is received by the second signal input terminal of the OR gate 2, so that the inverted rectangular pulse signal received by the first signal input terminal of the OR gate 2 is output by the signal output terminal of the OR gate 2;

[0020] The phase-detection safety gate drive circuit includes a phase-detection safety gate circuit, a relay drive circuit, and a fault detection relay J1. The phase-detection safety gate circuit has two signal input terminals. The two signal input terminals of the phase-detection safety gate circuit are respectively used to receive signals from the signal output terminal of OR gate 1 and the signal output terminal of OR gate 2. When the received signal output terminal of OR gate 1 and the signal output terminal of OR gate 2 output reverse pulse signals, a relay drive signal is generated. The relay drive signal controls the relay drive circuit to generate a relay drive power supply for the power supply circuit of the fault detection relay J1.

[0021] The redundancy detection circuit is a fault detection relay J1 switch contact state detection circuit structure, and the fault detection relay J1 switch contact is electrically connected to the I / O port of the communication processor CPU1 and / or the communication processor CPU2 to read the relay switch contact state of the fault detection relay J1;

[0022] In the diagnostic circuit of communication unit A, the signal input ends of the first input circuits of OR gate 1 and OR gate 2 are used to receive a CPU1 enable control signal sent by the communication processor CPU1 of communication unit A; the signal input ends of the second input circuits of OR gate 1 and OR gate 2 are used to receive a CPU2 enable control signal sent by the communication processor CPU2 of communication unit A; and the redundancy detection circuit is used to connect to the I / O ports of the communication processor CPU1 and / or the communication processor CPU2 of communication unit B to read the relay switch contact state of the fault detection relay J1 in the diagnostic circuit of communication unit A;

[0023] In the diagnostic circuit of communication unit B, the signal input ends of the first input circuits of OR gate 1 and OR gate 2 are used to receive a CPU1 enable control signal sent by the communication processor CPU1 of communication unit B; the signal input ends of the second input circuits of OR gate 1 and OR gate 2 are used to receive a CPU2 enable control signal sent by the communication processor CPU2 of communication unit B; and the redundancy detection circuit is used to connect to the I / O ports of the communication processor CPU1 and / or the communication processor CPU2 of communication unit A to read the relay switch contact state of the fault detection relay J1 in the diagnostic circuit of communication unit B;

[0024] Communication unit A and communication unit B detect whether the other party's working status is normal through the communication unit B diagnostic circuit and the communication unit A diagnostic circuit respectively, which serves as a redundancy switching judgment condition.

[0025] The present invention is further improved in that:

[0026] The phase detection safety gate circuit includes a capacitor C1 charging circuit controlled by the transistor Q2 and a capacitor C1 discharging circuit controlled by the transistor Q1 and the photoelectric coupler E1; the positive electrode of the capacitor charging power supply VCC is connected to the positive electrode of the capacitor C1 through the current limiting resistor R2, the emitter and collector of the transistor Q2 are connected in series between the negative electrode of the capacitor C1 and the ground GND, the positive electrode of the light emitting diode at the input end of the photoelectric coupler E1 is connected to the emitter of the transistor Q2, and its negative electrode is connected to the collector of the transistor Q2 through the current limiting resistor R8, so that The photocoupler E1 is connected in parallel between the emitter and collector of the transistor Q2; the base of the transistor Q2 is a signal input terminal of the phase-detection safety gate circuit, used to receive the signal output by the OR gate 2. When the OR gate 2 outputs a high level, the transistor Q2 is turned on; the emitter and collector of the transistor Q1 are connected in series between the positive electrode of the capacitor C1 and the ground GND. The base of the transistor Q1 is another signal input terminal of the phase-detection safety gate circuit, used to receive the signal output by the OR gate 1. When the OR gate 1 outputs a high level, the transistor Q1 is turned on.

[0027] When OR gate 1 and OR gate 2 output rectangular pulse signals with opposite phases, transistor Q2 and transistor Q1 are alternately turned on. When transistor Q2 is turned on, transistor Q1 is turned off, and capacitor charging power supply VCC charges capacitor C1 via current limiting resistor R2, capacitor C1, emitter and collector of transistor Q2, and ground GND, thereby forming a charging loop for capacitor C1. When transistor Q1 is turned on, transistor Q2 is turned off, and the positive electrode of capacitor C1 is discharged via the emitter and collector of transistor Q1, ground GND, the light-emitting diode at the input end of photocoupler E1, current limiting resistor R8, and the negative electrode of capacitor C1. During the discharge process of capacitor C1, the light-emitting diode at the input end of photocoupler E1 is in a conducting and emitting state, so that the output end of photocoupler E1 is in a conducting state, thereby forming a relay driving signal.

[0028] The relay drive circuit includes a transformer T01. The DC power supply circuit of the primary coil of the transformer T01 is connected in series with an electronic switch. The electronic switch is controlled by a relay drive signal so that the electronic switch is periodically turned on according to the discharge time of the capacitor C1. This causes the DC power supply circuit of the primary coil of the transformer T01 to be periodically turned on to generate a pulsating current, so that the secondary coil of the transformer T01 induces a pulsating voltage. The pulsating voltage generated by the secondary coil of the transformer T01 is output as a DC voltage through a rectifier and filter circuit, forming the relay drive power supply for the fault detection relay J1.

[0029] The electronic switch includes a composite tube formed by connecting a transistor Q3 as a front stage and a field effect transistor Q4 as a rear stage. The drain and source of the field effect transistor Q4 are connected in series in the power supply circuit of the primary coil of the transformer T01. The output end of the photoelectric coupler E1 is connected in series between the base of the transistor Q3 and the ground. The photoelectric coupler E1 is controlled by the relay drive signal to periodically conduct the base of the transistor Q3 and the ground, thereby controlling the emitter and collector of the transistor Q3 to periodically conduct, thereby generating a pulsating voltage at the collector of the transistor Q3, forming a switching control signal for the field effect transistor Q4, thereby controlling the gate of the field effect transistor Q4, causing the drain and source of the field effect transistor Q4 to periodically conduct, thereby periodically conducting the power supply circuit of the primary coil of the transformer T01 to generate a pulsating current.

[0030] A communication interface device redundancy control method comprises the following steps:

[0031] Let the time for communication processors CPU1 and CPU2 in communication unit A and communication processors CPU1 and CPU2 in communication unit B of the communication interface device to transmit information to the interlocking logic operation unit and the time for communication processors CPU1 and CPU2 to transmit information to the track inspection and control device be communication time T1; according to the length of communication time T1 under normal working conditions, set a safety communication time threshold T0;

[0032] (1) Communication unit A is in working state and communication unit B is in standby state;

[0033] a. Fault monitoring of communication unit A. The communication processor CPU1 and the communication processor CPU2 in communication unit A each collect the communication time T1 and compare the communication time T1 with the safe communication time threshold T0. If the comparison results are T1≤T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working normally, and the enable control signal outputted by it is set to a high level; if the comparison result shows T1>T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working abnormally, and the enable control signal outputted by it is set to a low level;

[0034] b. Redundant diagnosis: the communication processor CPU1 and / or the communication processor CPU2 of the communication unit B reads the status of the relay switch contacts of the fault detection relay J1 in the diagnostic circuit of the communication unit A. When the detection result is that the normally open contact is closed or the normally closed contact is disconnected, the judgment result is that the communication unit A is working normally, and step a is repeated; when the detection result is that the normally open contact is disconnected or the normally closed contact is closed, the judgment result is that the communication unit A is working abnormally, and the communication unit B replaces the communication unit A and sends a fault information of the communication unit A to the interlocking logic operation unit;

[0035] (2) Communication unit B is in working state and communication unit A is in standby state;

[0036] a. Fault monitoring of communication unit B. The communication processors CPU1 and CPU2 in communication unit B each collect the communication time T1 and compare the communication time T1 with the safe communication time threshold T0. If the comparison results are T1≤T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working normally, and the enable control signal outputted by it is set to a high level; if the comparison result shows T1>T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working abnormally, and the enable control signal outputted by it is set to a low level;

[0037] b. Redundant diagnosis. The communication processor CPU1 and / or the communication processor CPU2 of the communication unit A reads the status of the relay switch contacts of the fault detection relay J1 in the diagnostic circuit of the communication unit B. When the detection result is that the normally open contact is closed or the normally closed contact is disconnected, the judgment result is that the communication unit B is working normally, and step a is repeated; when the detection result is that the normally open contact is disconnected or the normally closed contact is closed, the judgment result is that the communication unit B is working abnormally, and the communication unit A replaces the communication unit B and sends the communication unit B fault information to the interlocking logic operation unit.

[0038] The safety communication time threshold T0 is 2 seconds.

[0039] The beneficial effects of adopting the above technical solution are:

[0040] The communication interface equipment in this control system is set up as a redundant system with one backup and one use through redundant diagnostic circuit units. Redundant detection is performed by hardware circuits instead of software, avoiding the traditional method of implementing redundant detection through software, reducing the software operation burden of the equipment, and also reducing the workload of software development and maintenance, thereby achieving centralized management and optimal control.

[0041] It has the characteristics of safety, reliability and high computing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the circuit module structure of the railway train operation control system;

[0043] Figure 2 It is a schematic diagram of the self-diagnosis circuit structure in the redundant diagnosis circuit;

[0044] Figure 3 yes Figure 2 Schematic diagram of the fault logic judgment circuit structure;

[0045] Figure 4 yes Figure 2 Schematic diagram of the phase-detection safety door drive circuit structure;

[0046] Figure 5 It is a schematic diagram of the structure of the redundant detection circuit in the redundant diagnosis circuit;

[0047] Figure 6 This is a schematic diagram of the connection structure between the self-diagnosis circuit and the communication interface device in the diagnostic circuit of communication unit A;

[0048] Figure 7 This is a schematic diagram of the connection structure between the redundancy detection circuit and the communication interface device in the diagnostic circuit of communication unit A;

[0049] Figure 8 It is a schematic diagram of the connection structure between the self-diagnosis circuit and the communication interface device in the diagnostic circuit of the communication unit B;

[0050] Figure 9 This is a schematic diagram of the connection structure between the redundancy detection circuit and the communication interface device in the communication unit B diagnostic circuit.

[0051] The track inspection and control equipment described in this application includes track detection equipment and track execution equipment. Track detection equipment is equipment used to collect information in the railway train operation control system (for example, track occupancy status detection equipment, switch position status detection equipment, etc.); track execution equipment is equipment used to execute control commands in the railway train operation control system (for example, signal lighting control equipment, switch switching control equipment, etc.). Track inspection and control equipment performing the same task is set up as a redundant one-backup and one-reserved. When the main track inspection and control equipment fails, the work is automatically switched to the secondary track inspection and control equipment. DETAILED DESCRIPTION

[0052] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] Depend on Figures 1 to 9 As can be seen from the embodiment shown, this embodiment includes an interlocking logic operation unit, a communication interface device, a track inspection and control device, and an electronic coding unit;

[0054] Track inspection and control equipment includes track detection equipment and track execution equipment;

[0055] The interlocking logic operation unit performs logic operations by reading the manually input driving instructions and the detection signals sent by the track detection equipment to generate the execution device control signal and the code position signal; the execution device control signal is sent to the track execution device, causing the track execution device to perform the corresponding operation;

[0056] The code position signal is sent to the electronic coding unit, which converts the received code position signal into a corresponding code position frequency signal and sends it to the locomotive signal control system on the locomotive for safety control of the locomotive;

[0057] The interlocking logic operation unit exchanges data with the track inspection and control equipment through the communication interface device. The communication interface device is used to perform consistency detection on the exchanged data to undertake the corresponding work tasks of the interlocking logic operation unit and form a distributed communication structure.

[0058] The communication interface device includes a communication unit A and a communication unit B. The communication unit A and the communication unit B have the same structure: they include a communication processor CPU1 and a communication processor CPU2, and the communication processors CPU1 and CPU2 are arranged in two-in-two configurations; the communication unit A and the communication unit B are arranged in a redundant configuration with one backup and one active.

[0059] The communication unit A and the communication unit B are redundantly provided via a redundant diagnostic circuit unit;

[0060] The redundant diagnostic circuit unit includes a communication unit A diagnostic circuit and a communication unit B diagnostic circuit; the communication unit A diagnostic circuit and the communication unit B diagnostic circuit have the same structure: including a self-diagnosis circuit and a redundant detection circuit;

[0061] The self-diagnosis circuit includes a fault logic judgment circuit and a phase-discrimination safety door drive circuit;

[0062] The fault logic judgment circuit includes an OR gate 1 logic circuit and an OR gate 2 logic circuit;

[0063] The OR gate 1 logic circuit includes an OR gate 1, a first input circuit of the OR gate 1, and a second input circuit of the OR gate 1; the signal input end of the first input circuit of the OR gate 1 is used to receive a CPU1 enable control signal sent by the communication processor CPU1, and the CPU1 enable control signal controls the opening and closing of the multivibrator. The output signal of the multivibrator is transmitted to the first signal input end of the OR gate 1, thereby forming the first input circuit of the OR gate 1; the signal input end of the second input circuit of the OR gate 1 is used to receive a CPU2 enable control signal sent by the communication processor CPU2, and the CPU2 enable control signal is connected to the second signal input end of the OR gate 1 via the NOT gate 1, thereby forming the second input circuit of the OR gate 1;

[0064] When the communication processor CPU1 is in normal working state, the CPU1 enable control signal is a high-level signal to control the multivibrator to start, and the rectangular pulse signal output by the multivibrator is received by the first signal input terminal of the OR gate 1; when the communication processor CPU2 is in normal working state, the CPU2 enable control signal is a high-level signal, which is inverted by the NOT gate 1, and the NOT gate 1 outputs a low-level signal which is received by the second signal input terminal of the OR gate 1, so that the rectangular pulse signal received by the first signal input terminal of the OR gate 1 is output by the signal output terminal of the OR gate 1;

[0065] The OR gate 2 logic circuit includes an OR gate 2, a first input circuit of the OR gate 2, and a second input circuit of the OR gate 2; the signal input end of the first input circuit of the OR gate 2 is used to receive a CPU1 enable control signal sent by the communication processor CPU1, the CPU1 enable control signal controls the switching of the multivibrator, and the output signal of the multivibrator is connected to the first signal input end of the OR gate 2 via the NOT gate 2, thereby forming the first input circuit of the OR gate 2; the signal input end of the second input circuit of the OR gate 2 is used to receive a CPU2 enable control signal sent by the communication processor CPU2, and the CPU2 enable control signal is connected to the second signal input end of the OR gate 2 via the NOT gate 1, thereby forming the second input circuit of the OR gate 2;

[0066] When the communication processor CPU1 is in a normal working state, the CPU1 enable control signal is a high-level signal to control the multivibrator to start, and the rectangular pulse signal output by the multivibrator is inverted by the NOT gate 2, and the inverted rectangular pulse signal output by the NOT gate 2 is received by the first signal input terminal of the OR gate 2; when the communication processor CPU2 is in a normal working state, the CPU2 enable control signal is a high-level signal, which is inverted by the NOT gate 1, and the NOT gate 1 outputs a low-level signal which is received by the second signal input terminal of the OR gate 2, so that the inverted rectangular pulse signal received by the first signal input terminal of the OR gate 2 is output by the signal output terminal of the OR gate 2;

[0067] The phase-detection safety gate drive circuit includes a phase-detection safety gate circuit, a relay drive circuit, and a fault detection relay J1. The phase-detection safety gate circuit has two signal input terminals. The two signal input terminals of the phase-detection safety gate circuit are respectively used to receive signals from the signal output terminal of OR gate 1 and the signal output terminal of OR gate 2. When the received signal output terminal of OR gate 1 and the signal output terminal of OR gate 2 output reverse pulse signals, a relay drive signal is generated. The relay drive signal controls the relay drive circuit to generate a relay drive power supply for the power supply circuit of the fault detection relay J1.

[0068] The redundancy detection circuit is a fault detection relay J1 switch contact state detection circuit structure, and the fault detection relay J1 switch contact is electrically connected to the I / O port of the communication processor CPU1 and / or the communication processor CPU2 to read the relay switch contact state of the fault detection relay J1 (from the prior art);

[0069] In the diagnostic circuit of communication unit A, the signal input ends of the first input circuits of OR gate 1 and OR gate 2 are used to receive a CPU1 enable control signal sent by the communication processor CPU1 of communication unit A; the signal input ends of the second input circuits of OR gate 1 and OR gate 2 are used to receive a CPU2 enable control signal sent by the communication processor CPU2 of communication unit A; and the redundancy detection circuit is used to connect to the I / O ports of the communication processor CPU1 and / or the communication processor CPU2 of communication unit B to read the relay switch contact state of the fault detection relay J1 in the diagnostic circuit of communication unit A;

[0070] In the diagnostic circuit of communication unit B, the signal input ends of the first input circuits of OR gate 1 and OR gate 2 are used to receive a CPU1 enable control signal sent by the communication processor CPU1 of communication unit B; the signal input ends of the second input circuits of OR gate 1 and OR gate 2 are used to receive a CPU2 enable control signal sent by the communication processor CPU2 of communication unit B; and the redundancy detection circuit is used to connect to the I / O ports of the communication processor CPU1 and / or the communication processor CPU2 of communication unit A to read the relay switch contact state of the fault detection relay J1 in the diagnostic circuit of communication unit B;

[0071] Communication unit A and communication unit B detect whether the other party's working status is normal through the communication unit B diagnostic circuit and the communication unit A diagnostic circuit respectively, which serves as a redundancy switching judgment condition.

[0072] The phase detection safety gate circuit includes a capacitor C1 charging circuit controlled by the transistor Q2 and a capacitor C1 discharging circuit controlled by the transistor Q1 and the photoelectric coupler E1; the positive electrode of the capacitor charging power supply VCC is connected to the positive electrode of the capacitor C1 through the current limiting resistor R2, the emitter and collector of the transistor Q2 are connected in series between the negative electrode of the capacitor C1 and the ground GND, the positive electrode of the light emitting diode at the input end of the photoelectric coupler E1 is connected to the emitter of the transistor Q2, and its negative electrode is connected to the collector of the transistor Q2 through the current limiting resistor R8, so that The photocoupler E1 is connected in parallel between the emitter and collector of the transistor Q2; the base of the transistor Q2 is a signal input terminal of the phase-detection safety gate circuit, used to receive the signal output by the OR gate 2. When the OR gate 2 outputs a high level, the transistor Q2 is turned on; the emitter and collector of the transistor Q1 are connected in series between the positive electrode of the capacitor C1 and the ground GND. The base of the transistor Q1 is another signal input terminal of the phase-detection safety gate circuit, used to receive the signal output by the OR gate 1. When the OR gate 1 outputs a high level, the transistor Q1 is turned on.

[0073] When OR gate 1 and OR gate 2 output rectangular pulse signals with opposite phases, transistor Q2 and transistor Q1 are alternately turned on. When transistor Q2 is turned on, transistor Q1 is turned off, and capacitor charging power supply VCC charges capacitor C1 via current limiting resistor R2, capacitor C1, emitter and collector of transistor Q2, and ground GND, thereby forming a charging loop for capacitor C1. When transistor Q1 is turned on, transistor Q2 is turned off, and the positive electrode of capacitor C1 is discharged via the emitter and collector of transistor Q1, ground GND, the light-emitting diode at the input end of photocoupler E1, current limiting resistor R8, and the negative electrode of capacitor C1. During the discharge process of capacitor C1, the light-emitting diode at the input end of photocoupler E1 is in a conducting and emitting state, so that the output end of photocoupler E1 is in a conducting state, thereby forming a relay driving signal.

[0074] The relay drive circuit includes a transformer T01. The DC power supply circuit of the primary coil of the transformer T01 is connected in series with an electronic switch. The electronic switch is controlled by a relay drive signal so that the electronic switch is periodically turned on according to the discharge time of the capacitor C1. This causes the DC power supply circuit of the primary coil of the transformer T01 to be periodically turned on to generate a pulsating current, so that the secondary coil of the transformer T01 induces a pulsating voltage. The pulsating voltage generated by the secondary coil of the transformer T01 is output as a DC voltage through a rectifier and filter circuit, forming the relay drive power supply of the fault detection relay J1 to drive its operation.

[0075] The electronic switch includes a composite tube formed by connecting a transistor Q3 as a front stage and a field effect transistor Q4 as a rear stage. The drain and source of the field effect transistor Q4 are connected in series in the power supply circuit of the primary coil of the transformer T01. The output end of the photoelectric coupler E1 is connected in series between the base of the transistor Q3 and the ground. The photoelectric coupler E1 is controlled by the relay drive signal to periodically conduct the base of the transistor Q3 and the ground, thereby controlling the emitter and collector of the transistor Q3 to periodically conduct, thereby generating a pulsating voltage at the collector of the transistor Q3, forming a switching control signal for the field effect transistor Q4, thereby controlling the gate of the field effect transistor Q4, causing the drain and source of the field effect transistor Q4 to periodically conduct, thereby periodically conducting the power supply circuit of the primary coil of the transformer T01 to generate a pulsating current.

[0076] A communication interface device redundancy control method comprises the following steps:

[0077] Let the time for communication processors CPU1 and CPU2 in communication unit A and communication processors CPU1 and CPU2 in communication unit B of the communication interface device to transmit information to the interlocking logic operation unit and the time for communication processors CPU1 and CPU2 to transmit information to the track inspection and control device be communication time T1; according to the length of communication time T1 under normal working conditions, set a safety communication time threshold T0;

[0078] (1) Communication unit A is in working state and communication unit B is in standby state;

[0079] a. Fault monitoring of communication unit A. The communication processor CPU1 and the communication processor CPU2 in communication unit A each collect the communication time T1 and compare the communication time T1 with the safe communication time threshold T0. If the comparison results are T1≤T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working normally, and the enable control signal outputted by it is set to a high level; if the comparison result shows T1>T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working abnormally, and the enable control signal outputted by it is set to a low level;

[0080] b. Redundant diagnosis: the communication processor CPU1 and / or the communication processor CPU2 of the communication unit B reads the status of the relay switch contacts of the fault detection relay J1 in the diagnostic circuit of the communication unit A. When the detection result is that the normally open contact is closed or the normally closed contact is disconnected, the judgment result is that the communication unit A is working normally, and step a is repeated; when the detection result is that the normally open contact is disconnected or the normally closed contact is closed, the judgment result is that the communication unit A is working abnormally, and the communication unit B replaces the communication unit A and sends a fault information of the communication unit A to the interlocking logic operation unit;

[0081] (2) Communication unit B is in working state and communication unit A is in standby state;

[0082] a. Fault monitoring of communication unit B. The communication processors CPU1 and CPU2 in communication unit B each collect the communication time T1 and compare the communication time T1 with the safe communication time threshold T0. If the comparison results are T1≤T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working normally, and the enable control signal outputted by it is set to a high level; if the comparison result shows T1>T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working abnormally, and the enable control signal outputted by it is set to a low level;

[0083] b. Redundant diagnosis. The communication processor CPU1 and / or the communication processor CPU2 of the communication unit A reads the status of the relay switch contacts of the fault detection relay J1 in the diagnostic circuit of the communication unit B. When the detection result is that the normally open contact is closed or the normally closed contact is disconnected, the judgment result is that the communication unit B is working normally, and step a is repeated; when the detection result is that the normally open contact is disconnected or the normally closed contact is closed, the judgment result is that the communication unit B is working abnormally, and the communication unit A replaces the communication unit B and sends the communication unit B fault information to the interlocking logic operation unit.

[0084] The safety communication time threshold T0 is 2 seconds.

Claims

1. A railway train operation control system with redundant diagnostic circuits, comprising an interlocking logic operation unit, a communication interface device, a track inspection and control device, and an electronic coding unit; The track inspection and control equipment includes a track detection device and a track execution device; The interlocking logic operation unit performs logic operations by reading the manually input driving instructions and the detection signals sent by the track detection equipment to generate an execution device control signal and a code position signal; the execution device control signal is sent to the track execution device, causing the track execution device to perform the corresponding operation; The code bit signal is sent to the electronic coding unit, and the electronic coding unit converts the received code bit signal into a corresponding code bit frequency signal and sends it to the locomotive signal control system on the locomotive for safety control of the locomotive; The interlocking logic operation unit exchanges data with the track inspection and control device through the communication interface device. The communication interface device is used to perform consistency detection on the exchanged data to undertake the corresponding work tasks of the interlocking logic operation unit, forming a distributed communication structure; The communication interface device includes a communication unit A and a communication unit B. The communication unit A and the communication unit B have the same structure: they include a communication processor CPU1 and a communication processor CPU2, and the communication processor CPU1 and the communication processor CPU2 are arranged in two-in-two configurations; the communication unit A and the communication unit B are arranged in a redundant configuration with one backup and one active; the characteristics are: The communication unit A and the communication unit B are redundantly configured via a redundant diagnostic circuit unit; The redundant diagnostic circuit unit includes a communication unit A diagnostic circuit and a communication unit B diagnostic circuit; the communication unit A diagnostic circuit and the communication unit B diagnostic circuit have the same structure: including a self-diagnosis circuit and a redundant detection circuit; The self-diagnosis circuit includes a fault logic judgment circuit and a phase detection safety door drive circuit; The fault logic judgment circuit includes an OR gate 1 logic circuit and an OR gate 2 logic circuit; The OR gate 1 logic circuit includes an OR gate 1, a first input circuit of the OR gate 1, and a second input circuit of the OR gate 1; the signal input end of the first input circuit of the OR gate 1 is used to receive a CPU1 enable control signal sent by the communication processor CPU1, the CPU1 enable control signal controls the opening and closing of the multivibrator, and the output signal of the multivibrator is transmitted to the first signal input end of the OR gate 1, thereby forming the first input circuit of the OR gate 1; the signal input end of the second input circuit of the OR gate 1 is used to receive a CPU2 enable control signal sent by the communication processor CPU2, and the CPU2 enable control signal is connected to the second signal input end of the OR gate 1 via the NOT gate 1, thereby forming the second input circuit of the OR gate 1; When the communication processor CPU1 is in a normal working state, the CPU1 enable control signal is a high-level signal to control the multivibrator to start, and the rectangular pulse signal output by the multivibrator is received by the first signal input terminal of the OR gate 1; when the communication processor CPU2 is in a normal working state, the CPU2 enable control signal is a high-level signal, which is inverted by the NOT gate 1, and the NOT gate 1 outputs a low-level signal which is received by the second signal input terminal of the OR gate 1, so that the rectangular pulse signal received by the first signal input terminal of the OR gate 1 is output by the signal output terminal of the OR gate 1; The OR gate 2 logic circuit includes an OR gate 2, a first input circuit of the OR gate 2, and a second input circuit of the OR gate 2; the signal input end of the first input circuit of the OR gate 2 is used to receive the CPU1 enable control signal sent by the communication processor CPU1, and the CPU1 enable control signal controls the opening and closing of the multivibrator, and the output signal of the multivibrator is connected to the first signal input end of the OR gate 2 via the NOT gate 2, thereby forming the first input circuit of the OR gate 2; the signal input end of the second input circuit of the OR gate 2 is used to receive the CPU2 enable control signal sent by the communication processor CPU2, and the CPU2 enable control signal is connected to the second signal input end of the OR gate 2 via the NOT gate 1, thereby forming the second input circuit of the OR gate 2; When the communication processor CPU1 is in a normal working state, the CPU1 enable control signal is a high-level signal to control the multivibrator to start, and the rectangular pulse signal output by the multivibrator is inverted by the NOT gate 2, and the inverted rectangular pulse signal output by the NOT gate 2 is received by the first signal input terminal of the OR gate 2; when the communication processor CPU2 is in a normal working state, the CPU2 enable control signal is a high-level signal, which is inverted by the NOT gate 1, and the NOT gate 1 outputs a low-level signal which is received by the second signal input terminal of the OR gate 2, so that the inverted rectangular pulse signal received by the first signal input terminal of the OR gate 2 is output by the signal output terminal of the OR gate 2; The phase-detection safety gate drive circuit includes a phase-detection safety gate circuit, a relay drive circuit, and a fault detection relay J1; the phase-detection safety gate circuit has two signal input terminals; the two signal input terminals of the phase-detection safety gate circuit are respectively used to receive signals from the OR gate 1 signal output terminal and the OR gate 2 signal output terminal, and when the received OR gate 1 signal output terminal and the OR gate 2 signal output terminal output reverse pulse signals, a relay drive signal is generated, and the relay drive signal controls the relay drive circuit to generate a relay drive power supply for the power supply circuit of the fault detection relay J1; The redundant detection circuit is a fault detection relay J1 switch contact state detection circuit structure, and the fault detection relay J1 switch contact is electrically connected to the I / O port of the communication processor CPU1 and / or the communication processor CPU2 to read the relay switch contact state of the fault detection relay J1; In the diagnostic circuit of the communication unit A, the signal input ends of the first input circuits of the OR gate 1 and the OR gate 2 are used to receive the CPU1 enable control signal sent by the communication processor CPU1 of the communication unit A; the signal input ends of the second input circuits of the OR gate 1 and the OR gate 2 are used to receive the CPU2 enable control signal sent by the communication processor CPU2 of the communication unit A; The redundancy detection circuit is used to connect to the I / O port of the communication processor CPU1 and / or the communication processor CPU2 of the communication unit B to read the relay switch contact state of the fault detection relay J1 in the diagnostic circuit of the communication unit A; In the diagnostic circuit of the communication unit B, the signal input ends of the first input circuits of the OR gate 1 and the OR gate 2 are used to receive the CPU1 enable control signal sent by the communication processor CPU1 of the communication unit B; the signal input ends of the second input circuits of the OR gate 1 and the OR gate 2 are used to receive the CPU2 enable control signal sent by the communication processor CPU2 of the communication unit B; The redundancy detection circuit is used to connect to the I / O port of the communication processor CPU1 and / or the communication processor CPU2 of the communication unit A to read the relay switch contact state of the fault detection relay J1 in the diagnostic circuit of the communication unit B; The communication unit A and the communication unit B respectively detect whether the other party's working status is normal through the communication unit B diagnostic circuit and the communication unit A diagnostic circuit, which serves as a redundancy switching judgment condition.

2. The railway train operation control system with redundant diagnostic circuit according to claim 1, characterized in that: The phase detection safety gate circuit includes a capacitor C1 charging circuit controlled by the transistor Q2 and a capacitor C1 discharging circuit controlled by the transistor Q1 and the photoelectric coupler E1; the positive electrode of the capacitor charging power supply VCC is connected to the positive electrode of the capacitor C1 through the current limiting resistor R2, the emitter and collector of the transistor Q2 are connected in series between the negative electrode of the capacitor C1 and the ground GND, the positive electrode of the light emitting diode at the input end of the photoelectric coupler E1 is connected to the emitter of the transistor Q2, and the negative electrode thereof is connected to the collector of the transistor Q2 through the current limiting resistor R8, so that the photoelectric coupler E1 1 is connected in parallel between the emitter and collector of the transistor Q2; the base of the transistor Q2 is a signal input terminal of the phase-detection safety gate circuit, used for receiving the signal output by the OR gate 2, and when the OR gate 2 outputs a high level, the transistor Q2 is turned on; the emitter and collector of the transistor Q1 are connected in series between the positive electrode of the capacitor C1 and the ground GND, and the base of the transistor Q1 is another signal input terminal of the phase-detection safety gate circuit, used for receiving the signal output by the OR gate 1, and when the OR gate 1 outputs a high level, the transistor Q1 is turned on; When the OR gate 1 and the OR gate 2 output rectangular pulse signals with opposite phases, the transistor Q2 and the transistor Q1 are alternately turned on. When the transistor Q2 is turned on, the transistor Q1 is turned off, and the capacitor charging power supply VCC charges the capacitor C1 through the current limiting resistor R2, the capacitor C1, the emitter and collector of the transistor Q2, and the ground GND, so as to form a charging circuit for the capacitor C1; when the transistor Q1 is turned on, the transistor Q2 is turned off, and the positive electrode of the capacitor C1 is discharged through the emitter and collector of the transistor Q1, the ground GND, the light-emitting diode at the input end of the photocoupler E1, the current limiting resistor R8, and the negative electrode of the capacitor C1. During the discharge process of the capacitor C1, the light-emitting diode at the input end of the photocoupler E1 is in a conducting and emitting state, so that the output end of the photocoupler E1 is in a conducting state, thereby forming a relay driving signal; The relay drive circuit includes a transformer T01. The DC power supply circuit of the primary coil of the transformer T01 is connected in series with an electronic switch. The electronic switch is controlled by the relay drive signal so that the electronic switch is periodically turned on according to the discharge time of the capacitor C1, thereby causing the DC power supply circuit of the primary coil of the transformer T01 to be periodically turned on to generate a pulsating current, so that the secondary coil of the transformer T01 induces a pulsating voltage. The pulsating voltage generated by the secondary coil of the transformer T01 outputs a DC voltage through a rectifier and filter circuit to form the relay drive power supply of the fault detection relay J1.

3. The railway train operation control system with redundant diagnostic circuit according to claim 2, characterized in that: The electronic switch includes a composite tube formed by connecting a transistor Q3 as a front stage and a field effect transistor Q4 as a back stage. The drain and source of the field effect transistor Q4 are connected in series in the power supply circuit of the primary coil of the transformer T01. The output end of the photoelectric coupler E1 is connected in series between the base of the transistor Q3 and the ground. The photoelectric coupler E1 is controlled by the relay drive signal to periodically conduct the base of the transistor Q3 and the ground, thereby controlling the emitter and collector of the transistor Q3 to periodically conduct, thereby generating a pulsating voltage at the collector of the transistor Q3, forming a switching control signal for the field effect transistor Q4, thereby controlling the gate of the field effect transistor Q4, causing the drain and source of the field effect transistor Q4 to periodically conduct, thereby periodically conducting the power supply circuit of the primary coil of the transformer T01 to generate a pulsating current.

4. A communication interface device redundancy control method, characterized in that: Implementation of a railway train operation control system with a redundant diagnostic circuit based on any one of claims 1 to 3; The method comprises the following steps: The communication time T1 is defined as the time for the communication processors CPU1 and CPU2 in the communication unit A and the communication processors CPU1 and CPU2 in the communication unit B of the communication interface device to transmit information to the interlocking logic operation unit and to transmit information to the track inspection and control device. The safety communication time threshold T0 is set based on the duration of the communication time T1 under normal working conditions. (1) Communication unit A is in working state and communication unit B is in standby state; a. Fault monitoring of the communication unit A. The communication processor CPU1 and the communication processor CPU2 in the communication unit A each collect the communication time T1, and compare the communication time T1 with the safe communication time threshold T0. If the comparison results are T1≤T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working normally, and the enable control signal outputted by it is set to a high level; if the comparison result shows T1>T0, the judgment result is that the communication processor CPU1 or the communication processor CPU2 is working abnormally, and the enable control signal outputted by it is set to a low level; b. Redundant diagnosis: the communication processor CPU1 and / or the communication processor CPU2 of the communication unit B reads the switch contact status of the fault detection relay J1 in the diagnostic circuit of the communication unit A. When the detection result is that the normally open contact is closed or the normally closed contact is disconnected, the judgment result is that the communication unit A is working normally, and step a is repeated; when the detection result is that the normally open contact is disconnected or the normally closed contact is closed, the judgment result is that the communication unit A is working abnormally, and the communication unit B replaces the communication unit A and sends the communication unit A fault information to the interlocking logic operation unit; (2) Communication unit B is in working state and communication unit A is in standby state; a. Fault monitoring of the communication unit B, the communication processor CPU1 and the communication processor CPU2 in the communication unit B each collect the communication time T1, the communication time T1 is compared with the safe communication time threshold T0, if the comparison results are T1≤T0, then the result is that the communication processor CPU1 or the communication processor CPU2 is working properly, and the enable control signal output is set to a high level; if the comparison result T1>T0, then the result is that the communication processor CPU1 or the communication processor CPU2 is working abnormally, and the enable control signal output is set to a low level; b. Redundant diagnosis: the communication processor CPU1 and / or the communication processor CPU2 of the communication unit A reads the relay switch contact status of the fault detection relay J1 in the diagnostic circuit of the communication unit B. When the detection result is that the normally open contact is closed or the normally closed contact is disconnected, it is judged that the communication unit B is working normally, and step a is repeated; when the detection result is that the normally open contact is disconnected or the normally closed contact is closed, it is judged that the communication unit B is working abnormally, and the communication unit A replaces the communication unit B and sends the fault information of the communication unit B to the interlocking logic operation unit.

5. The communication interface device redundancy control method according to claim 4, characterized in that: The secure communication time threshold T0 is 2 seconds.

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